* [PATCH 01/12] drm/i915: Bump RING_FAULT engine ID bits
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
@ 2025-02-11 23:19 ` Ville Syrjala
2025-02-21 13:34 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 02/12] drm/i915: Relocate RING_FAULT bits Ville Syrjala
` (18 subsequent siblings)
19 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjala @ 2025-02-11 23:19 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The fault engine ID field has been 5 bits since icl. Bump our
define to match. The extra bits were unused before icl so we
should be able to use the larger mask unconditionally.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 6dba65e54cdb..5e4f0545f558 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1041,7 +1041,7 @@
#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
#define XEHP_RING_FAULT_REG MCR_REG(0xcec4)
#define XELPMP_RING_FAULT_REG _MMIO(0xcec4)
-#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
+#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x1f)
#define RING_FAULT_GTTSEL_MASK (1 << 11)
#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
--
2.45.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 02/12] drm/i915: Relocate RING_FAULT bits
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
2025-02-11 23:19 ` [PATCH 01/12] drm/i915: Bump RING_FAULT engine ID bits Ville Syrjala
@ 2025-02-11 23:19 ` Ville Syrjala
2025-02-21 13:45 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 03/12] drm/i915: Use REG_BIT() & co. for ring fault registers Ville Syrjala
` (17 subsequent siblings)
19 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjala @ 2025-02-11 23:19 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We share the bit definitions between the older
RING_FAULT registers and their various gen12+
counterparts. Currently the bits are defined next
to the new registers which isn't what we typically do.
Move the bit definitions next the older register offsets,
and leave breadcrumbs around the gen12+ registers to make
it easier to find the right bits.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 5e4f0545f558..2d3da98e94f0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -326,6 +326,11 @@
_RING_FAULT_REG_VCS, \
_RING_FAULT_REG_VECS, \
_RING_FAULT_REG_BCS))
+#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x1f)
+#define RING_FAULT_GTTSEL_MASK (1 << 11)
+#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
+#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
+#define RING_FAULT_VALID (1 << 0)
#define ERROR_GEN6 _MMIO(0x40a0)
@@ -385,6 +390,8 @@
#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
+#define FAULT_GTT_SEL (1 << 4)
+#define FAULT_VA_HIGH_BITS (0xf << 0)
#define GEN11_GACB_PERF_CTRL _MMIO(0x4b80)
#define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
@@ -1035,17 +1042,12 @@
#define XEHP_FAULT_TLB_DATA0 MCR_REG(0xceb8)
#define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc)
#define XEHP_FAULT_TLB_DATA1 MCR_REG(0xcebc)
-#define FAULT_VA_HIGH_BITS (0xf << 0)
-#define FAULT_GTT_SEL (1 << 4)
+/* see GEN8_FAULT_TLB_DATA0/1 */
#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
#define XEHP_RING_FAULT_REG MCR_REG(0xcec4)
#define XELPMP_RING_FAULT_REG _MMIO(0xcec4)
-#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x1f)
-#define RING_FAULT_GTTSEL_MASK (1 << 11)
-#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
-#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
-#define RING_FAULT_VALID (1 << 0)
+/* see GEN8_RING_FAULT_REG */
#define GEN12_GFX_TLB_INV_CR _MMIO(0xced8)
#define XEHP_GFX_TLB_INV_CR MCR_REG(0xced8)
--
2.45.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH 02/12] drm/i915: Relocate RING_FAULT bits
2025-02-11 23:19 ` [PATCH 02/12] drm/i915: Relocate RING_FAULT bits Ville Syrjala
@ 2025-02-21 13:45 ` Andi Shyti
0 siblings, 0 replies; 36+ messages in thread
From: Andi Shyti @ 2025-02-21 13:45 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
Hi Ville,
On Wed, Feb 12, 2025 at 01:19:30AM +0200, Ville Syrjala wrote:
> We share the bit definitions between the older
> RING_FAULT registers and their various gen12+
> counterparts. Currently the bits are defined next
> to the new registers which isn't what we typically do.
>
> Move the bit definitions next the older register offsets,
> and leave breadcrumbs around the gen12+ registers to make
> it easier to find the right bits.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 16 +++++++++-------
> 1 file changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 5e4f0545f558..2d3da98e94f0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -326,6 +326,11 @@
> _RING_FAULT_REG_VCS, \
> _RING_FAULT_REG_VECS, \
> _RING_FAULT_REG_BCS))
> +#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x1f)
> +#define RING_FAULT_GTTSEL_MASK (1 << 11)
> +#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
> +#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
> +#define RING_FAULT_VALID (1 << 0)
Perhaps we can add a comment here to tell that this is referenced
below. But not a big deal, though.
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Thanks,
Andi
>
> #define ERROR_GEN6 _MMIO(0x40a0)
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 03/12] drm/i915: Use REG_BIT() & co. for ring fault registers
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
2025-02-11 23:19 ` [PATCH 01/12] drm/i915: Bump RING_FAULT engine ID bits Ville Syrjala
2025-02-11 23:19 ` [PATCH 02/12] drm/i915: Relocate RING_FAULT bits Ville Syrjala
@ 2025-02-11 23:19 ` Ville Syrjala
2025-02-24 9:52 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 04/12] drm/i915: Document which RING_FAULT bits apply to which platforms Ville Syrjala
` (16 subsequent siblings)
19 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjala @ 2025-02-11 23:19 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Update the ring fault registers to use the modern REG_BIT()
stuff.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 20 ++++++++++----------
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 14 +++++++-------
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index c4a351ebf395..04b43852a397 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -310,13 +310,13 @@ static void gen6_check_faults(struct intel_gt *gt)
gt_dbg(gt, "Unexpected fault\n"
"\tAddr: 0x%08lx\n"
"\tAddress space: %s\n"
- "\tSource ID: %ld\n"
- "\tType: %ld\n",
+ "\tSource ID: %d\n"
+ "\tType: %d\n",
fault & PAGE_MASK,
fault & RING_FAULT_GTTSEL_MASK ?
"GGTT" : "PPGTT",
- RING_FAULT_SRCID(fault),
- RING_FAULT_FAULT_TYPE(fault));
+ REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault),
+ REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault));
}
}
}
@@ -351,9 +351,9 @@ static void xehp_check_faults(struct intel_gt *gt)
"\tType: %d\n",
upper_32_bits(fault_addr), lower_32_bits(fault_addr),
fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
- GEN8_RING_FAULT_ENGINE_ID(fault),
- RING_FAULT_SRCID(fault),
- RING_FAULT_FAULT_TYPE(fault));
+ REG_FIELD_GET(RING_FAULT_ENGINE_ID_MASK, fault),
+ REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault),
+ REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault));
}
}
@@ -392,9 +392,9 @@ static void gen8_check_faults(struct intel_gt *gt)
"\tType: %d\n",
upper_32_bits(fault_addr), lower_32_bits(fault_addr),
fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
- GEN8_RING_FAULT_ENGINE_ID(fault),
- RING_FAULT_SRCID(fault),
- RING_FAULT_FAULT_TYPE(fault));
+ REG_FIELD_GET(RING_FAULT_ENGINE_ID_MASK, fault),
+ REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault),
+ REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault));
}
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 2d3da98e94f0..764424d48a25 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -326,11 +326,11 @@
_RING_FAULT_REG_VCS, \
_RING_FAULT_REG_VECS, \
_RING_FAULT_REG_BCS))
-#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x1f)
-#define RING_FAULT_GTTSEL_MASK (1 << 11)
-#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
-#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
-#define RING_FAULT_VALID (1 << 0)
+#define RING_FAULT_ENGINE_ID_MASK REG_GENMASK(16, 12)
+#define RING_FAULT_GTTSEL_MASK REG_BIT(11)
+#define RING_FAULT_SRCID_MASK REG_GENMASK(10, 3)
+#define RING_FAULT_FAULT_TYPE_MASK REG_GENMASK(2, 1)
+#define RING_FAULT_VALID REG_BIT(0)
#define ERROR_GEN6 _MMIO(0x40a0)
@@ -390,8 +390,8 @@
#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
-#define FAULT_GTT_SEL (1 << 4)
-#define FAULT_VA_HIGH_BITS (0xf << 0)
+#define FAULT_GTT_SEL REG_BIT(4)
+#define FAULT_VA_HIGH_BITS REG_GENMASK(3, 0)
#define GEN11_GACB_PERF_CTRL _MMIO(0x4b80)
#define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
--
2.45.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 04/12] drm/i915: Document which RING_FAULT bits apply to which platforms
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
` (2 preceding siblings ...)
2025-02-11 23:19 ` [PATCH 03/12] drm/i915: Use REG_BIT() & co. for ring fault registers Ville Syrjala
@ 2025-02-11 23:19 ` Ville Syrjala
2025-02-24 9:52 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 05/12] drm/i915: Introduce RING_FAULT_VADDR_MASK Ville Syrjala
` (15 subsequent siblings)
19 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjala @ 2025-02-11 23:19 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The RING_FAULT bits have change a bit over the years. Document
which platforms use which bits.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 764424d48a25..1d318993a652 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -326,10 +326,10 @@
_RING_FAULT_REG_VCS, \
_RING_FAULT_REG_VECS, \
_RING_FAULT_REG_BCS))
-#define RING_FAULT_ENGINE_ID_MASK REG_GENMASK(16, 12)
-#define RING_FAULT_GTTSEL_MASK REG_BIT(11)
+#define RING_FAULT_ENGINE_ID_MASK REG_GENMASK(16, 12) /* bdw+ */
+#define RING_FAULT_GTTSEL_MASK REG_BIT(11) /* pre-bdw */
#define RING_FAULT_SRCID_MASK REG_GENMASK(10, 3)
-#define RING_FAULT_FAULT_TYPE_MASK REG_GENMASK(2, 1)
+#define RING_FAULT_FAULT_TYPE_MASK REG_GENMASK(2, 1) /* ivb+ */
#define RING_FAULT_VALID REG_BIT(0)
#define ERROR_GEN6 _MMIO(0x40a0)
--
2.45.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 05/12] drm/i915: Introduce RING_FAULT_VADDR_MASK
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
` (3 preceding siblings ...)
2025-02-11 23:19 ` [PATCH 04/12] drm/i915: Document which RING_FAULT bits apply to which platforms Ville Syrjala
@ 2025-02-11 23:19 ` Ville Syrjala
2025-02-24 9:54 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 06/12] drm/i915: Extract gen8_report_fault() Ville Syrjala
` (14 subsequent siblings)
19 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjala @ 2025-02-11 23:19 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add a proper bitmask definition for the pre-bdw fault
virtual address bits insted of abusing PAGE_MASK.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 8 +++++---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 04b43852a397..b8189754edb7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -302,17 +302,19 @@ static void gen6_check_faults(struct intel_gt *gt)
{
struct intel_engine_cs *engine;
enum intel_engine_id id;
- unsigned long fault;
for_each_engine(engine, gt, id) {
+ u32 fault;
+
fault = GEN6_RING_FAULT_REG_READ(engine);
+
if (fault & RING_FAULT_VALID) {
gt_dbg(gt, "Unexpected fault\n"
- "\tAddr: 0x%08lx\n"
+ "\tAddr: 0x%08x\n"
"\tAddress space: %s\n"
"\tSource ID: %d\n"
"\tType: %d\n",
- fault & PAGE_MASK,
+ fault & RING_FAULT_VADDR_MASK,
fault & RING_FAULT_GTTSEL_MASK ?
"GGTT" : "PPGTT",
REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault),
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 1d318993a652..c58192e6f078 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -326,6 +326,7 @@
_RING_FAULT_REG_VCS, \
_RING_FAULT_REG_VECS, \
_RING_FAULT_REG_BCS))
+#define RING_FAULT_VADDR_MASK REG_GENMASK(31, 12) /* pre-bdw */
#define RING_FAULT_ENGINE_ID_MASK REG_GENMASK(16, 12) /* bdw+ */
#define RING_FAULT_GTTSEL_MASK REG_BIT(11) /* pre-bdw */
#define RING_FAULT_SRCID_MASK REG_GENMASK(10, 3)
--
2.45.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 06/12] drm/i915: Extract gen8_report_fault()
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
` (4 preceding siblings ...)
2025-02-11 23:19 ` [PATCH 05/12] drm/i915: Introduce RING_FAULT_VADDR_MASK Ville Syrjala
@ 2025-02-11 23:19 ` Ville Syrjala
2025-02-24 10:08 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 07/12] drm/i915: Use REG_BIT() & co. for CHV EU/slice fuse bits Ville Syrjala
` (13 subsequent siblings)
19 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjala @ 2025-02-11 23:19 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
gen8_check_faults() and xehp_check_faults() are nearly identical.
Refactor the common bits into gen8_report_fault().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 73 ++++++++++++------------------
1 file changed, 29 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index b8189754edb7..3d3b1ba76e2b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -323,6 +323,27 @@ static void gen6_check_faults(struct intel_gt *gt)
}
}
+static void gen8_report_fault(struct intel_gt *gt, u32 fault,
+ u32 fault_data0, u32 fault_data1)
+{
+ u64 fault_addr;
+
+ fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
+ ((u64)fault_data0 << 12);
+
+ gt_dbg(gt, "Unexpected fault\n"
+ "\tAddr: 0x%08x_%08x\n"
+ "\tAddress space: %s\n"
+ "\tEngine ID: %d\n"
+ "\tSource ID: %d\n"
+ "\tType: %d\n",
+ upper_32_bits(fault_addr), lower_32_bits(fault_addr),
+ fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
+ REG_FIELD_GET(RING_FAULT_ENGINE_ID_MASK, fault),
+ REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault),
+ REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault));
+}
+
static void xehp_check_faults(struct intel_gt *gt)
{
u32 fault;
@@ -335,28 +356,10 @@ static void xehp_check_faults(struct intel_gt *gt)
* toward the primary instance.
*/
fault = intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);
- if (fault & RING_FAULT_VALID) {
- u32 fault_data0, fault_data1;
- u64 fault_addr;
-
- fault_data0 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA0);
- fault_data1 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA1);
-
- fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
- ((u64)fault_data0 << 12);
-
- gt_dbg(gt, "Unexpected fault\n"
- "\tAddr: 0x%08x_%08x\n"
- "\tAddress space: %s\n"
- "\tEngine ID: %d\n"
- "\tSource ID: %d\n"
- "\tType: %d\n",
- upper_32_bits(fault_addr), lower_32_bits(fault_addr),
- fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
- REG_FIELD_GET(RING_FAULT_ENGINE_ID_MASK, fault),
- REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault),
- REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault));
- }
+ if (fault & RING_FAULT_VALID)
+ gen8_report_fault(gt, fault,
+ intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA0),
+ intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA1));
}
static void gen8_check_faults(struct intel_gt *gt)
@@ -376,28 +379,10 @@ static void gen8_check_faults(struct intel_gt *gt)
}
fault = intel_uncore_read(uncore, fault_reg);
- if (fault & RING_FAULT_VALID) {
- u32 fault_data0, fault_data1;
- u64 fault_addr;
-
- fault_data0 = intel_uncore_read(uncore, fault_data0_reg);
- fault_data1 = intel_uncore_read(uncore, fault_data1_reg);
-
- fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
- ((u64)fault_data0 << 12);
-
- gt_dbg(gt, "Unexpected fault\n"
- "\tAddr: 0x%08x_%08x\n"
- "\tAddress space: %s\n"
- "\tEngine ID: %d\n"
- "\tSource ID: %d\n"
- "\tType: %d\n",
- upper_32_bits(fault_addr), lower_32_bits(fault_addr),
- fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
- REG_FIELD_GET(RING_FAULT_ENGINE_ID_MASK, fault),
- REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault),
- REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault));
- }
+ if (fault & RING_FAULT_VALID)
+ gen8_report_fault(gt, fault,
+ intel_uncore_read(uncore, fault_data0_reg),
+ intel_uncore_read(uncore, fault_data1_reg));
}
void intel_gt_check_and_clear_faults(struct intel_gt *gt)
--
2.45.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 07/12] drm/i915: Use REG_BIT() & co. for CHV EU/slice fuse bits
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
` (5 preceding siblings ...)
2025-02-11 23:19 ` [PATCH 06/12] drm/i915: Extract gen8_report_fault() Ville Syrjala
@ 2025-02-11 23:19 ` Ville Syrjala
2025-02-24 10:09 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 08/12] drm/i915: Reoder " Ville Syrjala
` (12 subsequent siblings)
19 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjala @ 2025-02-11 23:19 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Convert the CHV EU/slice fuse bits to the modern REG_BIT()/etc.
style.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 26 +++++++++++--------------
drivers/gpu/drm/i915/gt/intel_sseu.c | 12 ++++--------
2 files changed, 15 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index c58192e6f078..f5ac73a2ed7d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -934,12 +934,12 @@
#define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
#define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
#define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
-#define CHV_SS_PG_ENABLE (1 << 1)
-#define CHV_EU08_PG_ENABLE (1 << 9)
-#define CHV_EU19_PG_ENABLE (1 << 17)
-#define CHV_EU210_PG_ENABLE (1 << 25)
+#define CHV_SS_PG_ENABLE REG_BIT(1)
+#define CHV_EU08_PG_ENABLE REG_BIT(9)
+#define CHV_EU19_PG_ENABLE REG_BIT(17)
+#define CHV_EU210_PG_ENABLE REG_BIT(25)
#define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
-#define CHV_EU311_PG_ENABLE (1 << 1)
+#define CHV_EU311_PG_ENABLE REG_BIT(1)
#define GEN7_SARCHKMD _MMIO(0xb000)
#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
@@ -1437,16 +1437,12 @@
#define XEHP_CCS_MODE_CSLICE(cslice, ccs) (ccs << (cslice * XEHP_CCS_MODE_CSLICE_WIDTH))
#define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168)
-#define CHV_FGT_DISABLE_SS0 (1 << 10)
-#define CHV_FGT_DISABLE_SS1 (1 << 11)
-#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
-#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
-#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
-#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
-#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
-#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
-#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
-#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
+#define CHV_FGT_DISABLE_SS0 REG_BIT(10)
+#define CHV_FGT_DISABLE_SS1 REG_BIT(11)
+#define CHV_FGT_EU_DIS_SS0_R0_MASK REG_GENMASK(19, 16)
+#define CHV_FGT_EU_DIS_SS0_R1_MASK REG_GENMASK(23, 20)
+#define CHV_FGT_EU_DIS_SS1_R0_MASK REG_GENMASK(27, 24)
+#define CHV_FGT_EU_DIS_SS1_R1_MASK REG_GENMASK(31, 28)
#define BCS_SWCTRL _MMIO(0x22200)
#define BCS_SRC_Y REG_BIT(0)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index e4538dd726c8..8ae1208f9da5 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -335,10 +335,8 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
if (!(fuse & CHV_FGT_DISABLE_SS0)) {
u8 disabled_mask =
- ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >>
- CHV_FGT_EU_DIS_SS0_R0_SHIFT) |
- (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
- CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
+ REG_FIELD_GET(CHV_FGT_EU_DIS_SS0_R0_MASK, fuse) |
+ REG_FIELD_GET(CHV_FGT_EU_DIS_SS0_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS0_R0_MASK);
sseu->subslice_mask.hsw[0] |= BIT(0);
sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xFF);
@@ -346,10 +344,8 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
if (!(fuse & CHV_FGT_DISABLE_SS1)) {
u8 disabled_mask =
- ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >>
- CHV_FGT_EU_DIS_SS1_R0_SHIFT) |
- (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
- CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
+ REG_FIELD_GET(CHV_FGT_EU_DIS_SS1_R0_MASK, fuse) |
+ REG_FIELD_GET(CHV_FGT_EU_DIS_SS1_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS1_R0_MASK);
sseu->subslice_mask.hsw[0] |= BIT(1);
sseu_set_eus(sseu, 0, 1, ~disabled_mask & 0xFF);
--
2.45.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 08/12] drm/i915: Reoder CHV EU/slice fuse bits
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
` (6 preceding siblings ...)
2025-02-11 23:19 ` [PATCH 07/12] drm/i915: Use REG_BIT() & co. for CHV EU/slice fuse bits Ville Syrjala
@ 2025-02-11 23:19 ` Ville Syrjala
2025-02-24 10:13 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 09/12] drm/i915: Use REG_BIT() & co. for BDW+ " Ville Syrjala
` (11 subsequent siblings)
19 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjala @ 2025-02-11 23:19 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We customarily define the bits of a register in big endian
order. Reorder the CHV fuse bits to match.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index f5ac73a2ed7d..3d3cdcc881d0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -934,10 +934,10 @@
#define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
#define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
#define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
-#define CHV_SS_PG_ENABLE REG_BIT(1)
-#define CHV_EU08_PG_ENABLE REG_BIT(9)
-#define CHV_EU19_PG_ENABLE REG_BIT(17)
#define CHV_EU210_PG_ENABLE REG_BIT(25)
+#define CHV_EU19_PG_ENABLE REG_BIT(17)
+#define CHV_EU08_PG_ENABLE REG_BIT(9)
+#define CHV_SS_PG_ENABLE REG_BIT(1)
#define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
#define CHV_EU311_PG_ENABLE REG_BIT(1)
@@ -1437,12 +1437,12 @@
#define XEHP_CCS_MODE_CSLICE(cslice, ccs) (ccs << (cslice * XEHP_CCS_MODE_CSLICE_WIDTH))
#define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168)
-#define CHV_FGT_DISABLE_SS0 REG_BIT(10)
-#define CHV_FGT_DISABLE_SS1 REG_BIT(11)
-#define CHV_FGT_EU_DIS_SS0_R0_MASK REG_GENMASK(19, 16)
-#define CHV_FGT_EU_DIS_SS0_R1_MASK REG_GENMASK(23, 20)
-#define CHV_FGT_EU_DIS_SS1_R0_MASK REG_GENMASK(27, 24)
#define CHV_FGT_EU_DIS_SS1_R1_MASK REG_GENMASK(31, 28)
+#define CHV_FGT_EU_DIS_SS1_R0_MASK REG_GENMASK(27, 24)
+#define CHV_FGT_EU_DIS_SS0_R1_MASK REG_GENMASK(23, 20)
+#define CHV_FGT_EU_DIS_SS0_R0_MASK REG_GENMASK(19, 16)
+#define CHV_FGT_DISABLE_SS1 REG_BIT(11)
+#define CHV_FGT_DISABLE_SS0 REG_BIT(10)
#define BCS_SWCTRL _MMIO(0x22200)
#define BCS_SRC_Y REG_BIT(0)
--
2.45.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 09/12] drm/i915: Use REG_BIT() & co. for BDW+ EU/slice fuse bits
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
` (7 preceding siblings ...)
2025-02-11 23:19 ` [PATCH 08/12] drm/i915: Reoder " Ville Syrjala
@ 2025-02-11 23:19 ` Ville Syrjala
2025-02-24 10:17 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 10/12] drm/i915: Reoder " Ville Syrjala
` (10 subsequent siblings)
19 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjala @ 2025-02-11 23:19 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Convert the BDW+ EU/slice fuse bits to the modern REG_BIT()/etc.
style.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 5 +-
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 5 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 62 ++++++++++-------------
drivers/gpu/drm/i915/gt/intel_sseu.c | 44 ++++++++--------
4 files changed, 53 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index ec136eb12d48..751e1203cf27 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -769,9 +769,8 @@ static void engine_mask_apply_media_fuses(struct intel_gt *gt)
if (MEDIA_VER_FULL(i915) < IP_VER(12, 55))
media_fuse = ~media_fuse;
- vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
- vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
- GEN11_GT_VEBOX_DISABLE_SHIFT;
+ vdbox_mask = REG_FIELD_GET(GEN11_GT_VDBOX_DISABLE_MASK, media_fuse);
+ vebox_mask = REG_FIELD_GET(GEN11_GT_VEBOX_DISABLE_MASK, media_fuse);
if (MEDIA_VER_FULL(i915) >= IP_VER(12, 55)) {
fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index aab20d6466f5..a60822e2b5d4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -121,9 +121,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
gt->info.mslice_mask =
intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
GEN_DSS_PER_MSLICE);
- gt->info.mslice_mask |=
- (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
- GEN12_MEML3_EN_MASK);
+ gt->info.mslice_mask |= REG_FIELD_GET(GEN12_MEML3_EN_MASK,
+ intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3));
if (!gt->info.mslice_mask) /* should be impossible! */
gt_warn(gt, "mslice mask all zero!\n");
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 3d3cdcc881d0..7a5fe084475f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -514,9 +514,9 @@
#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
((slice) % 3) * 0x4)
-#define GEN9_PGCTL_SLICE_ACK (1 << 0)
-#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2))
-#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
+#define GEN9_PGCTL_SLICE_ACK REG_BIT(0)
+#define GEN9_PGCTL_SS_ACK(subslice) REG_BIT(2 + (subslice) * 2)
+#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? REG_GENMASK(6, 0) : REG_GENMASK(4, 0))
#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)
#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
@@ -524,14 +524,14 @@
#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)
#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
((slice) % 3) * 0x8)
-#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
-#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
-#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
-#define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
-#define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
-#define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
-#define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
-#define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
+#define GEN9_PGCTL_SSA_EU08_ACK REG_BIT(0)
+#define GEN9_PGCTL_SSA_EU19_ACK REG_BIT(2)
+#define GEN9_PGCTL_SSA_EU210_ACK REG_BIT(4)
+#define GEN9_PGCTL_SSA_EU311_ACK REG_BIT(6)
+#define GEN9_PGCTL_SSB_EU08_ACK REG_BIT(8)
+#define GEN9_PGCTL_SSB_EU19_ACK REG_BIT(10)
+#define GEN9_PGCTL_SSB_EU210_ACK REG_BIT(12)
+#define GEN9_PGCTL_SSB_EU311_ACK REG_BIT(14)
#define VF_PREEMPTION _MMIO(0x83a4)
#define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
@@ -588,7 +588,7 @@
#define GEN10_L3BANK_MASK 0x0F
/* on Xe_HP the same fuses indicates mslices instead of L3 banks */
#define GEN12_MAX_MSLICES 4
-#define GEN12_MEML3_EN_MASK 0x0F
+#define GEN12_MEML3_EN_MASK REG_GENMASK(3, 0)
#define HSW_PAVP_FUSE1 _MMIO(0x911c)
#define XEHP_SFC_ENABLE_MASK REG_GENMASK(27, 24)
@@ -598,37 +598,30 @@
#define HSW_F1_EU_DIS_6EUS 2
#define GEN8_FUSE2 _MMIO(0x9120)
-#define GEN8_F2_SS_DIS_SHIFT 21
-#define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
-#define GEN8_F2_S_ENA_SHIFT 25
-#define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
-#define GEN9_F2_SS_DIS_SHIFT 20
-#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
-#define GEN10_F2_S_ENA_SHIFT 22
-#define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT)
-#define GEN10_F2_SS_DIS_SHIFT 18
-#define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
+#define GEN8_F2_SS_DIS_MASK REG_GENMASK(23, 21)
+#define GEN8_F2_S_ENA_MASK REG_GENMASK(27, 25)
+#define GEN9_F2_SS_DIS_MASK REG_GENMASK(23, 20)
+#define GEN10_F2_S_ENA_MASK REG_GENMASK(27, 22)
+#define GEN10_F2_SS_DIS_MASK REG_GENMASK(21, 18)
#define GEN8_EU_DISABLE0 _MMIO(0x9134)
#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4)
#define GEN11_EU_DISABLE _MMIO(0x9134)
-#define GEN8_EU_DIS0_S0_MASK 0xffffff
-#define GEN8_EU_DIS0_S1_SHIFT 24
-#define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
-#define GEN11_EU_DIS_MASK 0xFF
+#define GEN8_EU_DIS0_S0_MASK REG_GENMASK(23, 0)
+#define GEN8_EU_DIS0_S1_MASK REG_GENMASK(31, 24)
+#define GEN11_EU_DIS_MASK REG_GENMASK(7, 0)
#define XEHP_EU_ENABLE _MMIO(0x9134)
-#define XEHP_EU_ENA_MASK 0xFF
+#define XEHP_EU_ENA_MASK REG_GENMASK(7, 0)
#define GEN8_EU_DISABLE1 _MMIO(0x9138)
-#define GEN8_EU_DIS1_S1_MASK 0xffff
-#define GEN8_EU_DIS1_S2_SHIFT 16
-#define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
+#define GEN8_EU_DIS1_S1_MASK REG_GENMASK(15, 0)
+#define GEN8_EU_DIS1_S2_MASK REG_GENMASK(31, 16)
#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
-#define GEN11_GT_S_ENA_MASK 0xFF
+#define GEN11_GT_S_ENA_MASK REG_GENMASK(7, 0)
#define GEN8_EU_DISABLE2 _MMIO(0x913c)
-#define GEN8_EU_DIS2_S2_MASK 0xff
+#define GEN8_EU_DIS2_S2_MASK REG_GENMASK(7, 0)
#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913c)
#define GEN12_GT_GEOMETRY_DSS_ENABLE _MMIO(0x913c)
@@ -636,9 +629,8 @@
#define GEN10_EU_DISABLE3 _MMIO(0x9140)
#define GEN10_EU_DIS_SS_MASK 0xff
#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
-#define GEN11_GT_VDBOX_DISABLE_MASK 0xff
-#define GEN11_GT_VEBOX_DISABLE_SHIFT 16
-#define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
+#define GEN11_GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0)
+#define GEN11_GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16)
#define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144)
#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 8ae1208f9da5..9501d323d0d3 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -236,7 +236,8 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
GEN12_GT_COMPUTE_DSS_ENABLE,
XEHPC_GT_COMPUTE_DSS_ENABLE_EXT);
- eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
+ eu_en_fuse = REG_FIELD_GET(XEHP_EU_ENA_MASK,
+ intel_uncore_read(uncore, XEHP_EU_ENABLE));
if (HAS_ONE_EU_PER_FUSE_BIT(gt->i915))
eu_en = eu_en_fuse;
@@ -269,15 +270,15 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
* Although gen12 architecture supported multiple slices, TGL, RKL,
* DG1, and ADL only had a single slice.
*/
- s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
- GEN11_GT_S_ENA_MASK;
+ s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK,
+ intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE));
drm_WARN_ON(>->i915->drm, s_en != 0x1);
g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
/* one bit per pair of EUs */
- eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
- GEN11_EU_DIS_MASK);
+ eu_en_fuse = ~REG_FIELD_GET(GEN11_EU_DIS_MASK,
+ intel_uncore_read(uncore, GEN11_EU_DISABLE));
for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
if (eu_en_fuse & BIT(eu))
@@ -306,14 +307,14 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
* Although gen11 architecture supported multiple slices, ICL and
* EHL/JSL only had a single slice in practice.
*/
- s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
- GEN11_GT_S_ENA_MASK;
+ s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK,
+ intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE));
drm_WARN_ON(>->i915->drm, s_en != 0x1);
ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE);
- eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
- GEN11_EU_DIS_MASK);
+ eu_en = ~REG_FIELD_GET(GEN11_EU_DIS_MASK,
+ intel_uncore_read(uncore, GEN11_EU_DISABLE));
gen11_compute_sseu_info(sseu, ss_en, eu_en);
@@ -381,7 +382,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
int s, ss;
fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
- sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
+ sseu->slice_mask = REG_FIELD_GET(GEN8_F2_S_ENA_MASK, fuse2);
/* BXT has a single slice and at most 3 subslices. */
intel_sseu_set_info(sseu, IS_GEN9_LP(i915) ? 1 : 3,
@@ -392,8 +393,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
* to each of the enabled slices.
*/
subslice_mask = (1 << sseu->max_subslices) - 1;
- subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
- GEN9_F2_SS_DIS_SHIFT);
+ subslice_mask &= ~REG_FIELD_GET(GEN9_F2_SS_DIS_MASK, fuse2);
/*
* Iterate through enabled slices and subslices to
@@ -486,7 +486,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
u32 eu_disable0, eu_disable1, eu_disable2;
fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
- sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
+ sseu->slice_mask = REG_FIELD_GET(GEN8_F2_S_ENA_MASK, fuse2);
intel_sseu_set_info(sseu, 3, 3, 8);
/*
@@ -494,18 +494,18 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
* to each of the enabled slices.
*/
subslice_mask = GENMASK(sseu->max_subslices - 1, 0);
- subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
- GEN8_F2_SS_DIS_SHIFT);
+ subslice_mask &= ~REG_FIELD_GET(GEN8_F2_SS_DIS_MASK, fuse2);
eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0);
eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1);
eu_disable2 = intel_uncore_read(uncore, GEN8_EU_DISABLE2);
- eu_disable[0] = eu_disable0 & GEN8_EU_DIS0_S0_MASK;
- eu_disable[1] = (eu_disable0 >> GEN8_EU_DIS0_S1_SHIFT) |
- ((eu_disable1 & GEN8_EU_DIS1_S1_MASK) <<
- (32 - GEN8_EU_DIS0_S1_SHIFT));
- eu_disable[2] = (eu_disable1 >> GEN8_EU_DIS1_S2_SHIFT) |
- ((eu_disable2 & GEN8_EU_DIS2_S2_MASK) <<
- (32 - GEN8_EU_DIS1_S2_SHIFT));
+ eu_disable[0] =
+ REG_FIELD_GET(GEN8_EU_DIS0_S0_MASK, eu_disable0);
+ eu_disable[1] =
+ REG_FIELD_GET(GEN8_EU_DIS0_S1_MASK, eu_disable0) |
+ REG_FIELD_GET(GEN8_EU_DIS1_S1_MASK, eu_disable1) << hweight32(GEN8_EU_DIS0_S1_MASK);
+ eu_disable[2] =
+ REG_FIELD_GET(GEN8_EU_DIS1_S2_MASK, eu_disable1) |
+ REG_FIELD_GET(GEN8_EU_DIS2_S2_MASK, eu_disable2) << hweight32(GEN8_EU_DIS1_S2_MASK);
/*
* Iterate through enabled slices and subslices to
--
2.45.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH 09/12] drm/i915: Use REG_BIT() & co. for BDW+ EU/slice fuse bits
2025-02-11 23:19 ` [PATCH 09/12] drm/i915: Use REG_BIT() & co. for BDW+ " Ville Syrjala
@ 2025-02-24 10:17 ` Andi Shyti
2025-02-25 7:52 ` Jani Nikula
0 siblings, 1 reply; 36+ messages in thread
From: Andi Shyti @ 2025-02-24 10:17 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
Hi Ville,
On Wed, Feb 12, 2025 at 01:19:37AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Convert the BDW+ EU/slice fuse bits to the modern REG_BIT()/etc.
> style.
using REG_BIT() and co. doesn't alway make it more readable. In
some of the cases below I would have preferred not to use it.
But on the other hand we keep consistency and bit operations are
not supposed to be easy-readable, anyway.
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Thanks,
Andi
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 09/12] drm/i915: Use REG_BIT() & co. for BDW+ EU/slice fuse bits
2025-02-24 10:17 ` Andi Shyti
@ 2025-02-25 7:52 ` Jani Nikula
2025-02-25 14:54 ` Andi Shyti
0 siblings, 1 reply; 36+ messages in thread
From: Jani Nikula @ 2025-02-25 7:52 UTC (permalink / raw)
To: Andi Shyti, Ville Syrjala; +Cc: intel-gfx
On Mon, 24 Feb 2025, Andi Shyti <andi.shyti@linux.intel.com> wrote:
> Hi Ville,
>
> On Wed, Feb 12, 2025 at 01:19:37AM +0200, Ville Syrjala wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Convert the BDW+ EU/slice fuse bits to the modern REG_BIT()/etc.
>> style.
>
> using REG_BIT() and co. doesn't alway make it more readable. In
> some of the cases below I would have preferred not to use it.
Interesting. I read through the patch and I thought all of it was
good. Care to elaborate?
BR,
Jani.
>
> But on the other hand we keep consistency and bit operations are
> not supposed to be easy-readable, anyway.
>
> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
>
> Thanks,
> Andi
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 09/12] drm/i915: Use REG_BIT() & co. for BDW+ EU/slice fuse bits
2025-02-25 7:52 ` Jani Nikula
@ 2025-02-25 14:54 ` Andi Shyti
2025-02-25 16:11 ` Jani Nikula
0 siblings, 1 reply; 36+ messages in thread
From: Andi Shyti @ 2025-02-25 14:54 UTC (permalink / raw)
To: Jani Nikula; +Cc: Andi Shyti, Ville Syrjala, intel-gfx
Hi Jani,
On Tue, Feb 25, 2025 at 09:52:41AM +0200, Jani Nikula wrote:
> On Mon, 24 Feb 2025, Andi Shyti <andi.shyti@linux.intel.com> wrote:
> > Hi Ville,
> >
> > On Wed, Feb 12, 2025 at 01:19:37AM +0200, Ville Syrjala wrote:
> >> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>
> >> Convert the BDW+ EU/slice fuse bits to the modern REG_BIT()/etc.
> >> style.
> >
> > using REG_BIT() and co. doesn't alway make it more readable. In
> > some of the cases below I would have preferred not to use it.
>
> Interesting. I read through the patch and I thought all of it was
> good. Care to elaborate?
yes you're right, I should have given an example, but I had
already edited the e-mail and I was lazy to get it back.
In any case, this is an example:
- s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
- GEN11_GT_S_ENA_MASK;
+ s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK,
+ intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE));
The removed line to me is clearer than the added line.
I'm not saying that it's not good (otherwise I wouldn't have
r-b'ed it), I'm just saying that not always using the REG_*
macros makes the code clearer.
For consistency with the rest of the patch is anyway fine.
Thanks,
Andi
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 09/12] drm/i915: Use REG_BIT() & co. for BDW+ EU/slice fuse bits
2025-02-25 14:54 ` Andi Shyti
@ 2025-02-25 16:11 ` Jani Nikula
0 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2025-02-25 16:11 UTC (permalink / raw)
To: Andi Shyti; +Cc: Andi Shyti, Ville Syrjala, intel-gfx
On Tue, 25 Feb 2025, Andi Shyti <andi.shyti@kernel.org> wrote:
> Hi Jani,
>
> On Tue, Feb 25, 2025 at 09:52:41AM +0200, Jani Nikula wrote:
>> On Mon, 24 Feb 2025, Andi Shyti <andi.shyti@linux.intel.com> wrote:
>> > Hi Ville,
>> >
>> > On Wed, Feb 12, 2025 at 01:19:37AM +0200, Ville Syrjala wrote:
>> >> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >>
>> >> Convert the BDW+ EU/slice fuse bits to the modern REG_BIT()/etc.
>> >> style.
>> >
>> > using REG_BIT() and co. doesn't alway make it more readable. In
>> > some of the cases below I would have preferred not to use it.
>>
>> Interesting. I read through the patch and I thought all of it was
>> good. Care to elaborate?
>
> yes you're right, I should have given an example, but I had
> already edited the e-mail and I was lazy to get it back.
>
> In any case, this is an example:
>
> - s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
> - GEN11_GT_S_ENA_MASK;
> + s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK,
> + intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE));
>
>
> The removed line to me is clearer than the added line.
I suppose clarity could be improved with:
val = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE);
s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK, val);
but in general I think REG_FIELD_GET() is better than just val & mask,
because the former handles shifting.
(For the record I'm not suggesting separating the read in this patch.)
> I'm not saying that it's not good (otherwise I wouldn't have
> r-b'ed it), I'm just saying that not always using the REG_*
> macros makes the code clearer.
>
> For consistency with the rest of the patch is anyway fine.
Agreed.
BR,
Jani.
>
> Thanks,
> Andi
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 10/12] drm/i915: Reoder BDW+ EU/slice fuse bits
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
` (8 preceding siblings ...)
2025-02-11 23:19 ` [PATCH 09/12] drm/i915: Use REG_BIT() & co. for BDW+ " Ville Syrjala
@ 2025-02-11 23:19 ` Ville Syrjala
2025-02-24 10:18 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 11/12] drm/i915: Use REG_BIT() & co. for gen9+ timestamp freq registers Ville Syrjala
` (9 subsequent siblings)
19 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjala @ 2025-02-11 23:19 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We customarily define the bits of a register in big endian
order. Reorder the BDW+ fuse bits to match.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 31 +++++++++++++------------
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 7a5fe084475f..f5e6853b3a6c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -512,10 +512,11 @@
#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
+#define GEN9_PGCTL_SS_ACK(subslice) REG_BIT(2 + (subslice) * 2)
+#define GEN9_PGCTL_SLICE_ACK REG_BIT(0)
+
#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
((slice) % 3) * 0x4)
-#define GEN9_PGCTL_SLICE_ACK REG_BIT(0)
-#define GEN9_PGCTL_SS_ACK(subslice) REG_BIT(2 + (subslice) * 2)
#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? REG_GENMASK(6, 0) : REG_GENMASK(4, 0))
#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)
@@ -524,14 +525,14 @@
#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)
#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
((slice) % 3) * 0x8)
-#define GEN9_PGCTL_SSA_EU08_ACK REG_BIT(0)
-#define GEN9_PGCTL_SSA_EU19_ACK REG_BIT(2)
-#define GEN9_PGCTL_SSA_EU210_ACK REG_BIT(4)
-#define GEN9_PGCTL_SSA_EU311_ACK REG_BIT(6)
-#define GEN9_PGCTL_SSB_EU08_ACK REG_BIT(8)
-#define GEN9_PGCTL_SSB_EU19_ACK REG_BIT(10)
-#define GEN9_PGCTL_SSB_EU210_ACK REG_BIT(12)
#define GEN9_PGCTL_SSB_EU311_ACK REG_BIT(14)
+#define GEN9_PGCTL_SSB_EU210_ACK REG_BIT(12)
+#define GEN9_PGCTL_SSB_EU19_ACK REG_BIT(10)
+#define GEN9_PGCTL_SSB_EU08_ACK REG_BIT(8)
+#define GEN9_PGCTL_SSA_EU311_ACK REG_BIT(6)
+#define GEN9_PGCTL_SSA_EU210_ACK REG_BIT(4)
+#define GEN9_PGCTL_SSA_EU19_ACK REG_BIT(2)
+#define GEN9_PGCTL_SSA_EU08_ACK REG_BIT(0)
#define VF_PREEMPTION _MMIO(0x83a4)
#define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
@@ -598,24 +599,24 @@
#define HSW_F1_EU_DIS_6EUS 2
#define GEN8_FUSE2 _MMIO(0x9120)
-#define GEN8_F2_SS_DIS_MASK REG_GENMASK(23, 21)
-#define GEN8_F2_S_ENA_MASK REG_GENMASK(27, 25)
-#define GEN9_F2_SS_DIS_MASK REG_GENMASK(23, 20)
#define GEN10_F2_S_ENA_MASK REG_GENMASK(27, 22)
#define GEN10_F2_SS_DIS_MASK REG_GENMASK(21, 18)
+#define GEN8_F2_S_ENA_MASK REG_GENMASK(27, 25)
+#define GEN9_F2_SS_DIS_MASK REG_GENMASK(23, 20)
+#define GEN8_F2_SS_DIS_MASK REG_GENMASK(23, 21)
#define GEN8_EU_DISABLE0 _MMIO(0x9134)
#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4)
#define GEN11_EU_DISABLE _MMIO(0x9134)
-#define GEN8_EU_DIS0_S0_MASK REG_GENMASK(23, 0)
#define GEN8_EU_DIS0_S1_MASK REG_GENMASK(31, 24)
+#define GEN8_EU_DIS0_S0_MASK REG_GENMASK(23, 0)
#define GEN11_EU_DIS_MASK REG_GENMASK(7, 0)
#define XEHP_EU_ENABLE _MMIO(0x9134)
#define XEHP_EU_ENA_MASK REG_GENMASK(7, 0)
#define GEN8_EU_DISABLE1 _MMIO(0x9138)
-#define GEN8_EU_DIS1_S1_MASK REG_GENMASK(15, 0)
#define GEN8_EU_DIS1_S2_MASK REG_GENMASK(31, 16)
+#define GEN8_EU_DIS1_S1_MASK REG_GENMASK(15, 0)
#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
#define GEN11_GT_S_ENA_MASK REG_GENMASK(7, 0)
@@ -629,8 +630,8 @@
#define GEN10_EU_DISABLE3 _MMIO(0x9140)
#define GEN10_EU_DIS_SS_MASK 0xff
#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
-#define GEN11_GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0)
#define GEN11_GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16)
+#define GEN11_GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0)
#define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144)
#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148)
--
2.45.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 11/12] drm/i915: Use REG_BIT() & co. for gen9+ timestamp freq registers
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
` (9 preceding siblings ...)
2025-02-11 23:19 ` [PATCH 10/12] drm/i915: Reoder " Ville Syrjala
@ 2025-02-11 23:19 ` Ville Syrjala
2025-02-24 10:20 ` Andi Shyti
2025-02-11 23:19 ` [PATCH 12/12] drm/i915: Reoder gen9+ timestamp freq register bits Ville Syrjala
` (8 subsequent siblings)
19 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjala @ 2025-02-11 23:19 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Convert the gen9+ timestamo frequency related registers to
the modern REG_BIT()/etc. style.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../gpu/drm/i915/gt/intel_gt_clock_utils.c | 10 ++-----
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 30 ++++++++-----------
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 7 ++---
3 files changed, 18 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index 6e63505fe478..6c499692d61e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -35,9 +35,7 @@ static u32 gen11_get_crystal_clock_freq(struct intel_uncore *uncore,
u32 f24_mhz = 24000000;
u32 f25_mhz = 25000000;
u32 f38_4_mhz = 38400000;
- u32 crystal_clock =
- (rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
- GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
+ u32 crystal_clock = rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK;
switch (crystal_clock) {
case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
@@ -80,8 +78,7 @@ static u32 gen11_read_clock_frequency(struct intel_uncore *uncore)
* register increments from this frequency (it might
* increment only every few clock cycle).
*/
- freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
- GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
+ freq >>= 3 - REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0);
}
return freq;
@@ -102,8 +99,7 @@ static u32 gen9_read_clock_frequency(struct intel_uncore *uncore)
* register increments from this frequency (it might
* increment only every few clock cycle).
*/
- freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
- CTC_SHIFT_PARAMETER_SHIFT);
+ freq >>= 3 - REG_FIELD_GET(CTC_SHIFT_PARAMETER_MASK, ctc_reg);
}
return freq;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index f5e6853b3a6c..440ace1a0170 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -30,18 +30,15 @@
/* RPM unit config (Gen8+) */
#define RPM_CONFIG0 _MMIO(0xd00)
-#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
-#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
-#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0
-#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1
-#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
-#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
-#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
-#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
-#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2
-#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
-#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
-#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_BIT(3)
+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3)
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 2)
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 3)
+#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
#define RPM_CONFIG1 _MMIO(0xd04)
#define GEN10_GT_NOA_ENABLE (1 << 9)
@@ -879,11 +876,10 @@
/* GPM unit config (Gen9+) */
#define CTC_MODE _MMIO(0xa26c)
-#define CTC_SOURCE_PARAMETER_MASK 1
-#define CTC_SOURCE_CRYSTAL_CLOCK 0
-#define CTC_SOURCE_DIVIDE_LOGIC 1
-#define CTC_SHIFT_PARAMETER_SHIFT 1
-#define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
+#define CTC_SOURCE_PARAMETER_MASK REG_BIT(0)
+#define CTC_SOURCE_CRYSTAL_CLOCK REG_FIELD_PREP(CTC_SOURCE_PARAMETER_MASK, 0)
+#define CTC_SOURCE_DIVIDE_LOGIC REG_FIELD_PREP(CTC_SOURCE_PARAMETER_MASK, 1)
+#define CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
/* GPM MSG_IDLE */
#define MSG_IDLE_CS _MMIO(0x8000)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 90da23d09250..33227eccb67e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1285,15 +1285,12 @@ static void guc_update_engine_gt_clks(struct intel_engine_cs *engine)
static u32 gpm_timestamp_shift(struct intel_gt *gt)
{
intel_wakeref_t wakeref;
- u32 reg, shift;
+ u32 reg;
with_intel_runtime_pm(gt->uncore->rpm, wakeref)
reg = intel_uncore_read(gt->uncore, RPM_CONFIG0);
- shift = (reg & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
- GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT;
-
- return 3 - shift;
+ return 3 - REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
}
static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now)
--
2.45.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 12/12] drm/i915: Reoder gen9+ timestamp freq register bits
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
` (10 preceding siblings ...)
2025-02-11 23:19 ` [PATCH 11/12] drm/i915: Use REG_BIT() & co. for gen9+ timestamp freq registers Ville Syrjala
@ 2025-02-11 23:19 ` Ville Syrjala
2025-02-24 10:20 ` Andi Shyti
2025-02-12 0:04 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: some GT register fixes and cleanups Patchwork
` (7 subsequent siblings)
19 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjala @ 2025-02-11 23:19 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We customarily define the bits of a register in big endian
order. Reorder the gen9+ timestamp freq register bits to match.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 440ace1a0170..bcd8a09ed279 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -30,14 +30,14 @@
/* RPM unit config (Gen8+) */
#define RPM_CONFIG0 _MMIO(0xd00)
-#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_BIT(3)
-#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
-#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3)
#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 2)
#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 3)
+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_BIT(3)
+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
#define RPM_CONFIG1 _MMIO(0xd04)
@@ -876,10 +876,10 @@
/* GPM unit config (Gen9+) */
#define CTC_MODE _MMIO(0xa26c)
+#define CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
#define CTC_SOURCE_PARAMETER_MASK REG_BIT(0)
#define CTC_SOURCE_CRYSTAL_CLOCK REG_FIELD_PREP(CTC_SOURCE_PARAMETER_MASK, 0)
#define CTC_SOURCE_DIVIDE_LOGIC REG_FIELD_PREP(CTC_SOURCE_PARAMETER_MASK, 1)
-#define CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
/* GPM MSG_IDLE */
#define MSG_IDLE_CS _MMIO(0x8000)
--
2.45.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: some GT register fixes and cleanups
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
` (11 preceding siblings ...)
2025-02-11 23:19 ` [PATCH 12/12] drm/i915: Reoder gen9+ timestamp freq register bits Ville Syrjala
@ 2025-02-12 0:04 ` Patchwork
2025-02-12 1:08 ` ✗ i915.CI.BAT: failure " Patchwork
` (6 subsequent siblings)
19 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2025-02-12 0:04 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: some GT register fixes and cleanups
URL : https://patchwork.freedesktop.org/series/144683/
State : warning
== Summary ==
Error: dim checkpatch failed
db3d83fcc51c drm/i915: Bump RING_FAULT engine ID bits
638d9ba28764 drm/i915: Relocate RING_FAULT bits
20b5bbfc36c8 drm/i915: Use REG_BIT() & co. for ring fault registers
3f2886301c3f drm/i915: Document which RING_FAULT bits apply to which platforms
0a0b18802705 drm/i915: Introduce RING_FAULT_VADDR_MASK
8fc521817a8d drm/i915: Extract gen8_report_fault()
4def0c3d64cd drm/i915: Use REG_BIT() & co. for CHV EU/slice fuse bits
-:72: WARNING:LONG_LINE: line length of 113 exceeds 100 columns
#72: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:339:
+ REG_FIELD_GET(CHV_FGT_EU_DIS_SS0_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS0_R0_MASK);
-:85: WARNING:LONG_LINE: line length of 113 exceeds 100 columns
#85: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:348:
+ REG_FIELD_GET(CHV_FGT_EU_DIS_SS1_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS1_R0_MASK);
total: 0 errors, 2 warnings, 0 checks, 63 lines checked
b7f98d3da435 drm/i915: Reoder CHV EU/slice fuse bits
b8ad41efea8d drm/i915: Use REG_BIT() & co. for BDW+ EU/slice fuse bits
-:42: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#42: FILE: drivers/gpu/drm/i915/gt/intel_gt_mcr.c:125:
+ intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3));
-:59: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#59: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:519:
+#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? REG_GENMASK(6, 0) : REG_GENMASK(4, 0))
total: 0 errors, 2 warnings, 0 checks, 223 lines checked
de513234c0a7 drm/i915: Reoder BDW+ EU/slice fuse bits
4f61d80fda59 drm/i915: Use REG_BIT() & co. for gen9+ timestamp freq registers
-:71: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#71: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:34:
+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
-:72: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#72: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:35:
+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
-:74: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#74: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:37:
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
-:75: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#75: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:38:
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
-:76: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#76: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:39:
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 2)
-:77: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#77: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:40:
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 3)
total: 0 errors, 6 warnings, 0 checks, 87 lines checked
8d385d70f322 drm/i915: Reoder gen9+ timestamp freq register bits
-:31: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#31: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:39:
+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
-:32: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#32: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:40:
+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
total: 0 errors, 2 warnings, 0 checks, 28 lines checked
^ permalink raw reply [flat|nested] 36+ messages in thread* ✗ i915.CI.BAT: failure for drm/i915: some GT register fixes and cleanups
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
` (12 preceding siblings ...)
2025-02-12 0:04 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: some GT register fixes and cleanups Patchwork
@ 2025-02-12 1:08 ` Patchwork
2025-02-12 4:06 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: some GT register fixes and cleanups (rev2) Patchwork
` (5 subsequent siblings)
19 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2025-02-12 1:08 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6201 bytes --]
== Series Details ==
Series: drm/i915: some GT register fixes and cleanups
URL : https://patchwork.freedesktop.org/series/144683/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16111 -> Patchwork_144683v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_144683v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_144683v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v1/index.html
Participating hosts (44 -> 43)
------------------------------
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_144683v1:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_fence@basic-await@vecs0:
- bat-twl-1: [PASS][1] -> [FAIL][2] +1 other test fail
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16111/bat-twl-1/igt@gem_exec_fence@basic-await@vecs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v1/bat-twl-1/igt@gem_exec_fence@basic-await@vecs0.html
Known issues
------------
Here are the changes found in Patchwork_144683v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_auth@basic-auth:
- fi-bsw-nick: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16111/fi-bsw-nick/igt@core_auth@basic-auth.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v1/fi-bsw-nick/igt@core_auth@basic-auth.html
* igt@i915_selftest@live:
- bat-arlh-3: [PASS][5] -> [DMESG-FAIL][6] ([i915#12061] / [i915#12435])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16111/bat-arlh-3/igt@i915_selftest@live.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v1/bat-arlh-3/igt@i915_selftest@live.html
- bat-adlp-9: [PASS][7] -> [ABORT][8] ([i915#12435])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16111/bat-adlp-9/igt@i915_selftest@live.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v1/bat-adlp-9/igt@i915_selftest@live.html
* igt@i915_selftest@live@reset:
- bat-adlp-9: [PASS][9] -> [ABORT][10] ([i915#13399])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16111/bat-adlp-9/igt@i915_selftest@live@reset.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v1/bat-adlp-9/igt@i915_selftest@live@reset.html
* igt@i915_selftest@live@workarounds:
- bat-arlh-3: [PASS][11] -> [DMESG-FAIL][12] ([i915#12061])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16111/bat-arlh-3/igt@i915_selftest@live@workarounds.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v1/bat-arlh-3/igt@i915_selftest@live@workarounds.html
- bat-arls-5: [PASS][13] -> [DMESG-FAIL][14] ([i915#12061]) +1 other test dmesg-fail
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16111/bat-arls-5/igt@i915_selftest@live@workarounds.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v1/bat-arls-5/igt@i915_selftest@live@workarounds.html
- bat-mtlp-9: [PASS][15] -> [DMESG-FAIL][16] ([i915#12061])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16111/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v1/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
- bat-arls-6: [PASS][17] -> [DMESG-FAIL][18] ([i915#12061]) +1 other test dmesg-fail
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16111/bat-arls-6/igt@i915_selftest@live@workarounds.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v1/bat-arls-6/igt@i915_selftest@live@workarounds.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: [PASS][19] -> [SKIP][20] ([i915#9197]) +3 other tests skip
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16111/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v1/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
#### Possible fixes ####
* igt@dmabuf@all-tests:
- bat-apl-1: [INCOMPLETE][21] ([i915#12904]) -> [PASS][22] +1 other test pass
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16111/bat-apl-1/igt@dmabuf@all-tests.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v1/bat-apl-1/igt@dmabuf@all-tests.html
* igt@i915_selftest@live@workarounds:
- bat-adlp-6: [INCOMPLETE][23] ([i915#9413]) -> [PASS][24] +1 other test pass
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16111/bat-adlp-6/igt@i915_selftest@live@workarounds.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v1/bat-adlp-6/igt@i915_selftest@live@workarounds.html
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12435
[i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
[i915#13399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13399
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197
[i915#9413]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9413
Build changes
-------------
* Linux: CI_DRM_16111 -> Patchwork_144683v1
CI-20190529: 20190529
CI_DRM_16111: 76120b67a3d5e7a38cbc92fc39846297130fc6d0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8228: 8228
Patchwork_144683v1: 76120b67a3d5e7a38cbc92fc39846297130fc6d0 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v1/index.html
[-- Attachment #2: Type: text/html, Size: 7385 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: some GT register fixes and cleanups (rev2)
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
` (13 preceding siblings ...)
2025-02-12 1:08 ` ✗ i915.CI.BAT: failure " Patchwork
@ 2025-02-12 4:06 ` Patchwork
2025-02-12 4:35 ` ✗ i915.CI.BAT: failure " Patchwork
` (4 subsequent siblings)
19 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2025-02-12 4:06 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: some GT register fixes and cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/144683/
State : warning
== Summary ==
Error: dim checkpatch failed
812e24145d45 drm/i915: Bump RING_FAULT engine ID bits
f161c8a9b29c drm/i915: Relocate RING_FAULT bits
8d99ea77f7f1 drm/i915: Use REG_BIT() & co. for ring fault registers
4eb45b384617 drm/i915: Document which RING_FAULT bits apply to which platforms
07b144792152 drm/i915: Introduce RING_FAULT_VADDR_MASK
e3994fe05506 drm/i915: Extract gen8_report_fault()
62ce28e443c4 drm/i915: Use REG_BIT() & co. for CHV EU/slice fuse bits
-:72: WARNING:LONG_LINE: line length of 113 exceeds 100 columns
#72: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:339:
+ REG_FIELD_GET(CHV_FGT_EU_DIS_SS0_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS0_R0_MASK);
-:85: WARNING:LONG_LINE: line length of 113 exceeds 100 columns
#85: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:348:
+ REG_FIELD_GET(CHV_FGT_EU_DIS_SS1_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS1_R0_MASK);
total: 0 errors, 2 warnings, 0 checks, 63 lines checked
6114db748089 drm/i915: Reoder CHV EU/slice fuse bits
43fa07ab4c85 drm/i915: Use REG_BIT() & co. for BDW+ EU/slice fuse bits
-:42: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#42: FILE: drivers/gpu/drm/i915/gt/intel_gt_mcr.c:125:
+ intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3));
-:59: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#59: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:519:
+#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? REG_GENMASK(6, 0) : REG_GENMASK(4, 0))
total: 0 errors, 2 warnings, 0 checks, 223 lines checked
bda22ad40c17 drm/i915: Reoder BDW+ EU/slice fuse bits
536b3bf34fdd drm/i915: Use REG_BIT() & co. for gen9+ timestamp freq registers
-:71: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#71: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:34:
+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
-:72: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#72: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:35:
+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
-:74: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#74: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:37:
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
-:75: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#75: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:38:
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
-:76: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#76: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:39:
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 2)
-:77: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#77: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:40:
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 3)
total: 0 errors, 6 warnings, 0 checks, 87 lines checked
498f2b15c9de drm/i915: Reoder gen9+ timestamp freq register bits
-:31: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#31: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:39:
+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
-:32: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#32: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:40:
+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
total: 0 errors, 2 warnings, 0 checks, 28 lines checked
^ permalink raw reply [flat|nested] 36+ messages in thread* ✗ i915.CI.BAT: failure for drm/i915: some GT register fixes and cleanups (rev2)
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
` (14 preceding siblings ...)
2025-02-12 4:06 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: some GT register fixes and cleanups (rev2) Patchwork
@ 2025-02-12 4:35 ` Patchwork
2025-02-25 0:12 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: some GT register fixes and cleanups (rev3) Patchwork
` (3 subsequent siblings)
19 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2025-02-12 4:35 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5539 bytes --]
== Series Details ==
Series: drm/i915: some GT register fixes and cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/144683/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16111 -> Patchwork_144683v2
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_144683v2 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_144683v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v2/index.html
Participating hosts (44 -> 39)
------------------------------
Missing (5): bat-adlp-11 bat-adlm-1 fi-snb-2520m bat-arlh-2 bat-mtlp-6
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_144683v2:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live:
- bat-rplp-1: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16111/bat-rplp-1/igt@i915_selftest@live.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v2/bat-rplp-1/igt@i915_selftest@live.html
Known issues
------------
Here are the changes found in Patchwork_144683v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live:
- bat-twl-2: NOTRUN -> [ABORT][3] ([i915#12919] / [i915#13503])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v2/bat-twl-2/igt@i915_selftest@live.html
* igt@i915_selftest@live@gt_timelines:
- bat-twl-2: NOTRUN -> [ABORT][4] ([i915#12919])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v2/bat-twl-2/igt@i915_selftest@live@gt_timelines.html
* igt@i915_selftest@live@hangcheck:
- bat-rplp-1: [PASS][5] -> [ABORT][6] ([i915#13399])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16111/bat-rplp-1/igt@i915_selftest@live@hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v2/bat-rplp-1/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@workarounds:
- bat-mtlp-9: [PASS][7] -> [DMESG-FAIL][8] ([i915#12061])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16111/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v2/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
* igt@kms_busy@basic@modeset:
- bat-apl-1: [PASS][9] -> [DMESG-WARN][10] ([i915#13532]) +1 other test dmesg-warn
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16111/bat-apl-1/igt@kms_busy@basic@modeset.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v2/bat-apl-1/igt@kms_busy@basic@modeset.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: [PASS][11] -> [SKIP][12] ([i915#9197]) +3 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16111/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v2/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
#### Possible fixes ####
* igt@i915_selftest@live:
- fi-bsw-n3050: [ABORT][13] ([i915#12435]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16111/fi-bsw-n3050/igt@i915_selftest@live.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v2/fi-bsw-n3050/igt@i915_selftest@live.html
* igt@i915_selftest@live@late_gt_pm:
- fi-bsw-n3050: [ABORT][15] -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16111/fi-bsw-n3050/igt@i915_selftest@live@late_gt_pm.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v2/fi-bsw-n3050/igt@i915_selftest@live@late_gt_pm.html
#### Warnings ####
* igt@i915_selftest@live@workarounds:
- bat-adlp-6: [INCOMPLETE][17] ([i915#9413]) -> [ABORT][18] ([i915#13399]) +1 other test abort
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16111/bat-adlp-6/igt@i915_selftest@live@workarounds.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v2/bat-adlp-6/igt@i915_selftest@live@workarounds.html
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12435
[i915#12919]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12919
[i915#13399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13399
[i915#13503]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13503
[i915#13532]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13532
[i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197
[i915#9413]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9413
Build changes
-------------
* Linux: CI_DRM_16111 -> Patchwork_144683v2
CI-20190529: 20190529
CI_DRM_16111: 76120b67a3d5e7a38cbc92fc39846297130fc6d0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8228: 8228
Patchwork_144683v2: 76120b67a3d5e7a38cbc92fc39846297130fc6d0 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v2/index.html
[-- Attachment #2: Type: text/html, Size: 6535 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: some GT register fixes and cleanups (rev3)
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
` (15 preceding siblings ...)
2025-02-12 4:35 ` ✗ i915.CI.BAT: failure " Patchwork
@ 2025-02-25 0:12 ` Patchwork
2025-02-25 0:42 ` ✓ i915.CI.BAT: success " Patchwork
` (2 subsequent siblings)
19 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2025-02-25 0:12 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: some GT register fixes and cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/144683/
State : warning
== Summary ==
Error: dim checkpatch failed
067f8029ba78 drm/i915: Bump RING_FAULT engine ID bits
97af3013b359 drm/i915: Relocate RING_FAULT bits
63b71db24fe6 drm/i915: Use REG_BIT() & co. for ring fault registers
d1ae0ace5b0f drm/i915: Document which RING_FAULT bits apply to which platforms
508078e91db8 drm/i915: Introduce RING_FAULT_VADDR_MASK
99155f3b698a drm/i915: Extract gen8_report_fault()
f9f45ccda144 drm/i915: Use REG_BIT() & co. for CHV EU/slice fuse bits
-:73: WARNING:LONG_LINE: line length of 113 exceeds 100 columns
#73: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:339:
+ REG_FIELD_GET(CHV_FGT_EU_DIS_SS0_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS0_R0_MASK);
-:86: WARNING:LONG_LINE: line length of 113 exceeds 100 columns
#86: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:348:
+ REG_FIELD_GET(CHV_FGT_EU_DIS_SS1_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS1_R0_MASK);
total: 0 errors, 2 warnings, 0 checks, 63 lines checked
dfd190e63803 drm/i915: Reoder CHV EU/slice fuse bits
87c339b22681 drm/i915: Use REG_BIT() & co. for BDW+ EU/slice fuse bits
-:43: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#43: FILE: drivers/gpu/drm/i915/gt/intel_gt_mcr.c:125:
+ intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3));
-:60: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#60: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:522:
+#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? REG_GENMASK(6, 0) : REG_GENMASK(4, 0))
total: 0 errors, 2 warnings, 0 checks, 223 lines checked
7816fcabc2e1 drm/i915: Reoder BDW+ EU/slice fuse bits
ec39f6499741 drm/i915: Use REG_BIT() & co. for gen9+ timestamp freq registers
-:72: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#72: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:34:
+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
-:73: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#73: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:35:
+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
-:75: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#75: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:37:
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
-:76: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#76: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:38:
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
-:77: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#77: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:39:
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 2)
-:78: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#78: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:40:
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 3)
total: 0 errors, 6 warnings, 0 checks, 87 lines checked
eba59250e005 drm/i915: Reoder gen9+ timestamp freq register bits
-:32: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#32: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:39:
+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
-:33: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#33: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:40:
+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
total: 0 errors, 2 warnings, 0 checks, 28 lines checked
^ permalink raw reply [flat|nested] 36+ messages in thread* ✓ i915.CI.BAT: success for drm/i915: some GT register fixes and cleanups (rev3)
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
` (16 preceding siblings ...)
2025-02-25 0:12 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: some GT register fixes and cleanups (rev3) Patchwork
@ 2025-02-25 0:42 ` Patchwork
2025-02-25 3:49 ` ✓ i915.CI.Full: " Patchwork
2025-03-04 21:04 ` [PATCH 00/12] drm/i915: some GT register fixes and cleanups Andi Shyti
19 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2025-02-25 0:42 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5018 bytes --]
== Series Details ==
Series: drm/i915: some GT register fixes and cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/144683/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16174 -> Patchwork_144683v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/index.html
Participating hosts (43 -> 43)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_144683v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@load:
- bat-mtlp-9: [PASS][1] -> [DMESG-WARN][2] ([i915#13494])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/bat-mtlp-9/igt@i915_module_load@load.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/bat-mtlp-9/igt@i915_module_load@load.html
* igt@i915_pm_rpm@module-reload:
- bat-rpls-4: [PASS][3] -> [FAIL][4] ([i915#13633])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/bat-rpls-4/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/bat-rpls-4/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live:
- bat-adlp-6: [PASS][5] -> [ABORT][6] ([i915#12435])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/bat-adlp-6/igt@i915_selftest@live.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/bat-adlp-6/igt@i915_selftest@live.html
* igt@i915_selftest@live@guc:
- bat-adlp-6: [PASS][7] -> [ABORT][8] ([i915#13696])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/bat-adlp-6/igt@i915_selftest@live@guc.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/bat-adlp-6/igt@i915_selftest@live@guc.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: [PASS][9] -> [SKIP][10] ([i915#9197]) +3 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
#### Possible fixes ####
* igt@dmabuf@all-tests@dma_fence_chain:
- fi-bsw-nick: [INCOMPLETE][11] ([i915#12904]) -> [PASS][12] +1 other test pass
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/fi-bsw-nick/igt@dmabuf@all-tests@dma_fence_chain.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/fi-bsw-nick/igt@dmabuf@all-tests@dma_fence_chain.html
* igt@i915_selftest@live@reset:
- bat-twl-2: [INCOMPLETE][13] ([i915#12445]) -> [PASS][14] +1 other test pass
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/bat-twl-2/igt@i915_selftest@live@reset.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/bat-twl-2/igt@i915_selftest@live@reset.html
#### Warnings ####
* igt@i915_selftest@live:
- bat-twl-1: [INCOMPLETE][15] -> [ABORT][16] ([i915#12435] / [i915#12919] / [i915#13503])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/bat-twl-1/igt@i915_selftest@live.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/bat-twl-1/igt@i915_selftest@live.html
* igt@i915_selftest@live@perf:
- bat-twl-1: [INCOMPLETE][17] -> [ABORT][18] ([i915#12919])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/bat-twl-1/igt@i915_selftest@live@perf.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/bat-twl-1/igt@i915_selftest@live@perf.html
[i915#12435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12435
[i915#12445]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12445
[i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
[i915#12919]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12919
[i915#13494]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13494
[i915#13503]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13503
[i915#13633]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13633
[i915#13696]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13696
[i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197
Build changes
-------------
* Linux: CI_DRM_16174 -> Patchwork_144683v3
CI-20190529: 20190529
CI_DRM_16174: 0bd853a9790bbe9c4ccf3bf2c521958d1df41d54 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8246: 2670886863d5821273146d7f94cdd3c8e3a4fe0b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_144683v3: 0bd853a9790bbe9c4ccf3bf2c521958d1df41d54 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/index.html
[-- Attachment #2: Type: text/html, Size: 5979 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread* ✓ i915.CI.Full: success for drm/i915: some GT register fixes and cleanups (rev3)
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
` (17 preceding siblings ...)
2025-02-25 0:42 ` ✓ i915.CI.BAT: success " Patchwork
@ 2025-02-25 3:49 ` Patchwork
2025-03-04 21:04 ` [PATCH 00/12] drm/i915: some GT register fixes and cleanups Andi Shyti
19 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2025-02-25 3:49 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 97275 bytes --]
== Series Details ==
Series: drm/i915: some GT register fixes and cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/144683/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16174_full -> Patchwork_144683v3_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
New tests
---------
New tests have been introduced between CI_DRM_16174_full and Patchwork_144683v3_full:
### New IGT tests (25) ###
* igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-2:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_ccs@bad-pixel-format-y-tiled-ccs@pipe-c-hdmi-a-2:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs@pipe-a-dp-3:
- Statuses : 1 pass(s)
- Exec time: [2.96] s
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs@pipe-b-dp-3:
- Statuses : 1 pass(s)
- Exec time: [0.00] s
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs@pipe-c-dp-3:
- Statuses : 1 pass(s)
- Exec time: [0.01] s
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs@pipe-d-dp-3:
- Statuses : 1 pass(s)
- Exec time: [0.01] s
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-2:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-2:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-a-dp-3:
- Statuses : 1 skip(s)
- Exec time: [0.00] s
* igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-b-dp-3:
- Statuses : 1 skip(s)
- Exec time: [0.00] s
* igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-c-dp-3:
- Statuses : 1 skip(s)
- Exec time: [0.00] s
* igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-3:
- Statuses : 1 skip(s)
- Exec time: [0.00] s
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-a-dp-3:
- Statuses : 1 skip(s)
- Exec time: [0.00] s
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-b-dp-3:
- Statuses : 1 skip(s)
- Exec time: [0.00] s
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-c-dp-3:
- Statuses : 1 skip(s)
- Exec time: [0.00] s
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-d-dp-3:
- Statuses : 1 skip(s)
- Exec time: [0.00] s
* igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-2:
- Statuses : 1 skip(s)
- Exec time: [0.00] s
* igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc@pipe-a-dp-3:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc@pipe-b-dp-3:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc@pipe-c-dp-3:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-3:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_144683v3_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-dg2: NOTRUN -> [SKIP][1] ([i915#8411])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-8/igt@api_intel_bb@blit-reloc-purge-cache.html
* igt@api_intel_bb@crc32:
- shard-tglu: NOTRUN -> [SKIP][2] ([i915#6230])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-5/igt@api_intel_bb@crc32.html
* igt@api_intel_bb@object-reloc-keep-cache:
- shard-dg2-9: NOTRUN -> [SKIP][3] ([i915#8411])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@api_intel_bb@object-reloc-keep-cache.html
* igt@device_reset@unbind-reset-rebind:
- shard-tglu: [PASS][4] -> [ABORT][5] ([i915#12817] / [i915#5507])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-tglu-6/igt@device_reset@unbind-reset-rebind.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-7/igt@device_reset@unbind-reset-rebind.html
* igt@drm_fdinfo@most-busy-idle-check-all@vecs1:
- shard-dg2: NOTRUN -> [SKIP][6] ([i915#8414]) +18 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@drm_fdinfo@most-busy-idle-check-all@vecs1.html
* igt@gem_caching@reads:
- shard-mtlp: NOTRUN -> [SKIP][7] ([i915#4873])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-7/igt@gem_caching@reads.html
* igt@gem_ccs@ctrl-surf-copy:
- shard-tglu: NOTRUN -> [SKIP][8] ([i915#3555] / [i915#9323]) +1 other test skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-7/igt@gem_ccs@ctrl-surf-copy.html
* igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0:
- shard-dg2: [PASS][9] -> [INCOMPLETE][10] ([i915#13356])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg2-6/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-1/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
* igt@gem_compute@compute-square:
- shard-dg2: NOTRUN -> [FAIL][11] ([i915#13665])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@gem_compute@compute-square.html
* igt@gem_ctx_persistence@heartbeat-many:
- shard-dg2: NOTRUN -> [SKIP][12] ([i915#8555]) +1 other test skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-7/igt@gem_ctx_persistence@heartbeat-many.html
* igt@gem_ctx_sseu@invalid-args:
- shard-tglu-1: NOTRUN -> [SKIP][13] ([i915#280])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@gem_ctx_sseu@invalid-args.html
* igt@gem_ctx_sseu@mmap-args:
- shard-dg2-9: NOTRUN -> [SKIP][14] ([i915#280])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_eio@context-create:
- shard-mtlp: [PASS][15] -> [ABORT][16] ([i915#13193]) +1 other test abort
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-mtlp-5/igt@gem_eio@context-create.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-7/igt@gem_eio@context-create.html
* igt@gem_eio@kms:
- shard-dg2: [PASS][17] -> [FAIL][18] ([i915#5784])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg2-7/igt@gem_eio@kms.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-7/igt@gem_eio@kms.html
* igt@gem_exec_balancer@bonded-false-hang:
- shard-dg2: NOTRUN -> [SKIP][19] ([i915#4812]) +1 other test skip
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-7/igt@gem_exec_balancer@bonded-false-hang.html
* igt@gem_exec_balancer@bonded-true-hang:
- shard-dg2-9: NOTRUN -> [SKIP][20] ([i915#4812]) +1 other test skip
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@gem_exec_balancer@bonded-true-hang.html
* igt@gem_exec_balancer@noheartbeat:
- shard-dg2-9: NOTRUN -> [SKIP][21] ([i915#8555])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@gem_exec_balancer@noheartbeat.html
* igt@gem_exec_balancer@parallel:
- shard-rkl: NOTRUN -> [SKIP][22] ([i915#4525])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-tglu-1: NOTRUN -> [SKIP][23] ([i915#4525])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-tglu: NOTRUN -> [SKIP][24] ([i915#4525])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-5/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_flush@basic-wb-prw-default:
- shard-dg2: NOTRUN -> [SKIP][25] ([i915#3539] / [i915#4852]) +1 other test skip
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-8/igt@gem_exec_flush@basic-wb-prw-default.html
* igt@gem_exec_reloc@basic-cpu-gtt-noreloc:
- shard-dg2: NOTRUN -> [SKIP][26] ([i915#3281]) +8 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html
* igt@gem_exec_reloc@basic-wc:
- shard-dg2-9: NOTRUN -> [SKIP][27] ([i915#3281]) +1 other test skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@gem_exec_reloc@basic-wc.html
* igt@gem_exec_reloc@basic-wc-cpu-active:
- shard-rkl: NOTRUN -> [SKIP][28] ([i915#3281]) +1 other test skip
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@gem_exec_reloc@basic-wc-cpu-active.html
* igt@gem_exec_reloc@basic-write-wc-active:
- shard-mtlp: NOTRUN -> [SKIP][29] ([i915#3281]) +1 other test skip
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-7/igt@gem_exec_reloc@basic-write-wc-active.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain:
- shard-dg2-9: NOTRUN -> [SKIP][30] ([i915#4537] / [i915#4812])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@gem_exec_schedule@preempt-queue-contexts-chain.html
* igt@gem_exec_schedule@reorder-wide:
- shard-dg2: NOTRUN -> [SKIP][31] ([i915#4537] / [i915#4812])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@gem_exec_schedule@reorder-wide.html
* igt@gem_exec_suspend@basic-s3-devices:
- shard-rkl: NOTRUN -> [DMESG-WARN][32] ([i915#12964]) +6 other tests dmesg-warn
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@gem_exec_suspend@basic-s3-devices.html
* igt@gem_exec_suspend@basic-s4-devices:
- shard-mtlp: NOTRUN -> [ABORT][33] ([i915#7975]) +1 other test abort
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-1/igt@gem_exec_suspend@basic-s4-devices.html
- shard-rkl: NOTRUN -> [ABORT][34] ([i915#7975]) +1 other test abort
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-1/igt@gem_exec_suspend@basic-s4-devices.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible:
- shard-dg2: NOTRUN -> [SKIP][35] ([i915#4860])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-7/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html
* igt@gem_lmem_evict@dontneed-evict-race:
- shard-tglu: NOTRUN -> [SKIP][36] ([i915#4613] / [i915#7582])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-7/igt@gem_lmem_evict@dontneed-evict-race.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-rkl: NOTRUN -> [SKIP][37] ([i915#4613]) +1 other test skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-1/igt@gem_lmem_swapping@parallel-random-verify.html
- shard-mtlp: NOTRUN -> [SKIP][38] ([i915#4613])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-1/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_lmem_swapping@verify:
- shard-tglu-1: NOTRUN -> [SKIP][39] ([i915#4613]) +1 other test skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@gem_lmem_swapping@verify.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-tglu: NOTRUN -> [SKIP][40] ([i915#4613])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-5/igt@gem_lmem_swapping@verify-ccs.html
- shard-glk: NOTRUN -> [SKIP][41] ([i915#4613]) +1 other test skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-glk3/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_media_fill@media-fill:
- shard-dg2-9: NOTRUN -> [SKIP][42] ([i915#8289])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@gem_media_fill@media-fill.html
* igt@gem_media_vme:
- shard-tglu-1: NOTRUN -> [SKIP][43] ([i915#284])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@gem_media_vme.html
* igt@gem_mmap_gtt@big-copy-odd:
- shard-dg2-9: NOTRUN -> [SKIP][44] ([i915#4077]) +5 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@gem_mmap_gtt@big-copy-odd.html
* igt@gem_mmap_wc@bad-size:
- shard-mtlp: NOTRUN -> [SKIP][45] ([i915#4083])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-7/igt@gem_mmap_wc@bad-size.html
* igt@gem_mmap_wc@pf-nonblock:
- shard-dg2: NOTRUN -> [SKIP][46] ([i915#4083]) +5 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@gem_mmap_wc@pf-nonblock.html
* igt@gem_mmap_wc@write-read:
- shard-dg2-9: NOTRUN -> [SKIP][47] ([i915#4083]) +2 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@gem_mmap_wc@write-read.html
* igt@gem_partial_pwrite_pread@write:
- shard-dg2: NOTRUN -> [SKIP][48] ([i915#3282]) +3 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-8/igt@gem_partial_pwrite_pread@write.html
* igt@gem_pwrite@basic-exhaustion:
- shard-tglu-1: NOTRUN -> [WARN][49] ([i915#2658])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@create-regular-buffer:
- shard-rkl: NOTRUN -> [TIMEOUT][50] ([i915#12917] / [i915#12964])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@gem_pxp@create-regular-buffer.html
* igt@gem_pxp@display-protected-crc:
- shard-dg2: NOTRUN -> [SKIP][51] ([i915#4270]) +2 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-8/igt@gem_pxp@display-protected-crc.html
* igt@gem_pxp@fail-invalid-protected-context:
- shard-dg2-9: NOTRUN -> [SKIP][52] ([i915#4270])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@gem_pxp@fail-invalid-protected-context.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-rkl: [PASS][53] -> [TIMEOUT][54] ([i915#12964])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-rkl-8/igt@gem_pxp@regular-baseline-src-copy-readible.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
- shard-rkl: NOTRUN -> [SKIP][55] ([i915#4270])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
* igt@gem_readwrite@beyond-eob:
- shard-dg2-9: NOTRUN -> [SKIP][56] ([i915#3282]) +3 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@gem_readwrite@beyond-eob.html
* igt@gem_readwrite@read-write:
- shard-mtlp: NOTRUN -> [SKIP][57] ([i915#3282])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-7/igt@gem_readwrite@read-write.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-dg2-9: NOTRUN -> [SKIP][58] ([i915#5190] / [i915#8428]) +3 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled:
- shard-mtlp: NOTRUN -> [SKIP][59] ([i915#8428])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-7/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled.html
* igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled:
- shard-dg2: NOTRUN -> [SKIP][60] ([i915#5190] / [i915#8428]) +5 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-8/igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled.html
* igt@gem_render_tiled_blits@basic:
- shard-mtlp: NOTRUN -> [SKIP][61] ([i915#4079])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-7/igt@gem_render_tiled_blits@basic.html
* igt@gem_set_tiling_vs_pwrite:
- shard-rkl: NOTRUN -> [SKIP][62] ([i915#3282]) +2 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@gem_set_tiling_vs_pwrite.html
* igt@gem_softpin@evict-snoop:
- shard-rkl: NOTRUN -> [SKIP][63] +4 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@gem_softpin@evict-snoop.html
- shard-mtlp: NOTRUN -> [SKIP][64] ([i915#4885])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-7/igt@gem_softpin@evict-snoop.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-tglu: NOTRUN -> [SKIP][65] ([i915#3297] / [i915#3323])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-7/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@map-fixed-invalidate:
- shard-dg2: NOTRUN -> [SKIP][66] ([i915#3297] / [i915#4880])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-8/igt@gem_userptr_blits@map-fixed-invalidate.html
* igt@gem_userptr_blits@readonly-pwrite-unsync:
- shard-tglu: NOTRUN -> [SKIP][67] ([i915#3297])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-7/igt@gem_userptr_blits@readonly-pwrite-unsync.html
* igt@gem_userptr_blits@unsync-unmap:
- shard-dg2: NOTRUN -> [SKIP][68] ([i915#3297]) +3 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-7/igt@gem_userptr_blits@unsync-unmap.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-tglu-1: NOTRUN -> [SKIP][69] ([i915#3297])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gen9_exec_parse@basic-rejected:
- shard-dg2-9: NOTRUN -> [SKIP][70] ([i915#2856])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@gen9_exec_parse@basic-rejected.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-tglu: NOTRUN -> [SKIP][71] ([i915#2527] / [i915#2856]) +1 other test skip
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-5/igt@gen9_exec_parse@batch-invalid-length.html
* igt@gen9_exec_parse@bb-start-param:
- shard-dg2: NOTRUN -> [SKIP][72] ([i915#2856]) +1 other test skip
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-8/igt@gen9_exec_parse@bb-start-param.html
* igt@gen9_exec_parse@secure-batches:
- shard-tglu-1: NOTRUN -> [SKIP][73] ([i915#2527] / [i915#2856]) +1 other test skip
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@gen9_exec_parse@secure-batches.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg1: [PASS][74] -> [ABORT][75] ([i915#9820])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg1-12/igt@i915_module_load@reload-with-fault-injection.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg1-14/igt@i915_module_load@reload-with-fault-injection.html
- shard-tglu: NOTRUN -> [ABORT][76] ([i915#12817] / [i915#9820])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-8/igt@i915_module_load@reload-with-fault-injection.html
- shard-mtlp: [PASS][77] -> [ABORT][78] ([i915#10131] / [i915#9820])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-mtlp-7/igt@i915_module_load@reload-with-fault-injection.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-3/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_freq_api@freq-reset:
- shard-rkl: NOTRUN -> [SKIP][79] ([i915#8399])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@i915_pm_freq_api@freq-reset.html
* igt@i915_pm_freq_api@freq-suspend:
- shard-tglu: NOTRUN -> [SKIP][80] ([i915#8399])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-7/igt@i915_pm_freq_api@freq-suspend.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0:
- shard-tglu-1: NOTRUN -> [WARN][81] ([i915#2681]) +4 other tests warn
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
* igt@i915_selftest@mock@memory_region:
- shard-dg2-9: NOTRUN -> [DMESG-WARN][82] ([i915#9311]) +1 other test dmesg-warn
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@i915_selftest@mock@memory_region.html
* igt@i915_suspend@debugfs-reader:
- shard-glk: NOTRUN -> [INCOMPLETE][83] ([i915#4817])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-glk3/igt@i915_suspend@debugfs-reader.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-mtlp: NOTRUN -> [SKIP][84] ([i915#4077]) +1 other test skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-7/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_addfb_basic@bo-too-small-due-to-tiling:
- shard-dg2: NOTRUN -> [SKIP][85] ([i915#4212]) +1 other test skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
* igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-b-hdmi-a-1-y-rc-ccs-cc:
- shard-rkl: NOTRUN -> [SKIP][86] ([i915#8709]) +1 other test skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-4/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-b-hdmi-a-1-y-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-c-hdmi-a-2-4-mc-ccs:
- shard-dg2-9: NOTRUN -> [SKIP][87] ([i915#8709]) +7 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-c-hdmi-a-2-4-mc-ccs.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-dp-3-4-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][88] ([i915#8709]) +7 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-11/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-dp-3-4-mc-ccs.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc-ccs-cc:
- shard-dg1: NOTRUN -> [SKIP][89] ([i915#8709]) +3 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg1-12/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc-ccs-cc.html
* igt@kms_async_flips@invalid-async-flip-atomic:
- shard-dg2-9: NOTRUN -> [SKIP][90] ([i915#12967])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_async_flips@invalid-async-flip-atomic.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-dg2-9: NOTRUN -> [SKIP][91] ([i915#9531])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-4:
- shard-dg1: [PASS][92] -> [FAIL][93] ([i915#5956]) +1 other test fail
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg1-16/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-4.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg1-18/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-4.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-90:
- shard-mtlp: NOTRUN -> [SKIP][94] +2 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-7/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-90:
- shard-tglu-1: NOTRUN -> [SKIP][95] ([i915#5286]) +1 other test skip
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-90:
- shard-dg2-9: NOTRUN -> [SKIP][96] +6 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-rkl: NOTRUN -> [SKIP][97] ([i915#5286]) +2 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-tglu: NOTRUN -> [SKIP][98] ([i915#5286]) +3 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][99] ([i915#4538] / [i915#5190]) +8 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-2/igt@kms_big_fb@y-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-dg2-9: NOTRUN -> [SKIP][100] ([i915#4538] / [i915#5190]) +4 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-addfb:
- shard-dg2: NOTRUN -> [SKIP][101] ([i915#5190]) +1 other test skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@kms_big_fb@y-tiled-addfb.html
* igt@kms_big_fb@yf-tiled-addfb:
- shard-dg2-9: NOTRUN -> [SKIP][102] ([i915#5190])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_big_fb@yf-tiled-addfb.html
* igt@kms_ccs@bad-pixel-format-y-tiled-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][103] ([i915#10307] / [i915#10434] / [i915#6095]) +2 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-4/igt@kms_ccs@bad-pixel-format-y-tiled-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1:
- shard-tglu-1: NOTRUN -> [SKIP][104] ([i915#6095]) +24 other tests skip
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][105] ([i915#12313])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
* igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2:
- shard-glk: NOTRUN -> [SKIP][106] +139 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-glk9/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2.html
* igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs:
- shard-rkl: NOTRUN -> [SKIP][107] ([i915#12313])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-a-dp-3 (NEW):
- shard-dg2: NOTRUN -> [SKIP][108] ([i915#10307] / [i915#6095]) +184 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-11/igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-a-dp-3.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
- shard-dg2: NOTRUN -> [SKIP][109] ([i915#12313])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-2/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][110] ([i915#6095]) +29 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-b-hdmi-a-2:
- shard-dg2-9: NOTRUN -> [SKIP][111] ([i915#10307] / [i915#6095]) +24 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-tglu: NOTRUN -> [SKIP][112] ([i915#12805])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-7/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
- shard-dg2: NOTRUN -> [SKIP][113] ([i915#12805])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][114] ([i915#6095]) +86 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-1/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][115] ([i915#6095]) +19 other tests skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-1/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-a-edp-1.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][116] ([i915#6095]) +12 other tests skip
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-2/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-3.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
- shard-dg2-9: NOTRUN -> [SKIP][117] ([i915#12313])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
* igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][118] ([i915#6095]) +87 other tests skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg1-13/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-3.html
* igt@kms_cdclk@mode-transition:
- shard-tglu: NOTRUN -> [SKIP][119] ([i915#3742])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-7/igt@kms_cdclk@mode-transition.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-dg2-9: NOTRUN -> [SKIP][120] ([i915#11616] / [i915#7213])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][121] ([i915#11616] / [i915#7213]) +4 other tests skip
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-8/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html
* igt@kms_cdclk@plane-scaling@pipe-d-dp-4:
- shard-dg2: NOTRUN -> [SKIP][122] ([i915#4087]) +3 other tests skip
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@kms_cdclk@plane-scaling@pipe-d-dp-4.html
* igt@kms_chamelium_audio@hdmi-audio-edid:
- shard-tglu-1: NOTRUN -> [SKIP][123] ([i915#11151] / [i915#7828]) +6 other tests skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@kms_chamelium_audio@hdmi-audio-edid.html
* igt@kms_chamelium_frames@dp-frame-dump:
- shard-mtlp: NOTRUN -> [SKIP][124] ([i915#11151] / [i915#7828])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-7/igt@kms_chamelium_frames@dp-frame-dump.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- shard-dg2: NOTRUN -> [SKIP][125] ([i915#11151] / [i915#7828]) +7 other tests skip
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_frames@hdmi-crc-single:
- shard-tglu: NOTRUN -> [SKIP][126] ([i915#11151] / [i915#7828]) +3 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-5/igt@kms_chamelium_frames@hdmi-crc-single.html
* igt@kms_chamelium_frames@hdmi-frame-dump:
- shard-rkl: NOTRUN -> [SKIP][127] ([i915#11151] / [i915#7828]) +1 other test skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@kms_chamelium_frames@hdmi-frame-dump.html
* igt@kms_chamelium_hpd@vga-hpd-for-each-pipe:
- shard-dg2-9: NOTRUN -> [SKIP][128] ([i915#11151] / [i915#7828]) +4 other tests skip
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html
* igt@kms_content_protection@atomic:
- shard-tglu: NOTRUN -> [SKIP][129] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424]) +1 other test skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-7/igt@kms_content_protection@atomic.html
- shard-dg2: NOTRUN -> [SKIP][130] ([i915#7118] / [i915#9424])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-8/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-dg2: NOTRUN -> [SKIP][131] ([i915#3299])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-7/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@legacy@pipe-a-dp-3:
- shard-dg2: NOTRUN -> [FAIL][132] ([i915#7173])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-11/igt@kms_content_protection@legacy@pipe-a-dp-3.html
* igt@kms_content_protection@lic-type-0:
- shard-dg2-9: NOTRUN -> [SKIP][133] ([i915#9424])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@srm:
- shard-dg2-9: NOTRUN -> [SKIP][134] ([i915#7118])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-dg2: NOTRUN -> [SKIP][135] ([i915#13049])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-7/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x32:
- shard-tglu-1: NOTRUN -> [SKIP][136] ([i915#3555]) +2 other tests skip
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-dg2-9: NOTRUN -> [SKIP][137] ([i915#13049])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-64x21:
- shard-mtlp: NOTRUN -> [SKIP][138] ([i915#8814])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-7/igt@kms_cursor_crc@cursor-rapid-movement-64x21.html
* igt@kms_cursor_crc@cursor-suspend:
- shard-dg2: [PASS][139] -> [INCOMPLETE][140] ([i915#12358] / [i915#7882])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg2-3/igt@kms_cursor_crc@cursor-suspend.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-3/igt@kms_cursor_crc@cursor-suspend.html
* igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-3:
- shard-dg2: [PASS][141] -> [INCOMPLETE][142] ([i915#12358])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg2-3/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-3.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-3/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-3.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [PASS][143] -> [FAIL][144] ([i915#13028])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-dg2: NOTRUN -> [SKIP][145] ([i915#4103] / [i915#4213])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-tglu: NOTRUN -> [SKIP][146] ([i915#4103])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions:
- shard-mtlp: NOTRUN -> [SKIP][147] ([i915#9809])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-7/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic:
- shard-dg2: NOTRUN -> [SKIP][148] ([i915#13046] / [i915#5354]) +2 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-8/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
- shard-dg2-9: NOTRUN -> [SKIP][149] ([i915#13046] / [i915#5354]) +2 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
* igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
- shard-dg2: NOTRUN -> [SKIP][150] ([i915#9833])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-8/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
- shard-tglu: NOTRUN -> [SKIP][151] ([i915#9723])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-7/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
* igt@kms_dp_aux_dev:
- shard-tglu: NOTRUN -> [SKIP][152] ([i915#1257])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-5/igt@kms_dp_aux_dev.html
* igt@kms_dp_linktrain_fallback@dp-fallback:
- shard-dg2: [PASS][153] -> [SKIP][154] ([i915#13707])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg2-10/igt@kms_dp_linktrain_fallback@dp-fallback.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-6/igt@kms_dp_linktrain_fallback@dp-fallback.html
* igt@kms_dp_linktrain_fallback@dsc-fallback:
- shard-dg2: NOTRUN -> [SKIP][155] ([i915#13707])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-2/igt@kms_dp_linktrain_fallback@dsc-fallback.html
* igt@kms_draw_crc@draw-method-mmap-gtt:
- shard-dg2-9: NOTRUN -> [SKIP][156] ([i915#8812])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_draw_crc@draw-method-mmap-gtt.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-rkl: NOTRUN -> [SKIP][157] ([i915#3840])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-1/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_dsc@dsc-with-bpc:
- shard-tglu-1: NOTRUN -> [SKIP][158] ([i915#3555] / [i915#3840])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-dg2-9: NOTRUN -> [SKIP][159] ([i915#3555] / [i915#3840])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_dsc@dsc-with-formats:
- shard-dg2: NOTRUN -> [SKIP][160] ([i915#3555] / [i915#3840])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@kms_dsc@dsc-with-formats.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-dg2-9: NOTRUN -> [SKIP][161] ([i915#3840] / [i915#9053])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_feature_discovery@chamelium:
- shard-rkl: NOTRUN -> [SKIP][162] ([i915#4854])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@display-3x:
- shard-dg2-9: NOTRUN -> [SKIP][163] ([i915#1839])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_feature_discovery@display-3x.html
* igt@kms_flip@2x-blocking-wf_vblank:
- shard-dg2-9: NOTRUN -> [SKIP][164] ([i915#9934]) +4 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_flip@2x-blocking-wf_vblank.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-rkl: NOTRUN -> [SKIP][165] ([i915#9934])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@2x-flip-vs-modeset-vs-hang:
- shard-dg2: NOTRUN -> [SKIP][166] ([i915#9934]) +6 other tests skip
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-8/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html
- shard-tglu: NOTRUN -> [SKIP][167] ([i915#3637]) +1 other test skip
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-7/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-glk: NOTRUN -> [INCOMPLETE][168] ([i915#12745] / [i915#4839])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-glk9/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2:
- shard-glk: NOTRUN -> [INCOMPLETE][169] ([i915#4839])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-glk9/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-tglu-1: NOTRUN -> [SKIP][170] ([i915#3637]) +3 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-dg2: [PASS][171] -> [FAIL][172] ([i915#13027])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg2-7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a3:
- shard-dg2: [PASS][173] -> [FAIL][174] ([i915#13528])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg2-7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a3.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-6/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a3.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
- shard-dg2: NOTRUN -> [SKIP][175] ([i915#2672] / [i915#3555]) +3 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][176] ([i915#2672]) +2 other tests skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
- shard-tglu: NOTRUN -> [SKIP][177] ([i915#2587] / [i915#2672]) +3 other tests skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-7/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling:
- shard-tglu: NOTRUN -> [SKIP][178] ([i915#2672] / [i915#3555]) +3 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-5/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-dg2: NOTRUN -> [SKIP][179] ([i915#2672] / [i915#3555] / [i915#5190])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling:
- shard-rkl: NOTRUN -> [SKIP][180] ([i915#2672] / [i915#3555])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html
- shard-mtlp: NOTRUN -> [SKIP][181] ([i915#3555] / [i915#8813])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][182] ([i915#8810])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][183] ([i915#2672])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling:
- shard-dg2-9: NOTRUN -> [SKIP][184] ([i915#2672] / [i915#3555] / [i915#5190]) +1 other test skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling@pipe-a-valid-mode:
- shard-dg2-9: NOTRUN -> [SKIP][185] ([i915#2672]) +1 other test skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-dg2-9: NOTRUN -> [SKIP][186] ([i915#8708]) +5 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-dg2: [PASS][187] -> [FAIL][188] ([i915#6880])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt:
- shard-mtlp: NOTRUN -> [SKIP][189] ([i915#1825]) +2 other tests skip
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][190] ([i915#8708]) +15 other tests skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render:
- shard-tglu: NOTRUN -> [SKIP][191] +41 other tests skip
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][192] ([i915#8708]) +1 other test skip
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-glk: NOTRUN -> [INCOMPLETE][193] ([i915#10056] / [i915#13353])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-glk7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][194] ([i915#3458]) +11 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
- shard-dg2-9: NOTRUN -> [SKIP][195] ([i915#3458]) +9 other tests skip
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt:
- shard-rkl: NOTRUN -> [SKIP][196] ([i915#1825]) +11 other tests skip
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt:
- shard-snb: NOTRUN -> [SKIP][197] +58 other tests skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-snb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
- shard-tglu-1: NOTRUN -> [SKIP][198] +42 other tests skip
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
- shard-rkl: NOTRUN -> [SKIP][199] ([i915#3023]) +5 other tests skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
- shard-dg2-9: NOTRUN -> [SKIP][200] ([i915#10055])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-dg2-9: NOTRUN -> [SKIP][201] ([i915#5354]) +11 other tests skip
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-onoff:
- shard-dg2: NOTRUN -> [SKIP][202] ([i915#5354]) +25 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-onoff.html
* igt@kms_hdr@bpc-switch:
- shard-dg2: NOTRUN -> [SKIP][203] ([i915#3555] / [i915#8228])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-2/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-dg2: [PASS][204] -> [SKIP][205] ([i915#3555] / [i915#8228])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg2-10/igt@kms_hdr@bpc-switch-dpms.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-6/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_hdr@brightness-with-hdr:
- shard-dg2: NOTRUN -> [SKIP][206] ([i915#12713])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-7/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_hdr@static-swap:
- shard-tglu: NOTRUN -> [SKIP][207] ([i915#3555] / [i915#8228])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-5/igt@kms_hdr@static-swap.html
* igt@kms_joiner@basic-big-joiner:
- shard-tglu-1: NOTRUN -> [SKIP][208] ([i915#10656]) +1 other test skip
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@kms_joiner@basic-big-joiner.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-dg2: [PASS][209] -> [SKIP][210] ([i915#12388])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg2-10/igt@kms_joiner@invalid-modeset-force-big-joiner.html
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_joiner@invalid-modeset-force-ultra-joiner:
- shard-dg2-9: NOTRUN -> [SKIP][211] ([i915#10656])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-ultra-joiner:
- shard-tglu: NOTRUN -> [SKIP][212] ([i915#12339])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-7/igt@kms_joiner@invalid-modeset-ultra-joiner.html
- shard-dg2: NOTRUN -> [SKIP][213] ([i915#12339])
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-8/igt@kms_joiner@invalid-modeset-ultra-joiner.html
* igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
- shard-dg2: NOTRUN -> [SKIP][214] ([i915#13522])
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
* igt@kms_panel_fitting@legacy:
- shard-dg2-9: NOTRUN -> [SKIP][215] ([i915#6301])
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_panel_fitting@legacy.html
* igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
- shard-dg2: NOTRUN -> [SKIP][216] +6 other tests skip
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html
* igt@kms_plane_lowres@tiling-4:
- shard-tglu: NOTRUN -> [SKIP][217] ([i915#3555]) +2 other tests skip
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-5/igt@kms_plane_lowres@tiling-4.html
* igt@kms_plane_lowres@tiling-yf:
- shard-dg2-9: NOTRUN -> [SKIP][218] ([i915#3555] / [i915#8821])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation:
- shard-dg2: NOTRUN -> [SKIP][219] ([i915#12247] / [i915#9423]) +1 other test skip
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a:
- shard-rkl: NOTRUN -> [SKIP][220] ([i915#12247]) +2 other tests skip
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-c:
- shard-mtlp: NOTRUN -> [SKIP][221] ([i915#12247]) +4 other tests skip
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-7/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-c.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25:
- shard-dg2: NOTRUN -> [SKIP][222] ([i915#12247] / [i915#6953] / [i915#9423]) +1 other test skip
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-a:
- shard-dg2: NOTRUN -> [SKIP][223] ([i915#12247]) +15 other tests skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-a.html
* igt@kms_pm_backlight@basic-brightness:
- shard-tglu: NOTRUN -> [SKIP][224] ([i915#9812])
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-7/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_pm_backlight@brightness-with-dpms:
- shard-dg2: NOTRUN -> [SKIP][225] ([i915#12343])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@kms_pm_backlight@brightness-with-dpms.html
* igt@kms_pm_dc@dc5-retention-flops:
- shard-tglu-1: NOTRUN -> [SKIP][226] ([i915#3828])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@kms_pm_dc@dc5-retention-flops.html
* igt@kms_pm_dc@dc6-dpms:
- shard-rkl: NOTRUN -> [SKIP][227] ([i915#3361])
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-dg2-9: NOTRUN -> [SKIP][228] ([i915#9340])
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-tglu-1: NOTRUN -> [SKIP][229] ([i915#9519])
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-dg2: [PASS][230] -> [SKIP][231] ([i915#9519])
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg2-8/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-7/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-rkl: [PASS][232] -> [SKIP][233] ([i915#9519]) +2 other tests skip
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-rkl-3/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_pm_rpm@pm-tiling:
- shard-dg2: NOTRUN -> [SKIP][234] ([i915#4077]) +6 other tests skip
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-2/igt@kms_pm_rpm@pm-tiling.html
* igt@kms_prime@basic-crc-hybrid:
- shard-tglu-1: NOTRUN -> [SKIP][235] ([i915#6524])
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_prime@basic-modeset-hybrid:
- shard-dg2-9: NOTRUN -> [SKIP][236] ([i915#6524] / [i915#6805])
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_prime@basic-modeset-hybrid.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf:
- shard-rkl: NOTRUN -> [SKIP][237] ([i915#11520]) +2 other tests skip
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf.html
- shard-mtlp: NOTRUN -> [SKIP][238] ([i915#12316])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-7/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area:
- shard-glk: NOTRUN -> [SKIP][239] ([i915#11520]) +1 other test skip
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-glk7/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf:
- shard-dg2-9: NOTRUN -> [SKIP][240] ([i915#11520]) +3 other tests skip
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf:
- shard-snb: NOTRUN -> [SKIP][241] ([i915#11520])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-snb5/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area:
- shard-tglu: NOTRUN -> [SKIP][242] ([i915#11520]) +4 other tests skip
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-8/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
- shard-tglu-1: NOTRUN -> [SKIP][243] ([i915#11520]) +2 other tests skip
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@psr2-plane-move-sf-dmg-area:
- shard-dg2: NOTRUN -> [SKIP][244] ([i915#11520]) +4 other tests skip
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@kms_psr2_sf@psr2-plane-move-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-tglu-1: NOTRUN -> [SKIP][245] ([i915#9683])
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-pr-primary-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][246] ([i915#1072] / [i915#9732]) +15 other tests skip
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-8/igt@kms_psr@fbc-pr-primary-mmap-gtt.html
* igt@kms_psr@fbc-pr-sprite-plane-onoff:
- shard-mtlp: NOTRUN -> [SKIP][247] ([i915#9688])
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-7/igt@kms_psr@fbc-pr-sprite-plane-onoff.html
* igt@kms_psr@fbc-psr-primary-render:
- shard-tglu-1: NOTRUN -> [SKIP][248] ([i915#9732]) +9 other tests skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@kms_psr@fbc-psr-primary-render.html
* igt@kms_psr@fbc-psr2-suspend:
- shard-dg2-9: NOTRUN -> [SKIP][249] ([i915#1072] / [i915#9732]) +9 other tests skip
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_psr@fbc-psr2-suspend.html
* igt@kms_psr@pr-dpms:
- shard-tglu: NOTRUN -> [SKIP][250] ([i915#9732]) +9 other tests skip
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-5/igt@kms_psr@pr-dpms.html
* igt@kms_psr@psr-sprite-plane-move:
- shard-rkl: NOTRUN -> [SKIP][251] ([i915#1072] / [i915#9732]) +5 other tests skip
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-1/igt@kms_psr@psr-sprite-plane-move.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-dg2: NOTRUN -> [SKIP][252] ([i915#9685])
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-tglu: NOTRUN -> [SKIP][253] ([i915#5289]) +1 other test skip
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-dg2-9: NOTRUN -> [SKIP][254] ([i915#12755] / [i915#5190])
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_rotation_crc@sprite-rotation-270:
- shard-dg2-9: NOTRUN -> [SKIP][255] ([i915#12755])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_rotation_crc@sprite-rotation-270.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-rkl: [PASS][256] -> [DMESG-WARN][257] ([i915#12964]) +12 other tests dmesg-warn
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-rkl-8/igt@kms_rotation_crc@sprite-rotation-90.html
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-3/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@kms_scaling_modes@scaling-mode-none:
- shard-dg2: NOTRUN -> [SKIP][258] ([i915#3555]) +2 other tests skip
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-8/igt@kms_scaling_modes@scaling-mode-none.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-dg2: NOTRUN -> [SKIP][259] ([i915#8623])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-2/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_vrr@flip-suspend:
- shard-dg2-9: NOTRUN -> [SKIP][260] ([i915#3555]) +1 other test skip
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_vrr@flip-suspend.html
* igt@kms_vrr@negative-basic:
- shard-dg2-9: NOTRUN -> [SKIP][261] ([i915#3555] / [i915#9906])
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-9/igt@kms_vrr@negative-basic.html
* igt@kms_vrr@seamless-rr-switch-virtual:
- shard-tglu: NOTRUN -> [SKIP][262] ([i915#9906])
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-5/igt@kms_vrr@seamless-rr-switch-virtual.html
* igt@kms_vrr@seamless-rr-switch-vrr:
- shard-dg2: NOTRUN -> [SKIP][263] ([i915#9906]) +1 other test skip
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-7/igt@kms_vrr@seamless-rr-switch-vrr.html
* igt@kms_writeback@writeback-check-output-xrgb2101010:
- shard-dg2: NOTRUN -> [SKIP][264] ([i915#2437] / [i915#9412])
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-8/igt@kms_writeback@writeback-check-output-xrgb2101010.html
- shard-tglu: NOTRUN -> [SKIP][265] ([i915#2437] / [i915#9412])
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-7/igt@kms_writeback@writeback-check-output-xrgb2101010.html
* igt@kms_writeback@writeback-fb-id:
- shard-tglu-1: NOTRUN -> [SKIP][266] ([i915#2437])
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@kms_writeback@writeback-fb-id.html
* igt@perf_pmu@busy-start@vcs1:
- shard-dg2: NOTRUN -> [INCOMPLETE][267] ([i915#13520]) +1 other test incomplete
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@perf_pmu@busy-start@vcs1.html
* igt@perf_pmu@rc6-suspend:
- shard-glk: NOTRUN -> [INCOMPLETE][268] ([i915#13356]) +1 other test incomplete
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-glk2/igt@perf_pmu@rc6-suspend.html
* igt@perf_pmu@rc6@other-idle-gt0:
- shard-tglu-1: NOTRUN -> [SKIP][269] ([i915#8516])
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-1/igt@perf_pmu@rc6@other-idle-gt0.html
* igt@prime_mmap@test_aperture_limit:
- shard-dg2: NOTRUN -> [WARN][270] ([i915#9351])
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-2/igt@prime_mmap@test_aperture_limit.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: NOTRUN -> [CRASH][271] ([i915#9351])
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-2/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
* igt@prime_vgem@basic-read:
- shard-dg2: NOTRUN -> [SKIP][272] ([i915#3291] / [i915#3708])
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-7/igt@prime_vgem@basic-read.html
* igt@prime_vgem@coherency-gtt:
- shard-dg2: NOTRUN -> [SKIP][273] ([i915#3708] / [i915#4077])
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@prime_vgem@coherency-gtt.html
#### Possible fixes ####
* igt@gem_eio@in-flight-contexts-immediate:
- shard-mtlp: [ABORT][274] ([i915#13193]) -> [PASS][275] +1 other test pass
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-mtlp-7/igt@gem_eio@in-flight-contexts-immediate.html
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-1/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_exec_suspend@basic-s0@smem:
- shard-dg2: [INCOMPLETE][276] ([i915#11441] / [i915#13304]) -> [PASS][277] +1 other test pass
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg2-4/igt@gem_exec_suspend@basic-s0@smem.html
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-2/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_pxp@create-regular-context-1:
- shard-rkl: [TIMEOUT][278] ([i915#12917] / [i915#12964]) -> [PASS][279] +1 other test pass
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-rkl-5/igt@gem_pxp@create-regular-context-1.html
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-8/igt@gem_pxp@create-regular-context-1.html
* igt@gem_pxp@create-valid-protected-context:
- shard-rkl: [TIMEOUT][280] ([i915#12964]) -> [PASS][281]
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-rkl-3/igt@gem_pxp@create-valid-protected-context.html
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-8/igt@gem_pxp@create-valid-protected-context.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-snb: [ABORT][282] ([i915#9820]) -> [PASS][283]
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-snb6/igt@i915_module_load@reload-with-fault-injection.html
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-snb5/igt@i915_module_load@reload-with-fault-injection.html
- shard-dg2: [ABORT][284] ([i915#9820]) -> [PASS][285]
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg2-1/igt@i915_module_load@reload-with-fault-injection.html
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-7/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_atomic_interruptible@atomic-setmode:
- shard-rkl: [DMESG-WARN][286] ([i915#12964]) -> [PASS][287] +9 other tests pass
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-rkl-3/igt@kms_atomic_interruptible@atomic-setmode.html
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-8/igt@kms_atomic_interruptible@atomic-setmode.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-mtlp: [FAIL][288] ([i915#5138]) -> [PASS][289]
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_cursor_crc@cursor-random-256x85:
- shard-rkl: [FAIL][290] ([i915#13566]) -> [PASS][291] +5 other tests pass
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-rkl-5/igt@kms_cursor_crc@cursor-random-256x85.html
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-6/igt@kms_cursor_crc@cursor-random-256x85.html
* igt@kms_cursor_crc@cursor-sliding-128x42:
- shard-tglu: [FAIL][292] ([i915#13566]) -> [PASS][293] +5 other tests pass
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-tglu-7/igt@kms_cursor_crc@cursor-sliding-128x42.html
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-9/igt@kms_cursor_crc@cursor-sliding-128x42.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [FAIL][294] ([i915#13028]) -> [PASS][295]
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-glk2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_flip@flip-vs-panning-vs-hang:
- shard-dg2: [INCOMPLETE][296] ([i915#12314] / [i915#6113]) -> [PASS][297]
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg2-4/igt@kms_flip@flip-vs-panning-vs-hang.html
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@kms_flip@flip-vs-panning-vs-hang.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
- shard-dg2: [FAIL][298] ([i915#6880]) -> [PASS][299]
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
* igt@kms_hdr@static-toggle-suspend:
- shard-dg2: [SKIP][300] ([i915#3555] / [i915#8228]) -> [PASS][301]
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg2-4/igt@kms_hdr@static-toggle-suspend.html
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-10/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_invalid_mode@bad-hsync-start:
- shard-dg1: [DMESG-WARN][302] ([i915#4423]) -> [PASS][303] +1 other test pass
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg1-14/igt@kms_invalid_mode@bad-hsync-start.html
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg1-13/igt@kms_invalid_mode@bad-hsync-start.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-dg2: [SKIP][304] ([i915#12388]) -> [PASS][305]
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg2-5/igt@kms_joiner@basic-force-big-joiner.html
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-11/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-rkl: [SKIP][306] ([i915#9519]) -> [PASS][307] +1 other test pass
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-rkl-7/igt@kms_pm_rpm@modeset-non-lpsp.html
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-1/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-dg2: [SKIP][308] ([i915#9519]) -> [PASS][309] +2 other tests pass
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg2-8/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-2/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_setmode@basic:
- shard-rkl: [FAIL][310] ([i915#5465]) -> [PASS][311]
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-rkl-5/igt@kms_setmode@basic.html
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-7/igt@kms_setmode@basic.html
* igt@kms_universal_plane@cursor-fb-leak:
- shard-mtlp: [FAIL][312] ([i915#9196]) -> [PASS][313] +1 other test pass
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-mtlp-6/igt@kms_universal_plane@cursor-fb-leak.html
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-mtlp-5/igt@kms_universal_plane@cursor-fb-leak.html
#### Warnings ####
* igt@i915_suspend@basic-s3-without-i915:
- shard-tglu: [INCOMPLETE][314] ([i915#4817] / [i915#7443]) -> [INCOMPLETE][315] ([i915#7443])
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-tglu-8/igt@i915_suspend@basic-s3-without-i915.html
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-tglu-7/igt@i915_suspend@basic-s3-without-i915.html
* igt@i915_suspend@sysfs-reader:
- shard-glk: [INCOMPLETE][316] ([i915#4817]) -> [INCOMPLETE][317] ([i915#13502] / [i915#4817])
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-glk3/igt@i915_suspend@sysfs-reader.html
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-glk1/igt@i915_suspend@sysfs-reader.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc:
- shard-dg1: [SKIP][318] ([i915#4423] / [i915#6095]) -> [SKIP][319] ([i915#6095]) +1 other test skip
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg1-17/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc.html
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg1-14/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_content_protection@legacy:
- shard-dg2: [SKIP][320] ([i915#7118] / [i915#9424]) -> [FAIL][321] ([i915#7173])
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg2-5/igt@kms_content_protection@legacy.html
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg2-11/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@mei-interface:
- shard-dg1: [SKIP][322] ([i915#9424]) -> [SKIP][323] ([i915#9433])
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg1-14/igt@kms_content_protection@mei-interface.html
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg1-13/igt@kms_content_protection@mei-interface.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-dg1: [SKIP][324] ([i915#9934]) -> [SKIP][325] ([i915#4423] / [i915#9934])
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg1-17/igt@kms_flip@2x-absolute-wf_vblank.html
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg1-19/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
- shard-dg1: [SKIP][326] ([i915#2587] / [i915#2672] / [i915#3555]) -> [SKIP][327] ([i915#2587] / [i915#2672] / [i915#3555] / [i915#4423])
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg1-17/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg1-19/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-dg1: [SKIP][328] ([i915#2587] / [i915#2672]) -> [SKIP][329] ([i915#2587] / [i915#2672] / [i915#4423])
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg1-17/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg1-19/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc:
- shard-dg1: [SKIP][330] ([i915#8708]) -> [SKIP][331] ([i915#4423] / [i915#8708])
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg1-17/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg1-19/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render:
- shard-dg1: [SKIP][332] ([i915#3458] / [i915#4423]) -> [SKIP][333] ([i915#3458])
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg1-14/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render.html
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg1-13/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][334] ([i915#4816]) -> [SKIP][335] ([i915#4070] / [i915#4816])
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-5/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-rkl: [SKIP][336] ([i915#9340]) -> [SKIP][337] ([i915#3828])
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-rkl-1/igt@kms_pm_lpsp@kms-lpsp.html
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-rkl-4/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-sf:
- shard-dg1: [SKIP][338] ([i915#11520] / [i915#4423]) -> [SKIP][339] ([i915#11520])
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16174/shard-dg1-14/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-sf.html
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/shard-dg1-13/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-sf.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10055]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10055
[i915#10056]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10056
[i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
[i915#11441]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11441
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#11616]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11616
[i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
[i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
[i915#12314]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12314
[i915#12316]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12316
[i915#12339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12339
[i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
[i915#12358]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12358
[i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
[i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
[i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
[i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
[i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
[i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
[i915#12817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12817
[i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917
[i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964
[i915#12967]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12967
[i915#13027]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13027
[i915#13028]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13028
[i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
[i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
[i915#13193]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13193
[i915#13304]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13304
[i915#13353]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13353
[i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
[i915#13502]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13502
[i915#13520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13520
[i915#13522]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13522
[i915#13528]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13528
[i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
[i915#13665]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13665
[i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
[i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
[i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2681
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
[i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4087
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
[i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
[i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4873
[i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
[i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
[i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5465]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5465
[i915#5507]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5507
[i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
[i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6113]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6113
[i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
[i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#6805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6805
[i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
[i915#7213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7213
[i915#7443]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7443
[i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#7882]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7882
[i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8289
[i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
[i915#8810]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8810
[i915#8812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8812
[i915#8813]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8813
[i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
[i915#8821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8821
[i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
[i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
[i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9351]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9351
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
[i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9833]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9833
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_16174 -> Patchwork_144683v3
CI-20190529: 20190529
CI_DRM_16174: 0bd853a9790bbe9c4ccf3bf2c521958d1df41d54 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8246: 2670886863d5821273146d7f94cdd3c8e3a4fe0b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_144683v3: 0bd853a9790bbe9c4ccf3bf2c521958d1df41d54 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144683v3/index.html
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^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH 00/12] drm/i915: some GT register fixes and cleanups
2025-02-11 23:19 [PATCH 00/12] drm/i915: some GT register fixes and cleanups Ville Syrjala
` (18 preceding siblings ...)
2025-02-25 3:49 ` ✓ i915.CI.Full: " Patchwork
@ 2025-03-04 21:04 ` Andi Shyti
19 siblings, 0 replies; 36+ messages in thread
From: Andi Shyti @ 2025-03-04 21:04 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
Hi Ville,
> Ville Syrjälä (12):
> drm/i915: Bump RING_FAULT engine ID bits
> drm/i915: Relocate RING_FAULT bits
> drm/i915: Use REG_BIT() & co. for ring fault registers
> drm/i915: Document which RING_FAULT bits apply to which platforms
> drm/i915: Introduce RING_FAULT_VADDR_MASK
> drm/i915: Extract gen8_report_fault()
> drm/i915: Use REG_BIT() & co. for CHV EU/slice fuse bits
> drm/i915: Reoder CHV EU/slice fuse bits
> drm/i915: Use REG_BIT() & co. for BDW+ EU/slice fuse bits
> drm/i915: Reoder BDW+ EU/slice fuse bits
> drm/i915: Use REG_BIT() & co. for gen9+ timestamp freq registers
> drm/i915: Reoder gen9+ timestamp freq register bits
merged to drm-intel-gt-next.
Thanks,
Andi
^ permalink raw reply [flat|nested] 36+ messages in thread