From: Jani Nikula <jani.nikula@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH 07/12] drm/i915: extend the fsb_freq initialization to more platforms
Date: Thu, 06 Jun 2024 13:37:32 +0300 [thread overview]
Message-ID: <87bk4ebbmb.fsf@intel.com> (raw)
In-Reply-To: <ZmA84kK3SgPSbMOB@intel.com>
On Wed, 05 Jun 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, May 28, 2024 at 05:24:56PM +0300, Jani Nikula wrote:
>> Initialize fsb frequency for more platforms to be able to use it for GT
>> clock and rawclk frequency initialization.
>>
>> Note: There's a discrepancy between existing pnv_fsb_freq() and
>> i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is
>> mobile.
>>
>> FIXME: What should the default or failure mode be when the value is
>> unknown?
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/soc/intel_dram.c | 54 ++++++++++++++++++++-------
>> 1 file changed, 40 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
>> index ace9372244a4..74b5b70e91f9 100644
>> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
>> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
>> @@ -142,24 +142,50 @@ static void detect_mem_freq(struct drm_i915_private *i915)
>> drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
>> }
>>
>> -static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
>> +static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
>> {
>> u32 fsb;
>>
>> fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK;
>>
>> - switch (fsb) {
>> - case CLKCFG_FSB_400:
>> - return 400000;
>> - case CLKCFG_FSB_533:
>> - return 533333;
>> - case CLKCFG_FSB_667:
>> - return 666667;
>> - case CLKCFG_FSB_800:
>> - return 800000;
>> + if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) {
>> + switch (fsb) {
>> + case CLKCFG_FSB_400:
>> + return 400000;
>> + case CLKCFG_FSB_533:
>> + return 533333;
>> + case CLKCFG_FSB_667:
>> + return 666667;
>> + case CLKCFG_FSB_800:
>> + return 800000;
>> + case CLKCFG_FSB_1067:
>> + return 1066667;
>> + case CLKCFG_FSB_1333:
>> + return 1333333;
>> + default:
>> + MISSING_CASE(fsb);
>> + return 1333333;
>> + }
>> + } else {
>> + switch (fsb) {
>> + case CLKCFG_FSB_400_ALT:
>> + return 400000;
>> + case CLKCFG_FSB_533:
>> + return 533333;
>> + case CLKCFG_FSB_667:
>> + return 666667;
>> + case CLKCFG_FSB_800:
>> + return 800000;
>> + case CLKCFG_FSB_1067_ALT:
>> + return 1066667;
>> + case CLKCFG_FSB_1333_ALT:
>> + return 1333333;
>> + case CLKCFG_FSB_1600_ALT:
>> + return 1600000;
>> + default:
>
> No MISSING_CASE() here?
Whoops.
>
>> + return 533333;
>
> Why a different default value vs. the other branch?
No idea. :/
>
>> + }
>> }
>> -
>> - return 0;
>> }
>>
>> static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
>> @@ -193,8 +219,8 @@ static void detect_fsb_freq(struct drm_i915_private *i915)
>> {
>> if (GRAPHICS_VER(i915) == 5)
>> i915->fsb_freq = ilk_fsb_freq(i915);
>> - else if (IS_PINEVIEW(i915))
>> - i915->fsb_freq = pnv_fsb_freq(i915);
>> + else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4)
>> + i915->fsb_freq = i9xx_fsb_freq(i915);
>>
>> if (i915->fsb_freq)
>> drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq);
>> --
>> 2.39.2
--
Jani Nikula, Intel
next prev parent reply other threads:[~2024-06-06 10:37 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-28 14:24 [PATCH 00/12] drm/i915: mem/fsb/rawclk freq cleanups Jani Nikula
2024-05-28 14:24 ` [PATCH 01/12] drm/i915/wm: rename intel_get_cxsr_latency -> pnv_get_cxsr_latency Jani Nikula
2024-05-29 20:53 ` Matt Roper
2024-05-28 14:24 ` [PATCH 02/12] drm/i915/wm: clarify logging on not finding CxSR latency config Jani Nikula
2024-05-29 21:00 ` Matt Roper
2024-05-30 6:59 ` Jani Nikula
2024-05-28 14:24 ` [PATCH 03/12] drm/i915/dram: separate fsb freq detection from mem freq Jani Nikula
2024-05-29 21:08 ` Matt Roper
2024-05-28 14:24 ` [PATCH 04/12] drm/i915/dram: split out pnv DDR3 detection Jani Nikula
2024-05-29 21:12 ` Matt Roper
2024-05-28 14:24 ` [PATCH 05/12] drm/i915/dram: rearrange mem freq init Jani Nikula
2024-05-29 21:13 ` Matt Roper
2024-05-28 14:24 ` [PATCH 06/12] drm/i915: convert fsb_freq and mem_freq to kHz Jani Nikula
2024-05-29 21:16 ` Matt Roper
2024-05-30 7:01 ` Jani Nikula
2024-06-05 10:12 ` Ville Syrjälä
2024-06-05 12:42 ` Jani Nikula
2024-05-28 14:24 ` [PATCH 07/12] drm/i915: extend the fsb_freq initialization to more platforms Jani Nikula
2024-05-29 21:39 ` Matt Roper
2024-05-30 7:14 ` Jani Nikula
2024-06-04 11:46 ` Jani Nikula
2024-06-05 10:18 ` Ville Syrjälä
2024-06-05 10:24 ` Ville Syrjälä
2024-06-06 10:37 ` Jani Nikula [this message]
2024-05-28 14:24 ` [PATCH 08/12] drm/i915: use i9xx_fsb_freq() for GT clock frequency Jani Nikula
2024-05-28 14:24 ` [PATCH 09/12] drm/i915/cdclk: use i9xx_fsb_freq() for rawclk_freq initialization Jani Nikula
2024-06-05 10:31 ` Ville Syrjälä
2024-05-28 14:24 ` [PATCH 10/12] drm/i915: move rawclk init to intel_cdclk_init() Jani Nikula
2024-05-29 10:26 ` Jani Nikula
2024-05-28 14:25 ` [PATCH 11/12] drm/i915: move rawclk from runtime to display runtime info Jani Nikula
2024-05-28 14:25 ` [PATCH 12/12] drm/xe/display: drop unused rawclk_freq and RUNTIME_INFO() Jani Nikula
2024-05-28 14:32 ` ✓ CI.Patch_applied: success for drm/i915: mem/fsb/rawclk freq cleanups Patchwork
2024-05-28 14:32 ` ✓ CI.checkpatch: " Patchwork
2024-05-28 14:33 ` ✗ CI.KUnit: failure " Patchwork
2024-05-28 16:22 ` ✗ Fi.CI.SPARSE: warning " Patchwork
2024-05-28 16:30 ` ✓ Fi.CI.BAT: success " Patchwork
2024-05-29 10:08 ` ✗ Fi.CI.IGT: failure " Patchwork
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