Re: [PATCH 09/12] drm/i915/cdclk: use i9xx_fsb_freq() for rawclk_freq initialization

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Tue, May 28, 2024 at 05:24:58PM +0300, Jani Nikula wrote:
> Instead of duplicating the CLKCFG parsing, reuse i9xx_fsb_freq() to
> figure out rawclk_freq where applicable.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 46 ++--------------------
>  1 file changed, 3 insertions(+), 43 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index b78154c82a71..c731c489c925 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -23,6 +23,7 @@
>  
>  #include <linux/time.h>
>  
> +#include "soc/intel_dram.h"
>  #include "hsw_ips.h"
>  #include "i915_reg.h"
>  #include "intel_atomic.h"
> @@ -3529,10 +3530,8 @@ static int vlv_hrawclk(struct drm_i915_private *dev_priv)
>  				      CCK_DISPLAY_REF_CLOCK_CONTROL);
>  }
>  
> -static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
> +static int i9xx_hrawclk(struct drm_i915_private *i915)
>  {
> -	u32 clkcfg;
> -
>  	/*
>  	 * hrawclock is 1/4 the FSB frequency
>  	 *
> @@ -3543,46 +3542,7 @@ static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
>  	 * don't know which registers have that information,
>  	 * and all the relevant docs have gone to bit heaven :(
>  	 */

^ the note about the actual clock vs. straps should probably be moved
into i9xx_fsb_freq() as a followup.

> -	clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK;
> -
> -	if (IS_MOBILE(dev_priv)) {
> -		switch (clkcfg) {
> -		case CLKCFG_FSB_400:
> -			return 100000;
> -		case CLKCFG_FSB_533:
> -			return 133333;
> -		case CLKCFG_FSB_667:
> -			return 166667;
> -		case CLKCFG_FSB_800:
> -			return 200000;
> -		case CLKCFG_FSB_1067:
> -			return 266667;
> -		case CLKCFG_FSB_1333:
> -			return 333333;
> -		default:
> -			MISSING_CASE(clkcfg);
> -			return 133333;
> -		}
> -	} else {
> -		switch (clkcfg) {
> -		case CLKCFG_FSB_400_ALT:
> -			return 100000;
> -		case CLKCFG_FSB_533:
> -			return 133333;
> -		case CLKCFG_FSB_667:
> -			return 166667;
> -		case CLKCFG_FSB_800:
> -			return 200000;
> -		case CLKCFG_FSB_1067_ALT:
> -			return 266667;
> -		case CLKCFG_FSB_1333_ALT:
> -			return 333333;
> -		case CLKCFG_FSB_1600_ALT:
> -			return 400000;
> -		default:
> -			return 133333;
> -		}
> -	}
> +	return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4);
>  }
>  
>  /**
> -- 
> 2.39.2

-- 
Ville Syrjälä
Intel