* [PATCH v3 1/3] target/hexagon: move GETPC() calls to top level helpers
2023-10-08 22:09 [PATCH v3 0/3] hexagon: GETPC() fixes, shadowing fixes Brian Cain
@ 2023-10-08 22:09 ` Brian Cain
2023-10-09 6:10 ` Philippe Mathieu-Daudé
2023-10-08 22:09 ` [PATCH v3 2/3] target/hexagon: fix some occurrences of -Wshadow=local Brian Cain
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Brian Cain @ 2023-10-08 22:09 UTC (permalink / raw)
To: qemu-devel
Cc: bcain, armbru, richard.henderson, philmd, peter.maydell,
quic_mathbern, stefanha, ale, anjo, quic_mliebel, ltaylorsimpson
From: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
As docs/devel/loads-stores.rst states:
``GETPC()`` should be used with great care: calling
it in other functions that are *not* the top level
``HELPER(foo)`` will cause unexpected behavior. Instead, the
value of ``GETPC()`` should be read from the helper and passed
if needed to the functions that the helper calls.
Let's fix the GETPC() usage in Hexagon, making sure it's always called
from top level helpers and passed down to the places where it's
needed. There are a few snippets where that is not currently the case:
- probe_store(), which is only called from two helpers, so it's easy to
move GETPC() up.
- mem_load*() functions, which are also called directly from helpers,
but through the MEM_LOAD*() set of macros. Note that this are only
used when compiling with --disable-hexagon-idef-parser.
In this case, we also take this opportunity to simplify the code,
unifying the mem_load*() functions.
- HELPER(probe_hvx_stores), when called from another helper, ends up
using its own GETPC() expansion instead of the top level caller.
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Message-Id: <2c74c3696946edba7cc5b2942cf296a5af532052.1689070412.git.quic_mathbern@quicinc.com>-ne
Reviewed-by: Brian Cain <bcain@quicinc.com>
Signed-off-by: Brian Cain <bcain@quicinc.com>
---
target/hexagon/macros.h | 19 +++++-----
target/hexagon/op_helper.c | 75 +++++++++++++++-----------------------
target/hexagon/op_helper.h | 9 -----
3 files changed, 38 insertions(+), 65 deletions(-)
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index b356d85792..9a51b5709b 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -173,15 +173,6 @@
#define MEM_STORE8(VA, DATA, SLOT) \
MEM_STORE8_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
#else
-#define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD2s(VA) ((int16_t)mem_load2(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD2u(VA) ((uint16_t)mem_load2(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD4s(VA) ((int32_t)mem_load4(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD4u(VA) ((uint32_t)mem_load4(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD8s(VA) ((int64_t)mem_load8(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD8u(VA) ((uint64_t)mem_load8(env, pkt_has_store_s1, slot, VA))
-
#define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT)
#define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT)
#define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT)
@@ -530,8 +521,16 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
#ifdef QEMU_GENERATE
#define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA)
#else
+#define MEM_LOAD1 cpu_ldub_data_ra
+#define MEM_LOAD2 cpu_lduw_data_ra
+#define MEM_LOAD4 cpu_ldl_data_ra
+#define MEM_LOAD8 cpu_ldq_data_ra
+
#define fLOAD(NUM, SIZE, SIGN, EA, DST) \
- DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE##SIGN(EA)
+ do { \
+ check_noshuf(env, pkt_has_store_s1, slot, EA, SIZE, GETPC()); \
+ DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE(env, EA, GETPC()); \
+ } while (0)
#endif
#define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE)
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 12967ac21e..8ca3976a65 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -95,9 +95,8 @@ void HELPER(debug_check_store_width)(CPUHexagonState *env, int slot, int check)
}
}
-void HELPER(commit_store)(CPUHexagonState *env, int slot_num)
+static void commit_store(CPUHexagonState *env, int slot_num, uintptr_t ra)
{
- uintptr_t ra = GETPC();
uint8_t width = env->mem_log_stores[slot_num].width;
target_ulong va = env->mem_log_stores[slot_num].va;
@@ -119,6 +118,12 @@ void HELPER(commit_store)(CPUHexagonState *env, int slot_num)
}
}
+void HELPER(commit_store)(CPUHexagonState *env, int slot_num)
+{
+ uintptr_t ra = GETPC();
+ commit_store(env, slot_num, ra);
+}
+
void HELPER(gather_store)(CPUHexagonState *env, uint32_t addr, int slot)
{
mem_gather_store(env, addr, slot);
@@ -467,13 +472,12 @@ int32_t HELPER(cabacdecbin_pred)(int64_t RssV, int64_t RttV)
}
static void probe_store(CPUHexagonState *env, int slot, int mmu_idx,
- bool is_predicated)
+ bool is_predicated, uintptr_t retaddr)
{
if (!is_predicated || !(env->slot_cancelled & (1 << slot))) {
size1u_t width = env->mem_log_stores[slot].width;
target_ulong va = env->mem_log_stores[slot].va;
- uintptr_t ra = GETPC();
- probe_write(env, va, width, mmu_idx, ra);
+ probe_write(env, va, width, mmu_idx, retaddr);
}
}
@@ -494,12 +498,13 @@ void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState *env, int args)
int mmu_idx = FIELD_EX32(args, PROBE_PKT_SCALAR_STORE_S0, MMU_IDX);
bool is_predicated =
FIELD_EX32(args, PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED);
- probe_store(env, 0, mmu_idx, is_predicated);
+ uintptr_t ra = GETPC();
+ probe_store(env, 0, mmu_idx, is_predicated, ra);
}
-void HELPER(probe_hvx_stores)(CPUHexagonState *env, int mmu_idx)
+static void probe_hvx_stores(CPUHexagonState *env, int mmu_idx,
+ uintptr_t retaddr)
{
- uintptr_t retaddr = GETPC();
int i;
/* Normal (possibly masked) vector store */
@@ -538,6 +543,12 @@ void HELPER(probe_hvx_stores)(CPUHexagonState *env, int mmu_idx)
}
}
+void HELPER(probe_hvx_stores)(CPUHexagonState *env, int mmu_idx)
+{
+ uintptr_t retaddr = GETPC();
+ probe_hvx_stores(env, mmu_idx, retaddr);
+}
+
void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask)
{
bool has_st0 = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0);
@@ -547,18 +558,20 @@ void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask)
bool s0_is_pred = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED);
bool s1_is_pred = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED);
int mmu_idx = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX);
+ uintptr_t ra = GETPC();
if (has_st0) {
- probe_store(env, 0, mmu_idx, s0_is_pred);
+ probe_store(env, 0, mmu_idx, s0_is_pred, ra);
}
if (has_st1) {
- probe_store(env, 1, mmu_idx, s1_is_pred);
+ probe_store(env, 1, mmu_idx, s1_is_pred, ra);
}
if (has_hvx_stores) {
- HELPER(probe_hvx_stores)(env, mmu_idx);
+ probe_hvx_stores(env, mmu_idx, ra);
}
}
+#ifndef CONFIG_HEXAGON_IDEF_PARSER
/*
* mem_noshuf
* Section 5.5 of the Hexagon V67 Programmer's Reference Manual
@@ -567,46 +580,16 @@ void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask)
* wasn't cancelled), we have to do the store first.
*/
static void check_noshuf(CPUHexagonState *env, bool pkt_has_store_s1,
- uint32_t slot, target_ulong vaddr, int size)
+ uint32_t slot, target_ulong vaddr, int size,
+ uintptr_t ra)
{
if (slot == 0 && pkt_has_store_s1 &&
((env->slot_cancelled & (1 << 1)) == 0)) {
- HELPER(probe_noshuf_load)(env, vaddr, size, MMU_USER_IDX);
- HELPER(commit_store)(env, 1);
+ probe_read(env, vaddr, size, MMU_USER_IDX, ra);
+ commit_store(env, 1, ra);
}
}
-
-uint8_t mem_load1(CPUHexagonState *env, bool pkt_has_store_s1,
- uint32_t slot, target_ulong vaddr)
-{
- uintptr_t ra = GETPC();
- check_noshuf(env, pkt_has_store_s1, slot, vaddr, 1);
- return cpu_ldub_data_ra(env, vaddr, ra);
-}
-
-uint16_t mem_load2(CPUHexagonState *env, bool pkt_has_store_s1,
- uint32_t slot, target_ulong vaddr)
-{
- uintptr_t ra = GETPC();
- check_noshuf(env, pkt_has_store_s1, slot, vaddr, 2);
- return cpu_lduw_data_ra(env, vaddr, ra);
-}
-
-uint32_t mem_load4(CPUHexagonState *env, bool pkt_has_store_s1,
- uint32_t slot, target_ulong vaddr)
-{
- uintptr_t ra = GETPC();
- check_noshuf(env, pkt_has_store_s1, slot, vaddr, 4);
- return cpu_ldl_data_ra(env, vaddr, ra);
-}
-
-uint64_t mem_load8(CPUHexagonState *env, bool pkt_has_store_s1,
- uint32_t slot, target_ulong vaddr)
-{
- uintptr_t ra = GETPC();
- check_noshuf(env, pkt_has_store_s1, slot, vaddr, 8);
- return cpu_ldq_data_ra(env, vaddr, ra);
-}
+#endif
/* Floating point */
float64 HELPER(conv_sf2df)(CPUHexagonState *env, float32 RsV)
diff --git a/target/hexagon/op_helper.h b/target/hexagon/op_helper.h
index 8f3764d15e..66119cf3d4 100644
--- a/target/hexagon/op_helper.h
+++ b/target/hexagon/op_helper.h
@@ -19,15 +19,6 @@
#define HEXAGON_OP_HELPER_H
/* Misc functions */
-uint8_t mem_load1(CPUHexagonState *env, bool pkt_has_store_s1,
- uint32_t slot, target_ulong vaddr);
-uint16_t mem_load2(CPUHexagonState *env, bool pkt_has_store_s1,
- uint32_t slot, target_ulong vaddr);
-uint32_t mem_load4(CPUHexagonState *env, bool pkt_has_store_s1,
- uint32_t slot, target_ulong vaddr);
-uint64_t mem_load8(CPUHexagonState *env, bool pkt_has_store_s1,
- uint32_t slot, target_ulong vaddr);
-
void log_store64(CPUHexagonState *env, target_ulong addr,
int64_t val, int width, int slot);
void log_store32(CPUHexagonState *env, target_ulong addr,
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v3 1/3] target/hexagon: move GETPC() calls to top level helpers
2023-10-08 22:09 ` [PATCH v3 1/3] target/hexagon: move GETPC() calls to top level helpers Brian Cain
@ 2023-10-09 6:10 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 7+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-09 6:10 UTC (permalink / raw)
To: Brian Cain, qemu-devel
Cc: armbru, richard.henderson, peter.maydell, quic_mathbern, stefanha,
ale, anjo, quic_mliebel, ltaylorsimpson
On 9/10/23 00:09, Brian Cain wrote:
> From: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
>
> As docs/devel/loads-stores.rst states:
>
> ``GETPC()`` should be used with great care: calling
> it in other functions that are *not* the top level
> ``HELPER(foo)`` will cause unexpected behavior. Instead, the
> value of ``GETPC()`` should be read from the helper and passed
> if needed to the functions that the helper calls.
>
> Let's fix the GETPC() usage in Hexagon, making sure it's always called
> from top level helpers and passed down to the places where it's
> needed. There are a few snippets where that is not currently the case:
>
> - probe_store(), which is only called from two helpers, so it's easy to
> move GETPC() up.
>
> - mem_load*() functions, which are also called directly from helpers,
> but through the MEM_LOAD*() set of macros. Note that this are only
> used when compiling with --disable-hexagon-idef-parser.
>
> In this case, we also take this opportunity to simplify the code,
> unifying the mem_load*() functions.
>
> - HELPER(probe_hvx_stores), when called from another helper, ends up
> using its own GETPC() expansion instead of the top level caller.
>
> Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
> Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
> Message-Id: <2c74c3696946edba7cc5b2942cf296a5af532052.1689070412.git.quic_mathbern@quicinc.com>-ne
Again suspicious '-ne' trailing.
> Reviewed-by: Brian Cain <bcain@quicinc.com>
> Signed-off-by: Brian Cain <bcain@quicinc.com>
> ---
> target/hexagon/macros.h | 19 +++++-----
> target/hexagon/op_helper.c | 75 +++++++++++++++-----------------------
> target/hexagon/op_helper.h | 9 -----
> 3 files changed, 38 insertions(+), 65 deletions(-)
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3 2/3] target/hexagon: fix some occurrences of -Wshadow=local
2023-10-08 22:09 [PATCH v3 0/3] hexagon: GETPC() fixes, shadowing fixes Brian Cain
2023-10-08 22:09 ` [PATCH v3 1/3] target/hexagon: move GETPC() calls to top level helpers Brian Cain
@ 2023-10-08 22:09 ` Brian Cain
2023-10-09 6:12 ` Philippe Mathieu-Daudé
2023-10-08 22:09 ` [PATCH v3 3/3] target/hexagon: avoid shadowing globals Brian Cain
2023-10-09 6:18 ` [PATCH v3 0/3] hexagon: GETPC() fixes, shadowing fixes Markus Armbruster
3 siblings, 1 reply; 7+ messages in thread
From: Brian Cain @ 2023-10-08 22:09 UTC (permalink / raw)
To: qemu-devel
Cc: bcain, armbru, richard.henderson, philmd, peter.maydell,
quic_mathbern, stefanha, ale, anjo, quic_mliebel, ltaylorsimpson
Of the changes in this commit, the changes in `HELPER(commit_hvx_stores)()`
are less obvious. They are required because of some macro invocations like
SCATTER_OP_WRITE_TO_MEM().
e.g.:
In file included from ../target/hexagon/op_helper.c:31:
../target/hexagon/mmvec/macros.h:205:18: error: declaration of ‘i’ shadows a previous local [-Werror=shadow=compatible-local]
205 | for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \
| ^
../target/hexagon/op_helper.c:157:17: note: in expansion of macro ‘SCATTER_OP_WRITE_TO_MEM’
157 | SCATTER_OP_WRITE_TO_MEM(uint16_t);
| ^~~~~~~~~~~~~~~~~~~~~~~
../target/hexagon/op_helper.c:135:9: note: shadowed declaration is here
135 | int i;
| ^
In file included from ../target/hexagon/op_helper.c:31:
../target/hexagon/mmvec/macros.h:204:19: error: declaration of ‘ra’ shadows a previous local [-Werror=shadow=compatible-local]
204 | uintptr_t ra = GETPC(); \
| ^~
../target/hexagon/op_helper.c:160:17: note: in expansion of macro ‘SCATTER_OP_WRITE_TO_MEM’
160 | SCATTER_OP_WRITE_TO_MEM(uint32_t);
| ^~~~~~~~~~~~~~~~~~~~~~~
../target/hexagon/op_helper.c:134:15: note: shadowed declaration is here
134 | uintptr_t ra = GETPC();
| ^~
Reviewed-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Signed-off-by: Brian Cain <bcain@quicinc.com>
---
target/hexagon/imported/alu.idef | 6 +++---
target/hexagon/mmvec/macros.h | 2 +-
target/hexagon/op_helper.c | 9 +++------
target/hexagon/translate.c | 10 +++++-----
4 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/target/hexagon/imported/alu.idef b/target/hexagon/imported/alu.idef
index 12d2aac5d4..b855676989 100644
--- a/target/hexagon/imported/alu.idef
+++ b/target/hexagon/imported/alu.idef
@@ -1142,9 +1142,9 @@ Q6INSN(A4_cround_rr,"Rd32=cround(Rs32,Rt32)",ATTRIBS(),"Convergent Round", {RdV
tmp128 = fSHIFTR128(tmp128, SHIFT);\
DST = fCAST16S_8S(tmp128);\
} else {\
- size16s_t rndbit_128 = fCAST8S_16S((1LL << (SHIFT - 1))); \
- size16s_t src_128 = fCAST8S_16S(SRC); \
- size16s_t tmp128 = fADD128(src_128, rndbit_128);\
+ rndbit_128 = fCAST8S_16S((1LL << (SHIFT - 1))); \
+ src_128 = fCAST8S_16S(SRC); \
+ tmp128 = fADD128(src_128, rndbit_128);\
tmp128 = fSHIFTR128(tmp128, SHIFT);\
DST = fCAST16S_8S(tmp128);\
}
diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h
index a655634fd1..1ceb9453ee 100644
--- a/target/hexagon/mmvec/macros.h
+++ b/target/hexagon/mmvec/macros.h
@@ -201,7 +201,7 @@
} while (0)
#define SCATTER_OP_WRITE_TO_MEM(TYPE) \
do { \
- uintptr_t ra = GETPC(); \
+ ra = GETPC(); \
for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \
if (test_bit(i, env->vtcm_log.mask)) { \
TYPE dst = 0; \
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 8ca3976a65..da10ac5847 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -132,10 +132,9 @@ void HELPER(gather_store)(CPUHexagonState *env, uint32_t addr, int slot)
void HELPER(commit_hvx_stores)(CPUHexagonState *env)
{
uintptr_t ra = GETPC();
- int i;
/* Normal (possibly masked) vector store */
- for (i = 0; i < VSTORES_MAX; i++) {
+ for (int i = 0; i < VSTORES_MAX; i++) {
if (env->vstore_pending[i]) {
env->vstore_pending[i] = 0;
target_ulong va = env->vstore[i].va;
@@ -162,7 +161,7 @@ void HELPER(commit_hvx_stores)(CPUHexagonState *env)
g_assert_not_reached();
}
} else {
- for (i = 0; i < sizeof(MMVector); i++) {
+ for (int i = 0; i < sizeof(MMVector); i++) {
if (test_bit(i, env->vtcm_log.mask)) {
cpu_stb_data_ra(env, env->vtcm_log.va[i],
env->vtcm_log.data.ub[i], ra);
@@ -505,10 +504,8 @@ void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState *env, int args)
static void probe_hvx_stores(CPUHexagonState *env, int mmu_idx,
uintptr_t retaddr)
{
- int i;
-
/* Normal (possibly masked) vector store */
- for (i = 0; i < VSTORES_MAX; i++) {
+ for (int i = 0; i < VSTORES_MAX; i++) {
if (env->vstore_pending[i]) {
target_ulong va = env->vstore[i].va;
int size = env->vstore[i].size;
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 663b7bbc3a..666c061180 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -553,7 +553,7 @@ static void gen_start_packet(DisasContext *ctx)
/* Preload the predicated registers into get_result_gpr(ctx, i) */
if (ctx->need_commit &&
!bitmap_empty(ctx->predicated_regs, TOTAL_PER_THREAD_REGS)) {
- int i = find_first_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS);
+ i = find_first_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS);
while (i < TOTAL_PER_THREAD_REGS) {
tcg_gen_mov_tl(get_result_gpr(ctx, i), hex_gpr[i]);
i = find_next_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS,
@@ -566,7 +566,7 @@ static void gen_start_packet(DisasContext *ctx)
* Only endloop instructions conditionally write to pred registers
*/
if (ctx->need_commit && pkt->pkt_has_endloop) {
- for (int i = 0; i < ctx->preg_log_idx; i++) {
+ for (i = 0; i < ctx->preg_log_idx; i++) {
int pred_num = ctx->preg_log[i];
ctx->new_pred_value[pred_num] = tcg_temp_new();
tcg_gen_mov_tl(ctx->new_pred_value[pred_num], hex_pred[pred_num]);
@@ -575,7 +575,7 @@ static void gen_start_packet(DisasContext *ctx)
/* Preload the predicated HVX registers into future_VRegs and tmp_VRegs */
if (!bitmap_empty(ctx->predicated_future_vregs, NUM_VREGS)) {
- int i = find_first_bit(ctx->predicated_future_vregs, NUM_VREGS);
+ i = find_first_bit(ctx->predicated_future_vregs, NUM_VREGS);
while (i < NUM_VREGS) {
const intptr_t VdV_off =
ctx_future_vreg_off(ctx, i, 1, true);
@@ -588,7 +588,7 @@ static void gen_start_packet(DisasContext *ctx)
}
}
if (!bitmap_empty(ctx->predicated_tmp_vregs, NUM_VREGS)) {
- int i = find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS);
+ i = find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS);
while (i < NUM_VREGS) {
const intptr_t VdV_off =
ctx_tmp_vreg_off(ctx, i, 1, true);
@@ -1228,7 +1228,7 @@ void hexagon_translate_init(void)
offsetof(CPUHexagonState, mem_log_stores[i].data64),
store_val64_names[i]);
}
- for (int i = 0; i < VSTORES_MAX; i++) {
+ for (i = 0; i < VSTORES_MAX; i++) {
snprintf(vstore_addr_names[i], NAME_LEN, "vstore_addr_%d", i);
hex_vstore_addr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, vstore[i].va),
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v3 2/3] target/hexagon: fix some occurrences of -Wshadow=local
2023-10-08 22:09 ` [PATCH v3 2/3] target/hexagon: fix some occurrences of -Wshadow=local Brian Cain
@ 2023-10-09 6:12 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 7+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-09 6:12 UTC (permalink / raw)
To: Brian Cain, qemu-devel
Cc: armbru, richard.henderson, peter.maydell, quic_mathbern, stefanha,
ale, anjo, quic_mliebel, ltaylorsimpson
On 9/10/23 00:09, Brian Cain wrote:
> Of the changes in this commit, the changes in `HELPER(commit_hvx_stores)()`
> are less obvious. They are required because of some macro invocations like
> SCATTER_OP_WRITE_TO_MEM().
>
> e.g.:
>
> In file included from ../target/hexagon/op_helper.c:31:
> ../target/hexagon/mmvec/macros.h:205:18: error: declaration of ‘i’ shadows a previous local [-Werror=shadow=compatible-local]
> 205 | for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \
> | ^
> ../target/hexagon/op_helper.c:157:17: note: in expansion of macro ‘SCATTER_OP_WRITE_TO_MEM’
> 157 | SCATTER_OP_WRITE_TO_MEM(uint16_t);
> | ^~~~~~~~~~~~~~~~~~~~~~~
> ../target/hexagon/op_helper.c:135:9: note: shadowed declaration is here
> 135 | int i;
> | ^
> In file included from ../target/hexagon/op_helper.c:31:
> ../target/hexagon/mmvec/macros.h:204:19: error: declaration of ‘ra’ shadows a previous local [-Werror=shadow=compatible-local]
> 204 | uintptr_t ra = GETPC(); \
> | ^~
> ../target/hexagon/op_helper.c:160:17: note: in expansion of macro ‘SCATTER_OP_WRITE_TO_MEM’
> 160 | SCATTER_OP_WRITE_TO_MEM(uint32_t);
> | ^~~~~~~~~~~~~~~~~~~~~~~
> ../target/hexagon/op_helper.c:134:15: note: shadowed declaration is here
> 134 | uintptr_t ra = GETPC();
> | ^~
>
> Reviewed-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
> Signed-off-by: Brian Cain <bcain@quicinc.com>
> ---
> target/hexagon/imported/alu.idef | 6 +++---
> target/hexagon/mmvec/macros.h | 2 +-
> target/hexagon/op_helper.c | 9 +++------
> target/hexagon/translate.c | 10 +++++-----
> 4 files changed, 12 insertions(+), 15 deletions(-)
No change since v2:
https://lore.kernel.org/qemu-devel/45707b6e-6835-421f-e89b-6c1b0c50e35f@linaro.org/
Please carry reviewer tags so we don't re-review patches.
Again,
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3 3/3] target/hexagon: avoid shadowing globals
2023-10-08 22:09 [PATCH v3 0/3] hexagon: GETPC() fixes, shadowing fixes Brian Cain
2023-10-08 22:09 ` [PATCH v3 1/3] target/hexagon: move GETPC() calls to top level helpers Brian Cain
2023-10-08 22:09 ` [PATCH v3 2/3] target/hexagon: fix some occurrences of -Wshadow=local Brian Cain
@ 2023-10-08 22:09 ` Brian Cain
2023-10-09 6:18 ` [PATCH v3 0/3] hexagon: GETPC() fixes, shadowing fixes Markus Armbruster
3 siblings, 0 replies; 7+ messages in thread
From: Brian Cain @ 2023-10-08 22:09 UTC (permalink / raw)
To: qemu-devel
Cc: bcain, armbru, richard.henderson, philmd, peter.maydell,
quic_mathbern, stefanha, ale, anjo, quic_mliebel, ltaylorsimpson
The typedef `vaddr` is shadowed by `vaddr` identifiers, so we rename the
identifiers to avoid shadowing the type name.
The global `tcg_env` is shadowed by local `tcg_env` arguments, so we
rename the function arguments to avoid shadowing the global.
Signed-off-by: Brian Cain <bcain@quicinc.com>
---
target/hexagon/genptr.c | 56 ++++++++++++-------------
target/hexagon/genptr.h | 18 ++++----
target/hexagon/mmvec/system_ext_mmvec.c | 4 +-
target/hexagon/mmvec/system_ext_mmvec.h | 2 +-
target/hexagon/op_helper.c | 4 +-
5 files changed, 42 insertions(+), 42 deletions(-)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index dbae6c570a..fa577e05dc 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -334,28 +334,28 @@ void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
tcg_gen_deposit_i64(result, result, src64, N * 8, 8);
}
-static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index)
+static inline void gen_load_locked4u(TCGv dest, TCGv v_addr, int mem_index)
{
- tcg_gen_qemu_ld_tl(dest, vaddr, mem_index, MO_TEUL);
- tcg_gen_mov_tl(hex_llsc_addr, vaddr);
+ tcg_gen_qemu_ld_tl(dest, v_addr, mem_index, MO_TEUL);
+ tcg_gen_mov_tl(hex_llsc_addr, v_addr);
tcg_gen_mov_tl(hex_llsc_val, dest);
}
-static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_index)
+static inline void gen_load_locked8u(TCGv_i64 dest, TCGv v_addr, int mem_index)
{
- tcg_gen_qemu_ld_i64(dest, vaddr, mem_index, MO_TEUQ);
- tcg_gen_mov_tl(hex_llsc_addr, vaddr);
+ tcg_gen_qemu_ld_i64(dest, v_addr, mem_index, MO_TEUQ);
+ tcg_gen_mov_tl(hex_llsc_addr, v_addr);
tcg_gen_mov_i64(hex_llsc_val_i64, dest);
}
static inline void gen_store_conditional4(DisasContext *ctx,
- TCGv pred, TCGv vaddr, TCGv src)
+ TCGv pred, TCGv v_addr, TCGv src)
{
TCGLabel *fail = gen_new_label();
TCGLabel *done = gen_new_label();
TCGv one, zero, tmp;
- tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail);
+ tcg_gen_brcond_tl(TCG_COND_NE, v_addr, hex_llsc_addr, fail);
one = tcg_constant_tl(0xff);
zero = tcg_constant_tl(0);
@@ -374,13 +374,13 @@ static inline void gen_store_conditional4(DisasContext *ctx,
}
static inline void gen_store_conditional8(DisasContext *ctx,
- TCGv pred, TCGv vaddr, TCGv_i64 src)
+ TCGv pred, TCGv v_addr, TCGv_i64 src)
{
TCGLabel *fail = gen_new_label();
TCGLabel *done = gen_new_label();
TCGv_i64 one, zero, tmp;
- tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail);
+ tcg_gen_brcond_tl(TCG_COND_NE, v_addr, hex_llsc_addr, fail);
one = tcg_constant_i64(0xff);
zero = tcg_constant_i64(0);
@@ -407,57 +407,57 @@ static TCGv gen_slotval(DisasContext *ctx)
}
#endif
-void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
+void gen_store32(TCGv v_addr, TCGv src, int width, uint32_t slot)
{
- tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
+ tcg_gen_mov_tl(hex_store_addr[slot], v_addr);
tcg_gen_movi_tl(hex_store_width[slot], width);
tcg_gen_mov_tl(hex_store_val32[slot], src);
}
-void gen_store1(TCGv_env tcg_env, TCGv vaddr, TCGv src, uint32_t slot)
+void gen_store1(TCGv_env tcg_env_, TCGv v_addr, TCGv src, uint32_t slot)
{
- gen_store32(vaddr, src, 1, slot);
+ gen_store32(v_addr, src, 1, slot);
}
-void gen_store1i(TCGv_env tcg_env, TCGv vaddr, int32_t src, uint32_t slot)
+void gen_store1i(TCGv_env tcg_env_, TCGv v_addr, int32_t src, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
- gen_store1(tcg_env, vaddr, tmp, slot);
+ gen_store1(tcg_env_, v_addr, tmp, slot);
}
-void gen_store2(TCGv_env tcg_env, TCGv vaddr, TCGv src, uint32_t slot)
+void gen_store2(TCGv_env tcg_env_, TCGv v_addr, TCGv src, uint32_t slot)
{
- gen_store32(vaddr, src, 2, slot);
+ gen_store32(v_addr, src, 2, slot);
}
-void gen_store2i(TCGv_env tcg_env, TCGv vaddr, int32_t src, uint32_t slot)
+void gen_store2i(TCGv_env tcg_env_, TCGv v_addr, int32_t src, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
- gen_store2(tcg_env, vaddr, tmp, slot);
+ gen_store2(tcg_env_, v_addr, tmp, slot);
}
-void gen_store4(TCGv_env tcg_env, TCGv vaddr, TCGv src, uint32_t slot)
+void gen_store4(TCGv_env tcg_env_, TCGv v_addr, TCGv src, uint32_t slot)
{
- gen_store32(vaddr, src, 4, slot);
+ gen_store32(v_addr, src, 4, slot);
}
-void gen_store4i(TCGv_env tcg_env, TCGv vaddr, int32_t src, uint32_t slot)
+void gen_store4i(TCGv_env tcg_env_, TCGv v_addr, int32_t src, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
- gen_store4(tcg_env, vaddr, tmp, slot);
+ gen_store4(tcg_env_, v_addr, tmp, slot);
}
-void gen_store8(TCGv_env tcg_env, TCGv vaddr, TCGv_i64 src, uint32_t slot)
+void gen_store8(TCGv_env tcg_env_, TCGv v_addr, TCGv_i64 src, uint32_t slot)
{
- tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
+ tcg_gen_mov_tl(hex_store_addr[slot], v_addr);
tcg_gen_movi_tl(hex_store_width[slot], 8);
tcg_gen_mov_i64(hex_store_val64[slot], src);
}
-void gen_store8i(TCGv_env tcg_env, TCGv vaddr, int64_t src, uint32_t slot)
+void gen_store8i(TCGv_env tcg_env_, TCGv v_addr, int64_t src, uint32_t slot)
{
TCGv_i64 tmp = tcg_constant_i64(src);
- gen_store8(tcg_env, vaddr, tmp, slot);
+ gen_store8(tcg_env_, v_addr, tmp, slot);
}
TCGv gen_8bitsof(TCGv result, TCGv value)
diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h
index a4b43c2910..4a4d3e0be3 100644
--- a/target/hexagon/genptr.h
+++ b/target/hexagon/genptr.h
@@ -24,15 +24,15 @@
extern const SemanticInsn opcode_genptr[];
-void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot);
-void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot);
-void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot);
-void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot);
-void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, uint32_t slot);
-void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot);
-void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot);
-void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot);
-void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot);
+void gen_store32(TCGv v_addr, TCGv src, int width, uint32_t slot);
+void gen_store1(TCGv_env tcg_env_, TCGv v_addr, TCGv src, uint32_t slot);
+void gen_store2(TCGv_env tcg_env_, TCGv v_addr, TCGv src, uint32_t slot);
+void gen_store4(TCGv_env tcg_env_, TCGv v_addr, TCGv src, uint32_t slot);
+void gen_store8(TCGv_env tcg_env_, TCGv v_addr, TCGv_i64 src, uint32_t slot);
+void gen_store1i(TCGv_env tcg_env_, TCGv v_addr, int32_t src, uint32_t slot);
+void gen_store2i(TCGv_env tcg_env_, TCGv v_addr, int32_t src, uint32_t slot);
+void gen_store4i(TCGv_env tcg_env_, TCGv v_addr, int32_t src, uint32_t slot);
+void gen_store8i(TCGv_env tcg_env_, TCGv v_addr, int64_t src, uint32_t slot);
TCGv gen_read_reg(TCGv result, int num);
TCGv gen_read_preg(TCGv pred, uint8_t num);
TCGv get_result_gpr(DisasContext *ctx, int rnum);
diff --git a/target/hexagon/mmvec/system_ext_mmvec.c b/target/hexagon/mmvec/system_ext_mmvec.c
index 8351f2cc01..c339eee38b 100644
--- a/target/hexagon/mmvec/system_ext_mmvec.c
+++ b/target/hexagon/mmvec/system_ext_mmvec.c
@@ -19,12 +19,12 @@
#include "cpu.h"
#include "mmvec/system_ext_mmvec.h"
-void mem_gather_store(CPUHexagonState *env, target_ulong vaddr, int slot)
+void mem_gather_store(CPUHexagonState *env, target_ulong v_addr, int slot)
{
size_t size = sizeof(MMVector);
env->vstore_pending[slot] = 1;
- env->vstore[slot].va = vaddr;
+ env->vstore[slot].va = v_addr;
env->vstore[slot].size = size;
memcpy(&env->vstore[slot].data.ub[0], &env->tmp_VRegs[0], size);
diff --git a/target/hexagon/mmvec/system_ext_mmvec.h b/target/hexagon/mmvec/system_ext_mmvec.h
index bcefbffdf2..6a711fcb69 100644
--- a/target/hexagon/mmvec/system_ext_mmvec.h
+++ b/target/hexagon/mmvec/system_ext_mmvec.h
@@ -18,7 +18,7 @@
#ifndef HEXAGON_SYSTEM_EXT_MMVEC_H
#define HEXAGON_SYSTEM_EXT_MMVEC_H
-void mem_gather_store(CPUHexagonState *env, target_ulong vaddr, int slot);
+void mem_gather_store(CPUHexagonState *env, target_ulong v_addr, int slot);
void mem_vector_scatter_init(CPUHexagonState *env);
void mem_vector_gather_init(CPUHexagonState *env);
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index da10ac5847..aeafd78887 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -577,12 +577,12 @@ void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask)
* wasn't cancelled), we have to do the store first.
*/
static void check_noshuf(CPUHexagonState *env, bool pkt_has_store_s1,
- uint32_t slot, target_ulong vaddr, int size,
+ uint32_t slot, target_ulong v_addr, int size,
uintptr_t ra)
{
if (slot == 0 && pkt_has_store_s1 &&
((env->slot_cancelled & (1 << 1)) == 0)) {
- probe_read(env, vaddr, size, MMU_USER_IDX, ra);
+ probe_read(env, v_addr, size, MMU_USER_IDX, ra);
commit_store(env, 1, ra);
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v3 0/3] hexagon: GETPC() fixes, shadowing fixes
2023-10-08 22:09 [PATCH v3 0/3] hexagon: GETPC() fixes, shadowing fixes Brian Cain
` (2 preceding siblings ...)
2023-10-08 22:09 ` [PATCH v3 3/3] target/hexagon: avoid shadowing globals Brian Cain
@ 2023-10-09 6:18 ` Markus Armbruster
3 siblings, 0 replies; 7+ messages in thread
From: Markus Armbruster @ 2023-10-09 6:18 UTC (permalink / raw)
To: Brian Cain
Cc: qemu-devel, armbru, richard.henderson, philmd, peter.maydell,
quic_mathbern, stefanha, ale, anjo, quic_mliebel, ltaylorsimpson
I applied this series to my shadow-next in my public Git repository at
https://repo.or.cz/qemu/armbru.git. I don't intend to include it in
pull requests, because it does more than just fix -Wshadow issues.
Don't think that'll be a problem.
Thanks!
^ permalink raw reply [flat|nested] 7+ messages in thread