From: Marc Zyngier <maz@kernel.org>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Lokesh Vutla <lokeshvutla@ti.com>
Subject: Re: [PATCH 5/6] PCI: keystone: Add PCI legacy interrupt support for AM654
Date: Fri, 02 Apr 2021 12:11:24 +0100 [thread overview]
Message-ID: <87blaxeyar.wl-maz@kernel.org> (raw)
In-Reply-To: <20210325090026.8843-6-kishon@ti.com>
On Thu, 25 Mar 2021 09:00:25 +0000,
Kishon Vijay Abraham I <kishon@ti.com> wrote:
>
> Add PCI legacy interrupt support for AM654. AM654 has a single HW
> interrupt line for all the four legacy interrupts INTA/INTB/INTC/INTD.
> The HW interrupt line connected to GIC is a pulse interrupt whereas
> the legacy interrupts by definition is level interrupt. In order to
> provide level interrupt functionality to edge interrupt line, PCIe
> in AM654 has provided IRQ_EOI register. When the SW writes to IRQ_EOI
> register after handling the interrupt, the IP checks the state of
> legacy interrupt and re-triggers pulse interrupt invoking the handler
> again.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/pci/controller/dwc/pci-keystone.c | 87 +++++++++++++++++++++--
> 1 file changed, 82 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
> index dfa9a7fcf9b7..84a25207d0d3 100644
> --- a/drivers/pci/controller/dwc/pci-keystone.c
> +++ b/drivers/pci/controller/dwc/pci-keystone.c
> @@ -118,6 +118,7 @@ struct keystone_pcie {
> /* PCI Device ID */
> u32 device_id;
> struct device_node *legacy_intc_np;
> + struct irq_domain *legacy_irq_domain;
>
> int msi_host_irq;
> int num_lanes;
> @@ -289,6 +290,29 @@ static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie)
> return IRQ_HANDLED;
> }
>
> +static void ks_pcie_am654_legacy_irq_handler(struct irq_desc *desc)
> +{
> + struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
> + struct irq_chip *chip = irq_desc_get_chip(desc);
> + int virq, i;
> + u32 reg;
> +
> + chained_irq_enter(chip, desc);
> +
> + for (i = 0; i < PCI_NUM_INTX; i++) {
> + reg = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(i));
> + if (!(reg & INTx_EN))
> + continue;
> +
> + virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, i);
> + generic_handle_irq(virq);
I'm on my way to kill irq_linear_revmap(), so I'd rather you didn't
add more instances. Consider using irq_find_mapping() instead.
> + ks_pcie_app_writel(ks_pcie, IRQ_STATUS(i), INTx_EN);
> + ks_pcie_app_writel(ks_pcie, IRQ_EOI, i);
What are these writes for? The first one feels like an Ack, and the
second one has EOI written over it.
If that's what they are, llease move these to a proper irq_chip
structure and use the appropriate flow handler, instead of
dummy_irq_chip and handle_simple_irq.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Lokesh Vutla <lokeshvutla@ti.com>
Subject: Re: [PATCH 5/6] PCI: keystone: Add PCI legacy interrupt support for AM654
Date: Fri, 02 Apr 2021 12:11:24 +0100 [thread overview]
Message-ID: <87blaxeyar.wl-maz@kernel.org> (raw)
In-Reply-To: <20210325090026.8843-6-kishon@ti.com>
On Thu, 25 Mar 2021 09:00:25 +0000,
Kishon Vijay Abraham I <kishon@ti.com> wrote:
>
> Add PCI legacy interrupt support for AM654. AM654 has a single HW
> interrupt line for all the four legacy interrupts INTA/INTB/INTC/INTD.
> The HW interrupt line connected to GIC is a pulse interrupt whereas
> the legacy interrupts by definition is level interrupt. In order to
> provide level interrupt functionality to edge interrupt line, PCIe
> in AM654 has provided IRQ_EOI register. When the SW writes to IRQ_EOI
> register after handling the interrupt, the IP checks the state of
> legacy interrupt and re-triggers pulse interrupt invoking the handler
> again.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/pci/controller/dwc/pci-keystone.c | 87 +++++++++++++++++++++--
> 1 file changed, 82 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
> index dfa9a7fcf9b7..84a25207d0d3 100644
> --- a/drivers/pci/controller/dwc/pci-keystone.c
> +++ b/drivers/pci/controller/dwc/pci-keystone.c
> @@ -118,6 +118,7 @@ struct keystone_pcie {
> /* PCI Device ID */
> u32 device_id;
> struct device_node *legacy_intc_np;
> + struct irq_domain *legacy_irq_domain;
>
> int msi_host_irq;
> int num_lanes;
> @@ -289,6 +290,29 @@ static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie)
> return IRQ_HANDLED;
> }
>
> +static void ks_pcie_am654_legacy_irq_handler(struct irq_desc *desc)
> +{
> + struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
> + struct irq_chip *chip = irq_desc_get_chip(desc);
> + int virq, i;
> + u32 reg;
> +
> + chained_irq_enter(chip, desc);
> +
> + for (i = 0; i < PCI_NUM_INTX; i++) {
> + reg = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(i));
> + if (!(reg & INTx_EN))
> + continue;
> +
> + virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, i);
> + generic_handle_irq(virq);
I'm on my way to kill irq_linear_revmap(), so I'd rather you didn't
add more instances. Consider using irq_find_mapping() instead.
> + ks_pcie_app_writel(ks_pcie, IRQ_STATUS(i), INTx_EN);
> + ks_pcie_app_writel(ks_pcie, IRQ_EOI, i);
What are these writes for? The first one feels like an Ack, and the
second one has EOI written over it.
If that's what they are, llease move these to a proper irq_chip
structure and use the appropriate flow handler, instead of
dummy_irq_chip and handle_simple_irq.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-04-02 11:11 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-25 9:00 [PATCH 0/6] PCI: Add legacy interrupt support in Keystone Kishon Vijay Abraham I
2021-03-25 9:00 ` Kishon Vijay Abraham I
2021-03-25 9:00 ` [PATCH 1/6] dt-bindings: PCI: ti,am65: Add PCIe host mode dt-bindings for TI's AM65 SoC Kishon Vijay Abraham I
2021-03-25 9:00 ` [PATCH 1/6] dt-bindings: PCI: ti, am65: " Kishon Vijay Abraham I
2021-03-25 16:56 ` Rob Herring
2021-03-25 16:56 ` Rob Herring
2021-03-25 23:38 ` [PATCH 1/6] dt-bindings: PCI: ti,am65: " Rob Herring
2021-03-25 23:38 ` Rob Herring
2021-03-30 9:29 ` Kishon Vijay Abraham I
2021-03-30 9:29 ` Kishon Vijay Abraham I
2021-04-20 13:13 ` Rob Herring
2021-04-20 13:13 ` Rob Herring
2021-03-25 9:00 ` [PATCH 2/6] dt-bindings: PCI: ti,am65: Add PCIe endpoint " Kishon Vijay Abraham I
2021-03-25 9:00 ` [PATCH 2/6] dt-bindings: PCI: ti, am65: " Kishon Vijay Abraham I
2021-03-25 16:56 ` Rob Herring
2021-03-25 16:56 ` Rob Herring
2021-03-25 9:00 ` [PATCH 3/6] irqdomain: Export of_phandle_args_to_fwspec() Kishon Vijay Abraham I
2021-03-25 9:00 ` Kishon Vijay Abraham I
2021-03-25 9:00 ` [PATCH 4/6] PCI: keystone: Convert to using hierarchy domain for legacy interrupts Kishon Vijay Abraham I
2021-03-25 9:00 ` Kishon Vijay Abraham I
2021-03-26 6:58 ` Krzysztof Wilczyński
2021-03-26 6:58 ` Krzysztof Wilczyński
2021-03-25 9:00 ` [PATCH 5/6] PCI: keystone: Add PCI legacy interrupt support for AM654 Kishon Vijay Abraham I
2021-03-25 9:00 ` Kishon Vijay Abraham I
2021-03-26 7:14 ` Krzysztof Wilczyński
2021-03-26 7:14 ` Krzysztof Wilczyński
2021-04-02 11:11 ` Marc Zyngier [this message]
2021-04-02 11:11 ` Marc Zyngier
2021-03-25 9:00 ` [PATCH 6/6] PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0) Kishon Vijay Abraham I
2021-03-25 9:00 ` Kishon Vijay Abraham I
2021-03-26 7:19 ` Krzysztof Wilczyński
2021-03-26 7:19 ` Krzysztof Wilczyński
2021-05-17 13:15 ` [PATCH 0/6] PCI: Add legacy interrupt support in Keystone Christian Gmeiner
2021-05-17 13:15 ` Christian Gmeiner
2021-05-17 13:21 ` Kishon Vijay Abraham I
2021-05-17 13:21 ` Kishon Vijay Abraham I
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87blaxeyar.wl-maz@kernel.org \
--to=maz@kernel.org \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=kishon@ti.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lokeshvutla@ti.com \
--cc=lorenzo.pieralisi@arm.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.