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From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH v7] drm/i915: Enable second dbuf slice for ICL and TGL
Date: Mon, 18 Nov 2019 17:26:38 +0200	[thread overview]
Message-ID: <87blt9yzm9.fsf@intel.com> (raw)
In-Reply-To: <5ede07a6173da5f9d7bc63863c11f482f46ef9ae.camel@intel.com>

On Mon, 18 Nov 2019, "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com> wrote:
> I'm fine with fixing checkpatch and sparse failures(even though
> most of those are about 80 line width limitation violation or line
> continuations, which tbh are anyway quite common in our code). 

Please look through the warnings again. Only the COMMIT_LOG_LONG_LINE
one is to be ignored in this case. There's nothing else about 80
character line width. Line continuation is about using backslash to
continue to another line while that's only needed in macros.

Please let's just try to leave the code in neater shape after our
changes. We have these steps in CI so people wouldn't have to nitpick
about them separately.

> One thing I don't get is why this should cause any regression, as both
> BAT and IGT are green here for two runs in a row.
>
> What is the point of having a CI then.

Are you saying there's no point in having CI if it can't catch
absolutely everything?

Our CI is like every other CI everywhere; imperfect. Both in terms of
hardware and software coverage. We would have no bugs reported by the
community otherwise.


BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Lisovskiy\, Stanislav" <stanislav.lisovskiy@intel.com>,
	"intel-gfx\@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v7] drm/i915: Enable second dbuf slice for ICL and TGL
Date: Mon, 18 Nov 2019 17:26:38 +0200	[thread overview]
Message-ID: <87blt9yzm9.fsf@intel.com> (raw)
Message-ID: <20191118152638.lfWTYd5A8Kg0XdLg2ZRqIreI89QNZB2j3BcGOMYk0do@z> (raw)
In-Reply-To: <5ede07a6173da5f9d7bc63863c11f482f46ef9ae.camel@intel.com>

On Mon, 18 Nov 2019, "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com> wrote:
> I'm fine with fixing checkpatch and sparse failures(even though
> most of those are about 80 line width limitation violation or line
> continuations, which tbh are anyway quite common in our code). 

Please look through the warnings again. Only the COMMIT_LOG_LONG_LINE
one is to be ignored in this case. There's nothing else about 80
character line width. Line continuation is about using backslash to
continue to another line while that's only needed in macros.

Please let's just try to leave the code in neater shape after our
changes. We have these steps in CI so people wouldn't have to nitpick
about them separately.

> One thing I don't get is why this should cause any regression, as both
> BAT and IGT are green here for two runs in a row.
>
> What is the point of having a CI then.

Are you saying there's no point in having CI if it can't catch
absolutely everything?

Our CI is like every other CI everywhere; imperfect. Both in terms of
hardware and software coverage. We would have no bugs reported by the
community otherwise.


BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2019-11-18 15:26 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-14 12:24 [PATCH v7] drm/i915: Enable second dbuf slice for ICL and TGL Stanislav Lisovskiy
2019-11-14 12:24 ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-14 13:49 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable second dbuf slice for ICL and TGL (rev4) Patchwork
2019-11-14 13:49   ` [Intel-gfx] " Patchwork
2019-11-14 13:50 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-11-14 13:50   ` [Intel-gfx] " Patchwork
2019-11-14 14:18 ` ✓ Fi.CI.BAT: success " Patchwork
2019-11-14 14:18   ` [Intel-gfx] " Patchwork
2019-11-15  9:59 ` ✓ Fi.CI.IGT: " Patchwork
2019-11-15  9:59   ` [Intel-gfx] " Patchwork
2019-11-15 20:19 ` [PATCH v7] drm/i915: Enable second dbuf slice for ICL and TGL Ville Syrjälä
2019-11-15 20:19   ` [Intel-gfx] " Ville Syrjälä
2019-11-18  9:19   ` Lisovskiy, Stanislav
2019-11-18  9:19     ` [Intel-gfx] " Lisovskiy, Stanislav
2019-11-18 15:27     ` Ville Syrjälä
2019-11-18 15:27       ` [Intel-gfx] " Ville Syrjälä
2019-11-18 17:17       ` Lisovskiy, Stanislav
2019-11-18 17:17         ` [Intel-gfx] " Lisovskiy, Stanislav
2019-11-18 18:18         ` Ville Syrjälä
2019-11-18 18:18           ` [Intel-gfx] " Ville Syrjälä
2019-11-18 20:25           ` Lisovskiy, Stanislav
2019-11-18 20:25             ` [Intel-gfx] " Lisovskiy, Stanislav
2019-11-19 13:24             ` Lisovskiy, Stanislav
2019-11-19 13:24               ` [Intel-gfx] " Lisovskiy, Stanislav
2019-11-20 19:18             ` Ville Syrjälä
2019-11-20 19:18               ` [Intel-gfx] " Ville Syrjälä
2019-11-20 21:55               ` Lisovskiy, Stanislav
2019-11-20 21:55                 ` [Intel-gfx] " Lisovskiy, Stanislav
2019-11-18 14:22 ` Jani Nikula
2019-11-18 14:22   ` [Intel-gfx] " Jani Nikula
2019-11-18 14:32   ` Lisovskiy, Stanislav
2019-11-18 14:32     ` [Intel-gfx] " Lisovskiy, Stanislav
2019-11-18 15:26     ` Jani Nikula [this message]
2019-11-18 15:26       ` Jani Nikula

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