* [PATCH 2/3] drm/i915: Handle catastrophic error on engine reset
2019-04-12 15:37 [PATCH 1/3] drm/i915: Shortcut readiness to reset check Mika Kuoppala
@ 2019-04-12 15:37 ` Mika Kuoppala
2019-04-12 15:49 ` Chris Wilson
2019-04-12 15:37 ` [PATCH 3/3] drm/i915: Log catastrophic errors on gen11 Mika Kuoppala
` (4 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Mika Kuoppala @ 2019-04-12 15:37 UTC (permalink / raw)
To: intel-gfx
If cat error is set, we need to clear it by acking it. Further,
if it is set, we must not do a normal request for reset.
Bspec: 12567
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 +++--
drivers/gpu/drm/i915/i915_reset.c | 39 +++++++++++++++++++++----------
2 files changed, 31 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8ad2f0a03f28..c1c0f7ab03e9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2446,8 +2446,10 @@ enum i915_power_well_id {
#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
-#define RESET_CTL_REQUEST_RESET (1 << 0)
-#define RESET_CTL_READY_TO_RESET (1 << 1)
+#define RESET_CTL_CAT_ERROR REG_BIT(2)
+#define RESET_CTL_READY_TO_RESET REG_BIT(1)
+#define RESET_CTL_REQUEST_RESET REG_BIT(0)
+
#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
#define HSW_GTT_CACHE_EN _MMIO(0x4024)
diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c
index cde1a5309336..06310ee5a68a 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -490,25 +490,40 @@ static int gen11_reset_engines(struct drm_i915_private *i915,
static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
{
struct intel_uncore *uncore = engine->uncore;
- u32 ctl;
+ const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);
+ u32 ctl, ack = 0, mask = 0, request = 0;
int ret;
- ctl = intel_uncore_read_fw(uncore, RING_RESET_CTL(engine->mmio_base));
- if (ctl & RESET_CTL_READY_TO_RESET)
+ ctl = intel_uncore_read_fw(uncore, reg);
+
+ if (INTEL_GEN(engine->i915) > 9 && (ctl & RESET_CTL_CAT_ERROR)) {
+ request |= RESET_CTL_CAT_ERROR;
+ mask |= RESET_CTL_CAT_ERROR;
+
+ /* HAS#396813: Avoid reset request if cat error */
+ goto skip_ready_req;
+ }
+
+ if (!(ctl & RESET_CTL_READY_TO_RESET)) {
+ request |= RESET_CTL_REQUEST_RESET;
+
+ mask |= RESET_CTL_READY_TO_RESET;
+ ack |= RESET_CTL_READY_TO_RESET;
+ }
+
+ if (!request)
return 0;
- intel_uncore_write_fw(uncore,
- RING_RESET_CTL(engine->mmio_base),
- _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
+skip_ready_req:
+ intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
ret = __intel_wait_for_register_fw(uncore,
- RING_RESET_CTL(engine->mmio_base),
- RESET_CTL_READY_TO_RESET,
- RESET_CTL_READY_TO_RESET,
- 700, 0,
- NULL);
+ reg, mask, ack,
+ 700, 0, NULL);
if (ret)
- DRM_ERROR("%s: reset request timeout\n", engine->name);
+ DRM_ERROR("%s: reset request 0x%08x timeout 0x%08x\n",
+ engine->name, request,
+ intel_uncore_read_fw(uncore, reg));
return ret;
}
--
2.17.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 2/3] drm/i915: Handle catastrophic error on engine reset
2019-04-12 15:37 ` [PATCH 2/3] drm/i915: Handle catastrophic error on engine reset Mika Kuoppala
@ 2019-04-12 15:49 ` Chris Wilson
2019-04-12 15:58 ` Mika Kuoppala
0 siblings, 1 reply; 12+ messages in thread
From: Chris Wilson @ 2019-04-12 15:49 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-04-12 16:37:22)
> If cat error is set, we need to clear it by acking it. Further,
> if it is set, we must not do a normal request for reset.
>
> Bspec: 12567
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 +++--
> drivers/gpu/drm/i915/i915_reset.c | 39 +++++++++++++++++++++----------
> 2 files changed, 31 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8ad2f0a03f28..c1c0f7ab03e9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2446,8 +2446,10 @@ enum i915_power_well_id {
> #define RING_HWS_PGA(base) _MMIO((base) + 0x80)
> #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
> #define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
> -#define RESET_CTL_REQUEST_RESET (1 << 0)
> -#define RESET_CTL_READY_TO_RESET (1 << 1)
> +#define RESET_CTL_CAT_ERROR REG_BIT(2)
> +#define RESET_CTL_READY_TO_RESET REG_BIT(1)
> +#define RESET_CTL_REQUEST_RESET REG_BIT(0)
> +
> #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
>
> #define HSW_GTT_CACHE_EN _MMIO(0x4024)
> diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c
> index cde1a5309336..06310ee5a68a 100644
> --- a/drivers/gpu/drm/i915/i915_reset.c
> +++ b/drivers/gpu/drm/i915/i915_reset.c
> @@ -490,25 +490,40 @@ static int gen11_reset_engines(struct drm_i915_private *i915,
> static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
> {
> struct intel_uncore *uncore = engine->uncore;
> - u32 ctl;
> + const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);
> + u32 ctl, ack = 0, mask = 0, request = 0;
> int ret;
>
> - ctl = intel_uncore_read_fw(uncore, RING_RESET_CTL(engine->mmio_base));
> - if (ctl & RESET_CTL_READY_TO_RESET)
> + ctl = intel_uncore_read_fw(uncore, reg);
> +
> + if (INTEL_GEN(engine->i915) > 9 && (ctl & RESET_CTL_CAT_ERROR)) {
> + request |= RESET_CTL_CAT_ERROR;
> + mask |= RESET_CTL_CAT_ERROR;
> +
> + /* HAS#396813: Avoid reset request if cat error */
> + goto skip_ready_req;
> + }
Doesn't look like you need a goto here.
if (ctl & CAT_ERROR) { /* CAT_ERROR shouldn't be raised on gen8-9 */
request = RESET_CTL_CAT_ERROR;
mask = RESET_CTL_CAT_ERROR;
} else if (!(ctl & RESET_CTL_READY_TO_RESET))) {
request = RESET_CTL_REQUEST_RESET;
mask = RESET_CTL_READY_TO_RESET;
ack = RESET_CTL_READY_TO_RESET;
} else {
return 0;
}
Right?
> +
> + if (!(ctl & RESET_CTL_READY_TO_RESET)) {
> + request |= RESET_CTL_REQUEST_RESET;
> +
> + mask |= RESET_CTL_READY_TO_RESET;
> + ack |= RESET_CTL_READY_TO_RESET;
> + }
> +
> + if (!request)
> return 0;
>
> - intel_uncore_write_fw(uncore,
> - RING_RESET_CTL(engine->mmio_base),
> - _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
> +skip_ready_req:
> + intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
>
> ret = __intel_wait_for_register_fw(uncore,
> - RING_RESET_CTL(engine->mmio_base),
> - RESET_CTL_READY_TO_RESET,
> - RESET_CTL_READY_TO_RESET,
> - 700, 0,
> - NULL);
> + reg, mask, ack,
> + 700, 0, NULL);
> if (ret)
> - DRM_ERROR("%s: reset request timeout\n", engine->name);
> + DRM_ERROR("%s: reset request 0x%08x timeout 0x%08x\n",
> + engine->name, request,
> + intel_uncore_read_fw(uncore, reg));
Interesting, the only quible I have is with "request". But it works well
enough in context.
-Chris
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^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 2/3] drm/i915: Handle catastrophic error on engine reset
2019-04-12 15:49 ` Chris Wilson
@ 2019-04-12 15:58 ` Mika Kuoppala
0 siblings, 0 replies; 12+ messages in thread
From: Mika Kuoppala @ 2019-04-12 15:58 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Quoting Mika Kuoppala (2019-04-12 16:37:22)
>> If cat error is set, we need to clear it by acking it. Further,
>> if it is set, we must not do a normal request for reset.
>>
>> Bspec: 12567
>> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 6 +++--
>> drivers/gpu/drm/i915/i915_reset.c | 39 +++++++++++++++++++++----------
>> 2 files changed, 31 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 8ad2f0a03f28..c1c0f7ab03e9 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2446,8 +2446,10 @@ enum i915_power_well_id {
>> #define RING_HWS_PGA(base) _MMIO((base) + 0x80)
>> #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
>> #define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
>> -#define RESET_CTL_REQUEST_RESET (1 << 0)
>> -#define RESET_CTL_READY_TO_RESET (1 << 1)
>> +#define RESET_CTL_CAT_ERROR REG_BIT(2)
>> +#define RESET_CTL_READY_TO_RESET REG_BIT(1)
>> +#define RESET_CTL_REQUEST_RESET REG_BIT(0)
>> +
>> #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
>>
>> #define HSW_GTT_CACHE_EN _MMIO(0x4024)
>> diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c
>> index cde1a5309336..06310ee5a68a 100644
>> --- a/drivers/gpu/drm/i915/i915_reset.c
>> +++ b/drivers/gpu/drm/i915/i915_reset.c
>> @@ -490,25 +490,40 @@ static int gen11_reset_engines(struct drm_i915_private *i915,
>> static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
>> {
>> struct intel_uncore *uncore = engine->uncore;
>> - u32 ctl;
>> + const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);
>> + u32 ctl, ack = 0, mask = 0, request = 0;
>> int ret;
>>
>> - ctl = intel_uncore_read_fw(uncore, RING_RESET_CTL(engine->mmio_base));
>> - if (ctl & RESET_CTL_READY_TO_RESET)
>> + ctl = intel_uncore_read_fw(uncore, reg);
>> +
>> + if (INTEL_GEN(engine->i915) > 9 && (ctl & RESET_CTL_CAT_ERROR)) {
>> + request |= RESET_CTL_CAT_ERROR;
>> + mask |= RESET_CTL_CAT_ERROR;
>> +
>> + /* HAS#396813: Avoid reset request if cat error */
>> + goto skip_ready_req;
>> + }
>
> Doesn't look like you need a goto here.
>
> if (ctl & CAT_ERROR) { /* CAT_ERROR shouldn't be raised on gen8-9 */
> request = RESET_CTL_CAT_ERROR;
> mask = RESET_CTL_CAT_ERROR;
> } else if (!(ctl & RESET_CTL_READY_TO_RESET))) {
> request = RESET_CTL_REQUEST_RESET;
> mask = RESET_CTL_READY_TO_RESET;
> ack = RESET_CTL_READY_TO_RESET;
> } else {
> return 0;
> }
>
> Right?
Right no goto needed and ta for writing it out above.
The bit was 'reserved' on previous gen but we can safely assumed
it is zero and stay such.
-Mika
>
>> +
>> + if (!(ctl & RESET_CTL_READY_TO_RESET)) {
>> + request |= RESET_CTL_REQUEST_RESET;
>> +
>> + mask |= RESET_CTL_READY_TO_RESET;
>> + ack |= RESET_CTL_READY_TO_RESET;
>> + }
>> +
>> + if (!request)
>> return 0;
>>
>> - intel_uncore_write_fw(uncore,
>> - RING_RESET_CTL(engine->mmio_base),
>> - _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
>> +skip_ready_req:
>> + intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
>>
>> ret = __intel_wait_for_register_fw(uncore,
>> - RING_RESET_CTL(engine->mmio_base),
>> - RESET_CTL_READY_TO_RESET,
>> - RESET_CTL_READY_TO_RESET,
>> - 700, 0,
>> - NULL);
>> + reg, mask, ack,
>> + 700, 0, NULL);
>> if (ret)
>> - DRM_ERROR("%s: reset request timeout\n", engine->name);
>> + DRM_ERROR("%s: reset request 0x%08x timeout 0x%08x\n",
>> + engine->name, request,
>> + intel_uncore_read_fw(uncore, reg));
>
> Interesting, the only quible I have is with "request". But it works well
> enough in context.
> -Chris
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 3/3] drm/i915: Log catastrophic errors on gen11
2019-04-12 15:37 [PATCH 1/3] drm/i915: Shortcut readiness to reset check Mika Kuoppala
2019-04-12 15:37 ` [PATCH 2/3] drm/i915: Handle catastrophic error on engine reset Mika Kuoppala
@ 2019-04-12 15:37 ` Mika Kuoppala
2019-04-12 15:42 ` Chris Wilson
2019-04-12 15:51 ` [PATCH 1/3] drm/i915: Shortcut readiness to reset check Chris Wilson
` (3 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Mika Kuoppala @ 2019-04-12 15:37 UTC (permalink / raw)
To: intel-gfx
Add a log entry to indicate if engine reported an intr
condition that is a sign of halted command streamer.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 24 +++++++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d934545445e1..c64ef1291d62 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1480,7 +1480,7 @@ static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
}
static void
-gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
+gen8_cs_irq_handler(struct intel_engine_cs *engine, const u32 iir)
{
bool tasklet = false;
@@ -1496,6 +1496,20 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
tasklet_hi_schedule(&engine->execlists.tasklet);
}
+static void
+gen11_cs_irq_handler(struct intel_engine_cs *engine, const u32 iir)
+{
+ const u32 error_intrs =
+ GT_LEGACY_CONTEXT_PPGTT_PAGE_FAULT |
+ GT_CATASTROPHIC_ERROR_INTERRUPT |
+ GT_CS_MASTER_ERROR_INTERRUPT;
+
+ if (likely(!(error_intrs & iir)))
+ return gen8_cs_irq_handler(engine, iir);
+
+ DRM_ERROR("%s: intr 0x%08x\n", engine->name, iir);
+}
+
static void gen8_gt_irq_ack(struct drm_i915_private *i915,
u32 master_ctl, u32 gt_iir[4])
{
@@ -3002,7 +3016,7 @@ gen11_engine_irq_handler(struct drm_i915_private * const i915,
engine = NULL;
if (likely(engine))
- return gen8_cs_irq_handler(engine, iir);
+ return gen11_cs_irq_handler(engine, iir);
WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
class, instance);
@@ -4120,7 +4134,11 @@ static int gen8_irq_postinstall(struct drm_device *dev)
static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
{
- const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
+ const u32 irqs = GT_CATASTROPHIC_ERROR_INTERRUPT |
+ GT_LEGACY_CONTEXT_PPGTT_PAGE_FAULT |
+ GT_CS_MASTER_ERROR_INTERRUPT |
+ GT_RENDER_USER_INTERRUPT |
+ GT_CONTEXT_SWITCH_INTERRUPT;
BUILD_BUG_ON(irqs & 0xffff0000);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1c0f7ab03e9..fb1cff071f7a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2996,6 +2996,10 @@ enum i915_power_well_id {
#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
#define GT_RENDER_USER_INTERRUPT (1 << 0)
+#define GT_CATASTROPHIC_ERROR_INTERRUPT (1 << 15) /* gen11 */
+#define GT_LEGACY_CONTEXT_PPGTT_PAGE_FAULT (1 << 7) /* gen11 */
+#define GT_CS_MASTER_ERROR_INTERRUPT (1 << 3) /* gen11 */
+
#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
--
2.17.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 3/3] drm/i915: Log catastrophic errors on gen11
2019-04-12 15:37 ` [PATCH 3/3] drm/i915: Log catastrophic errors on gen11 Mika Kuoppala
@ 2019-04-12 15:42 ` Chris Wilson
2019-04-12 15:47 ` Mika Kuoppala
0 siblings, 1 reply; 12+ messages in thread
From: Chris Wilson @ 2019-04-12 15:42 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-04-12 16:37:23)
> Add a log entry to indicate if engine reported an intr
> condition that is a sign of halted command streamer.
It's a user error. Isn't that we spam the "there has been an error;
resetting the gpu" message enough?
You could just look at the iir in the error capture for the same effect.
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 24 +++++++++++++++++++++---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> 2 files changed, 25 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index d934545445e1..c64ef1291d62 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1480,7 +1480,7 @@ static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
> }
>
> static void
> -gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
> +gen8_cs_irq_handler(struct intel_engine_cs *engine, const u32 iir)
> {
> bool tasklet = false;
>
> @@ -1496,6 +1496,20 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
> tasklet_hi_schedule(&engine->execlists.tasklet);
> }
>
> +static void
> +gen11_cs_irq_handler(struct intel_engine_cs *engine, const u32 iir)
> +{
> + const u32 error_intrs =
> + GT_LEGACY_CONTEXT_PPGTT_PAGE_FAULT |
> + GT_CATASTROPHIC_ERROR_INTERRUPT |
> + GT_CS_MASTER_ERROR_INTERRUPT;
> +
> + if (likely(!(error_intrs & iir)))
Likely?
> + return gen8_cs_irq_handler(engine, iir);
> +
> + DRM_ERROR("%s: intr 0x%08x\n", engine->name, iir);
> +}
> +
> static void gen8_gt_irq_ack(struct drm_i915_private *i915,
> u32 master_ctl, u32 gt_iir[4])
> {
> @@ -3002,7 +3016,7 @@ gen11_engine_irq_handler(struct drm_i915_private * const i915,
> engine = NULL;
>
> if (likely(engine))
> - return gen8_cs_irq_handler(engine, iir);
> + return gen11_cs_irq_handler(engine, iir);
>
> WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
> class, instance);
> @@ -4120,7 +4134,11 @@ static int gen8_irq_postinstall(struct drm_device *dev)
>
> static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> - const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
> + const u32 irqs = GT_CATASTROPHIC_ERROR_INTERRUPT |
> + GT_LEGACY_CONTEXT_PPGTT_PAGE_FAULT |
> + GT_CS_MASTER_ERROR_INTERRUPT |
> + GT_RENDER_USER_INTERRUPT |
> + GT_CONTEXT_SWITCH_INTERRUPT;
>
> BUILD_BUG_ON(irqs & 0xffff0000);
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c1c0f7ab03e9..fb1cff071f7a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2996,6 +2996,10 @@ enum i915_power_well_id {
> #define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
> #define GT_RENDER_USER_INTERRUPT (1 << 0)
>
> +#define GT_CATASTROPHIC_ERROR_INTERRUPT (1 << 15) /* gen11 */
> +#define GT_LEGACY_CONTEXT_PPGTT_PAGE_FAULT (1 << 7) /* gen11 */
> +#define GT_CS_MASTER_ERROR_INTERRUPT (1 << 3) /* gen11 */
> +
> #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
> #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
>
> --
> 2.17.1
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 3/3] drm/i915: Log catastrophic errors on gen11
2019-04-12 15:42 ` Chris Wilson
@ 2019-04-12 15:47 ` Mika Kuoppala
2019-04-12 15:53 ` Chris Wilson
0 siblings, 1 reply; 12+ messages in thread
From: Mika Kuoppala @ 2019-04-12 15:47 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Quoting Mika Kuoppala (2019-04-12 16:37:23)
>> Add a log entry to indicate if engine reported an intr
>> condition that is a sign of halted command streamer.
>
> It's a user error. Isn't that we spam the "there has been an error;
> resetting the gpu" message enough?
>
> You could just look at the iir in the error capture for the same effect.
>
Yeah it is debatable if this adds any value at all in this form.
Could drop this and introduce only if I get motivation
to handle reset faster straight from encountering error
intr.
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_irq.c | 24 +++++++++++++++++++++---
>> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
>> 2 files changed, 25 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index d934545445e1..c64ef1291d62 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -1480,7 +1480,7 @@ static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
>> }
>>
>> static void
>> -gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
>> +gen8_cs_irq_handler(struct intel_engine_cs *engine, const u32 iir)
>> {
>> bool tasklet = false;
>>
>> @@ -1496,6 +1496,20 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
>> tasklet_hi_schedule(&engine->execlists.tasklet);
>> }
>>
>> +static void
>> +gen11_cs_irq_handler(struct intel_engine_cs *engine, const u32 iir)
>> +{
>> + const u32 error_intrs =
>> + GT_LEGACY_CONTEXT_PPGTT_PAGE_FAULT |
>> + GT_CATASTROPHIC_ERROR_INTERRUPT |
>> + GT_CS_MASTER_ERROR_INTERRUPT;
>> +
>> + if (likely(!(error_intrs & iir)))
>
> Likely?
>
Likely to not have errors.
-Mika
>> + return gen8_cs_irq_handler(engine, iir);
>> +
>> + DRM_ERROR("%s: intr 0x%08x\n", engine->name, iir);
>> +}
>> +
>> static void gen8_gt_irq_ack(struct drm_i915_private *i915,
>> u32 master_ctl, u32 gt_iir[4])
>> {
>> @@ -3002,7 +3016,7 @@ gen11_engine_irq_handler(struct drm_i915_private * const i915,
>> engine = NULL;
>>
>> if (likely(engine))
>> - return gen8_cs_irq_handler(engine, iir);
>> + return gen11_cs_irq_handler(engine, iir);
>>
>> WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
>> class, instance);
>> @@ -4120,7 +4134,11 @@ static int gen8_irq_postinstall(struct drm_device *dev)
>>
>> static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
>> {
>> - const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
>> + const u32 irqs = GT_CATASTROPHIC_ERROR_INTERRUPT |
>> + GT_LEGACY_CONTEXT_PPGTT_PAGE_FAULT |
>> + GT_CS_MASTER_ERROR_INTERRUPT |
>> + GT_RENDER_USER_INTERRUPT |
>> + GT_CONTEXT_SWITCH_INTERRUPT;
>>
>> BUILD_BUG_ON(irqs & 0xffff0000);
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index c1c0f7ab03e9..fb1cff071f7a 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2996,6 +2996,10 @@ enum i915_power_well_id {
>> #define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
>> #define GT_RENDER_USER_INTERRUPT (1 << 0)
>>
>> +#define GT_CATASTROPHIC_ERROR_INTERRUPT (1 << 15) /* gen11 */
>> +#define GT_LEGACY_CONTEXT_PPGTT_PAGE_FAULT (1 << 7) /* gen11 */
>> +#define GT_CS_MASTER_ERROR_INTERRUPT (1 << 3) /* gen11 */
>> +
>> #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
>> #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
>>
>> --
>> 2.17.1
>>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 3/3] drm/i915: Log catastrophic errors on gen11
2019-04-12 15:47 ` Mika Kuoppala
@ 2019-04-12 15:53 ` Chris Wilson
0 siblings, 0 replies; 12+ messages in thread
From: Chris Wilson @ 2019-04-12 15:53 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-04-12 16:47:11)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > Quoting Mika Kuoppala (2019-04-12 16:37:23)
> >> Add a log entry to indicate if engine reported an intr
> >> condition that is a sign of halted command streamer.
> >
> > It's a user error. Isn't that we spam the "there has been an error;
> > resetting the gpu" message enough?
> >
> > You could just look at the iir in the error capture for the same effect.
> >
>
> Yeah it is debatable if this adds any value at all in this form.
> Could drop this and introduce only if I get motivation
> to handle reset faster straight from encountering error
> intr.
>
> >> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> >> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> >> ---
> >> drivers/gpu/drm/i915/i915_irq.c | 24 +++++++++++++++++++++---
> >> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> >> 2 files changed, 25 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> >> index d934545445e1..c64ef1291d62 100644
> >> --- a/drivers/gpu/drm/i915/i915_irq.c
> >> +++ b/drivers/gpu/drm/i915/i915_irq.c
> >> @@ -1480,7 +1480,7 @@ static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
> >> }
> >>
> >> static void
> >> -gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
> >> +gen8_cs_irq_handler(struct intel_engine_cs *engine, const u32 iir)
> >> {
> >> bool tasklet = false;
> >>
> >> @@ -1496,6 +1496,20 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
> >> tasklet_hi_schedule(&engine->execlists.tasklet);
> >> }
> >>
> >> +static void
> >> +gen11_cs_irq_handler(struct intel_engine_cs *engine, const u32 iir)
> >> +{
> >> + const u32 error_intrs =
> >> + GT_LEGACY_CONTEXT_PPGTT_PAGE_FAULT |
> >> + GT_CATASTROPHIC_ERROR_INTERRUPT |
> >> + GT_CS_MASTER_ERROR_INTERRUPT;
> >> +
> >> + if (likely(!(error_intrs & iir)))
> >
> > Likely?
> >
>
> Likely to not have errors.
Oh, this is the CS/USER_INTERRUPT handler. Yeah, much more likely. So
much more, I'd push more for this to be polled by the error handler :)
-Chris
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/3] drm/i915: Shortcut readiness to reset check
2019-04-12 15:37 [PATCH 1/3] drm/i915: Shortcut readiness to reset check Mika Kuoppala
2019-04-12 15:37 ` [PATCH 2/3] drm/i915: Handle catastrophic error on engine reset Mika Kuoppala
2019-04-12 15:37 ` [PATCH 3/3] drm/i915: Log catastrophic errors on gen11 Mika Kuoppala
@ 2019-04-12 15:51 ` Chris Wilson
2019-04-12 15:54 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] " Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Chris Wilson @ 2019-04-12 15:51 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx; +Cc: Chris
Quoting Mika Kuoppala (2019-04-12 16:37:21)
> If the engine says it is ready for reset, it is ready
> so avoid further dancing and proceed.
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reset.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c
> index 68875ba43b8d..cde1a5309336 100644
> --- a/drivers/gpu/drm/i915/i915_reset.c
> +++ b/drivers/gpu/drm/i915/i915_reset.c
> @@ -490,8 +490,13 @@ static int gen11_reset_engines(struct drm_i915_private *i915,
> static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
> {
> struct intel_uncore *uncore = engine->uncore;
> + u32 ctl;
> int ret;
>
> + ctl = intel_uncore_read_fw(uncore, RING_RESET_CTL(engine->mmio_base));
> + if (ctl & RESET_CTL_READY_TO_RESET)
> + return 0;
> +
Would seem to not matter atm, but it does make the next patch easier.
How about pulling the i915_reg_t into this, so the second is more about
merging the CAT_ERROR handling?
-Chris
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Shortcut readiness to reset check
2019-04-12 15:37 [PATCH 1/3] drm/i915: Shortcut readiness to reset check Mika Kuoppala
` (2 preceding siblings ...)
2019-04-12 15:51 ` [PATCH 1/3] drm/i915: Shortcut readiness to reset check Chris Wilson
@ 2019-04-12 15:54 ` Patchwork
2019-04-12 16:32 ` ✓ Fi.CI.BAT: success " Patchwork
2019-04-12 19:38 ` ✓ Fi.CI.IGT: " Patchwork
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-04-12 15:54 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915: Shortcut readiness to reset check
URL : https://patchwork.freedesktop.org/series/59406/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b2a7ac10e21f drm/i915: Shortcut readiness to reset check
-:9: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Chris Wilson <chris@chris-wilson.co.uk'
#9:
Cc: Chris Wilson <chris@chris-wilson.co.uk
total: 1 errors, 0 warnings, 0 checks, 13 lines checked
66e5bb3569cc drm/i915: Handle catastrophic error on engine reset
7a1a2e7ea0f4 drm/i915: Log catastrophic errors on gen11
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Shortcut readiness to reset check
2019-04-12 15:37 [PATCH 1/3] drm/i915: Shortcut readiness to reset check Mika Kuoppala
` (3 preceding siblings ...)
2019-04-12 15:54 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] " Patchwork
@ 2019-04-12 16:32 ` Patchwork
2019-04-12 19:38 ` ✓ Fi.CI.IGT: " Patchwork
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-04-12 16:32 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915: Shortcut readiness to reset check
URL : https://patchwork.freedesktop.org/series/59406/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5923 -> Patchwork_12780
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/59406/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12780 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: PASS -> DMESG-WARN [fdo#108965]
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109315] +17
* igt@gem_exec_basic@gtt-bsd1:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109276] +7
* igt@gem_exec_parse@basic-rejected:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109289] +1
* igt@kms_busy@basic-flip-c:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@dp-crc-fast:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +43
* igt@kms_chamelium@hdmi-edid-read:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109284] +8
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109285] +3
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191]
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@i915_selftest@live_contexts:
- fi-skl-gvtdvm: DMESG-FAIL [fdo#110235 ] -> PASS
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: FAIL [fdo#103167] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
Participating hosts (48 -> 43)
------------------------------
Additional (1): fi-icl-u3
Missing (6): fi-kbl-soraka fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5923 -> Patchwork_12780
CI_DRM_5923: 8f69ca66d43ef57be72394ba23c2ff1718d94164 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4945: a52cc643cfe6733465cfc9ccb3d21cbdc4fd7506 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12780: 7a1a2e7ea0f49d99b64bacdf7186e5ad830c2311 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7a1a2e7ea0f4 drm/i915: Log catastrophic errors on gen11
66e5bb3569cc drm/i915: Handle catastrophic error on engine reset
b2a7ac10e21f drm/i915: Shortcut readiness to reset check
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12780/
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915: Shortcut readiness to reset check
2019-04-12 15:37 [PATCH 1/3] drm/i915: Shortcut readiness to reset check Mika Kuoppala
` (4 preceding siblings ...)
2019-04-12 16:32 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-04-12 19:38 ` Patchwork
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-04-12 19:38 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915: Shortcut readiness to reset check
URL : https://patchwork.freedesktop.org/series/59406/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5923_full -> Patchwork_12780_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_12780_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@i2c:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#107807]
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#107807]
* igt@i915_suspend@debugfs-reader:
- shard-apl: PASS -> DMESG-WARN [fdo#108566] +2
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: NOTRUN -> FAIL [fdo#103833]
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-kbl: PASS -> DMESG-WARN [fdo#103313]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-iclb: PASS -> FAIL [fdo#103167] +7
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-skl: NOTRUN -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: PASS -> FAIL [fdo#109247] +8
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt:
- shard-iclb: PASS -> INCOMPLETE [fdo#106978]
* igt@kms_lease@page_flip_implicit_plane:
- shard-skl: NOTRUN -> FAIL [fdo#110281]
* igt@kms_panel_fitting@legacy:
- shard-skl: NOTRUN -> FAIL [fdo#105456]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-f:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +15
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: PASS -> FAIL [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +3
* igt@kms_psr@cursor_blt:
- shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] +2
* igt@kms_psr@no_drrs:
- shard-iclb: PASS -> FAIL [fdo#108341]
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: PASS -> SKIP [fdo#109441]
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: PASS -> INCOMPLETE [fdo#103665]
* igt@kms_sysfs_edid_timing:
- shard-iclb: PASS -> FAIL [fdo#100047]
* igt@perf_pmu@busy-accuracy-50-vcs1:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +126
#### Possible fixes ####
* igt@gem_softpin@noreloc-s3:
- shard-kbl: DMESG-WARN [fdo#103313] -> PASS
* igt@i915_suspend@sysfs-reader:
- shard-apl: DMESG-WARN [fdo#108566] -> PASS +6
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: SKIP [fdo#109349] -> PASS
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: FAIL [fdo#105363] -> PASS
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: FAIL [fdo#105363] -> PASS
* igt@kms_flip@flip-vs-suspend:
- shard-skl: INCOMPLETE [fdo#109507] -> PASS
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt:
- shard-iclb: FAIL [fdo#109247] -> PASS +11
* igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
- shard-iclb: FAIL [fdo#103167] -> PASS +3
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: FAIL [fdo#103166] -> PASS
* igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_psr@psr2_suspend:
- shard-iclb: SKIP [fdo#109441] -> PASS +1
* igt@kms_psr@suspend:
- shard-skl: INCOMPLETE [fdo#107773] -> PASS
- shard-iclb: FAIL [fdo#107383] / [fdo#110215] -> PASS
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: DMESG-FAIL [fdo#105763] -> PASS
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: FAIL [fdo#109016] -> PASS
* igt@kms_setmode@basic:
- shard-iclb: FAIL [fdo#99912] -> PASS
* igt@tools_test@tools_test:
- shard-snb: SKIP [fdo#109271] -> PASS
#### Warnings ####
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-skl: INCOMPLETE [fdo#107807] -> SKIP [fdo#109271]
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103833]: https://bugs.freedesktop.org/show_bug.cgi?id=103833
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105456]: https://bugs.freedesktop.org/show_bug.cgi?id=105456
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#110215]: https://bugs.freedesktop.org/show_bug.cgi?id=110215
[fdo#110281]: https://bugs.freedesktop.org/show_bug.cgi?id=110281
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-hsw
Build changes
-------------
* Linux: CI_DRM_5923 -> Patchwork_12780
CI_DRM_5923: 8f69ca66d43ef57be72394ba23c2ff1718d94164 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4945: a52cc643cfe6733465cfc9ccb3d21cbdc4fd7506 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12780: 7a1a2e7ea0f49d99b64bacdf7186e5ad830c2311 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12780/
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