All of lore.kernel.org
 help / color / mirror / Atom feed
From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 13/31] drm/i915: Move the irq_counter inside the spinlock
Date: Wed, 27 Jun 2018 17:23:59 +0300	[thread overview]
Message-ID: <87bmbwux34.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20180625094842.8499-13-chris@chris-wilson.co.uk>

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Rather than have multiple locked instructions inside the notify_ring()
> irq handler, move them inside the spinlock and reduce their intrinsic
> locking.
>

Less is better, could note in commit message that we omit the non
wait ones.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/i915_irq.c          |  4 ++--
>  drivers/gpu/drm/i915/i915_request.c      |  4 ++--
>  drivers/gpu/drm/i915/intel_breadcrumbs.c | 11 +++++++----
>  drivers/gpu/drm/i915/intel_ringbuffer.h  |  2 +-
>  4 files changed, 12 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 53dad48f92ce..6730c1a7f135 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1153,8 +1153,6 @@ static void notify_ring(struct intel_engine_cs *engine)
>  	if (unlikely(!engine->breadcrumbs.irq_armed))
>  		return;
>  
> -	atomic_inc(&engine->irq_count);
> -
>  	rcu_read_lock();
>  
>  	spin_lock(&engine->breadcrumbs.irq_lock);
> @@ -1189,6 +1187,8 @@ static void notify_ring(struct intel_engine_cs *engine)
>  				tsk = wait->tsk;
>  			}
>  		}
> +
> +		engine->breadcrumbs.irq_count++;
>  	} else {
>  		if (engine->breadcrumbs.irq_armed)
>  			__intel_engine_disarm_breadcrumbs(engine);
> diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
> index 11f175554da8..696125663105 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -1161,7 +1161,7 @@ static bool __i915_spin_request(const struct i915_request *rq,
>  	 * takes to sleep on a request, on the order of a microsecond.
>  	 */
>  
> -	irq = atomic_read(&engine->irq_count);
> +	irq = READ_ONCE(engine->breadcrumbs.irq_count);
>  	timeout_us += local_clock_us(&cpu);
>  	do {
>  		if (i915_seqno_passed(intel_engine_get_seqno(engine), seqno))
> @@ -1173,7 +1173,7 @@ static bool __i915_spin_request(const struct i915_request *rq,
>  		 * assume we won't see one in the near future but require
>  		 * the engine->seqno_barrier() to fixup coherency.
>  		 */
> -		if (atomic_read(&engine->irq_count) != irq)
> +		if (READ_ONCE(engine->breadcrumbs.irq_count) != irq)
>  			break;
>  
>  		if (signal_pending_state(state, current))
> diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c
> index 86a987b8ac66..1db6ba7d926e 100644
> --- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
> +++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
> @@ -98,12 +98,14 @@ static void intel_breadcrumbs_hangcheck(struct timer_list *t)
>  	struct intel_engine_cs *engine =
>  		from_timer(engine, t, breadcrumbs.hangcheck);
>  	struct intel_breadcrumbs *b = &engine->breadcrumbs;
> +	unsigned int irq_count;
>  
>  	if (!b->irq_armed)
>  		return;
>  
> -	if (b->hangcheck_interrupts != atomic_read(&engine->irq_count)) {
> -		b->hangcheck_interrupts = atomic_read(&engine->irq_count);
> +	irq_count = READ_ONCE(b->irq_count);
> +	if (b->hangcheck_interrupts != irq_count) {
> +		b->hangcheck_interrupts = irq_count;
>  		mod_timer(&b->hangcheck, wait_timeout());
>  		return;
>  	}
> @@ -272,13 +274,14 @@ static bool use_fake_irq(const struct intel_breadcrumbs *b)
>  	if (!test_bit(engine->id, &engine->i915->gpu_error.missed_irq_rings))
>  		return false;
>  
> -	/* Only start with the heavy weight fake irq timer if we have not
> +	/*
> +	 * Only start with the heavy weight fake irq timer if we have not
>  	 * seen any interrupts since enabling it the first time. If the
>  	 * interrupts are still arriving, it means we made a mistake in our
>  	 * engine->seqno_barrier(), a timing error that should be transient
>  	 * and unlikely to reoccur.
>  	 */
> -	return atomic_read(&engine->irq_count) == b->hangcheck_interrupts;
> +	return READ_ONCE(b->irq_count) == b->hangcheck_interrupts;
>  }
>  
>  static void enable_fake_irq(struct intel_breadcrumbs *b)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 8dd34b9dc18a..33602eb1c77f 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -356,7 +356,6 @@ struct intel_engine_cs {
>  	struct drm_i915_gem_object *default_state;
>  	void *pinned_default_state;
>  
> -	atomic_t irq_count;
>  	unsigned long irq_posted;
>  #define ENGINE_IRQ_BREADCRUMB 0
>  
> @@ -390,6 +389,7 @@ struct intel_engine_cs {
>  
>  		unsigned int hangcheck_interrupts;
>  		unsigned int irq_enabled;
> +		unsigned int irq_count;
>  
>  		bool irq_armed : 1;
>  		I915_SELFTEST_DECLARE(bool mock : 1);
> -- 
> 2.18.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2018-06-27 14:24 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-25  9:48 [PATCH 01/31] drm/i915: Defer modeset cleanup to a secondary task Chris Wilson
2018-06-25  9:48 ` [PATCH 02/31] drm/i915/execlists: Check for ce->state before destroy Chris Wilson
2018-06-25  9:48 ` [PATCH 03/31] drm/i915/execlists: Pull submit after dequeue under timeline lock Chris Wilson
2018-06-25 10:51   ` Tvrtko Ursulin
2018-06-25 10:55     ` Chris Wilson
2018-06-25  9:48 ` [PATCH 04/31] drm/i915/execlists: Pull CSB reset under the timeline.lock Chris Wilson
2018-06-26 10:59   ` Tvrtko Ursulin
2018-06-26 11:04     ` Chris Wilson
2018-06-26 11:50   ` [PATCH v4] " Chris Wilson
2018-06-27  9:33     ` Tvrtko Ursulin
2018-06-25  9:48 ` [PATCH 05/31] drm/i915/execlists: Process one CSB update at a time Chris Wilson
2018-06-27  9:46   ` Tvrtko Ursulin
2018-06-27 10:26     ` Chris Wilson
2018-06-27 10:43   ` [PATCH v2] " Chris Wilson
2018-06-25  9:48 ` [PATCH 06/31] drm/i915/execlists: Unify CSB access pointers Chris Wilson
2018-06-27  9:52   ` Tvrtko Ursulin
2018-06-27 10:35     ` Chris Wilson
2018-06-27 13:03       ` Tvrtko Ursulin
2018-06-27 13:09         ` Chris Wilson
2018-06-27 13:24           ` Tvrtko Ursulin
2018-06-27 13:32             ` Chris Wilson
2018-06-27 11:21     ` [PATCH] drm/i915/execlists: Reset CSB write pointer after reset Chris Wilson
2018-06-25  9:48 ` [PATCH 07/31] drm/i915/execlists: Direct submission of new requests (avoid tasklet/ksoftirqd) Chris Wilson
2018-06-27 10:40   ` Tvrtko Ursulin
2018-06-27 10:58     ` Chris Wilson
2018-06-27 13:15       ` Tvrtko Ursulin
2018-06-27 13:29         ` Chris Wilson
2018-06-27 15:21           ` Tvrtko Ursulin
2018-06-27 15:28             ` Chris Wilson
2018-06-28 11:56               ` Tvrtko Ursulin
2018-06-28 12:07                 ` Chris Wilson
2018-06-28 12:11                   ` Chris Wilson
2018-06-28 12:29                     ` Tvrtko Ursulin
2018-06-28 12:35                       ` Chris Wilson
2018-06-28 13:03                         ` Tvrtko Ursulin
2018-06-25  9:48 ` [PATCH 08/31] drm/i915: Move rate-limiting request retire to after submission Chris Wilson
2018-06-27 10:57   ` Tvrtko Ursulin
2018-06-27 11:16     ` Chris Wilson
2018-06-27 13:28       ` Tvrtko Ursulin
2018-06-27 13:37         ` Chris Wilson
2018-06-25  9:48 ` [PATCH 09/31] drm/i915: Wait for engines to idle before retiring Chris Wilson
2018-06-27 11:32   ` Tvrtko Ursulin
2018-06-27 11:41     ` Chris Wilson
2018-06-25  9:48 ` [PATCH 10/31] drm/i915: Move engine request retirement to intel_engine_cs Chris Wilson
2018-06-25  9:48 ` [PATCH 11/31] drm/i915: Hold request reference for submission until retirement Chris Wilson
2018-06-25  9:48 ` [PATCH 12/31] drm/i915: Reduce spinlock hold time during notify_ring() interrupt Chris Wilson
2018-06-27 13:08   ` Mika Kuoppala
2018-06-27 13:14     ` Chris Wilson
2018-06-27 14:01       ` Mika Kuoppala
2018-06-25  9:48 ` [PATCH 13/31] drm/i915: Move the irq_counter inside the spinlock Chris Wilson
2018-06-27 14:23   ` Mika Kuoppala [this message]
2018-06-25  9:48 ` [PATCH 14/31] drm/i915: Only signal from interrupt when requested Chris Wilson
2018-06-27 14:52   ` Mika Kuoppala
2018-06-25  9:48 ` [PATCH 15/31] drm/i915/execlists: Switch to rb_root_cached Chris Wilson
2018-06-25  9:48 ` [PATCH 16/31] drm/i915: Reserve some priority bits for internal use Chris Wilson
2018-06-25  9:48 ` [PATCH 17/31] drm/i915: Combine multiple internal plists into the same i915_priolist bucket Chris Wilson
2018-06-25  9:48 ` [PATCH 18/31] drm/i915: Priority boost for new clients Chris Wilson
2018-06-25  9:48 ` [PATCH 19/31] drm/i915: Priority boost switching to an idle ring Chris Wilson
2018-06-25  9:48 ` [PATCH 20/31] drm/i915: Refactor export_fence() after i915_vma_move_to_active() Chris Wilson
2018-06-25  9:48 ` [PATCH 21/31] drm/i915: Export i915_request_skip() Chris Wilson
2018-06-25  9:48 ` [PATCH 22/31] drm/i915: Start returning an error from i915_vma_move_to_active() Chris Wilson
2018-06-25  9:48 ` [PATCH 23/31] drm/i915: Track vma activity per fence.context, not per engine Chris Wilson
2018-06-25  9:48 ` [PATCH 24/31] drm/i915: Track the last-active inside the i915_vma Chris Wilson
2018-06-25  9:48 ` [PATCH 25/31] drm/i915: Stop tracking MRU activity on VMA Chris Wilson
2018-06-25  9:48 ` [PATCH 26/31] drm/i915: Introduce i915_address_space.mutex Chris Wilson
2018-06-25  9:48 ` [PATCH 27/31] drm/i915: Move fence register tracking to GGTT Chris Wilson
2018-06-25  9:48 ` [PATCH 28/31] drm/i915: Convert fences to use a GGTT lock rather than struct_mutex Chris Wilson
2018-06-25  9:48 ` [PATCH 29/31] drm/i915: Tidy i915_gem_suspend() Chris Wilson
2018-06-25  9:48 ` [PATCH 30/31] drm/i915: Pull all the reset functionality together into i915_reset.c Chris Wilson
2018-06-25  9:48 ` [PATCH 31/31] drm/i915: Remove GPU reset dependence on struct_mutex Chris Wilson
2018-06-25 10:32 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/31] drm/i915: Defer modeset cleanup to a secondary task Patchwork
2018-06-25 10:44 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-06-25 10:57 ` ✓ Fi.CI.BAT: success " Patchwork
2018-06-25 14:44 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-06-26  9:28   ` Chris Wilson
2018-06-26 11:51 ` ✗ Fi.CI.BAT: failure for series starting with [01/31] drm/i915: Defer modeset cleanup to a secondary task (rev2) Patchwork
2018-06-27 11:00 ` ✗ Fi.CI.BAT: failure for series starting with [01/31] drm/i915: Defer modeset cleanup to a secondary task (rev3) Patchwork
2018-06-27 12:27 ` ✗ Fi.CI.BAT: failure for series starting with [01/31] drm/i915: Defer modeset cleanup to a secondary task (rev4) Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=87bmbwux34.fsf@gaia.fi.intel.com \
    --to=mika.kuoppala@linux.intel.com \
    --cc=chris@chris-wilson.co.uk \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.