Re: [Qemu-devel] [PATCH v11 00/20] tcg: generic vector operations

["Alex Bennée" <alex.bennee@linaro.org>]

Richard Henderson <richard.henderson@linaro.org> writes:

> Changes since v11:
>   * Use dup_const more.
>   * Cleanup some gvec 2i and 2s routines.
>   * Use more helpers and less gotos in target/arm/translate-a64.c.

I just noticed the aarch64 cross build breaks:

n file included from /root/src/github.com/stsquad/qemu/tcg/tcg.c:296:0:
/root/src/github.com/stsquad/qemu/tcg/aarch64/tcg-target.inc.c: In function 'tcg_out_dupi_vec':
/root/src/github.com/stsquad/qemu/tcg/aarch64/tcg-target.inc.c:806:9: error: implicit declaration of function 'new_pool_l2' [-Werror=implicit-function-declaration]
         new_pool_l2(s, R_AARCH64_CONDBR19, s->code_ptr, 0, v64, v64);

>
> Changes since v10:
>   * Squashed a fixup patch which escaped my attention while preparing
>     the patch set.  Ho hum.
>
> Changes since v9:
>   * Detect whether __attribute__((vector_size(16))) operations are
>     supported by the host compiler.  This includes the case affecting
>     ppc64 where gcc-4.8.5 crashes.  Note that gcc-7.2 does pass the
>     test on ppc64.
>
>   * Dropped support for vector interleaves and element size changes.
>     My target/arm patches were failing RISU checks on a big-endian host.
>     I need to re-think what to do about host endianness and target
>     representation of vector operations crossing lanes.  For now, only
>     support generic vector operations that are agnostic to element order.
>
>
> r~
>
>
> Richard Henderson (20):
>   tcg: Allow multiple word entries into the constant pool
>   tcg: Add types and basic operations for host vectors
>   tcg: Standardize integral arguments to expanders
>   tcg: Add generic vector expanders
>   tcg: Add generic vector ops for constant shifts
>   tcg: Add generic vector ops for comparisons
>   tcg: Add generic vector ops for multiplication
>   tcg: Add generic helpers for saturating arithmetic
>   tcg: Add generic vector helpers with a scalar operand
>   tcg/optimize: Handle vector opcodes during optimize
>   target/arm: Align vector registers
>   target/arm: Use vector infrastructure for aa64 add/sub/logic
>   target/arm: Use vector infrastructure for aa64 mov/not/neg
>   target/arm: Use vector infrastructure for aa64 dup/movi
>   target/arm: Use vector infrastructure for aa64 constant shifts
>   target/arm: Use vector infrastructure for aa64 compares
>   target/arm: Use vector infrastructure for aa64 multiplies
>   target/arm: Use vector infrastructure for aa64 orr/bic immediate
>   tcg/i386: Add vector operations
>   tcg/aarch64: Add vector operations
>
>  Makefile.target              |    4 +-
<snip>

--
Alex Bennée