From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org
Subject: Re: [Qemu-devel] [PATCH v11 03/20] tcg: Standardize integral arguments to expanders
Date: Tue, 06 Feb 2018 08:57:22 +0000 [thread overview]
Message-ID: <87y3k6wl59.fsf@linaro.org> (raw)
In-Reply-To: <20180126045742.5487-4-richard.henderson@linaro.org>
Richard Henderson <richard.henderson@linaro.org> writes:
> Some functions use intN_t arguments, some use uintN_t, some just
> used "unsigned". To aid putting function pointers in tables, we
> need consistency.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
I was a bit confused by converting unsigned into int64_t but I see the
asserts ensure they are all still positives and you need the same types
if you are going to mix things like "and" with "shr" in the same table.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> tcg/tcg-op.h | 16 ++++++++--------
> tcg/tcg-op.c | 42 +++++++++++++++++++++---------------------
> 2 files changed, 29 insertions(+), 29 deletions(-)
>
> diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
> index 0c02d86b8b..a684ab5890 100644
> --- a/tcg/tcg-op.h
> +++ b/tcg/tcg-op.h
> @@ -269,12 +269,12 @@ void tcg_gen_mb(TCGBar);
> void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
> void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2);
> void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
> -void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
> +void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
> void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
> void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
> -void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
> -void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
> -void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
> +void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
> +void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
> +void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
> void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
> void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
> void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
> @@ -458,12 +458,12 @@ static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
> void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
> void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2);
> void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
> -void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
> +void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
> void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
> void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
> -void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
> -void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
> -void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
> +void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
> +void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
> +void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
> void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
> void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
> void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
> diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
> index 0c509bfe46..3467787323 100644
> --- a/tcg/tcg-op.c
> +++ b/tcg/tcg-op.c
> @@ -140,7 +140,7 @@ void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
> }
> }
>
> -void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2)
> +void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
> {
> TCGv_i32 t0;
> /* Some cases can be optimized here. */
> @@ -148,17 +148,17 @@ void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2)
> case 0:
> tcg_gen_movi_i32(ret, 0);
> return;
> - case 0xffffffffu:
> + case -1:
> tcg_gen_mov_i32(ret, arg1);
> return;
> - case 0xffu:
> + case 0xff:
> /* Don't recurse with tcg_gen_ext8u_i32. */
> if (TCG_TARGET_HAS_ext8u_i32) {
> tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg1);
> return;
> }
> break;
> - case 0xffffu:
> + case 0xffff:
> if (TCG_TARGET_HAS_ext16u_i32) {
> tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg1);
> return;
> @@ -199,9 +199,9 @@ void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
> }
> }
>
> -void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2)
> +void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
> {
> - tcg_debug_assert(arg2 < 32);
> + tcg_debug_assert(arg2 >= 0 && arg2 < 32);
> if (arg2 == 0) {
> tcg_gen_mov_i32(ret, arg1);
> } else {
> @@ -211,9 +211,9 @@ void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2)
> }
> }
>
> -void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2)
> +void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
> {
> - tcg_debug_assert(arg2 < 32);
> + tcg_debug_assert(arg2 >= 0 && arg2 < 32);
> if (arg2 == 0) {
> tcg_gen_mov_i32(ret, arg1);
> } else {
> @@ -223,9 +223,9 @@ void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2)
> }
> }
>
> -void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2)
> +void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
> {
> - tcg_debug_assert(arg2 < 32);
> + tcg_debug_assert(arg2 >= 0 && arg2 < 32);
> if (arg2 == 0) {
> tcg_gen_mov_i32(ret, arg1);
> } else {
> @@ -1201,7 +1201,7 @@ void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
> }
> }
>
> -void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
> +void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
> {
> TCGv_i64 t0;
>
> @@ -1216,23 +1216,23 @@ void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
> case 0:
> tcg_gen_movi_i64(ret, 0);
> return;
> - case 0xffffffffffffffffull:
> + case -1:
> tcg_gen_mov_i64(ret, arg1);
> return;
> - case 0xffull:
> + case 0xff:
> /* Don't recurse with tcg_gen_ext8u_i64. */
> if (TCG_TARGET_HAS_ext8u_i64) {
> tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg1);
> return;
> }
> break;
> - case 0xffffu:
> + case 0xffff:
> if (TCG_TARGET_HAS_ext16u_i64) {
> tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg1);
> return;
> }
> break;
> - case 0xffffffffull:
> + case 0xffffffffu:
> if (TCG_TARGET_HAS_ext32u_i64) {
> tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg1);
> return;
> @@ -1332,9 +1332,9 @@ static inline void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1,
> }
> }
>
> -void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2)
> +void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
> {
> - tcg_debug_assert(arg2 < 64);
> + tcg_debug_assert(arg2 >= 0 && arg2 < 64);
> if (TCG_TARGET_REG_BITS == 32) {
> tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
> } else if (arg2 == 0) {
> @@ -1346,9 +1346,9 @@ void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2)
> }
> }
>
> -void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2)
> +void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
> {
> - tcg_debug_assert(arg2 < 64);
> + tcg_debug_assert(arg2 >= 0 && arg2 < 64);
> if (TCG_TARGET_REG_BITS == 32) {
> tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
> } else if (arg2 == 0) {
> @@ -1360,9 +1360,9 @@ void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2)
> }
> }
>
> -void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2)
> +void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
> {
> - tcg_debug_assert(arg2 < 64);
> + tcg_debug_assert(arg2 >= 0 && arg2 < 64);
> if (TCG_TARGET_REG_BITS == 32) {
> tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
> } else if (arg2 == 0) {
--
Alex Bennée
next prev parent reply other threads:[~2018-02-06 8:57 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-26 4:57 [Qemu-devel] [PATCH v11 00/20] tcg: generic vector operations Richard Henderson
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 01/20] tcg: Allow multiple word entries into the constant pool Richard Henderson
2018-02-06 8:51 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 02/20] tcg: Add types and basic operations for host vectors Richard Henderson
2018-02-06 8:53 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 03/20] tcg: Standardize integral arguments to expanders Richard Henderson
2018-02-06 8:57 ` Alex Bennée [this message]
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 04/20] tcg: Add generic vector expanders Richard Henderson
2018-02-06 10:59 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 05/20] tcg: Add generic vector ops for constant shifts Richard Henderson
2018-02-06 11:00 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 06/20] tcg: Add generic vector ops for comparisons Richard Henderson
2018-02-06 11:01 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 07/20] tcg: Add generic vector ops for multiplication Richard Henderson
2018-02-06 11:02 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 08/20] tcg: Add generic helpers for saturating arithmetic Richard Henderson
2018-02-06 11:03 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 09/20] tcg: Add generic vector helpers with a scalar operand Richard Henderson
2018-02-06 11:04 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 10/20] tcg/optimize: Handle vector opcodes during optimize Richard Henderson
2018-02-06 11:07 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 11/20] target/arm: Align vector registers Richard Henderson
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 12/20] target/arm: Use vector infrastructure for aa64 add/sub/logic Richard Henderson
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 13/20] target/arm: Use vector infrastructure for aa64 mov/not/neg Richard Henderson
2018-02-06 11:08 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 14/20] target/arm: Use vector infrastructure for aa64 dup/movi Richard Henderson
2018-02-06 11:09 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 15/20] target/arm: Use vector infrastructure for aa64 constant shifts Richard Henderson
2018-02-05 11:14 ` Peter Maydell
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 16/20] target/arm: Use vector infrastructure for aa64 compares Richard Henderson
2018-02-06 11:10 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 17/20] target/arm: Use vector infrastructure for aa64 multiplies Richard Henderson
2018-02-06 11:11 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 18/20] target/arm: Use vector infrastructure for aa64 orr/bic immediate Richard Henderson
2018-02-06 11:13 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 19/20] tcg/i386: Add vector operations Richard Henderson
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 20/20] tcg/aarch64: " Richard Henderson
2018-02-06 11:15 ` Alex Bennée
2018-01-26 17:25 ` [Qemu-devel] [PATCH v11 00/20] tcg: generic " no-reply
2018-02-06 11:24 ` Alex Bennée
2018-02-06 12:07 ` Philippe Mathieu-Daudé
2018-02-06 12:36 ` Alex Bennée
2018-02-06 16:24 ` Alex Bennée
2018-02-06 20:57 ` Alex Bennée
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