From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <rth@twiddle.net>
Cc: pbonzini@redhat.com, qemu-devel@nongnu.org, mttcg@greensocs.com,
fred.konrad@greensocs.com, a.rigo@virtualopensystems.com,
cota@braap.org, bobby.prani@gmail.com, nikunj@linux.vnet.ibm.com,
mark.burton@greensocs.com, jan.kiszka@siemens.com,
serge.fdrv@gmail.com, peter.maydell@linaro.org,
claudio.fontana@huawei.com,
"open list\:ARM" <qemu-arm@nongnu.org>
Subject: Re: [PATCH v5 30/33] target-arm/cpu: don't reset TLB structures, use cputlb to do it
Date: Fri, 28 Oct 2016 09:38:59 +0100 [thread overview]
Message-ID: <87bmy498bg.fsf@linaro.org> (raw)
In-Reply-To: <fa288bec-8178-590a-db42-abb4c6986db4@twiddle.net>
Richard Henderson <rth@twiddle.net> writes:
> On 10/27/2016 08:10 AM, Alex Bennée wrote:
>> cputlb owns the TLB entries and knows how to safely update them in
>> MTTCG.
>>
>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>> ---
>> target-arm/cpu.c | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
>> index 1b9540e..ff8c594 100644
>> --- a/target-arm/cpu.c
>> +++ b/target-arm/cpu.c
>> @@ -121,7 +121,13 @@ static void arm_cpu_reset(CPUState *s)
>>
>> acc->parent_reset(s);
>>
>> +#ifdef CONFIG_SOFTMMU
>> + memset(env, 0, offsetof(CPUARMState, tlb_table));
>> + tlb_flush(s, 0);
>> +#else
>> memset(env, 0, offsetof(CPUARMState, features));
>> +#endif
>> +
>
> Why special case this for softmmu?
I didn't want to move cpu->features to the other side of CPU_COMMON in
cpu.h as there is an explicit statement about being reset. Adding
another variable just to be an endpoint of a memset also seemed
sub-optimal.
> And don't we (or if not, shouldn't we)
> handle the tlb_flush generically for reset?
Probably. tlb_flush seems to be one of those things liberally sprinkled
in the arch code for all sorts of things but certainly cpu_reset is one
we could make the call from generic code.
>
>
> r~
--
Alex Bennée
WARNING: multiple messages have this Message-ID (diff)
From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <rth@twiddle.net>
Cc: pbonzini@redhat.com, qemu-devel@nongnu.org, mttcg@greensocs.com,
fred.konrad@greensocs.com, a.rigo@virtualopensystems.com,
cota@braap.org, bobby.prani@gmail.com, nikunj@linux.vnet.ibm.com,
mark.burton@greensocs.com, jan.kiszka@siemens.com,
serge.fdrv@gmail.com, peter.maydell@linaro.org,
claudio.fontana@huawei.com, "open list:ARM" <qemu-arm@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v5 30/33] target-arm/cpu: don't reset TLB structures, use cputlb to do it
Date: Fri, 28 Oct 2016 09:38:59 +0100 [thread overview]
Message-ID: <87bmy498bg.fsf@linaro.org> (raw)
In-Reply-To: <fa288bec-8178-590a-db42-abb4c6986db4@twiddle.net>
Richard Henderson <rth@twiddle.net> writes:
> On 10/27/2016 08:10 AM, Alex Bennée wrote:
>> cputlb owns the TLB entries and knows how to safely update them in
>> MTTCG.
>>
>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>> ---
>> target-arm/cpu.c | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
>> index 1b9540e..ff8c594 100644
>> --- a/target-arm/cpu.c
>> +++ b/target-arm/cpu.c
>> @@ -121,7 +121,13 @@ static void arm_cpu_reset(CPUState *s)
>>
>> acc->parent_reset(s);
>>
>> +#ifdef CONFIG_SOFTMMU
>> + memset(env, 0, offsetof(CPUARMState, tlb_table));
>> + tlb_flush(s, 0);
>> +#else
>> memset(env, 0, offsetof(CPUARMState, features));
>> +#endif
>> +
>
> Why special case this for softmmu?
I didn't want to move cpu->features to the other side of CPU_COMMON in
cpu.h as there is an explicit statement about being reset. Adding
another variable just to be an endpoint of a memset also seemed
sub-optimal.
> And don't we (or if not, shouldn't we)
> handle the tlb_flush generically for reset?
Probably. tlb_flush seems to be one of those things liberally sprinkled
in the arch code for all sorts of things but certainly cpu_reset is one
we could make the call from generic code.
>
>
> r~
--
Alex Bennée
next prev parent reply other threads:[~2016-10-28 8:38 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-27 15:09 [Qemu-devel] [PATCH v5 00/33] MTTCG Base Enabling patches with ARM on x86 defaults Alex Bennée
2016-10-27 15:09 ` [Qemu-devel] [PATCH v5 01/33] cpus: make all_vcpus_paused() return bool Alex Bennée
2016-10-27 15:09 ` [Qemu-devel] [PATCH v5 02/33] translate_all: DEBUG_FLUSH -> DEBUG_TB_FLUSH Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 03/33] translate-all: add DEBUG_LOCKING asserts Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 04/33] cpu-exec: include cpu_index in CPU_LOG_EXEC messages Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 05/33] docs: new design document multi-thread-tcg.txt (DRAFTING) Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 06/33] tcg: comment on which functions have to be called with tb_lock held Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 07/33] linux-user/elfload: ensure mmap_lock() held while setting up Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 08/33] translate-all: Add assert_(memory|tb)_lock annotations Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 09/33] tcg: protect translation related stuff with tb_lock Alex Bennée
2016-10-27 15:10 ` [PATCH v5 10/33] target-arm/arm-powerctl: wake up sleeping CPUs Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] " Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 11/33] tcg: move tcg_exec_all and helpers above thread fn Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 12/33] tcg: cpus rm tcg_exec_all() Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 13/33] tcg: add options for enabling MTTCG Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 14/33] tcg: add kick timer for single-threaded vCPU emulation Alex Bennée
2016-10-27 15:30 ` KONRAD Frederic
2016-10-27 15:35 ` Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 15/33] tcg: rename tcg_current_cpu to tcg_current_rr_cpu Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 16/33] tcg: drop global lock during TCG code execution Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 17/33] cpus: re-factor out handle_icount_deadline Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 18/33] tcg: remove global exit_request Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 19/33] tcg: move locking for tb_invalidate_phys_page_range up Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 20/33] tcg: enable tb_lock() for SoftMMU Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 21/33] tcg: enable thread-per-vCPU Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 22/33] atomic: introduce cmpxchg_bool Alex Bennée
2016-10-27 15:10 ` [PATCH v5 23/33] *_run_on_cpu: introduce run_on_cpu_data type Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] " Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 24/33] cputlb: add assert_cpu_is_self checks Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 25/33] cputlb: introduce tlb_flush_* async work Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 26/33] cputlb: tweak qemu_ram_addr_from_host_nofail reporting Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 27/33] cputlb: atomically update tlb fields used by tlb_reset_dirty Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 28/33] cputlb: make tlb_flush_by_mmuidx safe for MTTCG Alex Bennée
2016-11-01 5:20 ` Pranith Kumar
2016-11-01 7:45 ` Alex Bennée
2016-11-01 8:03 ` Peter Maydell
2016-11-01 13:22 ` Pranith Kumar
2016-11-01 16:53 ` Alex Bennée
2016-10-27 15:10 ` [PATCH v5 29/33] target-arm/powerctl: defer cpu reset work to CPU context Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] " Alex Bennée
2016-10-27 15:10 ` [PATCH v5 30/33] target-arm/cpu: don't reset TLB structures, use cputlb to do it Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] " Alex Bennée
2016-10-27 16:10 ` Richard Henderson
2016-10-27 16:10 ` [Qemu-devel] " Richard Henderson
2016-10-28 8:38 ` Alex Bennée [this message]
2016-10-28 8:38 ` Alex Bennée
2016-10-28 9:07 ` Peter Maydell
2016-10-28 9:07 ` [Qemu-devel] " Peter Maydell
2016-10-28 9:17 ` Alex Bennée
2016-10-28 9:17 ` [Qemu-devel] " Alex Bennée
2016-10-27 15:10 ` [PATCH v5 31/33] target-arm: ensure BQL taken for ARM_CP_IO register access Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] " Alex Bennée
2016-10-27 15:10 ` [PATCH v5 32/33] target-arm: helpers which may affect global state need the BQL Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] " Alex Bennée
2016-10-27 15:10 ` [Qemu-devel] [PATCH v5 33/33] tcg: enable MTTCG by default for ARM on x86 hosts Alex Bennée
2016-10-31 8:03 ` [Qemu-devel] [PATCH v5 00/33] MTTCG Base Enabling patches with ARM on x86 defaults Alex Bennée
2016-10-31 8:48 ` Paolo Bonzini
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