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* [Intel-gfx] [PATCH 0/3] Implement CMRR Support
@ 2023-11-22  6:59 Mitul Golani
  2023-11-22  6:59 ` [Intel-gfx] [PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
                   ` (7 more replies)
  0 siblings, 8 replies; 13+ messages in thread
From: Mitul Golani @ 2023-11-22  6:59 UTC (permalink / raw)
  To: intel-gfx

CMRR is a display feature that uses adaptive sync
framework to vary Vtotal slightly to match the
content rate exactly without frame drops. This
feature is a variation of VRR where it varies Vtotal
slightly (between additional 0 and 1 Vtotal scanlines)
to match content rate exactly without frame drops
using the adaptive sync framework.

enable this feature by programing new registers for
CMRR enable, CMRR_M, CMRR_N, vmin=vmax=flipline.The
CMRR_M/CMRR_N ratio represents the fractional part
in (actual refresh rate/target refresh rate) * origVTotal.

Mitul Golani (3):
  drm/i915: Define and compute Transcoder CMRR registers
  drm/i915: Add Enable/Disable for CMRR based on VRR state
  drm/i915: Compute CMRR and calculate vtotal

 .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  54 +++++++-
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_types.h    |   6 +
 drivers/gpu/drm/i915/display/intel_vrr.c      | 129 ++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h               |  10 ++
 6 files changed, 184 insertions(+), 20 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 0/3] Implement CMRR Support
@ 2023-12-05 18:36 Mitul Golani
  0 siblings, 0 replies; 13+ messages in thread
From: Mitul Golani @ 2023-12-05 18:36 UTC (permalink / raw)
  To: intel-gfx

CMRR is a display feature that uses adaptive sync
framework to vary Vtotal slightly to match the
content rate exactly without frame drops. This
feature is a variation of VRR where it varies Vtotal
slightly (between additional 0 and 1 Vtotal scanlines)
to match content rate exactly without frame drops
using the adaptive sync framework.

enable this feature by programing new registers for
CMRR enable, CMRR_M, CMRR_N, vmin=vmax=flipline.The
CMRR_M/CMRR_N ratio represents the fractional part
in (actual refresh rate/target refresh rate) * origVTotal.

--v6:
- CMRR handling in co-existatnce of LRR and DRRS
- Correct vtotal paramas accuracy and add 2 digit precision.

Mitul Golani (3):
  drm/i915: Define and compute Transcoder CMRR registers
  drm/i915: Add Enable/Disable for CMRR based on VRR state
  drm/i915: Compute CMRR and calculate vtotal

 .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  61 +++++++-
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_types.h    |   6 +
 drivers/gpu/drm/i915/display/intel_vrr.c      | 136 ++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h               |  10 ++
 6 files changed, 197 insertions(+), 21 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 0/3] Implement CMRR Support
@ 2023-11-21 17:35 Mitul Golani
  0 siblings, 0 replies; 13+ messages in thread
From: Mitul Golani @ 2023-11-21 17:35 UTC (permalink / raw)
  To: intel-gfx

CMRR is a display feature that uses adaptive sync
framework to vary Vtotal slightly to match the
content rate exactly without frame drops. This
feature is a variation of VRR where it varies Vtotal
slightly (between additional 0 and 1 Vtotal scanlines)
to match content rate exactly without frame drops
using the adaptive sync framework.

enable this feature by programing new registers for
CMRR enable, CMRR_M, CMRR_N, vmin=vmax=flipline.The
CMRR_M/CMRR_N ratio represents the fractional part
in (actual refresh rate/target refresh rate) * origVTotal.

Mitul Golani (3):
  drm/i915: Define and compute Transcoder CMRR registers
  drm/i915: Add Enable/Disable for CMRR based on VRR state
  drm/i915: Compute CMRR and calculate vtotal

 .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  54 +++++++-
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_types.h    |   6 +
 drivers/gpu/drm/i915/display/intel_vrr.c      | 126 ++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h               |  10 ++
 6 files changed, 181 insertions(+), 20 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 0/3] Implement CMRR Support
@ 2023-11-15 13:43 Mitul Golani
  0 siblings, 0 replies; 13+ messages in thread
From: Mitul Golani @ 2023-11-15 13:43 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, ville.syrjala

CMRR is a display feature that uses adaptive sync
framework to vary Vtotal slightly to match the
content rate exactly without frame drops. This
feature is a variation of VRR where it varies Vtotal
slightly (between additional 0 and 1 Vtotal scanlines)
to match content rate exactly without frame drops
using the adaptive sync framework.

enable this feature by programing new registers for
CMRR enable, CMRR_M, CMRR_N, vmin=vmax=flipline.The
CMRR_M/CMRR_N ratio represents the fractional part
in (actual refresh rate/target refresh rate) * origVTotal.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>

Mitul Golani (3):
  drm/i915: Define and compute Transcoder CMRR registers
  drm/i915: Add Enable/Disable for CMRR based on VRR state
  drm/i915: Compute CMRR and calculate vtotal

 .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  51 ++++++-
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_types.h    |   6 +
 drivers/gpu/drm/i915/display/intel_vrr.c      | 126 ++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h               |  10 ++
 6 files changed, 178 insertions(+), 20 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 13+ messages in thread

end of thread, other threads:[~2023-12-05 18:41 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-11-22  6:59 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani
2023-11-22  6:59 ` [Intel-gfx] [PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
2023-11-22  6:59 ` [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state Mitul Golani
2023-11-22  6:59 ` [Intel-gfx] [PATCH 3/3] drm/i915: Compute CMRR and calculate vtotal Mitul Golani
2023-11-22  8:16 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Implement CMRR Support (rev5) Patchwork
2023-11-22  8:16 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-11-22  8:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-11-22 11:04 ` [Intel-gfx] [PATCH 0/3] Implement CMRR Support Jani Nikula
2023-11-22 11:05   ` Jani Nikula
2023-11-22 22:10 ` [Intel-gfx] ✓ Fi.CI.IGT: success for Implement CMRR Support (rev5) Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2023-12-05 18:36 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani
2023-11-21 17:35 Mitul Golani
2023-11-15 13:43 Mitul Golani

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