[PATCH 0/2] tcg: ppc64: Fix mask generation for vextractdm

[PATCH 0/2] tcg: ppc64: Fix mask generation for vextractdm

[Shivaprasad G Bhat]

While debugging gitlab issue[1] 1536, I happen to try the
vextract[X]m instructions on the real hardware. The test
used in [1] is failing for vextractdm.

On debugging it is seen, in function do_extractm() the
mask is calculated as dup_const(1 << (element_width - 1)).
'1' being signed int works fine for MO_8,16,32. For MO_64,
on PPC64 host this ends up becoming 0 on compilation. The
vextractdm uses MO_64, and it ends up having mask as 0.

The first patch here fixes that by explicitly using
1ULL instead of signed int 1 like its used everywhere else.
Second patch introduces the test case from [1] into qemu
tcg/ppc64 along with fixes/tweaks to make it work for both
big and little-endian targets.

Let me know if both patches should be squashed into single
patch. Checkpatch flagged me to avoid use of __BYTE_ORDER__
in the test file(second patch), however I see it being
used in multiarch/sha1.c also this being arch specific
test, I think it is appropriate to use it here. Let me
know if otherwise.

References:
[1] : https://gitlab.com/qemu-project/qemu/-/issues/1536

---

Shivaprasad G Bhat (2):
      tcg: ppc64: Fix mask generation for vextractdm
      tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions


 target/ppc/translate/vmx-impl.c.inc |  2 +-
 tests/tcg/ppc64/Makefile.target     |  6 +++-
 tests/tcg/ppc64/vector.c            | 50 +++++++++++++++++++++++++++++
 3 files changed, 56 insertions(+), 2 deletions(-)
 create mode 100644 tests/tcg/ppc64/vector.c

--
Signature

[PATCH 1/2] tcg: ppc64: Fix mask generation for vextractdm

[Shivaprasad G Bhat]

In function do_extractm() the mask is calculated as
dup_const(1 << (element_width - 1)). '1' being signed int
works fine for MO_8,16,32. For MO_64, on PPC64 host
this ends up becoming 0 on compilation. The vextractdm
uses MO_64, and it ends up having mask as 0.

Explicitly use 1ULL instead of signed int 1 like its
used everywhere else.

Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
---
 target/ppc/translate/vmx-impl.c.inc |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 112233b541..c8712dd7d8 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -2058,7 +2058,7 @@ static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a)
 static bool do_vextractm(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
 {
     const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece,
-                   mask = dup_const(vece, 1 << (elem_width - 1));
+                   mask = dup_const(vece, 1ULL << (elem_width - 1));
     uint64_t i, j;
     TCGv_i64 lo, hi, t0, t1;
 

Re: [PATCH 1/2] tcg: ppc64: Fix mask generation for vextractdm

[Alex Bennée]

Shivaprasad G Bhat <sbhat@linux.ibm.com> writes:

> In function do_extractm() the mask is calculated as
> dup_const(1 << (element_width - 1)). '1' being signed int
> works fine for MO_8,16,32. For MO_64, on PPC64 host
> this ends up becoming 0 on compilation. The vextractdm
> uses MO_64, and it ends up having mask as 0.
>
> Explicitly use 1ULL instead of signed int 1 like its
> used everywhere else.
>
> Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

-- 
Alex Bennée
Virtualisation Tech Lead @ Linaro

Re: [PATCH 1/2] tcg: ppc64: Fix mask generation for vextractdm

[Richard Henderson]

On 4/13/23 20:01, Shivaprasad G Bhat wrote:
> In function do_extractm() the mask is calculated as
> dup_const(1 << (element_width - 1)). '1' being signed int
> works fine for MO_8,16,32. For MO_64, on PPC64 host
> this ends up becoming 0 on compilation. The vextractdm
> uses MO_64, and it ends up having mask as 0.
> 
> Explicitly use 1ULL instead of signed int 1 like its
> used everywhere else.
> 
> Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
> ---
>   target/ppc/translate/vmx-impl.c.inc |    2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
> index 112233b541..c8712dd7d8 100644
> --- a/target/ppc/translate/vmx-impl.c.inc
> +++ b/target/ppc/translate/vmx-impl.c.inc
> @@ -2058,7 +2058,7 @@ static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a)
>   static bool do_vextractm(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
>   {
>       const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece,
> -                   mask = dup_const(vece, 1 << (elem_width - 1));
> +                   mask = dup_const(vece, 1ULL << (elem_width - 1));

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 1/2] tcg: ppc64: Fix mask generation for vextractdm

[Lucas Mateus Martins Araujo e Castro]

On 13/04/2023 16:01, Shivaprasad G Bhat wrote:

> In function do_extractm() the mask is calculated as
> dup_const(1 << (element_width - 1)). '1' being signed int
> works fine for MO_8,16,32. For MO_64, on PPC64 host
> this ends up becoming 0 on compilation. The vextractdm
> uses MO_64, and it ends up having mask as 0.
> 
> Explicitly use 1ULL instead of signed int 1 like its
> used everywhere else.
> 
> Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
> ---
>   target/ppc/translate/vmx-impl.c.inc |    2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
> index 112233b541..c8712dd7d8 100644
> --- a/target/ppc/translate/vmx-impl.c.inc
> +++ b/target/ppc/translate/vmx-impl.c.inc
> @@ -2058,7 +2058,7 @@ static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a)
>   static bool do_vextractm(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
>   {
>       const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece,
> -                   mask = dup_const(vece, 1 << (elem_width - 1));
> +                   mask = dup_const(vece, 1ULL << (elem_width - 1));
>       uint64_t i, j;
>       TCGv_i64 lo, hi, t0, t1;
> 
> 
> 

Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br>
-- 
Lucas Mateus M. Araujo e Castro
Instituto de Pesquisas ELDORADO
<https://www.eldorado.org.br/?utm_campaign=assinatura_de_e-mail&utm_medium=email&utm_source=RD+Station>
Departamento Computação Embarcada
Analista de Software Junior
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>

[PATCH 2/2] tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions

[Shivaprasad G Bhat]

Add test for vextractbm, vextractwm, vextractdm and vextractqm
instructions. Test works for both qemu-ppc64 and qemu-ppc64le.

Based on the test case written by John Platts posted at [1]

References:
[1]: https://gitlab.com/qemu-project/qemu/-/issues/1536

Signed-off-by: John Platts <john_platts@hotmail.com>
Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
---
 tests/tcg/ppc64/Makefile.target |    6 ++++-
 tests/tcg/ppc64/vector.c        |   50 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 55 insertions(+), 1 deletion(-)
 create mode 100644 tests/tcg/ppc64/vector.c

diff --git a/tests/tcg/ppc64/Makefile.target b/tests/tcg/ppc64/Makefile.target
index f081f1c683..4fd543ce28 100644
--- a/tests/tcg/ppc64/Makefile.target
+++ b/tests/tcg/ppc64/Makefile.target
@@ -20,7 +20,7 @@ PPC64_TESTS += mtfsf
 PPC64_TESTS += mffsce
 
 ifneq ($(CROSS_CC_HAS_POWER10),)
-PPC64_TESTS += byte_reverse sha512-vector
+PPC64_TESTS += byte_reverse sha512-vector vector
 endif
 byte_reverse: CFLAGS += -mcpu=power10
 run-byte_reverse: QEMU_OPTS+=-cpu POWER10
@@ -33,6 +33,10 @@ sha512-vector: sha512.c
 run-sha512-vector: QEMU_OPTS+=-cpu POWER10
 run-plugin-sha512-vector-with-%: QEMU_OPTS+=-cpu POWER10
 
+vector: CFLAGS += -mcpu=power10
+run-vector: QEMU_OPTS += -cpu POWER10
+run-plugin-vector-with-%: QEMU_OPTS += -cpu POWER10
+
 PPC64_TESTS += signal_save_restore_xer
 PPC64_TESTS += xxspltw
 
diff --git a/tests/tcg/ppc64/vector.c b/tests/tcg/ppc64/vector.c
new file mode 100644
index 0000000000..3cb2b88c87
--- /dev/null
+++ b/tests/tcg/ppc64/vector.c
@@ -0,0 +1,50 @@
+#include <assert.h>
+#include <stdint.h>
+
+int main(void)
+{
+    unsigned int result_wi;
+    vector unsigned char vbc_bi_src = { 0xFF, 0xFF, 0, 0xFF, 0xFF, 0xFF,
+                                        0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0,
+                                        0, 0xFF, 0xFF};
+    vector unsigned short vbc_hi_src = { 0xFFFF, 0, 0, 0xFFFF,
+                                         0, 0, 0xFFFF, 0xFFFF};
+    vector unsigned int vbc_wi_src = {0, 0, 0xFFFFFFFF, 0xFFFFFFFF};
+    vector unsigned long long vbc_di_src = {0xFFFFFFFFFFFFFFFF, 0};
+    vector __uint128_t vbc_qi_src;
+
+    asm("vextractbm %0, %1" : "=r" (result_wi) : "v" (vbc_bi_src));
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+    assert(result_wi == 0b1101111111000011);
+#else
+    assert(result_wi == 0b1100001111111011);
+#endif
+
+    asm("vextracthm %0, %1" : "=r" (result_wi) : "v" (vbc_hi_src));
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+    assert(result_wi == 0b10010011);
+#else
+    assert(result_wi == 0b11001001);
+#endif
+
+    asm("vextractwm %0, %1" : "=r" (result_wi) : "v" (vbc_wi_src));
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+    assert(result_wi == 0b0011);
+#else
+    assert(result_wi == 0b1100);
+#endif
+
+    asm("vextractdm %0, %1" : "=r" (result_wi) : "v" (vbc_di_src));
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+    assert(result_wi == 0b10);
+#else
+    assert(result_wi == 0b01);
+#endif
+
+    vbc_qi_src[0] = 0x1;
+    vbc_qi_src[0] = vbc_qi_src[0] << 127;
+    asm("vextractqm %0, %1" : "=r" (result_wi) : "v" (vbc_qi_src));
+    assert(result_wi == 0b1);
+
+    return 0;
+}

Re: [PATCH 2/2] tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions

[Cédric Le Goater]

On 4/13/23 21:01, Shivaprasad G Bhat wrote:
> Add test for vextractbm, vextractwm, vextractdm and vextractqm
> instructions. Test works for both qemu-ppc64 and qemu-ppc64le.
> 
> Based on the test case written by John Platts posted at [1]
> 
> References:
> [1]: https://gitlab.com/qemu-project/qemu/-/issues/1536

Gitlab issues should be referenced as :

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1536

However, this patch adds a test, not a fix. So it is the previous patch
which should be annotated as resolving the issue.

Also, I think the code should be using  HOST_BIG_ENDIAN instead of
__ORDER_BIG_ENDIAN__

Thanks,

C.

> 
> Signed-off-by: John Platts <john_platts@hotmail.com>
> Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
> ---
>   tests/tcg/ppc64/Makefile.target |    6 ++++-
>   tests/tcg/ppc64/vector.c        |   50 +++++++++++++++++++++++++++++++++++++++
>   2 files changed, 55 insertions(+), 1 deletion(-)
>   create mode 100644 tests/tcg/ppc64/vector.c
> 
> diff --git a/tests/tcg/ppc64/Makefile.target b/tests/tcg/ppc64/Makefile.target
> index f081f1c683..4fd543ce28 100644
> --- a/tests/tcg/ppc64/Makefile.target
> +++ b/tests/tcg/ppc64/Makefile.target
> @@ -20,7 +20,7 @@ PPC64_TESTS += mtfsf
>   PPC64_TESTS += mffsce
>   
>   ifneq ($(CROSS_CC_HAS_POWER10),)
> -PPC64_TESTS += byte_reverse sha512-vector
> +PPC64_TESTS += byte_reverse sha512-vector vector
>   endif
>   byte_reverse: CFLAGS += -mcpu=power10
>   run-byte_reverse: QEMU_OPTS+=-cpu POWER10
> @@ -33,6 +33,10 @@ sha512-vector: sha512.c
>   run-sha512-vector: QEMU_OPTS+=-cpu POWER10
>   run-plugin-sha512-vector-with-%: QEMU_OPTS+=-cpu POWER10
>   
> +vector: CFLAGS += -mcpu=power10
> +run-vector: QEMU_OPTS += -cpu POWER10
> +run-plugin-vector-with-%: QEMU_OPTS += -cpu POWER10
> +
>   PPC64_TESTS += signal_save_restore_xer
>   PPC64_TESTS += xxspltw
>   
> diff --git a/tests/tcg/ppc64/vector.c b/tests/tcg/ppc64/vector.c
> new file mode 100644
> index 0000000000..3cb2b88c87
> --- /dev/null
> +++ b/tests/tcg/ppc64/vector.c
> @@ -0,0 +1,50 @@
> +#include <assert.h>
> +#include <stdint.h>
> +
> +int main(void)
> +{
> +    unsigned int result_wi;
> +    vector unsigned char vbc_bi_src = { 0xFF, 0xFF, 0, 0xFF, 0xFF, 0xFF,
> +                                        0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0,
> +                                        0, 0xFF, 0xFF};
> +    vector unsigned short vbc_hi_src = { 0xFFFF, 0, 0, 0xFFFF,
> +                                         0, 0, 0xFFFF, 0xFFFF};
> +    vector unsigned int vbc_wi_src = {0, 0, 0xFFFFFFFF, 0xFFFFFFFF};
> +    vector unsigned long long vbc_di_src = {0xFFFFFFFFFFFFFFFF, 0};
> +    vector __uint128_t vbc_qi_src;
> +
> +    asm("vextractbm %0, %1" : "=r" (result_wi) : "v" (vbc_bi_src));
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +    assert(result_wi == 0b1101111111000011);
> +#else
> +    assert(result_wi == 0b1100001111111011);
> +#endif
> +
> +    asm("vextracthm %0, %1" : "=r" (result_wi) : "v" (vbc_hi_src));
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +    assert(result_wi == 0b10010011);
> +#else
> +    assert(result_wi == 0b11001001);
> +#endif
> +
> +    asm("vextractwm %0, %1" : "=r" (result_wi) : "v" (vbc_wi_src));
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +    assert(result_wi == 0b0011);
> +#else
> +    assert(result_wi == 0b1100);
> +#endif
> +
> +    asm("vextractdm %0, %1" : "=r" (result_wi) : "v" (vbc_di_src));
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +    assert(result_wi == 0b10);
> +#else
> +    assert(result_wi == 0b01);
> +#endif
> +
> +    vbc_qi_src[0] = 0x1;
> +    vbc_qi_src[0] = vbc_qi_src[0] << 127;
> +    asm("vextractqm %0, %1" : "=r" (result_wi) : "v" (vbc_qi_src));
> +    assert(result_wi == 0b1);
> +
> +    return 0;
> +}
> 
> 

Re: [PATCH 2/2] tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions

[Shivaprasad G Bhat]

On 5/2/23 12:35, Cédric Le Goater wrote:
> On 4/13/23 21:01, Shivaprasad G Bhat wrote:
>> Add test for vextractbm, vextractwm, vextractdm and vextractqm
>> instructions. Test works for both qemu-ppc64 and qemu-ppc64le.
>>
>> Based on the test case written by John Platts posted at [1]
>>
>> References:
>> [1]: https://gitlab.com/qemu-project/qemu/-/issues/1536
>
> Gitlab issues should be referenced as :
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1536
>
> However, this patch adds a test, not a fix. So it is the previous patch
> which should be annotated as resolving the issue.
>
> Also, I think the code should be using  HOST_BIG_ENDIAN instead of
> __ORDER_BIG_ENDIAN__
>
Thanks for the comments Cédric.

Fixing these in v2.

Thanks,

Shivaprasad

Re: [PATCH 2/2] tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions

[Lucas Mateus Martins Araujo e Castro]

On 13/04/2023 16:01, Shivaprasad G Bhat wrote:

> Add test for vextractbm, vextractwm, vextractdm and vextractqm
> instructions. Test works for both qemu-ppc64 and qemu-ppc64le.
> 
> Based on the test case written by John Platts posted at [1]
> 
> References:
> [1]: https://gitlab.com/qemu-project/qemu/-/issues/1536
> 
> Signed-off-by: John Platts <john_platts@hotmail.com>
> Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
> ---
>   tests/tcg/ppc64/Makefile.target |    6 ++++-
>   tests/tcg/ppc64/vector.c        |   50 +++++++++++++++++++++++++++++++++++++++
>   2 files changed, 55 insertions(+), 1 deletion(-)
>   create mode 100644 tests/tcg/ppc64/vector.c
> 
> diff --git a/tests/tcg/ppc64/Makefile.target b/tests/tcg/ppc64/Makefile.target
> index f081f1c683..4fd543ce28 100644
> --- a/tests/tcg/ppc64/Makefile.target
> +++ b/tests/tcg/ppc64/Makefile.target
> @@ -20,7 +20,7 @@ PPC64_TESTS += mtfsf
>   PPC64_TESTS += mffsce
> 
>   ifneq ($(CROSS_CC_HAS_POWER10),)
> -PPC64_TESTS += byte_reverse sha512-vector
> +PPC64_TESTS += byte_reverse sha512-vector vector
>   endif
>   byte_reverse: CFLAGS += -mcpu=power10
>   run-byte_reverse: QEMU_OPTS+=-cpu POWER10
> @@ -33,6 +33,10 @@ sha512-vector: sha512.c
>   run-sha512-vector: QEMU_OPTS+=-cpu POWER10
>   run-plugin-sha512-vector-with-%: QEMU_OPTS+=-cpu POWER10
> 
> +vector: CFLAGS += -mcpu=power10
> +run-vector: QEMU_OPTS += -cpu POWER10
> +run-plugin-vector-with-%: QEMU_OPTS += -cpu POWER10
> +
>   PPC64_TESTS += signal_save_restore_xer
>   PPC64_TESTS += xxspltw
> 
> diff --git a/tests/tcg/ppc64/vector.c b/tests/tcg/ppc64/vector.c
> new file mode 100644
> index 0000000000..3cb2b88c87
> --- /dev/null
> +++ b/tests/tcg/ppc64/vector.c
> @@ -0,0 +1,50 @@
> +#include <assert.h>
> +#include <stdint.h>
> +
> +int main(void)
> +{
> +    unsigned int result_wi;
> +    vector unsigned char vbc_bi_src = { 0xFF, 0xFF, 0, 0xFF, 0xFF, 0xFF,
> +                                        0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0,
> +                                        0, 0xFF, 0xFF};
> +    vector unsigned short vbc_hi_src = { 0xFFFF, 0, 0, 0xFFFF,
> +                                         0, 0, 0xFFFF, 0xFFFF};
> +    vector unsigned int vbc_wi_src = {0, 0, 0xFFFFFFFF, 0xFFFFFFFF};
> +    vector unsigned long long vbc_di_src = {0xFFFFFFFFFFFFFFFF, 0};
> +    vector __uint128_t vbc_qi_src;
> +
> +    asm("vextractbm %0, %1" : "=r" (result_wi) : "v" (vbc_bi_src));
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +    assert(result_wi == 0b1101111111000011);
> +#else
> +    assert(result_wi == 0b1100001111111011);
> +#endif
> +
> +    asm("vextracthm %0, %1" : "=r" (result_wi) : "v" (vbc_hi_src));
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +    assert(result_wi == 0b10010011);
> +#else
> +    assert(result_wi == 0b11001001);
> +#endif
> +
> +    asm("vextractwm %0, %1" : "=r" (result_wi) : "v" (vbc_wi_src));
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +    assert(result_wi == 0b0011);
> +#else
> +    assert(result_wi == 0b1100);
> +#endif
> +
> +    asm("vextractdm %0, %1" : "=r" (result_wi) : "v" (vbc_di_src));
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +    assert(result_wi == 0b10);
> +#else
> +    assert(result_wi == 0b01);
> +#endif
> +
> +    vbc_qi_src[0] = 0x1;
> +    vbc_qi_src[0] = vbc_qi_src[0] << 127;
> +    asm("vextractqm %0, %1" : "=r" (result_wi) : "v" (vbc_qi_src));
> +    assert(result_wi == 0b1);
> +
> +    return 0;
> +}
> 
> 

Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br>
-- 
Lucas Mateus M. Araujo e Castro
Instituto de Pesquisas ELDORADO
<https://www.eldorado.org.br/?utm_campaign=assinatura_de_e-mail&utm_medium=email&utm_source=RD+Station>
Departamento Computação Embarcada
Analista de Software Junior
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>

Re: [PATCH 0/2] tcg: ppc64: Fix mask generation for vextractdm

[Daniel Henrique Barboza]

Shiva,

I just queued patch 1 adding this line in the commit msg:

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1536

This was mentioned by Cedric in patch 2. Also, speaking of patch 2, take a look
on Cedric's review and see if it's applicable or not.

I plan to send a ppc pull request at the end of the week.


Thanks,


Daniel


On 4/13/23 16:00, Shivaprasad G Bhat wrote:
> While debugging gitlab issue[1] 1536, I happen to try the
> vextract[X]m instructions on the real hardware. The test
> used in [1] is failing for vextractdm.
> 
> On debugging it is seen, in function do_extractm() the
> mask is calculated as dup_const(1 << (element_width - 1)).
> '1' being signed int works fine for MO_8,16,32. For MO_64,
> on PPC64 host this ends up becoming 0 on compilation. The
> vextractdm uses MO_64, and it ends up having mask as 0.
> 
> The first patch here fixes that by explicitly using
> 1ULL instead of signed int 1 like its used everywhere else.
> Second patch introduces the test case from [1] into qemu
> tcg/ppc64 along with fixes/tweaks to make it work for both
> big and little-endian targets.
> 
> Let me know if both patches should be squashed into single
> patch. Checkpatch flagged me to avoid use of __BYTE_ORDER__
> in the test file(second patch), however I see it being
> used in multiarch/sha1.c also this being arch specific
> test, I think it is appropriate to use it here. Let me
> know if otherwise.
> 
> References:
> [1] : https://gitlab.com/qemu-project/qemu/-/issues/1536
> 
> ---
> 
> Shivaprasad G Bhat (2):
>        tcg: ppc64: Fix mask generation for vextractdm
>        tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions
> 
> 
>   target/ppc/translate/vmx-impl.c.inc |  2 +-
>   tests/tcg/ppc64/Makefile.target     |  6 +++-
>   tests/tcg/ppc64/vector.c            | 50 +++++++++++++++++++++++++++++
>   3 files changed, 56 insertions(+), 2 deletions(-)
>   create mode 100644 tests/tcg/ppc64/vector.c
> 
> --
> Signature
>