From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 5/9] drm/i915: Clean up PCH_TRANSCONF/TRANS_DP_CTL bit defines
Date: Wed, 26 Jan 2022 16:40:07 +0200 [thread overview]
Message-ID: <87czkezhko.fsf@intel.com> (raw)
In-Reply-To: <20211112193813.8224-6-ville.syrjala@linux.intel.com>
On Fri, 12 Nov 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use REG_BIT & co. for PCH_TRANSCONF/TRANS_DP_CTL bits, and
> adjust the naming a some bits to be more consistent.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/intel_pch_display.c | 13 +++--
> drivers/gpu/drm/i915/i915_reg.h | 58 +++++++++----------
> 2 files changed, 33 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 81ab761251ae..155c2d19a6bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -166,11 +166,11 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
> if ((pipeconf_val & PIPECONF_INTERLACE_MASK_ILK) == PIPECONF_INTERLACE_IF_ID_ILK) {
> if (HAS_PCH_IBX(dev_priv) &&
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
> - val |= TRANS_LEGACY_INTERLACED_ILK;
> + val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX;
> else
> - val |= TRANS_INTERLACED;
> + val |= TRANS_INTERLACE_INTERLACED;
> } else {
> - val |= TRANS_PROGRESSIVE;
> + val |= TRANS_INTERLACE_PROGRESSIVE;
> }
>
> intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
> @@ -279,7 +279,8 @@ void ilk_pch_enable(struct intel_atomic_state *state,
>
> temp = intel_de_read(dev_priv, reg);
> temp &= ~(TRANS_DP_PORT_SEL_MASK |
> - TRANS_DP_SYNC_MASK |
> + TRANS_DP_VSYNC_ACTIVE_HIGH |
> + TRANS_DP_HSYNC_ACTIVE_HIGH |
> TRANS_DP_BPC_MASK);
> temp |= TRANS_DP_OUTPUT_ENABLE;
> temp |= bpc << 9; /* same format but at 11:9 */
> @@ -423,9 +424,9 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
> pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
>
> if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == PIPECONF_INTERLACE_IF_ID_ILK)
> - val |= TRANS_INTERLACED;
> + val |= TRANS_INTERLACE_INTERLACED;
> else
> - val |= TRANS_PROGRESSIVE;
> + val |= TRANS_INTERLACE_PROGRESSIVE;
>
> intel_de_write(dev_priv, LPT_TRANSCONF, val);
> if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d2d5b2fa2a4a..eea009e76e15 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8994,22 +8994,19 @@ enum {
> #define _PCH_TRANSBCONF 0xf1008
> #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
> #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
> -#define TRANS_DISABLE (0 << 31)
> -#define TRANS_ENABLE (1 << 31)
> -#define TRANS_STATE_MASK (1 << 30)
> -#define TRANS_STATE_DISABLE (0 << 30)
> -#define TRANS_STATE_ENABLE (1 << 30)
> -#define TRANS_FRAME_START_DELAY_MASK (3 << 27) /* ibx */
> -#define TRANS_FRAME_START_DELAY(x) ((x) << 27) /* ibx: 0-3 */
> -#define TRANS_INTERLACE_MASK (7 << 21)
> -#define TRANS_PROGRESSIVE (0 << 21)
> -#define TRANS_INTERLACED (3 << 21)
> -#define TRANS_LEGACY_INTERLACED_ILK (2 << 21)
> -#define TRANS_8BPC (0 << 5)
> -#define TRANS_10BPC (1 << 5)
> -#define TRANS_6BPC (2 << 5)
> -#define TRANS_12BPC (3 << 5)
> -
> +#define TRANS_ENABLE REG_BIT(31)
> +#define TRANS_STATE_ENABLE REG_BIT(30)
> +#define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */
> +#define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
> +#define TRANS_INTERLACE_MASK REG_GENMASK(23, 21)
> +#define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
> +#define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
> +#define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
> +#define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */
> +#define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)
> +#define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1)
> +#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
> +#define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3)
> #define _TRANSA_CHICKEN1 0xf0060
> #define _TRANSB_CHICKEN1 0xf1060
> #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
> @@ -9219,22 +9216,19 @@ enum {
> #define _TRANS_DP_CTL_B 0xe1300
> #define _TRANS_DP_CTL_C 0xe2300
> #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
> -#define TRANS_DP_OUTPUT_ENABLE (1 << 31)
> -#define TRANS_DP_PORT_SEL_MASK (3 << 29)
> -#define TRANS_DP_PORT_SEL_NONE (3 << 29)
> -#define TRANS_DP_PORT_SEL(port) (((port) - PORT_B) << 29)
> -#define TRANS_DP_AUDIO_ONLY (1 << 26)
> -#define TRANS_DP_ENH_FRAMING (1 << 18)
> -#define TRANS_DP_8BPC (0 << 9)
> -#define TRANS_DP_10BPC (1 << 9)
> -#define TRANS_DP_6BPC (2 << 9)
> -#define TRANS_DP_12BPC (3 << 9)
> -#define TRANS_DP_BPC_MASK (3 << 9)
> -#define TRANS_DP_VSYNC_ACTIVE_HIGH (1 << 4)
> -#define TRANS_DP_VSYNC_ACTIVE_LOW 0
> -#define TRANS_DP_HSYNC_ACTIVE_HIGH (1 << 3)
> -#define TRANS_DP_HSYNC_ACTIVE_LOW 0
> -#define TRANS_DP_SYNC_MASK (3 << 3)
> +#define TRANS_DP_OUTPUT_ENABLE REG_BIT(31)
> +#define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29)
> +#define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3)
> +#define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
> +#define TRANS_DP_AUDIO_ONLY REG_BIT(26)
> +#define TRANS_DP_ENH_FRAMING REG_BIT(18)
> +#define TRANS_DP_BPC_MASK REG_GENMASK(10, 9)
> +#define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
> +#define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1)
> +#define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2)
> +#define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3)
> +#define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4)
> +#define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3)
>
> #define _TRANS_DP2_CTL_A 0x600a0
> #define _TRANS_DP2_CTL_B 0x610a0
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2022-01-26 14:40 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-12 19:38 [Intel-gfx] [PATCH 0/9] drm/i915: Register define cleanups Ville Syrjala
2021-11-12 19:38 ` [Intel-gfx] [PATCH 1/9] drm/i915: Bump DSL linemask to 20 bits Ville Syrjala
2021-11-15 19:05 ` Rodrigo Vivi
2021-11-19 10:30 ` Ville Syrjälä
2022-01-26 14:34 ` Jani Nikula
2021-11-12 19:38 ` [Intel-gfx] [PATCH 2/9] drm/i915: Clean up PIPEMISC register defines Ville Syrjala
2021-11-15 19:12 ` Rodrigo Vivi
2021-11-19 10:24 ` Ville Syrjälä
2021-11-24 10:18 ` Jani Nikula
2022-01-26 14:36 ` Jani Nikula
2021-11-12 19:38 ` [Intel-gfx] [PATCH 3/9] drm/i915: Clean up SKL_BOTTOM_COLOR defines Ville Syrjala
2022-01-26 14:21 ` Jani Nikula
2021-11-12 19:38 ` [Intel-gfx] [PATCH 4/9] drm/i915: Clean up PIPECONF bit defines Ville Syrjala
2022-01-26 14:31 ` Jani Nikula
2021-11-12 19:38 ` [Intel-gfx] [PATCH 5/9] drm/i915: Clean up PCH_TRANSCONF/TRANS_DP_CTL " Ville Syrjala
2022-01-26 14:40 ` Jani Nikula [this message]
2021-11-12 19:38 ` [Intel-gfx] [PATCH 6/9] drm/i915: Clean up PIPESRC defines Ville Syrjala
2022-01-26 14:42 ` Jani Nikula
2022-01-26 21:39 ` Ville Syrjälä
2021-11-12 19:38 ` [Intel-gfx] [PATCH 7/9] drm/i915: Clean up CRC register defines Ville Syrjala
2021-11-15 19:07 ` Rodrigo Vivi
2021-11-12 19:38 ` [Intel-gfx] [PATCH 8/9] drm/i915: Clean up DPINVGTT/VLV_DPFLIPSTAT bits Ville Syrjala
2021-11-15 19:05 ` Rodrigo Vivi
2021-11-12 19:38 ` [Intel-gfx] [PATCH 9/9] drm/i915: Clean up FPGA_DBG/CLAIM_ER bits Ville Syrjala
2021-11-15 19:05 ` Rodrigo Vivi
2021-11-12 20:40 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Register define cleanups Patchwork
2021-11-12 20:46 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-11-12 21:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-11-12 23:41 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87czkezhko.fsf@intel.com \
--to=jani.nikula@linux.intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=ville.syrjala@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.