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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 3/9] drm/i915: Clean up SKL_BOTTOM_COLOR defines
Date: Wed, 26 Jan 2022 16:21:02 +0200	[thread overview]
Message-ID: <87o83yzigh.fsf@intel.com> (raw)
In-Reply-To: <20211112193813.8224-4-ville.syrjala@linux.intel.com>

On Fri, 12 Nov 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use REG_BIT() for SKL_BOTTOM_COLOR.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e300a202ce2d..8b227dabb10c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6341,8 +6341,8 @@ enum {
>  
>  /* Skylake+ pipe bottom (background) color */
>  #define _SKL_BOTTOM_COLOR_A		0x70034
> -#define   SKL_BOTTOM_COLOR_GAMMA_ENABLE	(1 << 31)
> -#define   SKL_BOTTOM_COLOR_CSC_ENABLE	(1 << 30)
> +#define   SKL_BOTTOM_COLOR_GAMMA_ENABLE		REG_BIT(31)
> +#define   SKL_BOTTOM_COLOR_CSC_ENABLE		REG_BIT(30)
>  #define SKL_BOTTOM_COLOR(pipe)		_MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
>  
>  #define _ICL_PIPE_A_STATUS			0x70058

-- 
Jani Nikula, Intel Open Source Graphics Center

  reply	other threads:[~2022-01-26 14:21 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-12 19:38 [Intel-gfx] [PATCH 0/9] drm/i915: Register define cleanups Ville Syrjala
2021-11-12 19:38 ` [Intel-gfx] [PATCH 1/9] drm/i915: Bump DSL linemask to 20 bits Ville Syrjala
2021-11-15 19:05   ` Rodrigo Vivi
2021-11-19 10:30     ` Ville Syrjälä
2022-01-26 14:34       ` Jani Nikula
2021-11-12 19:38 ` [Intel-gfx] [PATCH 2/9] drm/i915: Clean up PIPEMISC register defines Ville Syrjala
2021-11-15 19:12   ` Rodrigo Vivi
2021-11-19 10:24     ` Ville Syrjälä
2021-11-24 10:18       ` Jani Nikula
2022-01-26 14:36   ` Jani Nikula
2021-11-12 19:38 ` [Intel-gfx] [PATCH 3/9] drm/i915: Clean up SKL_BOTTOM_COLOR defines Ville Syrjala
2022-01-26 14:21   ` Jani Nikula [this message]
2021-11-12 19:38 ` [Intel-gfx] [PATCH 4/9] drm/i915: Clean up PIPECONF bit defines Ville Syrjala
2022-01-26 14:31   ` Jani Nikula
2021-11-12 19:38 ` [Intel-gfx] [PATCH 5/9] drm/i915: Clean up PCH_TRANSCONF/TRANS_DP_CTL " Ville Syrjala
2022-01-26 14:40   ` Jani Nikula
2021-11-12 19:38 ` [Intel-gfx] [PATCH 6/9] drm/i915: Clean up PIPESRC defines Ville Syrjala
2022-01-26 14:42   ` Jani Nikula
2022-01-26 21:39     ` Ville Syrjälä
2021-11-12 19:38 ` [Intel-gfx] [PATCH 7/9] drm/i915: Clean up CRC register defines Ville Syrjala
2021-11-15 19:07   ` Rodrigo Vivi
2021-11-12 19:38 ` [Intel-gfx] [PATCH 8/9] drm/i915: Clean up DPINVGTT/VLV_DPFLIPSTAT bits Ville Syrjala
2021-11-15 19:05   ` Rodrigo Vivi
2021-11-12 19:38 ` [Intel-gfx] [PATCH 9/9] drm/i915: Clean up FPGA_DBG/CLAIM_ER bits Ville Syrjala
2021-11-15 19:05   ` Rodrigo Vivi
2021-11-12 20:40 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Register define cleanups Patchwork
2021-11-12 20:46 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-11-12 21:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-11-12 23:41 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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