From: Marc Zyngier <maz@kernel.org>
To: Qianggui Song <qianggui.song@amlogic.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Kevin Hilman <khilman@baylibre.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-amlogic@lists.infradead.org>
Subject: Re: [PATCH v2 2/4] irqchip/meson-gpio: support more than 8 channels gpio irq line
Date: Wed, 19 Jan 2022 13:31:58 +0000 [thread overview]
Message-ID: <87czkn97ht.wl-maz@kernel.org> (raw)
In-Reply-To: <20220119070809.15563-3-qianggui.song@amlogic.com>
On Wed, 19 Jan 2022 07:08:07 +0000,
Qianggui Song <qianggui.song@amlogic.com> wrote:
>
> Current meson gpio irqchip driver only support 8 channels for gpio irq
> line, later chips may have more then 8 channels, so need to modify code
> to support more.
>
> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
> ---
> drivers/irqchip/irq-meson-gpio.c | 33 +++++++++++++++++++++++---------
> 1 file changed, 24 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
> index d90ff0b92480..eefe15e1b3a6 100644
> --- a/drivers/irqchip/irq-meson-gpio.c
> +++ b/drivers/irqchip/irq-meson-gpio.c
> @@ -16,7 +16,6 @@
> #include <linux/of.h>
> #include <linux/of_address.h>
>
> -#define NUM_CHANNEL 8
> #define MAX_INPUT_MUX 256
>
> #define REG_EDGE_POL 0x00
> @@ -60,6 +59,7 @@ struct irq_ctl_ops {
>
> struct meson_gpio_irq_params {
> unsigned int nr_hwirq;
> + unsigned int nr_channels;
> bool support_edge_both;
> unsigned int edge_both_offset;
> unsigned int edge_single_offset;
> @@ -81,6 +81,7 @@ struct meson_gpio_irq_params {
> .edge_single_offset = 0, \
> .pol_low_offset = 16, \
> .pin_sel_mask = 0xff, \
> + .nr_channels = 8, \
>
> #define INIT_MESON_A1_COMMON_DATA(irqs) \
> INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
> @@ -90,6 +91,7 @@ struct meson_gpio_irq_params {
> .edge_single_offset = 8, \
> .pol_low_offset = 0, \
> .pin_sel_mask = 0x7f, \
> + .nr_channels = 8, \
>
> static const struct meson_gpio_irq_params meson8_params = {
> INIT_MESON8_COMMON_DATA(134)
> @@ -136,8 +138,8 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
> struct meson_gpio_irq_controller {
> const struct meson_gpio_irq_params *params;
> void __iomem *base;
> - u32 channel_irqs[NUM_CHANNEL];
> - DECLARE_BITMAP(channel_map, NUM_CHANNEL);
> + u32 *channel_irqs;
> + unsigned long *channel_map;
This really is over-engineering at its best.
With your new fancy HW, you have at most 12 bits being used in this
bitmap. So why not have a single unsigned long, no dynamic allocation,
and simply an assertion somewhere that checks that nr_channel is never
bigger than BITS_PER_LONG? Less code, less memory wasted, less problems.
M.
--
Without deviation from the norm, progress is not possible.
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Qianggui Song <qianggui.song@amlogic.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Kevin Hilman <khilman@baylibre.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-amlogic@lists.infradead.org>
Subject: Re: [PATCH v2 2/4] irqchip/meson-gpio: support more than 8 channels gpio irq line
Date: Wed, 19 Jan 2022 13:31:58 +0000 [thread overview]
Message-ID: <87czkn97ht.wl-maz@kernel.org> (raw)
In-Reply-To: <20220119070809.15563-3-qianggui.song@amlogic.com>
On Wed, 19 Jan 2022 07:08:07 +0000,
Qianggui Song <qianggui.song@amlogic.com> wrote:
>
> Current meson gpio irqchip driver only support 8 channels for gpio irq
> line, later chips may have more then 8 channels, so need to modify code
> to support more.
>
> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
> ---
> drivers/irqchip/irq-meson-gpio.c | 33 +++++++++++++++++++++++---------
> 1 file changed, 24 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
> index d90ff0b92480..eefe15e1b3a6 100644
> --- a/drivers/irqchip/irq-meson-gpio.c
> +++ b/drivers/irqchip/irq-meson-gpio.c
> @@ -16,7 +16,6 @@
> #include <linux/of.h>
> #include <linux/of_address.h>
>
> -#define NUM_CHANNEL 8
> #define MAX_INPUT_MUX 256
>
> #define REG_EDGE_POL 0x00
> @@ -60,6 +59,7 @@ struct irq_ctl_ops {
>
> struct meson_gpio_irq_params {
> unsigned int nr_hwirq;
> + unsigned int nr_channels;
> bool support_edge_both;
> unsigned int edge_both_offset;
> unsigned int edge_single_offset;
> @@ -81,6 +81,7 @@ struct meson_gpio_irq_params {
> .edge_single_offset = 0, \
> .pol_low_offset = 16, \
> .pin_sel_mask = 0xff, \
> + .nr_channels = 8, \
>
> #define INIT_MESON_A1_COMMON_DATA(irqs) \
> INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
> @@ -90,6 +91,7 @@ struct meson_gpio_irq_params {
> .edge_single_offset = 8, \
> .pol_low_offset = 0, \
> .pin_sel_mask = 0x7f, \
> + .nr_channels = 8, \
>
> static const struct meson_gpio_irq_params meson8_params = {
> INIT_MESON8_COMMON_DATA(134)
> @@ -136,8 +138,8 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
> struct meson_gpio_irq_controller {
> const struct meson_gpio_irq_params *params;
> void __iomem *base;
> - u32 channel_irqs[NUM_CHANNEL];
> - DECLARE_BITMAP(channel_map, NUM_CHANNEL);
> + u32 *channel_irqs;
> + unsigned long *channel_map;
This really is over-engineering at its best.
With your new fancy HW, you have at most 12 bits being used in this
bitmap. So why not have a single unsigned long, no dynamic allocation,
and simply an assertion somewhere that checks that nr_channel is never
bigger than BITS_PER_LONG? Less code, less memory wasted, less problems.
M.
--
Without deviation from the norm, progress is not possible.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Qianggui Song <qianggui.song@amlogic.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Kevin Hilman <khilman@baylibre.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-amlogic@lists.infradead.org>
Subject: Re: [PATCH v2 2/4] irqchip/meson-gpio: support more than 8 channels gpio irq line
Date: Wed, 19 Jan 2022 13:31:58 +0000 [thread overview]
Message-ID: <87czkn97ht.wl-maz@kernel.org> (raw)
In-Reply-To: <20220119070809.15563-3-qianggui.song@amlogic.com>
On Wed, 19 Jan 2022 07:08:07 +0000,
Qianggui Song <qianggui.song@amlogic.com> wrote:
>
> Current meson gpio irqchip driver only support 8 channels for gpio irq
> line, later chips may have more then 8 channels, so need to modify code
> to support more.
>
> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
> ---
> drivers/irqchip/irq-meson-gpio.c | 33 +++++++++++++++++++++++---------
> 1 file changed, 24 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
> index d90ff0b92480..eefe15e1b3a6 100644
> --- a/drivers/irqchip/irq-meson-gpio.c
> +++ b/drivers/irqchip/irq-meson-gpio.c
> @@ -16,7 +16,6 @@
> #include <linux/of.h>
> #include <linux/of_address.h>
>
> -#define NUM_CHANNEL 8
> #define MAX_INPUT_MUX 256
>
> #define REG_EDGE_POL 0x00
> @@ -60,6 +59,7 @@ struct irq_ctl_ops {
>
> struct meson_gpio_irq_params {
> unsigned int nr_hwirq;
> + unsigned int nr_channels;
> bool support_edge_both;
> unsigned int edge_both_offset;
> unsigned int edge_single_offset;
> @@ -81,6 +81,7 @@ struct meson_gpio_irq_params {
> .edge_single_offset = 0, \
> .pol_low_offset = 16, \
> .pin_sel_mask = 0xff, \
> + .nr_channels = 8, \
>
> #define INIT_MESON_A1_COMMON_DATA(irqs) \
> INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
> @@ -90,6 +91,7 @@ struct meson_gpio_irq_params {
> .edge_single_offset = 8, \
> .pol_low_offset = 0, \
> .pin_sel_mask = 0x7f, \
> + .nr_channels = 8, \
>
> static const struct meson_gpio_irq_params meson8_params = {
> INIT_MESON8_COMMON_DATA(134)
> @@ -136,8 +138,8 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
> struct meson_gpio_irq_controller {
> const struct meson_gpio_irq_params *params;
> void __iomem *base;
> - u32 channel_irqs[NUM_CHANNEL];
> - DECLARE_BITMAP(channel_map, NUM_CHANNEL);
> + u32 *channel_irqs;
> + unsigned long *channel_map;
This really is over-engineering at its best.
With your new fancy HW, you have at most 12 bits being used in this
bitmap. So why not have a single unsigned long, no dynamic allocation,
and simply an assertion somewhere that checks that nr_channel is never
bigger than BITS_PER_LONG? Less code, less memory wasted, less problems.
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2022-01-19 13:32 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-19 7:08 [PATCH v2 0/4] irqchip/meson-gpio: Add support for Meson-S4 SoC Qianggui Song
2022-01-19 7:08 ` Qianggui Song
2022-01-19 7:08 ` Qianggui Song
2022-01-19 7:08 ` [PATCH v2 1/4] dt-bindings: interrupt-controller: New binding for Meson-S4 SoCs Qianggui Song
2022-01-19 7:08 ` Qianggui Song
2022-01-19 7:08 ` Qianggui Song
2022-02-07 22:15 ` Rob Herring
2022-02-07 22:15 ` Rob Herring
2022-02-07 22:15 ` Rob Herring
2022-01-19 7:08 ` [PATCH v2 2/4] irqchip/meson-gpio: support more than 8 channels gpio irq line Qianggui Song
2022-01-19 7:08 ` Qianggui Song
2022-01-19 7:08 ` Qianggui Song
2022-01-19 8:53 ` Neil Armstrong
2022-01-19 8:53 ` Neil Armstrong
2022-01-19 8:53 ` Neil Armstrong
2022-01-19 13:31 ` Marc Zyngier [this message]
2022-01-19 13:31 ` Marc Zyngier
2022-01-19 13:31 ` Marc Zyngier
2022-01-19 7:08 ` [PATCH v2 3/4] irqchip/meson-gpio: add select trigger type callback Qianggui Song
2022-01-19 7:08 ` Qianggui Song
2022-01-19 7:08 ` Qianggui Song
2022-01-19 8:52 ` Neil Armstrong
2022-01-19 8:52 ` Neil Armstrong
2022-01-19 8:52 ` Neil Armstrong
2022-01-19 7:08 ` [PATCH v2 4/4] irqchip/meson-gpio: Add support for meson s4 SoCs Qianggui Song
2022-01-19 7:08 ` Qianggui Song
2022-01-19 7:08 ` Qianggui Song
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