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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: "Tapani Pälli" <tapani.palli@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
Date: Wed, 23 Oct 2019 19:12:21 +0300	[thread overview]
Message-ID: <87d0enl9ui.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20191023120618.5344-1-tapani.palli@intel.com>

Tapani Pälli <tapani.palli@intel.com> writes:

> As with commit 3fe0107e45ab, this change fixes multiple tests that are
> using the invocation counts. Documentation doesn't list the workaround
> for TGL but applying it fixes the tests.
>
> Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index af8a8183154a..86ded203b2dd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1215,6 +1215,26 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
>  
>  static void tgl_whitelist_build(struct intel_engine_cs *engine)
>  {
> +	struct i915_wa_list *w = &engine->whitelist;
> +
> +	switch (engine->class) {
> +	case RENDER_CLASS:
> +		/*
> +		 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl

Tried to find info about this but failed.

> +		 *
> +		 * This covers 4 registers which are next to one another :
> +		 *   - PS_INVOCATION_COUNT
> +		 *   - PS_INVOCATION_COUNT_UDW
> +		 *   - PS_DEPTH_COUNT
> +		 *   - PS_DEPTH_COUNT_UDW
> +		 */
> +		whitelist_reg_ext(w, PS_INVOCATION_COUNT,
> +				  RING_FORCE_TO_NONPRIV_ACCESS_RD |
> +				  RING_FORCE_TO_NONPRIV_RANGE_4);

The register spec is identical with gen11 so ok to whitelist.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> +		break;
> +	default:
> +		break;
> +	}
>  }
>  
>  void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> -- 
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: "Tapani Pälli" <tapani.palli@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
Date: Wed, 23 Oct 2019 19:12:21 +0300	[thread overview]
Message-ID: <87d0enl9ui.fsf@gaia.fi.intel.com> (raw)
Message-ID: <20191023161221.LkICBVL8aP00ZMMKg3fGRNTcg9aoPpHlLx1xvGrMzMo@z> (raw)
In-Reply-To: <20191023120618.5344-1-tapani.palli@intel.com>

Tapani Pälli <tapani.palli@intel.com> writes:

> As with commit 3fe0107e45ab, this change fixes multiple tests that are
> using the invocation counts. Documentation doesn't list the workaround
> for TGL but applying it fixes the tests.
>
> Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index af8a8183154a..86ded203b2dd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1215,6 +1215,26 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
>  
>  static void tgl_whitelist_build(struct intel_engine_cs *engine)
>  {
> +	struct i915_wa_list *w = &engine->whitelist;
> +
> +	switch (engine->class) {
> +	case RENDER_CLASS:
> +		/*
> +		 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl

Tried to find info about this but failed.

> +		 *
> +		 * This covers 4 registers which are next to one another :
> +		 *   - PS_INVOCATION_COUNT
> +		 *   - PS_INVOCATION_COUNT_UDW
> +		 *   - PS_DEPTH_COUNT
> +		 *   - PS_DEPTH_COUNT_UDW
> +		 */
> +		whitelist_reg_ext(w, PS_INVOCATION_COUNT,
> +				  RING_FORCE_TO_NONPRIV_ACCESS_RD |
> +				  RING_FORCE_TO_NONPRIV_RANGE_4);

The register spec is identical with gen11 so ok to whitelist.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> +		break;
> +	default:
> +		break;
> +	}
>  }
>  
>  void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> -- 
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2019-10-23 16:13 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-23 12:06 [PATCH] drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT Tapani Pälli
2019-10-23 12:06 ` [Intel-gfx] " Tapani Pälli
2019-10-23 12:30 ` Chris Wilson
2019-10-23 12:30   ` [Intel-gfx] " Chris Wilson
2019-10-23 12:47 ` Lionel Landwerlin
2019-10-23 12:47   ` [Intel-gfx] " Lionel Landwerlin
2019-10-23 16:12 ` Mika Kuoppala [this message]
2019-10-23 16:12   ` Mika Kuoppala
2019-10-23 18:59   ` Lionel Landwerlin
2019-10-23 18:59     ` [Intel-gfx] " Lionel Landwerlin
2019-10-23 20:49 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2019-10-23 20:49   ` [Intel-gfx] " Patchwork
2019-10-23 21:20 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-10-23 21:20   ` [Intel-gfx] " Patchwork
2019-10-23 21:49   ` Chris Wilson
2019-10-23 21:49     ` [Intel-gfx] " Chris Wilson
2019-10-24  6:39     ` Tapani Pälli
2019-10-24  6:39       ` [Intel-gfx] " Tapani Pälli
2019-10-24  6:48       ` Chris Wilson
2019-10-24  6:48         ` [Intel-gfx] " Chris Wilson

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