Re: [PATCH 3/5] drm/i915: Reduce context alignment

From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/5] drm/i915: Reduce context alignment
Date: Fri, 24 Feb 2017 12:18:22 +0200	[thread overview]
Message-ID: <87d1e7dh8x.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20170223155757.10316-3-chris@chris-wilson.co.uk>

Chris Wilson <chris@chris-wilson.co.uk> writes:

> No hardware was ever shipped that needed more than 4096 byte alignment
> and future hardware will not use this legacy path. So reduce the
> alignment to make it easier and quicker to launch workloads.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gem_context.c | 17 -----------------
>  drivers/gpu/drm/i915/i915_gem_context.h |  2 --
>  drivers/gpu/drm/i915/intel_ringbuffer.c |  3 ++-
>  3 files changed, 2 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 521e6f4705b1..baceca14f5e0 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -92,21 +92,6 @@
>  
>  #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
>  
> -/* This is a HW constraint. The value below is the largest known requirement
> - * I've seen in a spec to date, and that was a workaround for a non-shipping
> - * part. It should be safe to decrease this, but it's more future proof as is.
> - */
> -#define GEN6_CONTEXT_ALIGN (64<<10)
> -#define GEN7_CONTEXT_ALIGN I915_GTT_MIN_ALIGNMENT
> -
> -static size_t get_context_alignment(struct drm_i915_private *dev_priv)
> -{
> -	if (IS_GEN6(dev_priv))
> -		return GEN6_CONTEXT_ALIGN;
> -
> -	return GEN7_CONTEXT_ALIGN;
> -}
> -
>  static int get_context_size(struct drm_i915_private *dev_priv)
>  {
>  	int ret;
> @@ -281,8 +266,6 @@ __create_hw_context(struct drm_i915_private *dev_priv,
>  	list_add_tail(&ctx->link, &dev_priv->context_list);
>  	ctx->i915 = dev_priv;
>  
> -	ctx->ggtt_alignment = get_context_alignment(dev_priv);
> -
>  	if (dev_priv->hw_context_size) {
>  		struct drm_i915_gem_object *obj;
>  		struct i915_vma *vma;
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h
> index 0ac750b90f3d..81268c9770a6 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.h
> +++ b/drivers/gpu/drm/i915/i915_gem_context.h
> @@ -140,8 +140,6 @@ struct i915_gem_context {
>  	 */
>  	int priority;
>  
> -	/** ggtt_alignment: alignment restriction for context objects */
> -	u32 ggtt_alignment;
>  	/** ggtt_offset_bias: placement restriction for context objects */
>  	u32 ggtt_offset_bias;
>  
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index f62afffef682..4a864f8c9387 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1431,7 +1431,8 @@ static int context_pin(struct i915_gem_context *ctx)
>  			return ret;
>  	}
>  
> -	return i915_vma_pin(vma, 0, ctx->ggtt_alignment, PIN_GLOBAL | PIN_HIGH);
> +	return i915_vma_pin(vma, 0, I915_GTT_MIN_ALIGNMENT,
> +			    PIN_GLOBAL | PIN_HIGH);
>  }
>  
>  static int intel_ring_context_pin(struct intel_engine_cs *engine,
> -- 
> 2.11.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx