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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/5] drm/i915: Remove redundant TLB invalidate	on switching ppgtt
Date: Fri, 24 Feb 2017 11:47:56 +0200	[thread overview]
Message-ID: <87fuj3dinn.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20170223155757.10316-2-chris@chris-wilson.co.uk>

Chris Wilson <chris@chris-wilson.co.uk> writes:

> We are required to reload the TLBs around ppgtt switches. However, we
> already do an unconditional TLB invalidate before every batch and a flush
> afterwards, so this condition is already satisfied without extra flushes
> around the LRI instructions.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 17 -----------------
>  1 file changed, 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 057239ab3f70..999f15455f48 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1431,13 +1431,8 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
>  {
>  	struct intel_engine_cs *engine = req->engine;
>  	u32 *cs;
> -	int ret;
>  
>  	/* NB: TLBs must be flushed and invalidated before a switch */
> -	ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH);

The pattern slightly changes as you dont get the flush on the first
switch.

But what is there to flush on first switch anyways.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> -	if (ret)
> -		return ret;
> -
>  	cs = intel_ring_begin(req, 6);
>  	if (IS_ERR(cs))
>  		return PTR_ERR(cs);
> @@ -1458,13 +1453,8 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
>  {
>  	struct intel_engine_cs *engine = req->engine;
>  	u32 *cs;
> -	int ret;
>  
>  	/* NB: TLBs must be flushed and invalidated before a switch */
> -	ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH);
> -	if (ret)
> -		return ret;
> -
>  	cs = intel_ring_begin(req, 6);
>  	if (IS_ERR(cs))
>  		return PTR_ERR(cs);
> @@ -1477,13 +1467,6 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
>  	*cs++ = MI_NOOP;
>  	intel_ring_advance(req, cs);
>  
> -	/* XXX: RCS is the only one to auto invalidate the TLBs? */
> -	if (engine->id != RCS) {
> -		ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH);
> -		if (ret)
> -			return ret;
> -	}
> -
>  	return 0;
>  }
>  
> -- 
> 2.11.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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  reply	other threads:[~2017-02-24  9:49 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-23 15:57 [PATCH 1/5] drm/i915: Remove redundant TLB invalidate on switching contexts Chris Wilson
2017-02-23 15:57 ` [PATCH 2/5] drm/i915: Remove redundant TLB invalidate on switching ppgtt Chris Wilson
2017-02-24  9:47   ` Mika Kuoppala [this message]
2017-02-24  9:54     ` Chris Wilson
2017-02-23 15:57 ` [PATCH 3/5] drm/i915: Reduce context alignment Chris Wilson
2017-02-24 10:18   ` Mika Kuoppala
2017-02-23 15:57 ` [PATCH 4/5] drm/i915: Suppress context restore w/a when using MI_RESTORE_INHIBIT Chris Wilson
2017-02-24 10:45   ` Mika Kuoppala
2017-02-24 10:58     ` Chris Wilson
2017-02-27 23:50     ` Chris Wilson
2017-02-23 15:57 ` [PATCH 5/5] drm/i915: Suppress switch_mm emission between the same aliasing_ppgtt Chris Wilson
2017-02-23 17:52 ` ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Remove redundant TLB invalidate on switching contexts Patchwork
2017-02-24  9:42 ` [PATCH 1/5] " Mika Kuoppala

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