the late arch/sparc64/mm/init.c:__flush_cache_all

the late arch/sparc64/mm/init.c:__flush_cache_all

[Ed L Cashin]

Hi.  I'm trying to find out which function to use to flush or disable
the ultrasparc's dcache, icache, and ecache.  On my way, I discovered
the __flush_cache_all function in arch/sparc64/mm/init.c.  It is
absent from the current kernel, but it was present a few months ago.

void __flush_cache_all(void)
{
	/* Cheetah should be fine here too. */
	if (tlb_type = spitfire) {
		unsigned long va;

		flushw_all();
		for (va =  0; va < (PAGE_SIZE << 1); va += 32)
			spitfire_put_icache_tag(va, 0x0);
		__asm__ __volatile__("flush %g6");
	}
}

My first question is why the function was removed.  With Seth Arnold's
help, I found the patch at bkbits.net that removes __flush_cache_all,
but the only clue is the subject header, "[SPARC64]: vmap/vunmap cache
flushing need not do anything."  I don't really understand why the
function was removed.

Can use flushw_all and flush g6 to clear the dcache, icache, and
ecache?

Also, and less important---in __flush_cache_all's inline asm, I
expected the percent sign to be escaped, as in the other init.c
functions.  Why is there only one percent sign?

-- 
--Ed L Cashin            |   PGP public key:
  ecashin@uga.edu        |   http://noserose.net/e/pgp/

Re: the late arch/sparc64/mm/init.c:__flush_cache_all

[David S. Miller]

On Wed, 28 Jan 2004 15:42:38 -0500
Ed L Cashin <ecashin@uga.edu> wrote:

> My first question is why the function was removed.  With Seth Arnold's
> help, I found the patch at bkbits.net that removes __flush_cache_all,
> but the only clue is the subject header, "[SPARC64]: vmap/vunmap cache
> flushing need not do anything."  I don't really understand why the
> function was removed.

Because we no longer need to flush the whole thing in the kernel
any more, only specific addresses.

> Can use flushw_all and flush g6 to clear the dcache, icache, and
> ecache?

No, flushw_all() flushes the cpu register windows and "flush g6" flushes
one cacheline in the instruction cache.

Please download the UltraSPARC programmers manual from, for example:

	http://www.sun.com/processors/manuals/805-0087.pdf

to learn how to program the chip.


> Also, and less important---in __flush_cache_all's inline asm, I
> expected the percent sign to be escaped, as in the other init.c
> functions.  Why is there only one percent sign?
> 
> -- 
> --Ed L Cashin            |   PGP public key:
>   ecashin@uga.edu        |   http://noserose.net/e/pgp/
> 
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Re: the late arch/sparc64/mm/init.c:__flush_cache_all

[Ed L Cashin]

"David S. Miller" <davem@redhat.com> writes:

...
> Please download the UltraSPARC programmers manual from, for example:
>
> 	http://www.sun.com/processors/manuals/805-0087.pdf
>
> to learn how to program the chip.

I re-read all the manual sections describing the cache features.  My
intention was to find something that would allow me to do benchmarks
on a process for which I could disable caching.

The i386 has wbinvd which makes the cache write dirty pages to memory
and invalidate all entries, but the ultrasparc doesn't seem to have
anything like that.  You can loop over addresses doing displacement
flushing, but you have to make sure that the addresses you use are
already in the TLB, and I'm not sure how that's being done in the
kernel. 

    8.2.3
    
    ... Care must be taken to ensure that the range of read-only
    addresses is mapped in the MMU before starting a displacement
    flush, otherwise the TLB miss handler may put new data into the
    caches.

The manual also says that there are different kinds of addresses,
cachable and non-cachable, but I don't see any way to say, "Make all
of the VA's in this process non-cachable."

-- 
--Ed L Cashin            |   PGP public key:
  ecashin@uga.edu        |   http://noserose.net/e/pgp/

Re: the late arch/sparc64/mm/init.c:__flush_cache_all

[David S. Miller]

On Mon, 02 Feb 2004 13:51:38 -0500
Ed L Cashin <ecashin@uga.edu> wrote:

> The manual also says that there are different kinds of addresses,
> cachable and non-cachable, but I don't see any way to say, "Make all
> of the VA's in this process non-cachable."

You make the "virtually cacheable" bit in all PTEs of that process
clear.