* [PATCH v5 1/6] dt-bindings: dma: rz-dmac: Restrict properties for RZ/A1H
2025-03-05 0:21 [PATCH v5 0/6] Add DMAC support to the RZ/V2H(P) Fabrizio Castro
@ 2025-03-05 0:21 ` Fabrizio Castro
2025-03-05 0:21 ` [PATCH v5 2/6] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs Fabrizio Castro
` (4 subsequent siblings)
5 siblings, 0 replies; 17+ messages in thread
From: Fabrizio Castro @ 2025-03-05 0:21 UTC (permalink / raw)
To: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven
Cc: Fabrizio Castro, Magnus Damm, Biju Das, Wolfram Sang, dmaengine,
devicetree, linux-kernel, linux-renesas-soc, Lad Prabhakar,
Conor Dooley
Make sure we don't allow for the clocks, clock-names, resets,
reset-names. and power-domains properties for the Renesas
RZ/A1H SoC because its DMAC doesn't have clocks, resets,
and power domains.
Fixes: 209efec19c4c ("dt-bindings: dma: rz-dmac: Document RZ/A1H SoC")
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v4->v5:
* Collected tags.
v3->v4:
* No change.
v2->v3:
* No change.
v1->v2:
* No change.
---
.../devicetree/bindings/dma/renesas,rz-dmac.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
index b356251de5a8..82de3b927479 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
@@ -112,6 +112,14 @@ allOf:
- resets
- reset-names
+ else:
+ properties:
+ clocks: false
+ clock-names: false
+ power-domains: false
+ resets: false
+ reset-names: false
+
additionalProperties: false
examples:
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 2/6] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs
2025-03-05 0:21 [PATCH v5 0/6] Add DMAC support to the RZ/V2H(P) Fabrizio Castro
2025-03-05 0:21 ` [PATCH v5 1/6] dt-bindings: dma: rz-dmac: Restrict properties for RZ/A1H Fabrizio Castro
@ 2025-03-05 0:21 ` Fabrizio Castro
2025-03-06 13:27 ` Geert Uytterhoeven
2025-03-05 0:21 ` [PATCH v5 3/6] irqchip/renesas-rzv2h: Add rzv2h_icu_register_dma_req() Fabrizio Castro
` (3 subsequent siblings)
5 siblings, 1 reply; 17+ messages in thread
From: Fabrizio Castro @ 2025-03-05 0:21 UTC (permalink / raw)
To: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven
Cc: Fabrizio Castro, Magnus Damm, Biju Das, dmaengine, devicetree,
linux-kernel, linux-renesas-soc, Lad Prabhakar, Conor Dooley
Document the Renesas RZ/V2H(P) family of SoCs DMAC block.
The Renesas RZ/V2H(P) DMAC is very similar to the one found on the
Renesas RZ/G2L family of SoCs, but there are some differences:
* It only uses one register area
* It only uses one clock
* It only uses one reset
* Instead of using MID/IRD it uses REQ No
* It is connected to the Interrupt Control Unit (ICU)
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v4->v5:
* Removed ACK No from the specification of the dma cell.
* I have kept the tags received as this is a minor change and the
structure remains the same as v4. Please let me know if this is
not okay.
v3->v4:
* No change.
v2->v3:
* No change.
v1->v2:
* Removed RZ/V2H DMAC example.
* Improved the readability of the `if` statement.
---
.../bindings/dma/renesas,rz-dmac.yaml | 106 +++++++++++++++---
1 file changed, 88 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
index 82de3b927479..8323da12fa26 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
@@ -11,19 +11,23 @@ maintainers:
properties:
compatible:
- items:
- - enum:
- - renesas,r7s72100-dmac # RZ/A1H
- - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
- - renesas,r9a07g044-dmac # RZ/G2{L,LC}
- - renesas,r9a07g054-dmac # RZ/V2L
- - renesas,r9a08g045-dmac # RZ/G3S
- - const: renesas,rz-dmac
+ oneOf:
+ - items:
+ - enum:
+ - renesas,r7s72100-dmac # RZ/A1H
+ - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
+ - renesas,r9a07g044-dmac # RZ/G2{L,LC}
+ - renesas,r9a07g054-dmac # RZ/V2L
+ - renesas,r9a08g045-dmac # RZ/G3S
+ - const: renesas,rz-dmac
+
+ - const: renesas,r9a09g057-dmac # RZ/V2H(P)
reg:
items:
- description: Control and channel register block
- description: DMA extended resource selector block
+ minItems: 1
interrupts:
maxItems: 17
@@ -52,6 +56,7 @@ properties:
items:
- description: DMA main clock
- description: DMA register access clock
+ minItems: 1
clock-names:
items:
@@ -61,14 +66,21 @@ properties:
'#dma-cells':
const: 1
description:
- The cell specifies the encoded MID/RID values of the DMAC port
- connected to the DMA client and the slave channel configuration
- parameters.
+ For the RZ/A1H, RZ/Five, RZ/G2{L,LC,UL}, RZ/V2L, and RZ/G3S SoCs, the cell
+ specifies the encoded MID/RID values of the DMAC port connected to the
+ DMA client and the slave channel configuration parameters.
bits[0:9] - Specifies MID/RID value
bit[10] - Specifies DMA request high enable (HIEN)
bit[11] - Specifies DMA request detection type (LVL)
bits[12:14] - Specifies DMAACK output mode (AM)
bit[15] - Specifies Transfer Mode (TM)
+ For the RZ/V2H(P) SoC the cell specifies the DMAC REQ No and the slave channel
+ configuration parameters.
+ bits[0:9] - Specifies the DMAC REQ No
+ bit[10] - Specifies DMA request high enable (HIEN)
+ bit[11] - Specifies DMA request detection type (LVL)
+ bits[12:14] - Specifies DMAACK output mode (AM)
+ bit[15] - Specifies Transfer Mode (TM)
dma-channels:
const: 16
@@ -80,12 +92,29 @@ properties:
items:
- description: Reset for DMA ARESETN reset terminal
- description: Reset for DMA RST_ASYNC reset terminal
+ minItems: 1
reset-names:
items:
- const: arst
- const: rst_async
+ renesas,icu:
+ description:
+ On the RZ/V2H(P) SoC configures the ICU to which the DMAC is connected to.
+ It must contain the phandle to the ICU, and the index of the DMAC as seen
+ from the ICU (e.g. parameter k from register ICU_DMkSELy).
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to the ICU node.
+ - description: The DMAC index.
+ 4 for DMAC0
+ 0 for DMAC1
+ 1 for DMAC2
+ 2 for DMAC3
+ 3 for DMAC4
+
required:
- compatible
- reg
@@ -98,13 +127,25 @@ allOf:
- $ref: dma-controller.yaml#
- if:
- not:
- properties:
- compatible:
- contains:
- enum:
- - renesas,r7s72100-dmac
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,r9a07g043-dmac
+ - renesas,r9a07g044-dmac
+ - renesas,r9a07g054-dmac
+ - renesas,r9a08g045-dmac
then:
+ properties:
+ reg:
+ minItems: 2
+ clocks:
+ minItems: 2
+ resets:
+ minItems: 2
+
+ renesas,icu: false
+
required:
- clocks
- clock-names
@@ -112,13 +153,42 @@ allOf:
- resets
- reset-names
- else:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r7s72100-dmac
+ then:
properties:
clocks: false
clock-names: false
power-domains: false
resets: false
reset-names: false
+ renesas,icu: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g057-dmac
+ then:
+ properties:
+ reg:
+ maxItems: 1
+ clocks:
+ maxItems: 1
+ resets:
+ maxItems: 1
+
+ clock-names: false
+ reset-names: false
+
+ required:
+ - clocks
+ - power-domains
+ - renesas,icu
+ - resets
additionalProperties: false
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v5 2/6] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs
2025-03-05 0:21 ` [PATCH v5 2/6] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs Fabrizio Castro
@ 2025-03-06 13:27 ` Geert Uytterhoeven
2025-03-06 13:41 ` Fabrizio Castro
0 siblings, 1 reply; 17+ messages in thread
From: Geert Uytterhoeven @ 2025-03-06 13:27 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Magnus Damm, Biju Das, dmaengine, devicetree, linux-kernel,
linux-renesas-soc, Lad Prabhakar, Conor Dooley
Hi Fabrizio,
On Wed, 5 Mar 2025 at 01:21, Fabrizio Castro
<fabrizio.castro.jz@renesas.com> wrote:
> Document the Renesas RZ/V2H(P) family of SoCs DMAC block.
> The Renesas RZ/V2H(P) DMAC is very similar to the one found on the
> Renesas RZ/G2L family of SoCs, but there are some differences:
> * It only uses one register area
> * It only uses one clock
> * It only uses one reset
> * Instead of using MID/IRD it uses REQ No
> * It is connected to the Interrupt Control Unit (ICU)
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v4->v5:
> * Removed ACK No from the specification of the dma cell.
> * I have kept the tags received as this is a minor change and the
> structure remains the same as v4. Please let me know if this is
> not okay.
Thanks for the update!
> --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> @@ -61,14 +66,21 @@ properties:
> '#dma-cells':
> const: 1
> description:
> - The cell specifies the encoded MID/RID values of the DMAC port
Please just insert "or the REQ No" and be done with it?
> - connected to the DMA client and the slave channel configuration
> - parameters.
> + For the RZ/A1H, RZ/Five, RZ/G2{L,LC,UL}, RZ/V2L, and RZ/G3S SoCs, the cell
> + specifies the encoded MID/RID values of the DMAC port connected to the
> + DMA client and the slave channel configuration parameters.
> bits[0:9] - Specifies MID/RID value
> bit[10] - Specifies DMA request high enable (HIEN)
> bit[11] - Specifies DMA request detection type (LVL)
> bits[12:14] - Specifies DMAACK output mode (AM)
> bit[15] - Specifies Transfer Mode (TM)
> + For the RZ/V2H(P) SoC the cell specifies the DMAC REQ No and the slave channel
> + configuration parameters.
> + bits[0:9] - Specifies the DMAC REQ No
> + bit[10] - Specifies DMA request high enable (HIEN)
> + bit[11] - Specifies DMA request detection type (LVL)
> + bits[12:14] - Specifies DMAACK output mode (AM)
> + bit[15] - Specifies Transfer Mode (TM)
... so the casual reader doesn't have to look for the (nonexisting)
differences in the other bits.
>
> dma-channels:
> const: 16
> @@ -80,12 +92,29 @@ properties:
> items:
> - description: Reset for DMA ARESETN reset terminal
> - description: Reset for DMA RST_ASYNC reset terminal
> + minItems: 1
>
> reset-names:
> items:
> - const: arst
> - const: rst_async
>
> + renesas,icu:
> + description:
> + On the RZ/V2H(P) SoC configures the ICU to which the DMAC is connected to.
Are other SoCs with ICU planned?
> + It must contain the phandle to the ICU, and the index of the DMAC as seen
> + from the ICU (e.g. parameter k from register ICU_DMkSELy).
This is already described more formally below
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - items:
> + - description: phandle to the ICU node.
> + - description: The DMAC index.
> + 4 for DMAC0
> + 0 for DMAC1
> + 1 for DMAC2
> + 2 for DMAC3
> + 3 for DMAC4
Other SoCs may have other mappings.
So perhaps leave out the translation table, but write:
The number of the DMAC as seen from the ICU, i.e. parameter k from
register ICU_DMkSELy.
This may differ from the actual DMAC instance number!
> +
> required:
> - compatible
> - reg
> @@ -98,13 +127,25 @@ allOf:
> - $ref: dma-controller.yaml#
>
> - if:
> - not:
> - properties:
> - compatible:
> - contains:
> - enum:
> - - renesas,r7s72100-dmac
> + properties:
> + compatible:
> + contains:
> + enum:
> + - renesas,r9a07g043-dmac
> + - renesas,r9a07g044-dmac
> + - renesas,r9a07g054-dmac
> + - renesas,r9a08g045-dmac
> then:
> + properties:
> + reg:
> + minItems: 2
> + clocks:
> + minItems: 2
> + resets:
> + minItems: 2
> +
> + renesas,icu: false
> +
> required:
> - clocks
> - clock-names
> @@ -112,13 +153,42 @@ allOf:
> - resets
> - reset-names
>
> - else:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r7s72100-dmac
> + then:
> properties:
reg:
minItems: 2
> clocks: false
> clock-names: false
> power-domains: false
> resets: false
> reset-names: false
> + renesas,icu: false
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a09g057-dmac
> + then:
> + properties:
> + reg:
> + maxItems: 1
> + clocks:
> + maxItems: 1
> + resets:
> + maxItems: 1
> +
> + clock-names: false
> + reset-names: false
> +
> + required:
> + - clocks
> + - power-domains
> + - renesas,icu
> + - resets
>
> additionalProperties: false
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread* RE: [PATCH v5 2/6] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs
2025-03-06 13:27 ` Geert Uytterhoeven
@ 2025-03-06 13:41 ` Fabrizio Castro
2025-03-06 16:52 ` Fabrizio Castro
0 siblings, 1 reply; 17+ messages in thread
From: Fabrizio Castro @ 2025-03-06 13:41 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Magnus Damm, Biju Das, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad,
Conor Dooley
Hi Geert,
Thanks for your feedback!
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 06 March 2025 13:27
> Subject: Re: [PATCH v5 2/6] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs
>
> Hi Fabrizio,
>
> On Wed, 5 Mar 2025 at 01:21, Fabrizio Castro
> <fabrizio.castro.jz@renesas.com> wrote:
> > Document the Renesas RZ/V2H(P) family of SoCs DMAC block.
> > The Renesas RZ/V2H(P) DMAC is very similar to the one found on the
> > Renesas RZ/G2L family of SoCs, but there are some differences:
> > * It only uses one register area
> > * It only uses one clock
> > * It only uses one reset
> > * Instead of using MID/IRD it uses REQ No
> > * It is connected to the Interrupt Control Unit (ICU)
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v4->v5:
> > * Removed ACK No from the specification of the dma cell.
> > * I have kept the tags received as this is a minor change and the
> > structure remains the same as v4. Please let me know if this is
> > not okay.
>
> Thanks for the update!
>
> > --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > @@ -61,14 +66,21 @@ properties:
> > '#dma-cells':
> > const: 1
> > description:
> > - The cell specifies the encoded MID/RID values of the DMAC port
>
> Please just insert "or the REQ No" and be done with it?
Will do.
>
> > - connected to the DMA client and the slave channel configuration
> > - parameters.
> > + For the RZ/A1H, RZ/Five, RZ/G2{L,LC,UL}, RZ/V2L, and RZ/G3S SoCs, the cell
> > + specifies the encoded MID/RID values of the DMAC port connected to the
> > + DMA client and the slave channel configuration parameters.
> > bits[0:9] - Specifies MID/RID value
> > bit[10] - Specifies DMA request high enable (HIEN)
> > bit[11] - Specifies DMA request detection type (LVL)
> > bits[12:14] - Specifies DMAACK output mode (AM)
> > bit[15] - Specifies Transfer Mode (TM)
> > + For the RZ/V2H(P) SoC the cell specifies the DMAC REQ No and the slave channel
> > + configuration parameters.
> > + bits[0:9] - Specifies the DMAC REQ No
> > + bit[10] - Specifies DMA request high enable (HIEN)
> > + bit[11] - Specifies DMA request detection type (LVL)
> > + bits[12:14] - Specifies DMAACK output mode (AM)
> > + bit[15] - Specifies Transfer Mode (TM)
>
> ... so the casual reader doesn't have to look for the (nonexisting)
> differences in the other bits.
Agreed.
>
> >
> > dma-channels:
> > const: 16
> > @@ -80,12 +92,29 @@ properties:
> > items:
> > - description: Reset for DMA ARESETN reset terminal
> > - description: Reset for DMA RST_ASYNC reset terminal
> > + minItems: 1
> >
> > reset-names:
> > items:
> > - const: arst
> > - const: rst_async
> >
> > + renesas,icu:
> > + description:
> > + On the RZ/V2H(P) SoC configures the ICU to which the DMAC is connected to.
>
> Are other SoCs with ICU planned?
Yes.
Also the DMACs on RZ/G3E are connected to the ICU in a similar fashion.
>
> > + It must contain the phandle to the ICU, and the index of the DMAC as seen
> > + from the ICU (e.g. parameter k from register ICU_DMkSELy).
>
> This is already described more formally below
>
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + items:
> > + - items:
> > + - description: phandle to the ICU node.
> > + - description: The DMAC index.
> > + 4 for DMAC0
> > + 0 for DMAC1
> > + 1 for DMAC2
> > + 2 for DMAC3
> > + 3 for DMAC4
>
> Other SoCs may have other mappings.
> So perhaps leave out the translation table, but write:
>
> The number of the DMAC as seen from the ICU, i.e. parameter k from
> register ICU_DMkSELy.
> This may differ from the actual DMAC instance number!
Good shout, I will adjust accordingly.
I'll wait for your feedback on the ICU driver patch and on the DMAC driver patch
before sending v6.
Thanks!
Cheers,
Fab
>
> > +
> > required:
> > - compatible
> > - reg
> > @@ -98,13 +127,25 @@ allOf:
> > - $ref: dma-controller.yaml#
> >
> > - if:
> > - not:
> > - properties:
> > - compatible:
> > - contains:
> > - enum:
> > - - renesas,r7s72100-dmac
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - renesas,r9a07g043-dmac
> > + - renesas,r9a07g044-dmac
> > + - renesas,r9a07g054-dmac
> > + - renesas,r9a08g045-dmac
> > then:
> > + properties:
> > + reg:
> > + minItems: 2
> > + clocks:
> > + minItems: 2
> > + resets:
> > + minItems: 2
> > +
> > + renesas,icu: false
> > +
> > required:
> > - clocks
> > - clock-names
> > @@ -112,13 +153,42 @@ allOf:
> > - resets
> > - reset-names
> >
> > - else:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: renesas,r7s72100-dmac
> > + then:
> > properties:
>
> reg:
> minItems: 2
>
> > clocks: false
> > clock-names: false
> > power-domains: false
> > resets: false
> > reset-names: false
> > + renesas,icu: false
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: renesas,r9a09g057-dmac
> > + then:
> > + properties:
> > + reg:
> > + maxItems: 1
> > + clocks:
> > + maxItems: 1
> > + resets:
> > + maxItems: 1
> > +
> > + clock-names: false
> > + reset-names: false
> > +
> > + required:
> > + - clocks
> > + - power-domains
> > + - renesas,icu
> > + - resets
> >
> > additionalProperties: false
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread* RE: [PATCH v5 2/6] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs
2025-03-06 13:41 ` Fabrizio Castro
@ 2025-03-06 16:52 ` Fabrizio Castro
0 siblings, 0 replies; 17+ messages in thread
From: Fabrizio Castro @ 2025-03-06 16:52 UTC (permalink / raw)
To: Fabrizio Castro, Geert Uytterhoeven
Cc: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Magnus Damm, Biju Das, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad,
Conor Dooley
Hi Geert,
> From: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> Sent: 06 March 2025 13:41
> Subject: RE: [PATCH v5 2/6] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs
>
> Hi Geert,
>
> Thanks for your feedback!
>
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > Sent: 06 March 2025 13:27
> > Subject: Re: [PATCH v5 2/6] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs
> >
> > Hi Fabrizio,
> >
> > On Wed, 5 Mar 2025 at 01:21, Fabrizio Castro
> > <fabrizio.castro.jz@renesas.com> wrote:
> > > Document the Renesas RZ/V2H(P) family of SoCs DMAC block.
> > > The Renesas RZ/V2H(P) DMAC is very similar to the one found on the
> > > Renesas RZ/G2L family of SoCs, but there are some differences:
> > > * It only uses one register area
> > > * It only uses one clock
> > > * It only uses one reset
> > > * Instead of using MID/IRD it uses REQ No
> > > * It is connected to the Interrupt Control Unit (ICU)
> > >
> > > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> > > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v4->v5:
> > > * Removed ACK No from the specification of the dma cell.
> > > * I have kept the tags received as this is a minor change and the
> > > structure remains the same as v4. Please let me know if this is
> > > not okay.
> >
> > Thanks for the update!
> >
> > > --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > > @@ -61,14 +66,21 @@ properties:
> > > '#dma-cells':
> > > const: 1
> > > description:
> > > - The cell specifies the encoded MID/RID values of the DMAC port
> >
> > Please just insert "or the REQ No" and be done with it?
>
> Will do.
>
> >
> > > - connected to the DMA client and the slave channel configuration
> > > - parameters.
> > > + For the RZ/A1H, RZ/Five, RZ/G2{L,LC,UL}, RZ/V2L, and RZ/G3S SoCs, the cell
> > > + specifies the encoded MID/RID values of the DMAC port connected to the
> > > + DMA client and the slave channel configuration parameters.
> > > bits[0:9] - Specifies MID/RID value
> > > bit[10] - Specifies DMA request high enable (HIEN)
> > > bit[11] - Specifies DMA request detection type (LVL)
> > > bits[12:14] - Specifies DMAACK output mode (AM)
> > > bit[15] - Specifies Transfer Mode (TM)
> > > + For the RZ/V2H(P) SoC the cell specifies the DMAC REQ No and the slave channel
> > > + configuration parameters.
> > > + bits[0:9] - Specifies the DMAC REQ No
> > > + bit[10] - Specifies DMA request high enable (HIEN)
> > > + bit[11] - Specifies DMA request detection type (LVL)
> > > + bits[12:14] - Specifies DMAACK output mode (AM)
> > > + bit[15] - Specifies Transfer Mode (TM)
> >
> > ... so the casual reader doesn't have to look for the (nonexisting)
> > differences in the other bits.
>
> Agreed.
>
> >
> > >
> > > dma-channels:
> > > const: 16
> > > @@ -80,12 +92,29 @@ properties:
> > > items:
> > > - description: Reset for DMA ARESETN reset terminal
> > > - description: Reset for DMA RST_ASYNC reset terminal
> > > + minItems: 1
> > >
> > > reset-names:
> > > items:
> > > - const: arst
> > > - const: rst_async
> > >
> > > + renesas,icu:
> > > + description:
> > > + On the RZ/V2H(P) SoC configures the ICU to which the DMAC is connected to.
I'll take out this line, as the remainder of the description is sufficient enough I think,
and it'll be more generic.
> >
> > Are other SoCs with ICU planned?
>
> Yes.
> Also the DMACs on RZ/G3E are connected to the ICU in a similar fashion.
>
> >
> > > + It must contain the phandle to the ICU, and the index of the DMAC as seen
> > > + from the ICU (e.g. parameter k from register ICU_DMkSELy).
> >
> > This is already described more formally below
> >
> > > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > > + items:
> > > + - items:
> > > + - description: phandle to the ICU node.
> > > + - description: The DMAC index.
> > > + 4 for DMAC0
> > > + 0 for DMAC1
> > > + 1 for DMAC2
> > > + 2 for DMAC3
> > > + 3 for DMAC4
> >
> > Other SoCs may have other mappings.
> > So perhaps leave out the translation table, but write:
> >
> > The number of the DMAC as seen from the ICU, i.e. parameter k from
> > register ICU_DMkSELy.
> > This may differ from the actual DMAC instance number!
>
> Good shout, I will adjust accordingly.
>
> I'll wait for your feedback on the ICU driver patch and on the DMAC driver patch
> before sending v6.
>
> Thanks!
>
> Cheers,
> Fab
>
>
> >
> > > +
> > > required:
> > > - compatible
> > > - reg
> > > @@ -98,13 +127,25 @@ allOf:
> > > - $ref: dma-controller.yaml#
> > >
> > > - if:
> > > - not:
> > > - properties:
> > > - compatible:
> > > - contains:
> > > - enum:
> > > - - renesas,r7s72100-dmac
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + enum:
> > > + - renesas,r9a07g043-dmac
> > > + - renesas,r9a07g044-dmac
> > > + - renesas,r9a07g054-dmac
> > > + - renesas,r9a08g045-dmac
> > > then:
> > > + properties:
> > > + reg:
> > > + minItems: 2
> > > + clocks:
> > > + minItems: 2
> > > + resets:
> > > + minItems: 2
> > > +
> > > + renesas,icu: false
> > > +
> > > required:
> > > - clocks
> > > - clock-names
> > > @@ -112,13 +153,42 @@ allOf:
> > > - resets
> > > - reset-names
> > >
> > > - else:
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + const: renesas,r7s72100-dmac
> > > + then:
> > > properties:
> >
> > reg:
> > minItems: 2
Sorry I missed this. Good point.
I'll add it.
Thanks!
Cheers,
Fab
> >
> > > clocks: false
> > > clock-names: false
> > > power-domains: false
> > > resets: false
> > > reset-names: false
> > > + renesas,icu: false
> > > +
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + const: renesas,r9a09g057-dmac
> > > + then:
> > > + properties:
> > > + reg:
> > > + maxItems: 1
> > > + clocks:
> > > + maxItems: 1
> > > + resets:
> > > + maxItems: 1
> > > +
> > > + clock-names: false
> > > + reset-names: false
> > > +
> > > + required:
> > > + - clocks
> > > + - power-domains
> > > + - renesas,icu
> > > + - resets
> > >
> > > additionalProperties: false
> >
> > Gr{oetje,eeting}s,
> >
> > Geert
> >
> > --
> > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> >
> > In personal conversations with technical people, I call myself a hacker. But
> > when I'm talking to journalists I just say "programmer" or something like that.
> > -- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v5 3/6] irqchip/renesas-rzv2h: Add rzv2h_icu_register_dma_req()
2025-03-05 0:21 [PATCH v5 0/6] Add DMAC support to the RZ/V2H(P) Fabrizio Castro
2025-03-05 0:21 ` [PATCH v5 1/6] dt-bindings: dma: rz-dmac: Restrict properties for RZ/A1H Fabrizio Castro
2025-03-05 0:21 ` [PATCH v5 2/6] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs Fabrizio Castro
@ 2025-03-05 0:21 ` Fabrizio Castro
2025-03-07 8:09 ` Thomas Gleixner
` (2 more replies)
2025-03-05 0:21 ` [PATCH v5 4/6] dmaengine: sh: rz-dmac: Allow for multiple DMACs Fabrizio Castro
` (2 subsequent siblings)
5 siblings, 3 replies; 17+ messages in thread
From: Fabrizio Castro @ 2025-03-05 0:21 UTC (permalink / raw)
To: Thomas Gleixner, Geert Uytterhoeven
Cc: Fabrizio Castro, linux-kernel, Biju Das, Lad Prabhakar,
linux-renesas-soc
On the Renesas RZ/V2H(P) family of SoCs, DMAC IPs are connected
to the Interrupt Control Unit (ICU).
For DMA transfers, a request number must be registered with the
ICU, which means that the DMAC driver has to be able to instruct
the ICU driver with the registration of such id.
Export rzv2h_icu_register_dma_req() so that the DMAC driver can
register the DMAC request number.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
v4->v5:
* Dropped the registration of ACK No.
* Removed some #define in the driver and in the header file.
* Renamed the exported function to rzv2h_icu_register_dma_req.
* Rebased on top of the latest ICU related changes from Biju.
* Reworked changelog and title.
* Dropped Thomas' Reviewed-by tag as too much has changed since v4.
v3->v4:
* No change.
v2->v3:
* Replaced rzv2h_icu_register_dma_req_ack with
rzv2h_icu_register_dma_req_ack() in changelog.
* Added dummy for rzv2h_icu_register_dma_req_ack().
* Added Rb Thomas.
v1->v2:
* Improved macros.
* Shared new macros for minimum values.
---
drivers/irqchip/irq-renesas-rzv2h.c | 35 +++++++++++++++++++++++
include/linux/irqchip/irq-renesas-rzv2h.h | 23 +++++++++++++++
2 files changed, 58 insertions(+)
create mode 100644 include/linux/irqchip/irq-renesas-rzv2h.h
diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index 3d5b5fdf9bde..c0322bdfc69f 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -15,6 +15,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irqchip.h>
+#include <linux/irqchip/irq-renesas-rzv2h.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
@@ -41,6 +42,8 @@
#define ICU_TSCLR 0x24
#define ICU_TITSR(k) (0x28 + (k) * 4)
#define ICU_TSSR(k) (0x30 + (k) * 4)
+#define ICU_DMkSELy(k, y) (0x420 + (k) * 0x20 + (y) * 4)
+#define ICU_DMACKSELk(k) (0x500 + (k) * 4)
/* NMI */
#define ICU_NMI_EDGE_FALLING 0
@@ -103,6 +106,15 @@ struct rzv2h_hw_info {
u8 field_width;
};
+/* DMAC */
+#define ICU_DMAC_DkRQ_SEL_MASK GENMASK(9, 0)
+
+#define ICU_DMAC_DMAREQ_SHIFT(up) ((up) * 16)
+#define ICU_DMAC_DMAREQ_MASK(up) (ICU_DMAC_DkRQ_SEL_MASK \
+ << ICU_DMAC_DMAREQ_SHIFT(up))
+#define ICU_DMAC_PREP_DMAREQ(sel, up) (FIELD_PREP(ICU_DMAC_DkRQ_SEL_MASK, (sel)) \
+ << ICU_DMAC_DMAREQ_SHIFT(up))
+
/**
* struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure.
* @base: Controller's base address
@@ -117,6 +129,27 @@ struct rzv2h_icu_priv {
const struct rzv2h_hw_info *info;
};
+void rzv2h_icu_register_dma_req(struct platform_device *icu_dev, u8 dmac_index, u8 dmac_channel,
+ u16 req_no)
+{
+ struct rzv2h_icu_priv *priv = platform_get_drvdata(icu_dev);
+ u32 icu_dmksely, dmareq, dmareq_mask;
+ u8 y, upper;
+
+ y = dmac_channel / 2;
+ upper = dmac_channel % 2;
+
+ dmareq = ICU_DMAC_PREP_DMAREQ(req_no, upper);
+ dmareq_mask = ICU_DMAC_DMAREQ_MASK(upper);
+
+ guard(raw_spinlock_irqsave)(&priv->lock);
+
+ icu_dmksely = readl(priv->base + ICU_DMkSELy(dmac_index, y));
+ icu_dmksely = (icu_dmksely & ~dmareq_mask) | dmareq;
+ writel(icu_dmksely, priv->base + ICU_DMkSELy(dmac_index, y));
+}
+EXPORT_SYMBOL_GPL(rzv2h_icu_register_dma_req);
+
static inline struct rzv2h_icu_priv *irq_data_to_priv(struct irq_data *data)
{
return data->domain->host_data;
@@ -483,6 +516,8 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p
if (!rzv2h_icu_data)
return -ENOMEM;
+ platform_set_drvdata(pdev, rzv2h_icu_data);
+
rzv2h_icu_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
if (IS_ERR(rzv2h_icu_data->base))
return PTR_ERR(rzv2h_icu_data->base);
diff --git a/include/linux/irqchip/irq-renesas-rzv2h.h b/include/linux/irqchip/irq-renesas-rzv2h.h
new file mode 100644
index 000000000000..618a60d2eac0
--- /dev/null
+++ b/include/linux/irqchip/irq-renesas-rzv2h.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Renesas RZ/V2H(P) Interrupt Control Unit (ICU)
+ *
+ * Copyright (C) 2025 Renesas Electronics Corporation.
+ */
+
+#ifndef __LINUX_IRQ_RENESAS_RZV2H
+#define __LINUX_IRQ_RENESAS_RZV2H
+
+#include <linux/platform_device.h>
+
+#define RZV2H_ICU_DMAC_REQ_NO_DEFAULT 0x3ff
+
+#ifdef CONFIG_RENESAS_RZV2H_ICU
+void rzv2h_icu_register_dma_req(struct platform_device *icu_dev, u8 dmac_index, u8 dmac_channel,
+ u16 req_no);
+#else
+static inline void rzv2h_icu_register_dma_req(struct platform_device *icu_dev, u8 dmac_index,
+ u8 dmac_channel, u16 req_no) { }
+#endif
+
+#endif /* __LINUX_IRQ_RENESAS_RZV2H */
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v5 3/6] irqchip/renesas-rzv2h: Add rzv2h_icu_register_dma_req()
2025-03-05 0:21 ` [PATCH v5 3/6] irqchip/renesas-rzv2h: Add rzv2h_icu_register_dma_req() Fabrizio Castro
@ 2025-03-07 8:09 ` Thomas Gleixner
2025-04-09 10:42 ` Lad, Prabhakar
2025-04-15 12:31 ` Geert Uytterhoeven
2 siblings, 0 replies; 17+ messages in thread
From: Thomas Gleixner @ 2025-03-07 8:09 UTC (permalink / raw)
To: Fabrizio Castro, Geert Uytterhoeven
Cc: Fabrizio Castro, linux-kernel, Biju Das, Lad Prabhakar,
linux-renesas-soc
On Wed, Mar 05 2025 at 00:21, Fabrizio Castro wrote:
> On the Renesas RZ/V2H(P) family of SoCs, DMAC IPs are connected
> to the Interrupt Control Unit (ICU).
> For DMA transfers, a request number must be registered with the
> ICU, which means that the DMAC driver has to be able to instruct
> the ICU driver with the registration of such id.
>
> Export rzv2h_icu_register_dma_req() so that the DMAC driver can
> register the DMAC request number.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v5 3/6] irqchip/renesas-rzv2h: Add rzv2h_icu_register_dma_req()
2025-03-05 0:21 ` [PATCH v5 3/6] irqchip/renesas-rzv2h: Add rzv2h_icu_register_dma_req() Fabrizio Castro
2025-03-07 8:09 ` Thomas Gleixner
@ 2025-04-09 10:42 ` Lad, Prabhakar
2025-04-15 12:31 ` Geert Uytterhoeven
2 siblings, 0 replies; 17+ messages in thread
From: Lad, Prabhakar @ 2025-04-09 10:42 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Thomas Gleixner, Geert Uytterhoeven, linux-kernel, Biju Das,
Lad Prabhakar, linux-renesas-soc
On Wed, Mar 5, 2025 at 12:22 AM Fabrizio Castro
<fabrizio.castro.jz@renesas.com> wrote:
>
> On the Renesas RZ/V2H(P) family of SoCs, DMAC IPs are connected
> to the Interrupt Control Unit (ICU).
> For DMA transfers, a request number must be registered with the
> ICU, which means that the DMAC driver has to be able to instruct
> the ICU driver with the registration of such id.
>
> Export rzv2h_icu_register_dma_req() so that the DMAC driver can
> register the DMAC request number.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> ---
> v4->v5:
> * Dropped the registration of ACK No.
> * Removed some #define in the driver and in the header file.
> * Renamed the exported function to rzv2h_icu_register_dma_req.
> * Rebased on top of the latest ICU related changes from Biju.
> * Reworked changelog and title.
> * Dropped Thomas' Reviewed-by tag as too much has changed since v4.
> v3->v4:
> * No change.
> v2->v3:
> * Replaced rzv2h_icu_register_dma_req_ack with
> rzv2h_icu_register_dma_req_ack() in changelog.
> * Added dummy for rzv2h_icu_register_dma_req_ack().
> * Added Rb Thomas.
> v1->v2:
> * Improved macros.
> * Shared new macros for minimum values.
> ---
> drivers/irqchip/irq-renesas-rzv2h.c | 35 +++++++++++++++++++++++
> include/linux/irqchip/irq-renesas-rzv2h.h | 23 +++++++++++++++
> 2 files changed, 58 insertions(+)
> create mode 100644 include/linux/irqchip/irq-renesas-rzv2h.h
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cheers,
Prabhakar
> diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
> index 3d5b5fdf9bde..c0322bdfc69f 100644
> --- a/drivers/irqchip/irq-renesas-rzv2h.c
> +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> @@ -15,6 +15,7 @@
> #include <linux/err.h>
> #include <linux/io.h>
> #include <linux/irqchip.h>
> +#include <linux/irqchip/irq-renesas-rzv2h.h>
> #include <linux/irqdomain.h>
> #include <linux/of_address.h>
> #include <linux/of_platform.h>
> @@ -41,6 +42,8 @@
> #define ICU_TSCLR 0x24
> #define ICU_TITSR(k) (0x28 + (k) * 4)
> #define ICU_TSSR(k) (0x30 + (k) * 4)
> +#define ICU_DMkSELy(k, y) (0x420 + (k) * 0x20 + (y) * 4)
> +#define ICU_DMACKSELk(k) (0x500 + (k) * 4)
>
> /* NMI */
> #define ICU_NMI_EDGE_FALLING 0
> @@ -103,6 +106,15 @@ struct rzv2h_hw_info {
> u8 field_width;
> };
>
> +/* DMAC */
> +#define ICU_DMAC_DkRQ_SEL_MASK GENMASK(9, 0)
> +
> +#define ICU_DMAC_DMAREQ_SHIFT(up) ((up) * 16)
> +#define ICU_DMAC_DMAREQ_MASK(up) (ICU_DMAC_DkRQ_SEL_MASK \
> + << ICU_DMAC_DMAREQ_SHIFT(up))
> +#define ICU_DMAC_PREP_DMAREQ(sel, up) (FIELD_PREP(ICU_DMAC_DkRQ_SEL_MASK, (sel)) \
> + << ICU_DMAC_DMAREQ_SHIFT(up))
> +
> /**
> * struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure.
> * @base: Controller's base address
> @@ -117,6 +129,27 @@ struct rzv2h_icu_priv {
> const struct rzv2h_hw_info *info;
> };
>
> +void rzv2h_icu_register_dma_req(struct platform_device *icu_dev, u8 dmac_index, u8 dmac_channel,
> + u16 req_no)
> +{
> + struct rzv2h_icu_priv *priv = platform_get_drvdata(icu_dev);
> + u32 icu_dmksely, dmareq, dmareq_mask;
> + u8 y, upper;
> +
> + y = dmac_channel / 2;
> + upper = dmac_channel % 2;
> +
> + dmareq = ICU_DMAC_PREP_DMAREQ(req_no, upper);
> + dmareq_mask = ICU_DMAC_DMAREQ_MASK(upper);
> +
> + guard(raw_spinlock_irqsave)(&priv->lock);
> +
> + icu_dmksely = readl(priv->base + ICU_DMkSELy(dmac_index, y));
> + icu_dmksely = (icu_dmksely & ~dmareq_mask) | dmareq;
> + writel(icu_dmksely, priv->base + ICU_DMkSELy(dmac_index, y));
> +}
> +EXPORT_SYMBOL_GPL(rzv2h_icu_register_dma_req);
> +
> static inline struct rzv2h_icu_priv *irq_data_to_priv(struct irq_data *data)
> {
> return data->domain->host_data;
> @@ -483,6 +516,8 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p
> if (!rzv2h_icu_data)
> return -ENOMEM;
>
> + platform_set_drvdata(pdev, rzv2h_icu_data);
> +
> rzv2h_icu_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
> if (IS_ERR(rzv2h_icu_data->base))
> return PTR_ERR(rzv2h_icu_data->base);
> diff --git a/include/linux/irqchip/irq-renesas-rzv2h.h b/include/linux/irqchip/irq-renesas-rzv2h.h
> new file mode 100644
> index 000000000000..618a60d2eac0
> --- /dev/null
> +++ b/include/linux/irqchip/irq-renesas-rzv2h.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Renesas RZ/V2H(P) Interrupt Control Unit (ICU)
> + *
> + * Copyright (C) 2025 Renesas Electronics Corporation.
> + */
> +
> +#ifndef __LINUX_IRQ_RENESAS_RZV2H
> +#define __LINUX_IRQ_RENESAS_RZV2H
> +
> +#include <linux/platform_device.h>
> +
> +#define RZV2H_ICU_DMAC_REQ_NO_DEFAULT 0x3ff
> +
> +#ifdef CONFIG_RENESAS_RZV2H_ICU
> +void rzv2h_icu_register_dma_req(struct platform_device *icu_dev, u8 dmac_index, u8 dmac_channel,
> + u16 req_no);
> +#else
> +static inline void rzv2h_icu_register_dma_req(struct platform_device *icu_dev, u8 dmac_index,
> + u8 dmac_channel, u16 req_no) { }
> +#endif
> +
> +#endif /* __LINUX_IRQ_RENESAS_RZV2H */
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v5 3/6] irqchip/renesas-rzv2h: Add rzv2h_icu_register_dma_req()
2025-03-05 0:21 ` [PATCH v5 3/6] irqchip/renesas-rzv2h: Add rzv2h_icu_register_dma_req() Fabrizio Castro
2025-03-07 8:09 ` Thomas Gleixner
2025-04-09 10:42 ` Lad, Prabhakar
@ 2025-04-15 12:31 ` Geert Uytterhoeven
2 siblings, 0 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2025-04-15 12:31 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Thomas Gleixner, linux-kernel, Biju Das, Lad Prabhakar,
linux-renesas-soc
On Wed, 5 Mar 2025 at 01:21, Fabrizio Castro
<fabrizio.castro.jz@renesas.com> wrote:
> On the Renesas RZ/V2H(P) family of SoCs, DMAC IPs are connected
> to the Interrupt Control Unit (ICU).
> For DMA transfers, a request number must be registered with the
> ICU, which means that the DMAC driver has to be able to instruct
> the ICU driver with the registration of such id.
>
> Export rzv2h_icu_register_dma_req() so that the DMAC driver can
> register the DMAC request number.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> ---
> v4->v5:
> * Dropped the registration of ACK No.
> * Removed some #define in the driver and in the header file.
> * Renamed the exported function to rzv2h_icu_register_dma_req.
> * Rebased on top of the latest ICU related changes from Biju.
> * Reworked changelog and title.
> * Dropped Thomas' Reviewed-by tag as too much has changed since v4.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v5 4/6] dmaengine: sh: rz-dmac: Allow for multiple DMACs
2025-03-05 0:21 [PATCH v5 0/6] Add DMAC support to the RZ/V2H(P) Fabrizio Castro
` (2 preceding siblings ...)
2025-03-05 0:21 ` [PATCH v5 3/6] irqchip/renesas-rzv2h: Add rzv2h_icu_register_dma_req() Fabrizio Castro
@ 2025-03-05 0:21 ` Fabrizio Castro
2025-03-05 0:21 ` [PATCH v5 5/6] dmaengine: sh: rz-dmac: Add RZ/V2H(P) support Fabrizio Castro
2025-03-05 0:21 ` [PATCH v5 6/6] arm64: dts: renesas: r9a09g057: Add DMAC nodes Fabrizio Castro
5 siblings, 0 replies; 17+ messages in thread
From: Fabrizio Castro @ 2025-03-05 0:21 UTC (permalink / raw)
To: Vinod Koul, Geert Uytterhoeven
Cc: Fabrizio Castro, Wolfram Sang, Biju Das, Uwe Kleine-König,
dmaengine, linux-kernel, Lad Prabhakar, linux-renesas-soc
dma_request_channel() calls into __dma_request_channel() with
NULL as value for np, which won't allow for the selection of the
correct DMAC when multiple DMACs are available.
Switch to using __dma_request_channel() directly so that we can
choose the desired DMA for the channel. This is in preparation
of adding DMAC support for the Renesas RZ/V2H(P) and similar SoCs.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v4->v5:
* Collected tags.
v3->v4:
* No change.
v2->v3:
* Added () for calls in changelog.
v1->v2:
* No change.
---
drivers/dma/sh/rz-dmac.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
index 9235db551026..d7a4ce28040b 100644
--- a/drivers/dma/sh/rz-dmac.c
+++ b/drivers/dma/sh/rz-dmac.c
@@ -748,7 +748,8 @@ static struct dma_chan *rz_dmac_of_xlate(struct of_phandle_args *dma_spec,
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
- return dma_request_channel(mask, rz_dmac_chan_filter, dma_spec);
+ return __dma_request_channel(&mask, rz_dmac_chan_filter, dma_spec,
+ ofdma->of_node);
}
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 5/6] dmaengine: sh: rz-dmac: Add RZ/V2H(P) support
2025-03-05 0:21 [PATCH v5 0/6] Add DMAC support to the RZ/V2H(P) Fabrizio Castro
` (3 preceding siblings ...)
2025-03-05 0:21 ` [PATCH v5 4/6] dmaengine: sh: rz-dmac: Allow for multiple DMACs Fabrizio Castro
@ 2025-03-05 0:21 ` Fabrizio Castro
2025-04-07 8:43 ` Fabrizio Castro
` (2 more replies)
2025-03-05 0:21 ` [PATCH v5 6/6] arm64: dts: renesas: r9a09g057: Add DMAC nodes Fabrizio Castro
5 siblings, 3 replies; 17+ messages in thread
From: Fabrizio Castro @ 2025-03-05 0:21 UTC (permalink / raw)
To: Vinod Koul, Geert Uytterhoeven
Cc: Fabrizio Castro, Magnus Damm, Biju Das, Wolfram Sang,
Uwe Kleine-König, dmaengine, linux-kernel, linux-renesas-soc,
Lad Prabhakar
The DMAC IP found on the Renesas RZ/V2H(P) family of SoCs is
similar to the version found on the Renesas RZ/G2L family of
SoCs, but there are some differences:
* It only uses one register area
* It only uses one clock
* It only uses one reset
* Instead of using MID/IRD it uses REQ No
* It is connected to the Interrupt Control Unit (ICU)
* On the RZ/G2L there is only 1 DMAC, on the RZ/V2H(P) there are 5
Add specific support for the Renesas RZ/V2H(P) family of SoC by
tackling the aforementioned differences.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
v4->v5:
* Reused RZ/G2L cell specification (with REQ No in place of MID/RID).
* Dropped ACK No.
* Removed mid_rid/req_no/ack_no union and reused mid_rid for REQ No.
* Other small improvements.
v3->v4:
* Fixed an issue with mid_rid/req_no/ack_no initialization
v2->v3:
* Dropped change to Kconfig.
* Replaced rz_dmac_type with has_icu flag.
* Put req_no and ack_no in an anonymous struct, nested under an
anonymous union with mid_rid.
* Dropped data field of_rz_dmac_match[], and added logic to determine
value of has_icu flag from DT parsing.
v1->v2:
* Switched to new macros for minimum values.
---
drivers/dma/sh/rz-dmac.c | 81 ++++++++++++++++++++++++++++++++++++----
1 file changed, 74 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
index d7a4ce28040b..1f687b08d6b8 100644
--- a/drivers/dma/sh/rz-dmac.c
+++ b/drivers/dma/sh/rz-dmac.c
@@ -14,6 +14,7 @@
#include <linux/dmaengine.h>
#include <linux/interrupt.h>
#include <linux/iopoll.h>
+#include <linux/irqchip/irq-renesas-rzv2h.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of.h>
@@ -89,8 +90,14 @@ struct rz_dmac_chan {
#define to_rz_dmac_chan(c) container_of(c, struct rz_dmac_chan, vc.chan)
+struct rz_dmac_icu {
+ struct platform_device *pdev;
+ u8 dmac_index;
+};
+
struct rz_dmac {
struct dma_device engine;
+ struct rz_dmac_icu icu;
struct device *dev;
struct reset_control *rstc;
void __iomem *base;
@@ -99,6 +106,8 @@ struct rz_dmac {
unsigned int n_channels;
struct rz_dmac_chan *channels;
+ bool has_icu;
+
DECLARE_BITMAP(modules, 1024);
};
@@ -167,6 +176,9 @@ struct rz_dmac {
#define RZ_DMAC_MAX_CHANNELS 16
#define DMAC_NR_LMDESC 64
+/* RZ/V2H ICU related */
+#define RZV2H_MAX_DMAC_INDEX 4
+
/*
* -----------------------------------------------------------------------------
* Device access
@@ -324,7 +336,13 @@ static void rz_dmac_prepare_desc_for_memcpy(struct rz_dmac_chan *channel)
lmdesc->chext = 0;
lmdesc->header = HEADER_LV;
- rz_dmac_set_dmars_register(dmac, channel->index, 0);
+ if (dmac->has_icu) {
+ rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index,
+ channel->index,
+ RZV2H_ICU_DMAC_REQ_NO_DEFAULT);
+ } else {
+ rz_dmac_set_dmars_register(dmac, channel->index, 0);
+ }
channel->chcfg = chcfg;
channel->chctrl = CHCTRL_STG | CHCTRL_SETEN;
@@ -375,7 +393,13 @@ static void rz_dmac_prepare_descs_for_slave_sg(struct rz_dmac_chan *channel)
channel->lmdesc.tail = lmdesc;
- rz_dmac_set_dmars_register(dmac, channel->index, channel->mid_rid);
+ if (dmac->has_icu) {
+ rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index,
+ channel->index, channel->mid_rid);
+ } else {
+ rz_dmac_set_dmars_register(dmac, channel->index, channel->mid_rid);
+ }
+
channel->chctrl = CHCTRL_SETEN;
}
@@ -647,7 +671,13 @@ static void rz_dmac_device_synchronize(struct dma_chan *chan)
if (ret < 0)
dev_warn(dmac->dev, "DMA Timeout");
- rz_dmac_set_dmars_register(dmac, channel->index, 0);
+ if (dmac->has_icu) {
+ rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index,
+ channel->index,
+ RZV2H_ICU_DMAC_REQ_NO_DEFAULT);
+ } else {
+ rz_dmac_set_dmars_register(dmac, channel->index, 0);
+ }
}
/*
@@ -824,6 +854,38 @@ static int rz_dmac_chan_probe(struct rz_dmac *dmac,
return 0;
}
+static int rz_dmac_parse_of_icu(struct device *dev, struct rz_dmac *dmac)
+{
+ struct device_node *np = dev->of_node;
+ struct of_phandle_args args;
+ uint32_t dmac_index;
+ int ret;
+
+ ret = of_parse_phandle_with_fixed_args(np, "renesas,icu", 1, 0, &args);
+ if (ret == -ENOENT)
+ return 0;
+ if (ret)
+ return ret;
+
+ dmac->has_icu = true;
+
+ dmac->icu.pdev = of_find_device_by_node(args.np);
+ of_node_put(args.np);
+ if (!dmac->icu.pdev) {
+ dev_err(dev, "ICU device not found.\n");
+ return -ENODEV;
+ }
+
+ dmac_index = args.args[0];
+ if (dmac_index > RZV2H_MAX_DMAC_INDEX) {
+ dev_err(dev, "DMAC index %u invalid.\n", dmac_index);
+ return -EINVAL;
+ }
+ dmac->icu.dmac_index = dmac_index;
+
+ return 0;
+}
+
static int rz_dmac_parse_of(struct device *dev, struct rz_dmac *dmac)
{
struct device_node *np = dev->of_node;
@@ -840,7 +902,7 @@ static int rz_dmac_parse_of(struct device *dev, struct rz_dmac *dmac)
return -EINVAL;
}
- return 0;
+ return rz_dmac_parse_of_icu(dev, dmac);
}
static int rz_dmac_probe(struct platform_device *pdev)
@@ -874,9 +936,11 @@ static int rz_dmac_probe(struct platform_device *pdev)
if (IS_ERR(dmac->base))
return PTR_ERR(dmac->base);
- dmac->ext_base = devm_platform_ioremap_resource(pdev, 1);
- if (IS_ERR(dmac->ext_base))
- return PTR_ERR(dmac->ext_base);
+ if (!dmac->has_icu) {
+ dmac->ext_base = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(dmac->ext_base))
+ return PTR_ERR(dmac->ext_base);
+ }
/* Register interrupt handler for error */
irq = platform_get_irq_byname(pdev, irqname);
@@ -991,9 +1055,12 @@ static void rz_dmac_remove(struct platform_device *pdev)
reset_control_assert(dmac->rstc);
pm_runtime_put(&pdev->dev);
pm_runtime_disable(&pdev->dev);
+
+ platform_device_put(dmac->icu.pdev);
}
static const struct of_device_id of_rz_dmac_match[] = {
+ { .compatible = "renesas,r9a09g057-dmac", },
{ .compatible = "renesas,rz-dmac", },
{ /* Sentinel */ }
};
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* RE: [PATCH v5 5/6] dmaengine: sh: rz-dmac: Add RZ/V2H(P) support
2025-03-05 0:21 ` [PATCH v5 5/6] dmaengine: sh: rz-dmac: Add RZ/V2H(P) support Fabrizio Castro
@ 2025-04-07 8:43 ` Fabrizio Castro
2025-04-09 10:49 ` Lad, Prabhakar
2025-04-15 12:39 ` Geert Uytterhoeven
2 siblings, 0 replies; 17+ messages in thread
From: Fabrizio Castro @ 2025-04-07 8:43 UTC (permalink / raw)
To: Fabrizio Castro, Vinod Koul, Geert Uytterhoeven
Cc: Magnus Damm, Biju Das, Wolfram Sang, Uwe Kleine-König,
dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad
Gentle ping.
Kind regards,
Fab
> From: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> Sent: 05 March 2025 00:21
> Subject: [PATCH v5 5/6] dmaengine: sh: rz-dmac: Add RZ/V2H(P) support
>
> The DMAC IP found on the Renesas RZ/V2H(P) family of SoCs is
> similar to the version found on the Renesas RZ/G2L family of
> SoCs, but there are some differences:
> * It only uses one register area
> * It only uses one clock
> * It only uses one reset
> * Instead of using MID/IRD it uses REQ No
> * It is connected to the Interrupt Control Unit (ICU)
> * On the RZ/G2L there is only 1 DMAC, on the RZ/V2H(P) there are 5
>
> Add specific support for the Renesas RZ/V2H(P) family of SoC by
> tackling the aforementioned differences.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> ---
> v4->v5:
> * Reused RZ/G2L cell specification (with REQ No in place of MID/RID).
> * Dropped ACK No.
> * Removed mid_rid/req_no/ack_no union and reused mid_rid for REQ No.
> * Other small improvements.
> v3->v4:
> * Fixed an issue with mid_rid/req_no/ack_no initialization
> v2->v3:
> * Dropped change to Kconfig.
> * Replaced rz_dmac_type with has_icu flag.
> * Put req_no and ack_no in an anonymous struct, nested under an
> anonymous union with mid_rid.
> * Dropped data field of_rz_dmac_match[], and added logic to determine
> value of has_icu flag from DT parsing.
> v1->v2:
> * Switched to new macros for minimum values.
> ---
> drivers/dma/sh/rz-dmac.c | 81 ++++++++++++++++++++++++++++++++++++----
> 1 file changed, 74 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
> index d7a4ce28040b..1f687b08d6b8 100644
> --- a/drivers/dma/sh/rz-dmac.c
> +++ b/drivers/dma/sh/rz-dmac.c
> @@ -14,6 +14,7 @@
> #include <linux/dmaengine.h>
> #include <linux/interrupt.h>
> #include <linux/iopoll.h>
> +#include <linux/irqchip/irq-renesas-rzv2h.h>
> #include <linux/list.h>
> #include <linux/module.h>
> #include <linux/of.h>
> @@ -89,8 +90,14 @@ struct rz_dmac_chan {
>
> #define to_rz_dmac_chan(c) container_of(c, struct rz_dmac_chan, vc.chan)
>
> +struct rz_dmac_icu {
> + struct platform_device *pdev;
> + u8 dmac_index;
> +};
> +
> struct rz_dmac {
> struct dma_device engine;
> + struct rz_dmac_icu icu;
> struct device *dev;
> struct reset_control *rstc;
> void __iomem *base;
> @@ -99,6 +106,8 @@ struct rz_dmac {
> unsigned int n_channels;
> struct rz_dmac_chan *channels;
>
> + bool has_icu;
> +
> DECLARE_BITMAP(modules, 1024);
> };
>
> @@ -167,6 +176,9 @@ struct rz_dmac {
> #define RZ_DMAC_MAX_CHANNELS 16
> #define DMAC_NR_LMDESC 64
>
> +/* RZ/V2H ICU related */
> +#define RZV2H_MAX_DMAC_INDEX 4
> +
> /*
> * -----------------------------------------------------------------------------
> * Device access
> @@ -324,7 +336,13 @@ static void rz_dmac_prepare_desc_for_memcpy(struct rz_dmac_chan *channel)
> lmdesc->chext = 0;
> lmdesc->header = HEADER_LV;
>
> - rz_dmac_set_dmars_register(dmac, channel->index, 0);
> + if (dmac->has_icu) {
> + rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index,
> + channel->index,
> + RZV2H_ICU_DMAC_REQ_NO_DEFAULT);
> + } else {
> + rz_dmac_set_dmars_register(dmac, channel->index, 0);
> + }
>
> channel->chcfg = chcfg;
> channel->chctrl = CHCTRL_STG | CHCTRL_SETEN;
> @@ -375,7 +393,13 @@ static void rz_dmac_prepare_descs_for_slave_sg(struct rz_dmac_chan *channel)
>
> channel->lmdesc.tail = lmdesc;
>
> - rz_dmac_set_dmars_register(dmac, channel->index, channel->mid_rid);
> + if (dmac->has_icu) {
> + rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index,
> + channel->index, channel->mid_rid);
> + } else {
> + rz_dmac_set_dmars_register(dmac, channel->index, channel->mid_rid);
> + }
> +
> channel->chctrl = CHCTRL_SETEN;
> }
>
> @@ -647,7 +671,13 @@ static void rz_dmac_device_synchronize(struct dma_chan *chan)
> if (ret < 0)
> dev_warn(dmac->dev, "DMA Timeout");
>
> - rz_dmac_set_dmars_register(dmac, channel->index, 0);
> + if (dmac->has_icu) {
> + rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index,
> + channel->index,
> + RZV2H_ICU_DMAC_REQ_NO_DEFAULT);
> + } else {
> + rz_dmac_set_dmars_register(dmac, channel->index, 0);
> + }
> }
>
> /*
> @@ -824,6 +854,38 @@ static int rz_dmac_chan_probe(struct rz_dmac *dmac,
> return 0;
> }
>
> +static int rz_dmac_parse_of_icu(struct device *dev, struct rz_dmac *dmac)
> +{
> + struct device_node *np = dev->of_node;
> + struct of_phandle_args args;
> + uint32_t dmac_index;
> + int ret;
> +
> + ret = of_parse_phandle_with_fixed_args(np, "renesas,icu", 1, 0, &args);
> + if (ret == -ENOENT)
> + return 0;
> + if (ret)
> + return ret;
> +
> + dmac->has_icu = true;
> +
> + dmac->icu.pdev = of_find_device_by_node(args.np);
> + of_node_put(args.np);
> + if (!dmac->icu.pdev) {
> + dev_err(dev, "ICU device not found.\n");
> + return -ENODEV;
> + }
> +
> + dmac_index = args.args[0];
> + if (dmac_index > RZV2H_MAX_DMAC_INDEX) {
> + dev_err(dev, "DMAC index %u invalid.\n", dmac_index);
> + return -EINVAL;
> + }
> + dmac->icu.dmac_index = dmac_index;
> +
> + return 0;
> +}
> +
> static int rz_dmac_parse_of(struct device *dev, struct rz_dmac *dmac)
> {
> struct device_node *np = dev->of_node;
> @@ -840,7 +902,7 @@ static int rz_dmac_parse_of(struct device *dev, struct rz_dmac *dmac)
> return -EINVAL;
> }
>
> - return 0;
> + return rz_dmac_parse_of_icu(dev, dmac);
> }
>
> static int rz_dmac_probe(struct platform_device *pdev)
> @@ -874,9 +936,11 @@ static int rz_dmac_probe(struct platform_device *pdev)
> if (IS_ERR(dmac->base))
> return PTR_ERR(dmac->base);
>
> - dmac->ext_base = devm_platform_ioremap_resource(pdev, 1);
> - if (IS_ERR(dmac->ext_base))
> - return PTR_ERR(dmac->ext_base);
> + if (!dmac->has_icu) {
> + dmac->ext_base = devm_platform_ioremap_resource(pdev, 1);
> + if (IS_ERR(dmac->ext_base))
> + return PTR_ERR(dmac->ext_base);
> + }
>
> /* Register interrupt handler for error */
> irq = platform_get_irq_byname(pdev, irqname);
> @@ -991,9 +1055,12 @@ static void rz_dmac_remove(struct platform_device *pdev)
> reset_control_assert(dmac->rstc);
> pm_runtime_put(&pdev->dev);
> pm_runtime_disable(&pdev->dev);
> +
> + platform_device_put(dmac->icu.pdev);
> }
>
> static const struct of_device_id of_rz_dmac_match[] = {
> + { .compatible = "renesas,r9a09g057-dmac", },
> { .compatible = "renesas,rz-dmac", },
> { /* Sentinel */ }
> };
> --
> 2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v5 5/6] dmaengine: sh: rz-dmac: Add RZ/V2H(P) support
2025-03-05 0:21 ` [PATCH v5 5/6] dmaengine: sh: rz-dmac: Add RZ/V2H(P) support Fabrizio Castro
2025-04-07 8:43 ` Fabrizio Castro
@ 2025-04-09 10:49 ` Lad, Prabhakar
2025-04-15 12:39 ` Geert Uytterhoeven
2 siblings, 0 replies; 17+ messages in thread
From: Lad, Prabhakar @ 2025-04-09 10:49 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Vinod Koul, Geert Uytterhoeven, Magnus Damm, Biju Das,
Wolfram Sang, Uwe Kleine-König, dmaengine, linux-kernel,
linux-renesas-soc, Lad Prabhakar
On Wed, Mar 5, 2025 at 12:33 AM Fabrizio Castro
<fabrizio.castro.jz@renesas.com> wrote:
>
> The DMAC IP found on the Renesas RZ/V2H(P) family of SoCs is
> similar to the version found on the Renesas RZ/G2L family of
> SoCs, but there are some differences:
> * It only uses one register area
> * It only uses one clock
> * It only uses one reset
> * Instead of using MID/IRD it uses REQ No
> * It is connected to the Interrupt Control Unit (ICU)
> * On the RZ/G2L there is only 1 DMAC, on the RZ/V2H(P) there are 5
>
> Add specific support for the Renesas RZ/V2H(P) family of SoC by
> tackling the aforementioned differences.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> ---
> v4->v5:
> * Reused RZ/G2L cell specification (with REQ No in place of MID/RID).
> * Dropped ACK No.
> * Removed mid_rid/req_no/ack_no union and reused mid_rid for REQ No.
> * Other small improvements.
> v3->v4:
> * Fixed an issue with mid_rid/req_no/ack_no initialization
> v2->v3:
> * Dropped change to Kconfig.
> * Replaced rz_dmac_type with has_icu flag.
> * Put req_no and ack_no in an anonymous struct, nested under an
> anonymous union with mid_rid.
> * Dropped data field of_rz_dmac_match[], and added logic to determine
> value of has_icu flag from DT parsing.
> v1->v2:
> * Switched to new macros for minimum values.
> ---
> drivers/dma/sh/rz-dmac.c | 81 ++++++++++++++++++++++++++++++++++++----
> 1 file changed, 74 insertions(+), 7 deletions(-)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cheers,
Prabhakar
> diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
> index d7a4ce28040b..1f687b08d6b8 100644
> --- a/drivers/dma/sh/rz-dmac.c
> +++ b/drivers/dma/sh/rz-dmac.c
> @@ -14,6 +14,7 @@
> #include <linux/dmaengine.h>
> #include <linux/interrupt.h>
> #include <linux/iopoll.h>
> +#include <linux/irqchip/irq-renesas-rzv2h.h>
> #include <linux/list.h>
> #include <linux/module.h>
> #include <linux/of.h>
> @@ -89,8 +90,14 @@ struct rz_dmac_chan {
>
> #define to_rz_dmac_chan(c) container_of(c, struct rz_dmac_chan, vc.chan)
>
> +struct rz_dmac_icu {
> + struct platform_device *pdev;
> + u8 dmac_index;
> +};
> +
> struct rz_dmac {
> struct dma_device engine;
> + struct rz_dmac_icu icu;
> struct device *dev;
> struct reset_control *rstc;
> void __iomem *base;
> @@ -99,6 +106,8 @@ struct rz_dmac {
> unsigned int n_channels;
> struct rz_dmac_chan *channels;
>
> + bool has_icu;
> +
> DECLARE_BITMAP(modules, 1024);
> };
>
> @@ -167,6 +176,9 @@ struct rz_dmac {
> #define RZ_DMAC_MAX_CHANNELS 16
> #define DMAC_NR_LMDESC 64
>
> +/* RZ/V2H ICU related */
> +#define RZV2H_MAX_DMAC_INDEX 4
> +
> /*
> * -----------------------------------------------------------------------------
> * Device access
> @@ -324,7 +336,13 @@ static void rz_dmac_prepare_desc_for_memcpy(struct rz_dmac_chan *channel)
> lmdesc->chext = 0;
> lmdesc->header = HEADER_LV;
>
> - rz_dmac_set_dmars_register(dmac, channel->index, 0);
> + if (dmac->has_icu) {
> + rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index,
> + channel->index,
> + RZV2H_ICU_DMAC_REQ_NO_DEFAULT);
> + } else {
> + rz_dmac_set_dmars_register(dmac, channel->index, 0);
> + }
>
> channel->chcfg = chcfg;
> channel->chctrl = CHCTRL_STG | CHCTRL_SETEN;
> @@ -375,7 +393,13 @@ static void rz_dmac_prepare_descs_for_slave_sg(struct rz_dmac_chan *channel)
>
> channel->lmdesc.tail = lmdesc;
>
> - rz_dmac_set_dmars_register(dmac, channel->index, channel->mid_rid);
> + if (dmac->has_icu) {
> + rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index,
> + channel->index, channel->mid_rid);
> + } else {
> + rz_dmac_set_dmars_register(dmac, channel->index, channel->mid_rid);
> + }
> +
> channel->chctrl = CHCTRL_SETEN;
> }
>
> @@ -647,7 +671,13 @@ static void rz_dmac_device_synchronize(struct dma_chan *chan)
> if (ret < 0)
> dev_warn(dmac->dev, "DMA Timeout");
>
> - rz_dmac_set_dmars_register(dmac, channel->index, 0);
> + if (dmac->has_icu) {
> + rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index,
> + channel->index,
> + RZV2H_ICU_DMAC_REQ_NO_DEFAULT);
> + } else {
> + rz_dmac_set_dmars_register(dmac, channel->index, 0);
> + }
> }
>
> /*
> @@ -824,6 +854,38 @@ static int rz_dmac_chan_probe(struct rz_dmac *dmac,
> return 0;
> }
>
> +static int rz_dmac_parse_of_icu(struct device *dev, struct rz_dmac *dmac)
> +{
> + struct device_node *np = dev->of_node;
> + struct of_phandle_args args;
> + uint32_t dmac_index;
> + int ret;
> +
> + ret = of_parse_phandle_with_fixed_args(np, "renesas,icu", 1, 0, &args);
> + if (ret == -ENOENT)
> + return 0;
> + if (ret)
> + return ret;
> +
> + dmac->has_icu = true;
> +
> + dmac->icu.pdev = of_find_device_by_node(args.np);
> + of_node_put(args.np);
> + if (!dmac->icu.pdev) {
> + dev_err(dev, "ICU device not found.\n");
> + return -ENODEV;
> + }
> +
> + dmac_index = args.args[0];
> + if (dmac_index > RZV2H_MAX_DMAC_INDEX) {
> + dev_err(dev, "DMAC index %u invalid.\n", dmac_index);
> + return -EINVAL;
> + }
> + dmac->icu.dmac_index = dmac_index;
> +
> + return 0;
> +}
> +
> static int rz_dmac_parse_of(struct device *dev, struct rz_dmac *dmac)
> {
> struct device_node *np = dev->of_node;
> @@ -840,7 +902,7 @@ static int rz_dmac_parse_of(struct device *dev, struct rz_dmac *dmac)
> return -EINVAL;
> }
>
> - return 0;
> + return rz_dmac_parse_of_icu(dev, dmac);
> }
>
> static int rz_dmac_probe(struct platform_device *pdev)
> @@ -874,9 +936,11 @@ static int rz_dmac_probe(struct platform_device *pdev)
> if (IS_ERR(dmac->base))
> return PTR_ERR(dmac->base);
>
> - dmac->ext_base = devm_platform_ioremap_resource(pdev, 1);
> - if (IS_ERR(dmac->ext_base))
> - return PTR_ERR(dmac->ext_base);
> + if (!dmac->has_icu) {
> + dmac->ext_base = devm_platform_ioremap_resource(pdev, 1);
> + if (IS_ERR(dmac->ext_base))
> + return PTR_ERR(dmac->ext_base);
> + }
>
> /* Register interrupt handler for error */
> irq = platform_get_irq_byname(pdev, irqname);
> @@ -991,9 +1055,12 @@ static void rz_dmac_remove(struct platform_device *pdev)
> reset_control_assert(dmac->rstc);
> pm_runtime_put(&pdev->dev);
> pm_runtime_disable(&pdev->dev);
> +
> + platform_device_put(dmac->icu.pdev);
> }
>
> static const struct of_device_id of_rz_dmac_match[] = {
> + { .compatible = "renesas,r9a09g057-dmac", },
> { .compatible = "renesas,rz-dmac", },
> { /* Sentinel */ }
> };
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v5 5/6] dmaengine: sh: rz-dmac: Add RZ/V2H(P) support
2025-03-05 0:21 ` [PATCH v5 5/6] dmaengine: sh: rz-dmac: Add RZ/V2H(P) support Fabrizio Castro
2025-04-07 8:43 ` Fabrizio Castro
2025-04-09 10:49 ` Lad, Prabhakar
@ 2025-04-15 12:39 ` Geert Uytterhoeven
2 siblings, 0 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2025-04-15 12:39 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Vinod Koul, Magnus Damm, Biju Das, Wolfram Sang,
Uwe Kleine-König, dmaengine, linux-kernel, linux-renesas-soc,
Lad Prabhakar
On Wed, 5 Mar 2025 at 01:21, Fabrizio Castro
<fabrizio.castro.jz@renesas.com> wrote:
> The DMAC IP found on the Renesas RZ/V2H(P) family of SoCs is
> similar to the version found on the Renesas RZ/G2L family of
> SoCs, but there are some differences:
> * It only uses one register area
> * It only uses one clock
> * It only uses one reset
> * Instead of using MID/IRD it uses REQ No
> * It is connected to the Interrupt Control Unit (ICU)
> * On the RZ/G2L there is only 1 DMAC, on the RZ/V2H(P) there are 5
>
> Add specific support for the Renesas RZ/V2H(P) family of SoC by
> tackling the aforementioned differences.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> ---
> v4->v5:
> * Reused RZ/G2L cell specification (with REQ No in place of MID/RID).
> * Dropped ACK No.
> * Removed mid_rid/req_no/ack_no union and reused mid_rid for REQ No.
> * Other small improvements.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v5 6/6] arm64: dts: renesas: r9a09g057: Add DMAC nodes
2025-03-05 0:21 [PATCH v5 0/6] Add DMAC support to the RZ/V2H(P) Fabrizio Castro
` (4 preceding siblings ...)
2025-03-05 0:21 ` [PATCH v5 5/6] dmaengine: sh: rz-dmac: Add RZ/V2H(P) support Fabrizio Castro
@ 2025-03-05 0:21 ` Fabrizio Castro
2025-04-09 10:53 ` Lad, Prabhakar
5 siblings, 1 reply; 17+ messages in thread
From: Fabrizio Castro @ 2025-03-05 0:21 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven
Cc: Fabrizio Castro, Magnus Damm, linux-renesas-soc, devicetree,
linux-kernel, Biju Das, Lad Prabhakar
Add nodes for the DMAC IPs found on the Renesas RZ/V2H(P) SoC.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v4->v5:
* Collected tags.
v3->v4:
* No change.
v2->v3:
* No change.
v1->v2:
* No change.
---
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 165 +++++++++++++++++++++
1 file changed, 165 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 1c550b22b164..0a7d0c801e32 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -252,6 +252,171 @@ sys: system-controller@10430000 {
status = "disabled";
};
+ dmac0: dma-controller@11400000 {
+ compatible = "renesas,r9a09g057-dmac";
+ reg = <0 0x11400000 0 0x10000>;
+ interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x0>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x31>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 4>;
+ };
+
+ dmac1: dma-controller@14830000 {
+ compatible = "renesas,r9a09g057-dmac";
+ reg = <0 0x14830000 0 0x10000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x1>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x32>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 0>;
+ };
+
+ dmac2: dma-controller@14840000 {
+ compatible = "renesas,r9a09g057-dmac";
+ reg = <0 0x14840000 0 0x10000>;
+ interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x2>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x33>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 1>;
+ };
+
+ dmac3: dma-controller@12000000 {
+ compatible = "renesas,r9a09g057-dmac";
+ reg = <0 0x12000000 0 0x10000>;
+ interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x3>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x34>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 2>;
+ };
+
+ dmac4: dma-controller@12010000 {
+ compatible = "renesas,r9a09g057-dmac";
+ reg = <0 0x12010000 0 0x10000>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x4>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x35>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 3>;
+ };
+
ostm0: timer@11800000 {
compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
reg = <0x0 0x11800000 0x0 0x1000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v5 6/6] arm64: dts: renesas: r9a09g057: Add DMAC nodes
2025-03-05 0:21 ` [PATCH v5 6/6] arm64: dts: renesas: r9a09g057: Add DMAC nodes Fabrizio Castro
@ 2025-04-09 10:53 ` Lad, Prabhakar
0 siblings, 0 replies; 17+ messages in thread
From: Lad, Prabhakar @ 2025-04-09 10:53 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, linux-renesas-soc, devicetree,
linux-kernel, Biju Das, Lad Prabhakar
On Wed, Mar 5, 2025 at 12:24 AM Fabrizio Castro
<fabrizio.castro.jz@renesas.com> wrote:
>
> Add nodes for the DMAC IPs found on the Renesas RZ/V2H(P) SoC.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v4->v5:
> * Collected tags.
> v3->v4:
> * No change.
> v2->v3:
> * No change.
> v1->v2:
> * No change.
> ---
> arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 165 +++++++++++++++++++++
> 1 file changed, 165 insertions(+)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cheers,
Prabhakar
> diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> index 1c550b22b164..0a7d0c801e32 100644
> --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> @@ -252,6 +252,171 @@ sys: system-controller@10430000 {
> status = "disabled";
> };
>
> + dmac0: dma-controller@11400000 {
> + compatible = "renesas,r9a09g057-dmac";
> + reg = <0 0x11400000 0 0x10000>;
> + interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "error",
> + "ch0", "ch1", "ch2", "ch3",
> + "ch4", "ch5", "ch6", "ch7",
> + "ch8", "ch9", "ch10", "ch11",
> + "ch12", "ch13", "ch14", "ch15";
> + clocks = <&cpg CPG_MOD 0x0>;
> + power-domains = <&cpg>;
> + resets = <&cpg 0x31>;
> + #dma-cells = <1>;
> + dma-channels = <16>;
> + renesas,icu = <&icu 4>;
> + };
> +
> + dmac1: dma-controller@14830000 {
> + compatible = "renesas,r9a09g057-dmac";
> + reg = <0 0x14830000 0 0x10000>;
> + interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "error",
> + "ch0", "ch1", "ch2", "ch3",
> + "ch4", "ch5", "ch6", "ch7",
> + "ch8", "ch9", "ch10", "ch11",
> + "ch12", "ch13", "ch14", "ch15";
> + clocks = <&cpg CPG_MOD 0x1>;
> + power-domains = <&cpg>;
> + resets = <&cpg 0x32>;
> + #dma-cells = <1>;
> + dma-channels = <16>;
> + renesas,icu = <&icu 0>;
> + };
> +
> + dmac2: dma-controller@14840000 {
> + compatible = "renesas,r9a09g057-dmac";
> + reg = <0 0x14840000 0 0x10000>;
> + interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "error",
> + "ch0", "ch1", "ch2", "ch3",
> + "ch4", "ch5", "ch6", "ch7",
> + "ch8", "ch9", "ch10", "ch11",
> + "ch12", "ch13", "ch14", "ch15";
> + clocks = <&cpg CPG_MOD 0x2>;
> + power-domains = <&cpg>;
> + resets = <&cpg 0x33>;
> + #dma-cells = <1>;
> + dma-channels = <16>;
> + renesas,icu = <&icu 1>;
> + };
> +
> + dmac3: dma-controller@12000000 {
> + compatible = "renesas,r9a09g057-dmac";
> + reg = <0 0x12000000 0 0x10000>;
> + interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "error",
> + "ch0", "ch1", "ch2", "ch3",
> + "ch4", "ch5", "ch6", "ch7",
> + "ch8", "ch9", "ch10", "ch11",
> + "ch12", "ch13", "ch14", "ch15";
> + clocks = <&cpg CPG_MOD 0x3>;
> + power-domains = <&cpg>;
> + resets = <&cpg 0x34>;
> + #dma-cells = <1>;
> + dma-channels = <16>;
> + renesas,icu = <&icu 2>;
> + };
> +
> + dmac4: dma-controller@12010000 {
> + compatible = "renesas,r9a09g057-dmac";
> + reg = <0 0x12010000 0 0x10000>;
> + interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "error",
> + "ch0", "ch1", "ch2", "ch3",
> + "ch4", "ch5", "ch6", "ch7",
> + "ch8", "ch9", "ch10", "ch11",
> + "ch12", "ch13", "ch14", "ch15";
> + clocks = <&cpg CPG_MOD 0x4>;
> + power-domains = <&cpg>;
> + resets = <&cpg 0x35>;
> + #dma-cells = <1>;
> + dma-channels = <16>;
> + renesas,icu = <&icu 3>;
> + };
> +
> ostm0: timer@11800000 {
> compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
> reg = <0x0 0x11800000 0x0 0x1000>;
> --
> 2.34.1
>
>
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