* [Intel-gfx] [PATCH v2] drm/i915/gt: Initialize reserved and unspecified MOCS indices
@ 2020-06-04 18:26 Ayaz A Siddiqui
2020-06-04 19:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Ayaz A Siddiqui @ 2020-06-04 18:26 UTC (permalink / raw)
To: intel-gfx
In order to avoid functional breakage of mis-programmed applications that
have grown to depend on unused MOCS entries, we are programming
those entries to be equal to fully cached ("L3 + LLC") entry as per the
recommendation from architecture team.
These reserved and unspecified entries should not be used as they may be
changed to less performant variants with better coherency in the future
if more entries are needed.
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 93 ++++++++++++++++++++++++++--
1 file changed, 89 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 632e08a4592b..1089bd5fdba2 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -234,10 +234,6 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
L3_1_UC)
static const struct drm_i915_mocs_entry tgl_mocs_table[] = {
- /* Base - Error (Reserved for Non-Use) */
- MOCS_ENTRY(0, 0x0, 0x0),
- /* Base - Reserved */
- MOCS_ENTRY(1, 0x0, 0x0),
GEN11_MOCS_ENTRIES,
@@ -265,6 +261,95 @@ static const struct drm_i915_mocs_entry tgl_mocs_table[] = {
MOCS_ENTRY(61,
LE_1_UC | LE_TC_1_LLC,
L3_3_WB),
+
+ /* NOTE:
+ * Reserved and unspecified MOCS indices have been set to (L3 + LCC).
+ * These reserved entry should never be used, they may be chanaged
+ * to low performant variants with better coherency in the future if
+ * more entries are needed.
+ */
+
+ /* Reserved index 0 and 1 */
+ MOCS_ENTRY(0, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(1, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+
+ /* Reserved index 16 and 17 */
+ MOCS_ENTRY(16, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(17, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+
+ /* Reserved index 24 and 25 */
+ MOCS_ENTRY(24, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(25, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+
+ /* Unspecified indices 26 to 47 */
+ MOCS_ENTRY(26, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(27, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(28, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(29, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(30, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(31, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(32, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(33, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(34, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(35, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(36, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(37, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(38, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(39, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(40, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(41, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(42, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(43, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(44, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(45, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(46, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(47, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+
+ /* Unspecified indices 52 to 59 */
+ MOCS_ENTRY(52, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(53, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(54, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(55, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(56, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(57, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(58, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ MOCS_ENTRY(59, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB)
};
static const struct drm_i915_mocs_entry icl_mocs_table[] = {
--
2.26.2
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Initialize reserved and unspecified MOCS indices 2020-06-04 18:26 [Intel-gfx] [PATCH v2] drm/i915/gt: Initialize reserved and unspecified MOCS indices Ayaz A Siddiqui @ 2020-06-04 19:08 ` Patchwork 2020-06-04 21:34 ` [Intel-gfx] [PATCH v2] " Francisco Jerez 2020-06-04 23:10 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork 2 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2020-06-04 19:08 UTC (permalink / raw) To: Ayaz A Siddiqui; +Cc: intel-gfx == Series Details == Series: drm/i915/gt: Initialize reserved and unspecified MOCS indices URL : https://patchwork.freedesktop.org/series/78012/ State : success == Summary == CI Bug Log - changes from CI_DRM_8585 -> Patchwork_17875 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/index.html Known issues ------------ Here are the changes found in Patchwork_17875 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_module_load@reload: - fi-apl-guc: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-apl-guc/igt@i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-apl-guc/igt@i915_module_load@reload.html * igt@kms_frontbuffer_tracking@basic: - fi-tgl-y: [PASS][3] -> [DMESG-FAIL][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-tgl-y/igt@kms_frontbuffer_tracking@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-tgl-y/igt@kms_frontbuffer_tracking@basic.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-tgl-y/igt@kms_pipe_crc_basic@read-crc-pipe-c.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-tgl-y/igt@kms_pipe_crc_basic@read-crc-pipe-c.html #### Possible fixes #### * igt@i915_pm_backlight@basic-brightness: - fi-whl-u: [DMESG-WARN][7] ([i915#95]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-whl-u/igt@i915_pm_backlight@basic-brightness.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-whl-u/igt@i915_pm_backlight@basic-brightness.html * igt@i915_selftest@live@execlists: - fi-icl-y: [DMESG-FAIL][9] ([i915#1993]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-icl-y/igt@i915_selftest@live@execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-icl-y/igt@i915_selftest@live@execlists.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: - fi-tgl-y: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-tgl-y/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-tgl-y/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - {fi-tgl-dsi}: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-tgl-dsi/igt@kms_pipe_crc_basic@read-crc-pipe-c.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-tgl-dsi/igt@kms_pipe_crc_basic@read-crc-pipe-c.html #### Warnings #### * igt@gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt@kms_pipe_crc_basic@read-crc-pipe-b: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc-pipe-b.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc-pipe-b.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1897]: https://gitlab.freedesktop.org/drm/intel/issues/1897 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#1993]: https://gitlab.freedesktop.org/drm/intel/issues/1993 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 43) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8585 -> Patchwork_17875 CI-20190529: 20190529 CI_DRM_8585: 3aef9a510cfe66ba71ed397e91c517402f7c26ac @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17875: 74e4956ad45f89c7f37ff7f79108099c834ff6d8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 74e4956ad45f drm/i915/gt: Initialize reserved and unspecified MOCS indices == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/gt: Initialize reserved and unspecified MOCS indices 2020-06-04 18:26 [Intel-gfx] [PATCH v2] drm/i915/gt: Initialize reserved and unspecified MOCS indices Ayaz A Siddiqui 2020-06-04 19:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork @ 2020-06-04 21:34 ` Francisco Jerez 2020-06-08 9:47 ` Joonas Lahtinen 2020-06-04 23:10 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork 2 siblings, 1 reply; 6+ messages in thread From: Francisco Jerez @ 2020-06-04 21:34 UTC (permalink / raw) To: Ayaz A Siddiqui, intel-gfx [-- Attachment #1.1.1: Type: text/plain, Size: 5550 bytes --] Ayaz A Siddiqui <ayaz.siddiqui@intel.com> writes: > In order to avoid functional breakage of mis-programmed applications that > have grown to depend on unused MOCS entries, we are programming > those entries to be equal to fully cached ("L3 + LLC") entry as per the > recommendation from architecture team. > > These reserved and unspecified entries should not be used as they may be > changed to less performant variants with better coherency in the future > if more entries are needed. > This change seems highly questionable to me... If a future kernel release introduces a new MOCS entry with more strict coherency semantics, and an application starts relying on it, that application won't work when run on an older kernel version with this patch is applied. IOW setting uninitialized entries to the most strict caching setting available (UC) ensures forwards compatibility with future userspace, which seems like a more important design principle than giving full caching to broken userspace that accidentally makes use of an undefined MOCS entry not part of the kernel ABI. > Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_mocs.c | 93 ++++++++++++++++++++++++++-- > 1 file changed, 89 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c > index 632e08a4592b..1089bd5fdba2 100644 > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c > @@ -234,10 +234,6 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { > L3_1_UC) > > static const struct drm_i915_mocs_entry tgl_mocs_table[] = { > - /* Base - Error (Reserved for Non-Use) */ > - MOCS_ENTRY(0, 0x0, 0x0), > - /* Base - Reserved */ > - MOCS_ENTRY(1, 0x0, 0x0), > > GEN11_MOCS_ENTRIES, > > @@ -265,6 +261,95 @@ static const struct drm_i915_mocs_entry tgl_mocs_table[] = { > MOCS_ENTRY(61, > LE_1_UC | LE_TC_1_LLC, > L3_3_WB), > + > + /* NOTE: > + * Reserved and unspecified MOCS indices have been set to (L3 + LCC). > + * These reserved entry should never be used, they may be chanaged > + * to low performant variants with better coherency in the future if > + * more entries are needed. > + */ > + > + /* Reserved index 0 and 1 */ > + MOCS_ENTRY(0, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(1, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + > + /* Reserved index 16 and 17 */ > + MOCS_ENTRY(16, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(17, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + > + /* Reserved index 24 and 25 */ > + MOCS_ENTRY(24, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(25, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + > + /* Unspecified indices 26 to 47 */ > + MOCS_ENTRY(26, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(27, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(28, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(29, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(30, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(31, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(32, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(33, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(34, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(35, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(36, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(37, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(38, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(39, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(40, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(41, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(42, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(43, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(44, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(45, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(46, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(47, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + > + /* Unspecified indices 52 to 59 */ > + MOCS_ENTRY(52, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(53, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(54, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(55, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(56, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(57, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(58, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(59, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB) > }; > > static const struct drm_i915_mocs_entry icl_mocs_table[] = { > -- > 2.26.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 227 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/gt: Initialize reserved and unspecified MOCS indices 2020-06-04 21:34 ` [Intel-gfx] [PATCH v2] " Francisco Jerez @ 2020-06-08 9:47 ` Joonas Lahtinen 2020-06-09 1:39 ` Francisco Jerez 0 siblings, 1 reply; 6+ messages in thread From: Joonas Lahtinen @ 2020-06-08 9:47 UTC (permalink / raw) To: Ayaz A Siddiqui, Francisco Jerez, intel-gfx; +Cc: Kenneth Graunke + Jason and Ken Quoting Francisco Jerez (2020-06-05 00:34:57) > Ayaz A Siddiqui <ayaz.siddiqui@intel.com> writes: > > > In order to avoid functional breakage of mis-programmed applications that > > have grown to depend on unused MOCS entries, we are programming > > those entries to be equal to fully cached ("L3 + LLC") entry as per the > > recommendation from architecture team. > > > > These reserved and unspecified entries should not be used as they may be > > changed to less performant variants with better coherency in the future > > if more entries are needed. This patch message needs reworking. It should just standalone describe the technical reasoning behind the patch completely, without referring to elsewhere or to some other decision. The patch should also Cc: relevant developers who have previously been working on the MOCS code and the userspace driver folks (Mesa, compute and media). > This change seems highly questionable to me... If a future kernel > release introduces a new MOCS entry with more strict coherency > semantics, and an application starts relying on it, that application > won't work when run on an older kernel version with this patch is > applied. IOW setting uninitialized entries to the most strict caching > setting available (UC) ensures forwards compatibility with future > userspace, which seems like a more important design principle than > giving full caching to broken userspace that accidentally makes use of > an undefined MOCS entry not part of the kernel ABI. Both choices were considered, and ultimately Ken and Jason were more in favor of 'worst coherency' if using reserved MOCS entry. Your concern about newer software on older kernel is valid. But the starting point of the decision is the no-regression policy of Linux. If we have some application developed on an older kernel where the MOCS entry is unused and would be UC (best coherency), we would have no choice but to keep that entry unused indefinitely not to break the mis-programmed application. Now we have the worst coherency by default if an application is using reserved entry, making it more likely to be noticed at develop time. And even if it would not be noticed, modifying the entry for better coherency should not functionally break the application. Regards, Joonas > > Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com> > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > > --- > > drivers/gpu/drm/i915/gt/intel_mocs.c | 93 ++++++++++++++++++++++++++-- > > 1 file changed, 89 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c > > index 632e08a4592b..1089bd5fdba2 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c > > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c > > @@ -234,10 +234,6 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { > > L3_1_UC) > > > > static const struct drm_i915_mocs_entry tgl_mocs_table[] = { > > - /* Base - Error (Reserved for Non-Use) */ > > - MOCS_ENTRY(0, 0x0, 0x0), > > - /* Base - Reserved */ > > - MOCS_ENTRY(1, 0x0, 0x0), > > > > GEN11_MOCS_ENTRIES, > > > > @@ -265,6 +261,95 @@ static const struct drm_i915_mocs_entry tgl_mocs_table[] = { > > MOCS_ENTRY(61, > > LE_1_UC | LE_TC_1_LLC, > > L3_3_WB), > > + > > + /* NOTE: > > + * Reserved and unspecified MOCS indices have been set to (L3 + LCC). > > + * These reserved entry should never be used, they may be chanaged > > + * to low performant variants with better coherency in the future if > > + * more entries are needed. > > + */ > > + > > + /* Reserved index 0 and 1 */ > > + MOCS_ENTRY(0, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(1, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + > > + /* Reserved index 16 and 17 */ > > + MOCS_ENTRY(16, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(17, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + > > + /* Reserved index 24 and 25 */ > > + MOCS_ENTRY(24, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(25, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + > > + /* Unspecified indices 26 to 47 */ > > + MOCS_ENTRY(26, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(27, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(28, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(29, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(30, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(31, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(32, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(33, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(34, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(35, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(36, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(37, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(38, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(39, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(40, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(41, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(42, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(43, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(44, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(45, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(46, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(47, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + > > + /* Unspecified indices 52 to 59 */ > > + MOCS_ENTRY(52, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(53, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(54, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(55, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(56, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(57, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(58, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(59, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB) > > }; > > > > static const struct drm_i915_mocs_entry icl_mocs_table[] = { > > -- > > 2.26.2 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/gt: Initialize reserved and unspecified MOCS indices 2020-06-08 9:47 ` Joonas Lahtinen @ 2020-06-09 1:39 ` Francisco Jerez 0 siblings, 0 replies; 6+ messages in thread From: Francisco Jerez @ 2020-06-09 1:39 UTC (permalink / raw) To: Joonas Lahtinen, Ayaz A Siddiqui, intel-gfx; +Cc: Kenneth Graunke [-- Attachment #1.1.1: Type: text/plain, Size: 9200 bytes --] Joonas Lahtinen <joonas.lahtinen@linux.intel.com> writes: > + Jason and Ken > > Quoting Francisco Jerez (2020-06-05 00:34:57) >> Ayaz A Siddiqui <ayaz.siddiqui@intel.com> writes: >> >> > In order to avoid functional breakage of mis-programmed applications that >> > have grown to depend on unused MOCS entries, we are programming >> > those entries to be equal to fully cached ("L3 + LLC") entry as per the >> > recommendation from architecture team. >> > >> > These reserved and unspecified entries should not be used as they may be >> > changed to less performant variants with better coherency in the future >> > if more entries are needed. > > This patch message needs reworking. It should just standalone describe > the technical reasoning behind the patch completely, without referring > to elsewhere or to some other decision. > > The patch should also Cc: relevant developers who have previously been > working on the MOCS code and the userspace driver folks (Mesa, compute > and media). > >> This change seems highly questionable to me... If a future kernel >> release introduces a new MOCS entry with more strict coherency >> semantics, and an application starts relying on it, that application >> won't work when run on an older kernel version with this patch is >> applied. IOW setting uninitialized entries to the most strict caching >> setting available (UC) ensures forwards compatibility with future >> userspace, which seems like a more important design principle than >> giving full caching to broken userspace that accidentally makes use of >> an undefined MOCS entry not part of the kernel ABI. > > Both choices were considered, and ultimately Ken and Jason were more in > favor of 'worst coherency' if using reserved MOCS entry. n> > Your concern about newer software on older kernel is valid. But the > starting point of the decision is the no-regression policy of Linux. > > If we have some application developed on an older kernel where the MOCS > entry is unused and would be UC (best coherency), we would have no > choice but to keep that entry unused indefinitely not to break the > mis-programmed application. > That's a valid concern too, however it didn't seem like much an issue with the original Gen9 workflow that gave i915 the freedom to assign MOCS indices as it would see fit. If some broken userspace starts relying on the caching semantics of a random MOCS index not part of the currently exposed kernel ABI, and that userspace isn't some proprietary blob broken beyond repair, the kernel has the possibility (or the obligation?) to give that application the semantics it expected for that MOCS entry alone -- Which would likely improve the performance of the application beyond the original behavior unless UC was what it was actually expecting. IOW it seems to me that this conflict between forwards and backwards ABI compatibility is created by the rather artificial imperative to follow the reference MOCS tables without modification, which could conceivably tie our hands in the future and give us no choice but to break the no-regression policy if the reference MOCS tables change in a non-backwards-compatible way as has happened in the past (though luckily before any software started relying on it AFAIA), and largely defeats the point of having programmable MOCS tables IMO. Not really thrilled about that decision :P. > Now we have the worst coherency by default if an application is using > reserved entry, making it more likely to be noticed at develop time. And > even if it would not be noticed, modifying the entry for better > coherency should not functionally break the application. > > Regards, Joonas > >> > Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com> >> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> >> > --- >> > drivers/gpu/drm/i915/gt/intel_mocs.c | 93 ++++++++++++++++++++++++++-- >> > 1 file changed, 89 insertions(+), 4 deletions(-) >> > >> > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c >> > index 632e08a4592b..1089bd5fdba2 100644 >> > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c >> > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c >> > @@ -234,10 +234,6 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { >> > L3_1_UC) >> > >> > static const struct drm_i915_mocs_entry tgl_mocs_table[] = { >> > - /* Base - Error (Reserved for Non-Use) */ >> > - MOCS_ENTRY(0, 0x0, 0x0), >> > - /* Base - Reserved */ >> > - MOCS_ENTRY(1, 0x0, 0x0), >> > >> > GEN11_MOCS_ENTRIES, >> > >> > @@ -265,6 +261,95 @@ static const struct drm_i915_mocs_entry tgl_mocs_table[] = { >> > MOCS_ENTRY(61, >> > LE_1_UC | LE_TC_1_LLC, >> > L3_3_WB), >> > + >> > + /* NOTE: >> > + * Reserved and unspecified MOCS indices have been set to (L3 + LCC). >> > + * These reserved entry should never be used, they may be chanaged >> > + * to low performant variants with better coherency in the future if >> > + * more entries are needed. >> > + */ >> > + >> > + /* Reserved index 0 and 1 */ >> > + MOCS_ENTRY(0, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(1, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + >> > + /* Reserved index 16 and 17 */ >> > + MOCS_ENTRY(16, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(17, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + >> > + /* Reserved index 24 and 25 */ >> > + MOCS_ENTRY(24, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(25, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + >> > + /* Unspecified indices 26 to 47 */ >> > + MOCS_ENTRY(26, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(27, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(28, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(29, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(30, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(31, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(32, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(33, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(34, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(35, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(36, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(37, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(38, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(39, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(40, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(41, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(42, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(43, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(44, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(45, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(46, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(47, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + >> > + /* Unspecified indices 52 to 59 */ >> > + MOCS_ENTRY(52, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(53, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(54, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(55, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(56, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(57, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(58, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(59, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB) >> > }; >> > >> > static const struct drm_i915_mocs_entry icl_mocs_table[] = { >> > -- >> > 2.26.2 >> > >> > _______________________________________________ >> > Intel-gfx mailing list >> > Intel-gfx@lists.freedesktop.org >> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 227 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Initialize reserved and unspecified MOCS indices 2020-06-04 18:26 [Intel-gfx] [PATCH v2] drm/i915/gt: Initialize reserved and unspecified MOCS indices Ayaz A Siddiqui 2020-06-04 19:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork 2020-06-04 21:34 ` [Intel-gfx] [PATCH v2] " Francisco Jerez @ 2020-06-04 23:10 ` Patchwork 2 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2020-06-04 23:10 UTC (permalink / raw) To: Ayaz A Siddiqui; +Cc: intel-gfx == Series Details == Series: drm/i915/gt: Initialize reserved and unspecified MOCS indices URL : https://patchwork.freedesktop.org/series/78012/ State : success == Summary == CI Bug Log - changes from CI_DRM_8585_full -> Patchwork_17875_full ==================================================== Summary ------- **SUCCESS** No regressions found. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17875_full: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt@gem_exec_reloc@basic-concurrent16}: - shard-kbl: [TIMEOUT][1] ([i915#1930]) -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl4/igt@gem_exec_reloc@basic-concurrent16.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-kbl2/igt@gem_exec_reloc@basic-concurrent16.html Known issues ------------ Here are the changes found in Patchwork_17875_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_whisper@basic-contexts-forked: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-glk9/igt@gem_exec_whisper@basic-contexts-forked.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-glk8/igt@gem_exec_whisper@basic-contexts-forked.html * igt@i915_suspend@debugfs-reader: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#69]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl7/igt@i915_suspend@debugfs-reader.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-skl10/igt@i915_suspend@debugfs-reader.html * igt@kms_big_fb@x-tiled-64bpp-rotate-0: - shard-glk: [PASS][7] -> [DMESG-FAIL][8] ([i915#118] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-glk4/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-glk8/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html * igt@kms_big_fb@x-tiled-8bpp-rotate-0: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl6/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-apl6/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html * igt@kms_big_fb@y-tiled-32bpp-rotate-270: - shard-tglb: [PASS][11] -> [FAIL][12] ([i915#1172] / [i915#1897]) +10 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-tglb1/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-tglb1/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html * igt@kms_cursor_crc@pipe-b-cursor-256x85-offscreen: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#54]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl6/igt@kms_cursor_crc@pipe-b-cursor-256x85-offscreen.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-256x85-offscreen.html * igt@kms_flip_tiling@flip-x-tiled: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#95]) +15 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl8/igt@kms_flip_tiling@flip-x-tiled.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-apl4/igt@kms_flip_tiling@flip-x-tiled.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc: - shard-iclb: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#93] / [i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt: - shard-tglb: [PASS][21] -> [FAIL][22] ([i915#1897]) +139 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#49]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl9/igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-skl3/igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html * igt@kms_plane_scaling@pipe-c-plane-scaling: - shard-skl: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +7 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl8/igt@kms_plane_scaling@pipe-c-plane-scaling.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-skl4/igt@kms_plane_scaling@pipe-c-plane-scaling.html * igt@kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-iclb7/igt@kms_psr@psr2_primary_mmap_gtt.html * igt@kms_vblank@pipe-c-ts-continuation-suspend: - shard-apl: [PASS][29] -> [DMESG-WARN][30] ([i915#180]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl4/igt@kms_vblank@pipe-c-ts-continuation-suspend.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-apl1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html #### Possible fixes #### * {igt@gem_ctx_isolation@preservation-s3@rcs0}: - shard-apl: [DMESG-WARN][31] ([i915#180]) -> [PASS][32] +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl4/igt@gem_ctx_isolation@preservation-s3@rcs0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-apl8/igt@gem_ctx_isolation@preservation-s3@rcs0.html * {igt@gem_exec_schedule@implicit-boths@bcs0}: - shard-snb: [INCOMPLETE][33] ([i915#82]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-snb4/igt@gem_exec_schedule@implicit-boths@bcs0.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-snb4/igt@gem_exec_schedule@implicit-boths@bcs0.html * {igt@gem_exec_schedule@preempt@bcs0}: - shard-tglb: [DMESG-WARN][35] ([i915#402]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-tglb8/igt@gem_exec_schedule@preempt@bcs0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-tglb1/igt@gem_exec_schedule@preempt@bcs0.html * igt@gem_exec_whisper@basic-queues-forked-all: - shard-glk: [DMESG-WARN][37] ([i915#118] / [i915#95]) -> [PASS][38] +3 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-glk4/igt@gem_exec_whisper@basic-queues-forked-all.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-glk1/igt@gem_exec_whisper@basic-queues-forked-all.html * igt@gen9_exec_parse@allowed-all: - shard-kbl: [DMESG-WARN][39] ([i915#1436] / [i915#716]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl3/igt@gen9_exec_parse@allowed-all.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-kbl2/igt@gen9_exec_parse@allowed-all.html * igt@kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][41] ([i915#118] / [i915#95]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-glk8/igt@kms_big_fb@linear-64bpp-rotate-180.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-glk5/igt@kms_big_fb@linear-64bpp-rotate-180.html * igt@kms_big_fb@x-tiled-32bpp-rotate-180: - shard-skl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +4 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl1/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-skl2/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html * igt@kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][45] ([i915#93] / [i915#95]) -> [PASS][46] +2 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl1/igt@kms_color@pipe-c-ctm-red-to-blue.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-kbl1/igt@kms_color@pipe-c-ctm-red-to-blue.html * igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen: - shard-skl: [FAIL][47] ([i915#54]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-skl9/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html * igt@kms_cursor_crc@pipe-a-cursor-64x21-random: - shard-kbl: [DMESG-FAIL][49] ([i915#54] / [i915#95]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-64x21-random.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-64x21-random.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-kbl: [DMESG-WARN][51] ([i915#180]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-suspend.html * igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge: - shard-glk: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-glk5/igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-glk7/igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge.html * igt@kms_cursor_legacy@pipe-c-torture-move: - shard-hsw: [DMESG-WARN][55] ([i915#128]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-hsw7/igt@kms_cursor_legacy@pipe-c-torture-move.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-hsw7/igt@kms_cursor_legacy@pipe-c-torture-move.html * igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size: - shard-tglb: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-tglb7/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-tglb2/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html - shard-apl: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl3/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-apl1/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html * {igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1}: - shard-skl: [FAIL][61] ([i915#1928]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html * {igt@kms_getfb@getfb2-handle-protection}: - shard-apl: [DMESG-WARN][63] ([i915#95]) -> [PASS][64] +15 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl7/igt@kms_getfb@getfb2-handle-protection.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-apl4/igt@kms_getfb@getfb2-handle-protection.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][65] ([i915#1188]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl5/igt@kms_hdr@bpc-switch-suspend.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [SKIP][67] ([fdo#109441]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html #### Warnings #### * igt@kms_content_protection@atomic-dpms: - shard-apl: [FAIL][69] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][70] ([i915#1319] / [i915#1635]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl4/igt@kms_content_protection@atomic-dpms.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-apl2/igt@kms_content_protection@atomic-dpms.html * igt@kms_content_protection@lic: - shard-apl: [TIMEOUT][71] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][72] ([fdo#110321] / [i915#95]) +1 similar issue [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl4/igt@kms_content_protection@lic.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-apl8/igt@kms_content_protection@lic.html * igt@kms_content_protection@srm: - shard-kbl: [DMESG-FAIL][73] ([fdo#110321] / [i915#95]) -> [TIMEOUT][74] ([i915#1319]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl2/igt@kms_content_protection@srm.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-kbl1/igt@kms_content_protection@srm.html * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-glk: [INCOMPLETE][75] ([i915#58] / [k.org#198133]) -> [TIMEOUT][76] ([i915#1958]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-glk6/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-glk9/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#1172]: https://gitlab.freedesktop.org/drm/intel/issues/1172 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1897]: https://gitlab.freedesktop.org/drm/intel/issues/1897 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8585 -> Patchwork_17875 CI-20190529: 20190529 CI_DRM_8585: 3aef9a510cfe66ba71ed397e91c517402f7c26ac @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17875: 74e4956ad45f89c7f37ff7f79108099c834ff6d8 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-06-09 1:39 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-06-04 18:26 [Intel-gfx] [PATCH v2] drm/i915/gt: Initialize reserved and unspecified MOCS indices Ayaz A Siddiqui 2020-06-04 19:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork 2020-06-04 21:34 ` [Intel-gfx] [PATCH v2] " Francisco Jerez 2020-06-08 9:47 ` Joonas Lahtinen 2020-06-09 1:39 ` Francisco Jerez 2020-06-04 23:10 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
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