[v10][PATCH 0/8] drm/i915: adding state checker for gamma lut values

[v10][PATCH 0/8] drm/i915: adding state checker for gamma lut values

[Swati Sharma]

In this patch series, added state checker to validate gamma
(8BIT and 10BIT).This reads hardware state, and compares the originally
requested state(s/w) to the state read from the hardware.
This is done for legacy, ilk, glk and their variant platforms. Rest of
the platforms will be enabled on top of this later.

Intentionally, excluded bdw and ivb since they have spilt gamma mode;
for which degamma read outs are required (which I think shouldn't be
included in this patch series). Will include after degamma state checker
is completed.

v1:  -Implementation done for legacy platforms
      (removed all the placeholders) (Jani)
v2:  -Restructured code and created platform specific patch series for 
      gamma validation
v3:  -Rebase
v4:  -Minor changes-function name changes mainly
v5:  -Added degamma validation (Ville)
v6:  -Removed degamma changes, debugging was becoming difficult
     -Added function to assign bit_precision for gamma/degamma
      lut values /platform
     -Added debug info into intel_dump_pipe_config() (Jani)
v7:  -Added platform specific functions to compute gamma bit precision
      on the basis of GAMMA_MODE (Ville)
     -Corrected checkpatch warnings
v8:  -Restructured code
     -Removed bdw and ivb platform state checker
v9:  -Obliged 80 character word limit [Uma]
     -Added state checker for icl
     -Added bit precision func for icl
v10: -Dropped multi-seg gamma mode [Jani]
     -Enabled basic infrastructure only [Jani]
     -Minor fixes [Jani]

Swati Sharma (8):
  drm/i915/display: Add func to get gamma bit precision
  drm/i915/display: Add debug log for color parameters
  drm/i915/display: Add func to compare hw/sw gamma lut
  drm/i915/display: Add macro to compare gamma hw/sw lut
  drm/i915/display: Extract i9xx_read_luts()
  drm/i915/display: Extract ilk_read_luts()
  drm/i915/display: Extract glk_read_luts()
  FOR_TESTING_ONLY: Print rgb values of hw and sw blobs

 drivers/gpu/drm/i915/display/intel_color.c   | 284 ++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_color.h   |   7 +
 drivers/gpu/drm/i915/display/intel_display.c |  34 ++++
 drivers/gpu/drm/i915/i915_reg.h              |   9 +
 4 files changed, 331 insertions(+), 3 deletions(-)

-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[v10][PATCH 1/8] drm/i915/display: Add func to get gamma bit precision

[Swati Sharma]

Each platform supports different gamma modes and each gamma mode
has different bit precision. Here bit precision corresponds
to number of bits the hw LUT supports.

Add func per platform to return bit precision corresponding to gamma mode
which will be later used as a parameter in lut comparison function
intel_color_lut_equal().

This is done for legacy, ilk, glk and their variant platforms.

v6:  -Added func intel_color_get_bit_precision() to get bit precision for
      gamma and degamma lut readout depending upon platform and
      corresponding to load_luts() [Ankit]
     -Made patch11 as patch3 [Jani]
v7:  -Renamed func intel_color_get_bit_precision() to
      intel_color_get_gamma_bit_precision()
     -Added separate function/platform for gamma bit precision [Ville]
     -Corrected checkpatch warnings
v8:  -Split patch 3 into 4 separate patches
v9:  -Changed commit message, gave more info [Uma]
     -Added precision func for icl+ platform
v10: -Removed precision func for chv and icl+ platforms [Jani]
     -Added gamma_enable check once [Jani]

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 60 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_color.h |  1 +
 2 files changed, 61 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 71a0201..b5c0c65 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1371,6 +1371,66 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
 	return 0;
 }
 
+static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
+{
+	switch (crtc_state->gamma_mode) {
+	case GAMMA_MODE_MODE_8BIT:
+		return 8;
+	case GAMMA_MODE_MODE_10BIT:
+		return 16;
+	default:
+		MISSING_CASE(crtc_state->gamma_mode);
+		return 0;
+	}
+}
+
+static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
+{
+	if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
+		return 0;
+
+	switch (crtc_state->gamma_mode) {
+	case GAMMA_MODE_MODE_8BIT:
+		return 8;
+	case GAMMA_MODE_MODE_10BIT:
+		return 10;
+	default:
+		MISSING_CASE(crtc_state->gamma_mode);
+		return 0;
+	}
+}
+
+static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
+{
+	switch (crtc_state->gamma_mode) {
+	case GAMMA_MODE_MODE_8BIT:
+		return 8;
+	case GAMMA_MODE_MODE_10BIT:
+		return 10;
+	default:
+		MISSING_CASE(crtc_state->gamma_mode);
+		return 0;
+	}
+}
+
+int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+	if (!crtc_state->gamma_enable)
+		return 0;
+
+	if (HAS_GMCH(dev_priv) && !IS_CHERRYVIEW(dev_priv))
+		return i9xx_gamma_precision(crtc_state);
+	else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+		return glk_gamma_precision(crtc_state);
+	else if (IS_IRONLAKE(dev_priv))
+		return ilk_gamma_precision(crtc_state);
+
+	return 0;
+}
+
 void intel_color_init(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h
index 057e8ac..0226d3a 100644
--- a/drivers/gpu/drm/i915/display/intel_color.h
+++ b/drivers/gpu/drm/i915/display/intel_color.h
@@ -14,5 +14,6 @@
 void intel_color_commit(const struct intel_crtc_state *crtc_state);
 void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
 void intel_color_get_config(struct intel_crtc_state *crtc_state);
+int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_COLOR_H__ */
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[v10][PATCH 2/8] drm/i915/display: Add debug log for color parameters

[Swati Sharma]

Add debug log for color related parameters like gamma_mode, gamma_enable,
csc_enable, etc inside intel_dump_pipe_config().

v6: -Added debug log for color para in intel_dump_pipe_config [Jani]
v7: -Split patch 3 into 4 patches
v8: -Corrected alignment [Uma]

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ea2915d..f9c0842 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12138,6 +12138,15 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 
 	intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
 
+	if (IS_CHERRYVIEW(dev_priv))
+		DRM_DEBUG_KMS("cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
+			      pipe_config->cgm_mode, pipe_config->gamma_mode,
+			      pipe_config->gamma_enable, pipe_config->csc_enable);
+	else
+		DRM_DEBUG_KMS("csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
+			      pipe_config->csc_mode, pipe_config->gamma_mode,
+			      pipe_config->gamma_enable, pipe_config->csc_enable);
+
 dump_planes:
 	if (!state)
 		return;
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[v10][PATCH 3/8] drm/i915/display: Add func to compare hw/sw gamma lut

[Swati Sharma]

Add func intel_color_lut_equal() to compare hw/sw gamma
lut values. Since hw/sw gamma lut sizes and lut entries comparison
will be different for different gamma modes, add gamma mode dependent
checks.

v3:  -Rebase
v4:  -Renamed intel_compare_color_lut() to intel_color_lut_equal() [Jani]
     -Added the default label above the correct label [Jani]
     -Corrected smatch warn "variable dereferenced before check"
      [Dan Carpenter]
v5:  -Added condition (!blob1 && !blob2) return true [Jani]
v6:  -Made patch11 as patch3 [Jani]
v8:  -Split patch 3 into 4 patches
     -Optimized blob check condition [Ville]
v9:  -Exclude spilt gamma mode (bdw and ivb platforms)
      as there is exception in way gamma values are written in
      hardware [Ville]
     -Added exception made in commit [Uma]
     -Dropped else, character limit and indentation [Uma]
     -Added multi segmented gama mode for icl+ platforms [Uma]
v10: -Dropped multi segmented mode for icl+ platforms [Jani]
     -Removed references of sw and hw state in compare code [Jani]
     -Dropped inline from func [Jani]

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 72 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_color.h |  6 +++
 2 files changed, 78 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index b5c0c65..1ab561d 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1431,6 +1431,78 @@ int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_stat
 	return 0;
 }
 
+static bool err_check(struct drm_color_lut *lut1,
+		      struct drm_color_lut *lut2, u32 err)
+{
+	return ((abs((long)lut2->red - lut1->red)) <= err) &&
+		((abs((long)lut2->blue - lut1->blue)) <= err) &&
+		((abs((long)lut2->green - lut1->green)) <= err);
+}
+
+static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1,
+					struct drm_color_lut *lut2,
+					int lut_size, u32 err)
+{
+	int i;
+
+	for (i = 0; i < lut_size; i++) {
+		if (!err_check(&lut1[i], &lut2[i], err))
+			return false;
+	}
+
+	return true;
+}
+
+bool intel_color_lut_equal(struct drm_property_blob *blob1,
+			   struct drm_property_blob *blob2,
+			   u32 gamma_mode, u32 bit_precision)
+{
+	struct drm_color_lut *lut1, *lut2;
+	int lut_size1, lut_size2;
+	u32 err;
+
+	if (!blob1 != !blob2)
+		return false;
+
+	if (!blob1)
+		return true;
+
+	lut_size1 = drm_color_lut_size(blob1);
+	lut_size2 = drm_color_lut_size(blob2);
+
+	/* check sw and hw lut size */
+	switch (gamma_mode) {
+	case GAMMA_MODE_MODE_8BIT:
+	case GAMMA_MODE_MODE_10BIT:
+		if (lut_size1 != lut_size2)
+			return false;
+		break;
+	default:
+		MISSING_CASE(gamma_mode);
+			return false;
+	}
+
+	lut1 = blob1->data;
+	lut2 = blob2->data;
+
+	err = 0xffff >> bit_precision;
+
+	/* check sw and hw lut entry to be equal */
+	switch (gamma_mode) {
+	case GAMMA_MODE_MODE_8BIT:
+	case GAMMA_MODE_MODE_10BIT:
+		if (!intel_color_lut_entry_equal(lut1, lut2,
+						 lut_size2, err))
+			return false;
+		break;
+	default:
+		MISSING_CASE(gamma_mode);
+			return false;
+	}
+
+	return true;
+}
+
 void intel_color_init(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h
index 0226d3a..173727a 100644
--- a/drivers/gpu/drm/i915/display/intel_color.h
+++ b/drivers/gpu/drm/i915/display/intel_color.h
@@ -6,8 +6,11 @@
 #ifndef __INTEL_COLOR_H__
 #define __INTEL_COLOR_H__
 
+#include <linux/types.h>
+
 struct intel_crtc_state;
 struct intel_crtc;
+struct drm_property_blob;
 
 void intel_color_init(struct intel_crtc *crtc);
 int intel_color_check(struct intel_crtc_state *crtc_state);
@@ -15,5 +18,8 @@
 void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
 void intel_color_get_config(struct intel_crtc_state *crtc_state);
 int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state);
+bool intel_color_lut_equal(struct drm_property_blob *blob1,
+			   struct drm_property_blob *blob2,
+			   u32 gamma_mode, u32 bit_precision);
 
 #endif /* __INTEL_COLOR_H__ */
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[v10][PATCH 4/8] drm/i915/display: Add macro to compare gamma hw/sw lut

[Swati Sharma]

Add macro to compare hw/sw gamma lut values. First need to
check whether hw/sw gamma mode matches or not. If not
no need to compare lut values, if matches then only compare
lut entries.

v5: -Called PIPE_CONF_CHECK_COLOR_LUT inside if (!adjust) [Jani]
    -Added #undef PIPE_CONF_CHECK_COLOR_LUT [Jani]
v8: -Added check for gamma mode before gamma lut entry comparison
     [Jani]
    -Split patch 3 into 4 patches

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f9c0842..776b365 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12529,6 +12529,7 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
 {
 	struct drm_i915_private *dev_priv = to_i915(current_config->base.crtc->dev);
 	bool ret = true;
+	u32 bp_gamma = 0;
 	bool fixup_inherited = fastset &&
 		(current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
 		!(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
@@ -12680,6 +12681,24 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
 	} \
 } while (0)
 
+#define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
+	if (current_config->name1 != pipe_config->name1) { \
+		pipe_config_mismatch(fastset, __stringify(name1), \
+				"(expected %i, found %i, won't compare lut values)\n", \
+				current_config->name1, \
+				pipe_config->name1); \
+		ret = false;\
+	} else { \
+		if (!intel_color_lut_equal(current_config->name2, \
+					pipe_config->name2, pipe_config->name1, \
+					bit_precision)) { \
+			pipe_config_mismatch(fastset, __stringify(name2), \
+					"hw_state doesn't match sw_state\n"); \
+			ret = false; \
+		} \
+	} \
+} while (0)
+
 #define PIPE_CONF_QUIRK(quirk) \
 	((current_config->quirks | pipe_config->quirks) & (quirk))
 
@@ -12775,6 +12794,11 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
 			PIPE_CONF_CHECK_X(csc_mode);
 		PIPE_CONF_CHECK_BOOL(gamma_enable);
 		PIPE_CONF_CHECK_BOOL(csc_enable);
+
+		bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
+		if (bp_gamma)
+			PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, base.gamma_lut, bp_gamma);
+
 	}
 
 	PIPE_CONF_CHECK_BOOL(double_wide);
@@ -12837,6 +12861,7 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
 #undef PIPE_CONF_CHECK_P
 #undef PIPE_CONF_CHECK_FLAGS
 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
+#undef PIPE_CONF_CHECK_COLOR_LUT
 #undef PIPE_CONF_QUIRK
 
 	return ret;
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[v10][PATCH 5/8] drm/i915/display: Extract i9xx_read_luts()

[Swati Sharma]

For the legacy(gen < 4) gamma, add hw read out to create hw blob of gamma
lut values. Also, add function intel_color_lut_pack to convert hw value
with given bit precision to lut property val.

v4:  -No need to initialize *blob [Jani]
     -Removed right shifts [Jani]
     -Dropped dev local var [Jani]
v5:  -Returned blob instead of assigning it internally within the
      function [Ville]
     -Renamed function i9xx_get_color_config() to i9xx_read_luts()
     -Renamed i9xx_get_config_internal() to i9xx_read_lut_8() [Ville]
v9:  -Change in commit message [Jani, Uma]
     -Wrap commit within 75 characters [Uma]
     -Use macro for 256 [Uma]
     -Made read func para as const [Ville, Uma]
v10: -Made i9xx_read_luts() static [Jani]

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 54 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h            |  3 ++
 2 files changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 1ab561d..55076de 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1503,6 +1503,59 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
 	return true;
 }
 
+/* convert hw value with given bit_precision to lut property val */
+static u32 intel_color_lut_pack(u32 val, u32 bit_precision)
+{
+	u32 max = 0xffff >> (16 - bit_precision);
+
+	val = clamp_val(val, 0, max);
+
+	if (bit_precision < 16)
+		val <<= 16 - bit_precision;
+
+	return val;
+}
+
+static struct drm_property_blob *
+i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+	struct drm_property_blob *blob;
+	struct drm_color_lut *blob_data;
+	u32 i, val;
+
+	blob = drm_property_create_blob(&dev_priv->drm,
+					sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
+					NULL);
+	if (IS_ERR(blob))
+		return NULL;
+
+	blob_data = blob->data;
+
+	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
+		if (HAS_GMCH(dev_priv))
+			val = I915_READ(PALETTE(pipe, i));
+		else
+			val = I915_READ(LGC_PALETTE(pipe, i));
+
+		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+							LGC_PALETTE_RED_MASK, val), 8);
+		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+							  LGC_PALETTE_GREEN_MASK, val), 8);
+		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+							 LGC_PALETTE_BLUE_MASK, val), 8);
+	}
+
+	return blob;
+}
+
+static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
+{
+	crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+}
+
 void intel_color_init(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1523,6 +1576,7 @@ void intel_color_init(struct intel_crtc *crtc)
 			dev_priv->display.color_check = i9xx_color_check;
 			dev_priv->display.color_commit = i9xx_color_commit;
 			dev_priv->display.load_luts = i9xx_load_luts;
+			dev_priv->display.read_luts = i9xx_read_luts;
 		}
 	} else {
 		if (INTEL_GEN(dev_priv) >= 11)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 02e1ef1..09ea5b1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7192,6 +7192,9 @@ enum {
 /* legacy palette */
 #define _LGC_PALETTE_A           0x4a000
 #define _LGC_PALETTE_B           0x4a800
+#define LGC_PALETTE_RED_MASK     REG_GENMASK(23, 16)
+#define LGC_PALETTE_GREEN_MASK   REG_GENMASK(15, 8)
+#define LGC_PALETTE_BLUE_MASK    REG_GENMASK(7, 0)
 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
 
 /* ilk/snb precision palette */
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[v10][PATCH 6/8] drm/i915/display: Extract ilk_read_luts()

[Swati Sharma]

For ilk, add hw read out to create hw blob of gamma
lut values.

v4:  -No need to initialize *blob [Jani]
     -Removed right shifts [Jani]
     -Dropped dev local var [Jani]
v5:  -Returned blob instead of assigning it internally within the
      function [Ville]
     -Renamed ilk_get_color_config() to ilk_read_luts() [Ville]
v9:  -80 character limit [Uma]
     -Made read func para as const [Ville, Uma]
     -Renamed ilk_read_gamma_lut() to ilk_read_lut_10() [Uma, Ville]
v10: -Made ilk_read_luts() static [Jani]
     -ilk_load_lut_10 has lut_size, not (lut_size - 1) [Jani]

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 45 +++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h            |  3 ++
 2 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 55076de..80f82b2 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1556,6 +1556,47 @@ static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
 	crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
 }
 
+static struct drm_property_blob *
+ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	enum pipe pipe = crtc->pipe;
+	struct drm_property_blob *blob;
+	struct drm_color_lut *blob_data;
+	u32 i, val;
+
+	blob = drm_property_create_blob(&dev_priv->drm,
+					sizeof(struct drm_color_lut) * lut_size,
+					NULL);
+	if (IS_ERR(blob))
+		return NULL;
+
+	blob_data = blob->data;
+
+	for (i = 0; i < lut_size; i++) {
+		val = I915_READ(PREC_PALETTE(pipe, i));
+
+		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+							PREC_PALETTE_RED_MASK, val), 10);
+		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+							  PREC_PALETTE_GREEN_MASK, val), 10);
+		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+							 PREC_PALETTE_BLUE_MASK, val), 10);
+	}
+
+	return blob;
+}
+
+static void ilk_read_luts(struct intel_crtc_state *crtc_state)
+{
+	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+		crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+	else
+		crtc_state->base.gamma_lut = ilk_read_lut_10(crtc_state);
+}
+
 void intel_color_init(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1603,8 +1644,10 @@ void intel_color_init(struct intel_crtc *crtc)
 			dev_priv->display.load_luts = bdw_load_luts;
 		else if (INTEL_GEN(dev_priv) >= 7)
 			dev_priv->display.load_luts = ivb_load_luts;
-		else
+		else {
 			dev_priv->display.load_luts = ilk_load_luts;
+			dev_priv->display.read_luts = ilk_read_luts;
+		}
 	}
 
 	drm_crtc_enable_color_mgmt(&crtc->base,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 09ea5b1..67d8cad 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7200,6 +7200,9 @@ enum {
 /* ilk/snb precision palette */
 #define _PREC_PALETTE_A           0x4b000
 #define _PREC_PALETTE_B           0x4c000
+#define   PREC_PALETTE_RED_MASK   REG_GENMASK(29, 20)
+#define   PREC_PALETTE_GREEN_MASK REG_GENMASK(19, 10)
+#define   PREC_PALETTE_BLUE_MASK  REG_GENMASK(9, 0)
 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
 
 #define  _PREC_PIPEAGCMAX              0x4d000
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[v10][PATCH 7/8] drm/i915/display: Extract glk_read_luts()

[Swati Sharma]

For glk, add hw read out to create hw blob of gamma
lut values.

v4: -No need to initialize *blob [Jani]
    -Removed right shifts [Jani]
    -Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally within the
     function [Ville]
    -Renamed glk_get_color_config() to glk_read_luts() [Ville]
    -Added degamma validation [Ville]
v9: -80 character limit [Uma]
    -Made read func para as const [Ville, Uma]

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 51 ++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h            |  3 ++
 2 files changed, 52 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 80f82b2..6d641e1 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1597,6 +1597,52 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
 		crtc_state->base.gamma_lut = ilk_read_lut_10(crtc_state);
 }
 
+static struct drm_property_blob *
+glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	int hw_lut_size = ivb_lut_10_size(prec_index);
+	enum pipe pipe = crtc->pipe;
+	struct drm_property_blob *blob;
+	struct drm_color_lut *blob_data;
+	u32 i, val;
+
+	I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
+		   PAL_PREC_AUTO_INCREMENT);
+
+	blob = drm_property_create_blob(&dev_priv->drm,
+					sizeof(struct drm_color_lut) * hw_lut_size,
+					NULL);
+	if (IS_ERR(blob))
+		return NULL;
+
+	blob_data = blob->data;
+
+	for (i = 0; i < hw_lut_size; i++) {
+		val = I915_READ(PREC_PAL_DATA(pipe));
+
+		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+							PREC_PAL_DATA_RED_MASK, val), 10);
+		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+							PREC_PAL_DATA_GREEN_MASK, val), 10);
+		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+							PREC_PAL_DATA_BLUE_MASK, val), 10);
+	}
+
+	I915_WRITE(PREC_PAL_INDEX(pipe), 0);
+
+	return blob;
+}
+
+static void glk_read_luts(struct intel_crtc_state *crtc_state)
+{
+	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+		crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+	else
+		crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
+}
+
 void intel_color_init(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1638,9 +1684,10 @@ void intel_color_init(struct intel_crtc *crtc)
 
 		if (INTEL_GEN(dev_priv) >= 11)
 			dev_priv->display.load_luts = icl_load_luts;
-		else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+		else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
 			dev_priv->display.load_luts = glk_load_luts;
-		else if (INTEL_GEN(dev_priv) >= 8)
+			dev_priv->display.read_luts = glk_read_luts;
+		} else if (INTEL_GEN(dev_priv) >= 8)
 			dev_priv->display.load_luts = bdw_load_luts;
 		else if (INTEL_GEN(dev_priv) >= 7)
 			dev_priv->display.load_luts = ivb_load_luts;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 67d8cad..c584d0e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10259,6 +10259,9 @@ enum skl_power_gate {
 #define _PAL_PREC_GC_MAX_A	0x4A410
 #define _PAL_PREC_GC_MAX_B	0x4AC10
 #define _PAL_PREC_GC_MAX_C	0x4B410
+#define   PREC_PAL_DATA_RED_MASK	REG_GENMASK(29, 20)
+#define   PREC_PAL_DATA_GREEN_MASK	REG_GENMASK(19, 10)
+#define   PREC_PAL_DATA_BLUE_MASK	REG_GENMASK(9, 0)
 #define _PAL_PREC_EXT_GC_MAX_A	0x4A420
 #define _PAL_PREC_EXT_GC_MAX_B	0x4AC20
 #define _PAL_PREC_EXT_GC_MAX_C	0x4B420
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[v10][PATCH 8/8] FOR_TESTING_ONLY: Print rgb values of hw and sw blobs

[Swati Sharma]

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 6d641e1..78608a5 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1434,6 +1434,8 @@ int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_stat
 static bool err_check(struct drm_color_lut *lut1,
 		      struct drm_color_lut *lut2, u32 err)
 {
+	DRM_DEBUG_KMS("hw_lut->red=0x%x sw_lut->red=0x%x hw_lut->blue=0x%x sw_lut->blue=0x%x hw_lut->green=0x%x sw_lut->green=0x%x", lut2->red, lut1->red, lut2->blue, lut1->blue, lut2->green, lut1->green);
+
 	return ((abs((long)lut2->red - lut1->red)) <= err) &&
 		((abs((long)lut2->blue - lut1->blue)) <= err) &&
 		((abs((long)lut2->green - lut1->green)) <= err);
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for drm/i915: adding state checker for gamma lut values (rev14)

[Patchwork]

== Series Details ==

Series: drm/i915: adding state checker for gamma lut values (rev14)
URL   : https://patchwork.freedesktop.org/series/58039/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
122b0ae456db drm/i915/display: Add func to get gamma bit precision
ad9f91835ee7 drm/i915/display: Add debug log for color parameters
8352876a8f80 drm/i915/display: Add func to compare hw/sw gamma lut
6206ac8d1f9c drm/i915/display: Add macro to compare gamma hw/sw lut
-:36: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name1' - possible side-effects?
#36: FILE: drivers/gpu/drm/i915/display/intel_display.c:12686:
+#define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
+	if (current_config->name1 != pipe_config->name1) { \
+		pipe_config_mismatch(fastset, __stringify(name1), \
+				"(expected %i, found %i, won't compare lut values)\n", \
+				current_config->name1, \
+				pipe_config->name1); \
+		ret = false;\
+	} else { \
+		if (!intel_color_lut_equal(current_config->name2, \
+					pipe_config->name2, pipe_config->name1, \
+					bit_precision)) { \
+			pipe_config_mismatch(fastset, __stringify(name2), \
+					"hw_state doesn't match sw_state\n"); \
+			ret = false; \
+		} \
+	} \
+} while (0)

-:36: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name1' may be better as '(name1)' to avoid precedence issues
#36: FILE: drivers/gpu/drm/i915/display/intel_display.c:12686:
+#define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
+	if (current_config->name1 != pipe_config->name1) { \
+		pipe_config_mismatch(fastset, __stringify(name1), \
+				"(expected %i, found %i, won't compare lut values)\n", \
+				current_config->name1, \
+				pipe_config->name1); \
+		ret = false;\
+	} else { \
+		if (!intel_color_lut_equal(current_config->name2, \
+					pipe_config->name2, pipe_config->name1, \
+					bit_precision)) { \
+			pipe_config_mismatch(fastset, __stringify(name2), \
+					"hw_state doesn't match sw_state\n"); \
+			ret = false; \
+		} \
+	} \
+} while (0)

-:36: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name2' - possible side-effects?
#36: FILE: drivers/gpu/drm/i915/display/intel_display.c:12686:
+#define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
+	if (current_config->name1 != pipe_config->name1) { \
+		pipe_config_mismatch(fastset, __stringify(name1), \
+				"(expected %i, found %i, won't compare lut values)\n", \
+				current_config->name1, \
+				pipe_config->name1); \
+		ret = false;\
+	} else { \
+		if (!intel_color_lut_equal(current_config->name2, \
+					pipe_config->name2, pipe_config->name1, \
+					bit_precision)) { \
+			pipe_config_mismatch(fastset, __stringify(name2), \
+					"hw_state doesn't match sw_state\n"); \
+			ret = false; \
+		} \
+	} \
+} while (0)

-:36: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name2' may be better as '(name2)' to avoid precedence issues
#36: FILE: drivers/gpu/drm/i915/display/intel_display.c:12686:
+#define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
+	if (current_config->name1 != pipe_config->name1) { \
+		pipe_config_mismatch(fastset, __stringify(name1), \
+				"(expected %i, found %i, won't compare lut values)\n", \
+				current_config->name1, \
+				pipe_config->name1); \
+		ret = false;\
+	} else { \
+		if (!intel_color_lut_equal(current_config->name2, \
+					pipe_config->name2, pipe_config->name1, \
+					bit_precision)) { \
+			pipe_config_mismatch(fastset, __stringify(name2), \
+					"hw_state doesn't match sw_state\n"); \
+			ret = false; \
+		} \
+	} \
+} while (0)

total: 0 errors, 0 warnings, 4 checks, 49 lines checked
0ee282955ff1 drm/i915/display: Extract i9xx_read_luts()
-:71: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#71: FILE: drivers/gpu/drm/i915/display/intel_color.c:1543:
+		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:73: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#73: FILE: drivers/gpu/drm/i915/display/intel_color.c:1545:
+		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:75: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#75: FILE: drivers/gpu/drm/i915/display/intel_color.c:1547:
+		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(

total: 0 errors, 0 warnings, 3 checks, 75 lines checked
aac65c8c33e5 drm/i915/display: Extract ilk_read_luts()
-:54: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#54: FILE: drivers/gpu/drm/i915/display/intel_color.c:1581:
+		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:56: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#56: FILE: drivers/gpu/drm/i915/display/intel_color.c:1583:
+		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:58: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#58: FILE: drivers/gpu/drm/i915/display/intel_color.c:1585:
+		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:81: CHECK:BRACES: Unbalanced braces around else statement
#81: FILE: drivers/gpu/drm/i915/display/intel_color.c:1647:
+		else {

total: 0 errors, 0 warnings, 4 checks, 67 lines checked
51f505e22c73 drm/i915/display: Extract glk_read_luts()
-:54: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#54: FILE: drivers/gpu/drm/i915/display/intel_color.c:1625:
+		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:56: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#56: FILE: drivers/gpu/drm/i915/display/intel_color.c:1627:
+		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:58: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#58: FILE: drivers/gpu/drm/i915/display/intel_color.c:1629:
+		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(

total: 0 errors, 0 warnings, 3 checks, 73 lines checked
b2aefcd3a19b FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:16: WARNING:LONG_LINE: line over 100 characters
#16: FILE: drivers/gpu/drm/i915/display/intel_color.c:1437:
+	DRM_DEBUG_KMS("hw_lut->red=0x%x sw_lut->red=0x%x hw_lut->blue=0x%x sw_lut->blue=0x%x hw_lut->green=0x%x sw_lut->green=0x%x", lut2->red, lut1->red, lut2->blue, lut1->blue, lut2->green, lut1->green);

total: 0 errors, 2 warnings, 0 checks, 8 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for drm/i915: adding state checker for gamma lut values (rev14)

[Patchwork]

== Series Details ==

Series: drm/i915: adding state checker for gamma lut values (rev14)
URL   : https://patchwork.freedesktop.org/series/58039/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6829 -> Patchwork_14271
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/

Known issues
------------

  Here are the changes found in Patchwork_14271 that come from known issues:

### IGT changes ###

#### Warnings ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][1] ([fdo#111407]) -> [FAIL][2] ([fdo#111096])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407


Participating hosts (53 -> 45)
------------------------------

  Missing    (8): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6829 -> Patchwork_14271

  CI-20190529: 20190529
  CI_DRM_6829: f079fd4ac5dcc7e76550a7068f655d3e665088d1 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5167: 81f7a49bc80e6d9f27e33859fd94fd11e13cafa0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14271: b2aefcd3a19b12de0e844f800841a7acc7946d3c @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

b2aefcd3a19b FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
51f505e22c73 drm/i915/display: Extract glk_read_luts()
aac65c8c33e5 drm/i915/display: Extract ilk_read_luts()
0ee282955ff1 drm/i915/display: Extract i9xx_read_luts()
6206ac8d1f9c drm/i915/display: Add macro to compare gamma hw/sw lut
8352876a8f80 drm/i915/display: Add func to compare hw/sw gamma lut
ad9f91835ee7 drm/i915/display: Add debug log for color parameters
122b0ae456db drm/i915/display: Add func to get gamma bit precision

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for drm/i915: adding state checker for gamma lut values (rev14)

[Patchwork]

== Series Details ==

Series: drm/i915: adding state checker for gamma lut values (rev14)
URL   : https://patchwork.freedesktop.org/series/58039/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6829_full -> Patchwork_14271_full
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_14271_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_14271_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14271_full:

### IGT changes ###

#### Warnings ####

  * igt@kms_chamelium@hdmi-audio:
    - shard-kbl:          [SKIP][1] ([fdo#109271]) -> [TIMEOUT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-kbl3/igt@kms_chamelium@hdmi-audio.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-kbl6/igt@kms_chamelium@hdmi-audio.html

  
Known issues
------------

  Here are the changes found in Patchwork_14271_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_switch@queue-light:
    - shard-apl:          [PASS][3] -> [INCOMPLETE][4] ([fdo#103927]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-apl5/igt@gem_ctx_switch@queue-light.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-apl7/igt@gem_ctx_switch@queue-light.html

  * igt@gem_exec_schedule@preemptive-hang-bsd:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#111325]) +7 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-iclb3/igt@gem_exec_schedule@preemptive-hang-bsd.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-iclb4/igt@gem_exec_schedule@preemptive-hang-bsd.html

  * igt@gem_exec_schedule@promotion-bsd1:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#109276]) +12 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-iclb2/igt@gem_exec_schedule@promotion-bsd1.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-iclb3/igt@gem_exec_schedule@promotion-bsd1.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-skl:          [PASS][9] -> [INCOMPLETE][10] ([fdo#104108]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-skl4/igt@gem_workarounds@suspend-resume-fd.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-skl9/igt@gem_workarounds@suspend-resume-fd.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
    - shard-kbl:          [PASS][11] -> [SKIP][12] ([fdo#109271])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-kbl4/igt@i915_pm_rc6_residency@rc6-accuracy.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-kbl7/igt@i915_pm_rc6_residency@rc6-accuracy.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x128-random:
    - shard-skl:          [PASS][13] -> [FAIL][14] ([fdo#103232])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-skl8/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-skl1/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-hsw:          [PASS][15] -> [INCOMPLETE][16] ([fdo#103540])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-hsw6/igt@kms_flip@2x-flip-vs-suspend.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-hsw2/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
    - shard-iclb:         [PASS][17] -> [FAIL][18] ([fdo#103167])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-apl:          [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +4 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-apl5/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-apl1/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen:
    - shard-skl:          [PASS][21] -> [FAIL][22] ([fdo#108040]) +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-skl8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-skl1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#108145])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][25] -> [SKIP][26] ([fdo#109441]) +3 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-iclb7/igt@kms_psr@psr2_cursor_render.html

  * igt@perf_pmu@cpu-hotplug:
    - shard-kbl:          [PASS][27] -> [TIMEOUT][28] ([fdo#111546])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-kbl3/igt@perf_pmu@cpu-hotplug.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-kbl6/igt@perf_pmu@cpu-hotplug.html

  * igt@prime_self_import@basic-with_two_bos:
    - shard-kbl:          [PASS][29] -> [INCOMPLETE][30] ([fdo#103665])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-kbl3/igt@prime_self_import@basic-with_two_bos.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-kbl6/igt@prime_self_import@basic-with_two_bos.html

  
#### Possible fixes ####

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [SKIP][31] ([fdo#110841]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-iclb3/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_eio@reset-stress:
    - shard-kbl:          [FAIL][33] ([fdo#109661]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-kbl6/igt@gem_eio@reset-stress.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-kbl6/igt@gem_eio@reset-stress.html
    - shard-iclb:         [FAIL][35] ([fdo#109661]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-iclb7/igt@gem_eio@reset-stress.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-iclb5/igt@gem_eio@reset-stress.html

  * igt@gem_exec_schedule@reorder-wide-bsd:
    - shard-iclb:         [SKIP][37] ([fdo#111325]) -> [PASS][38] +5 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-iclb5/igt@gem_exec_schedule@reorder-wide-bsd.html

  * igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen:
    - shard-iclb:         [INCOMPLETE][39] ([fdo#107713]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-iclb7/igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-iclb3/igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          [FAIL][41] ([fdo#102670]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt:
    - shard-iclb:         [FAIL][43] ([fdo#103167]) -> [PASS][44] +2 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-iclb:         [INCOMPLETE][45] ([fdo#106978] / [fdo#107713]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-iclb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-iclb8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_psr@psr2_cursor_mmap_gtt:
    - shard-iclb:         [SKIP][47] ([fdo#109441]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_gtt.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html

  * igt@kms_vblank@pipe-c-query-forked-busy-hang:
    - shard-hsw:          [INCOMPLETE][49] ([fdo#103540]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-hsw5/igt@kms_vblank@pipe-c-query-forked-busy-hang.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-hsw1/igt@kms_vblank@pipe-c-query-forked-busy-hang.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [SKIP][51] ([fdo#109276]) -> [PASS][52] +18 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-iclb6/igt@prime_busy@hang-bsd2.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-iclb1/igt@prime_busy@hang-bsd2.html

  * igt@tools_test@tools_test:
    - shard-skl:          [SKIP][53] ([fdo#109271]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-skl9/igt@tools_test@tools_test.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-skl4/igt@tools_test@tools_test.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [SKIP][55] ([fdo#109276]) -> [FAIL][56] ([fdo#111329])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@gem_mocs_settings@mocs-rc6-bsd2:
    - shard-iclb:         [SKIP][57] ([fdo#109276]) -> [FAIL][58] ([fdo#111330])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-iclb8/igt@gem_mocs_settings@mocs-rc6-bsd2.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-iclb2/igt@gem_mocs_settings@mocs-rc6-bsd2.html

  * igt@gem_mocs_settings@mocs-settings-bsd2:
    - shard-iclb:         [FAIL][59] ([fdo#111330]) -> [SKIP][60] ([fdo#109276]) +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-iclb1/igt@gem_mocs_settings@mocs-settings-bsd2.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-iclb3/igt@gem_mocs_settings@mocs-settings-bsd2.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt:
    - shard-skl:          [FAIL][61] ([fdo#108040]) -> [FAIL][62] ([fdo#103167])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-skl4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-skl2/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt.html

  * igt@perf_pmu@cpu-hotplug:
    - shard-apl:          [INCOMPLETE][63] ([fdo#103927]) -> [TIMEOUT][64] ([fdo#111546])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6829/shard-apl3/igt@perf_pmu@cpu-hotplug.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/shard-apl4/igt@perf_pmu@cpu-hotplug.html

  
  [fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
  [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
  [fdo#111546]: https://bugs.freedesktop.org/show_bug.cgi?id=111546


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6829 -> Patchwork_14271

  CI-20190529: 20190529
  CI_DRM_6829: f079fd4ac5dcc7e76550a7068f655d3e665088d1 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5167: 81f7a49bc80e6d9f27e33859fd94fd11e13cafa0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14271: b2aefcd3a19b12de0e844f800841a7acc7946d3c @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14271/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v10][PATCH 0/8] drm/i915: adding state checker for gamma lut values

[Jani Nikula]

On Wed, 04 Sep 2019, Swati Sharma <swati2.sharma@intel.com> wrote:
> In this patch series, added state checker to validate gamma
> (8BIT and 10BIT).This reads hardware state, and compares the originally
> requested state(s/w) to the state read from the hardware.
> This is done for legacy, ilk, glk and their variant platforms. Rest of
> the platforms will be enabled on top of this later.
>
> Intentionally, excluded bdw and ivb since they have spilt gamma mode;
> for which degamma read outs are required (which I think shouldn't be
> included in this patch series). Will include after degamma state checker
> is completed.

Pushed the series, thanks for the patches and review!

Please proceed with the next steps! It should be easier now that you can
focus on enabling the checks for one feature or platform, and if needed,
one patch, at a time. :)

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v10][PATCH 0/8] drm/i915: adding state checker for gamma lut values

[Sharma, Swati2]

Yay! Thanks Jani. 

Thanks and Regards,
Swati

-----Original Message-----
From: Jani Nikula <jani.nikula@intel.com> 
Sent: Wednesday, September 4, 2019 3:01 PM
To: Sharma, Swati2 <swati2.sharma@intel.com>; intel-gfx@lists.freedesktop.org
Cc: Roper, Matthew D <matthew.d.roper@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; Sharma, Shashank <shashank.sharma@intel.com>; Manna, Animesh <animesh.manna@intel.com>; Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; daniel.vetter@ffwll.ch; ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>; Sharma, Swati2 <swati2.sharma@intel.com>
Subject: Re: [v10][PATCH 0/8] drm/i915: adding state checker for gamma lut values

On Wed, 04 Sep 2019, Swati Sharma <swati2.sharma@intel.com> wrote:
> In this patch series, added state checker to validate gamma (8BIT and 
> 10BIT).This reads hardware state, and compares the originally 
> requested state(s/w) to the state read from the hardware.
> This is done for legacy, ilk, glk and their variant platforms. Rest of 
> the platforms will be enabled on top of this later.
>
> Intentionally, excluded bdw and ivb since they have spilt gamma mode; 
> for which degamma read outs are required (which I think shouldn't be 
> included in this patch series). Will include after degamma state 
> checker is completed.

Pushed the series, thanks for the patches and review!

Please proceed with the next steps! It should be easier now that you can focus on enabling the checks for one feature or platform, and if needed, one patch, at a time. :)

BR,
Jani.


--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx