* [Intel-gfx] [PATCH 01/17] drm/i915/dp: Factor out helpers to compute the link limits
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
@ 2023-08-17 16:14 ` Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 02/17] drm/i915/dp: Track the pipe and link bpp limits separately Imre Deak
` (19 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx
Factor out helpers that DP / DP_MST encoders can use to compute the link
rate/lane count and bpp limits. A follow-up patch will call these to
recalculate the limits if DSC compression is required.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 61 +++++++++++++--------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 52 ++++++++++--------
2 files changed, 68 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 964bf0551bdc9..89de444cfc4da 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1796,29 +1796,25 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return 0;
}
-static int
-intel_dp_compute_link_config(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config,
- struct drm_connector_state *conn_state,
- bool respect_downstream_limits)
+static void
+intel_dp_compute_config_limits(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ bool respect_downstream_limits,
+ struct link_config_limits *limits)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
const struct drm_display_mode *adjusted_mode =
- &pipe_config->hw.adjusted_mode;
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- struct link_config_limits limits;
- bool joiner_needs_dsc = false;
- int ret;
+ &crtc_state->hw.adjusted_mode;
- limits.min_rate = intel_dp_common_rate(intel_dp, 0);
- limits.max_rate = intel_dp_max_link_rate(intel_dp);
+ limits->min_rate = intel_dp_common_rate(intel_dp, 0);
+ limits->max_rate = intel_dp_max_link_rate(intel_dp);
- limits.min_lane_count = 1;
- limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
+ limits->min_lane_count = 1;
+ limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
- limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
- limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config, respect_downstream_limits);
+ limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
+ limits->max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
+ respect_downstream_limits);
if (intel_dp->use_max_params) {
/*
@@ -1829,16 +1825,35 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
* configuration, and typically on older panels these
* values correspond to the native resolution of the panel.
*/
- limits.min_lane_count = limits.max_lane_count;
- limits.min_rate = limits.max_rate;
+ limits->min_lane_count = limits->max_lane_count;
+ limits->min_rate = limits->max_rate;
}
- intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
+ intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
"max rate %d max bpp %d pixel clock %iKHz\n",
- limits.max_lane_count, limits.max_rate,
- limits.max_bpp, adjusted_mode->crtc_clock);
+ limits->max_lane_count, limits->max_rate,
+ limits->max_bpp, adjusted_mode->crtc_clock);
+}
+
+static int
+intel_dp_compute_link_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state,
+ bool respect_downstream_limits)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ const struct drm_display_mode *adjusted_mode =
+ &pipe_config->hw.adjusted_mode;
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct link_config_limits limits;
+ bool joiner_needs_dsc = false;
+ int ret;
+
+ intel_dp_compute_config_limits(intel_dp, pipe_config,
+ respect_downstream_limits, &limits);
if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
adjusted_mode->crtc_clock))
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index e3f176a093d2f..998d8a186cc6f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -303,6 +303,35 @@ static bool intel_dp_mst_has_audio(const struct drm_connector_state *conn_state)
return intel_conn_state->force_audio == HDMI_AUDIO_ON;
}
+static void
+intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ struct link_config_limits *limits)
+{
+ /*
+ * for MST we always configure max link bw - the spec doesn't
+ * seem to suggest we should do otherwise.
+ */
+ limits->min_rate = limits->max_rate =
+ intel_dp_max_link_rate(intel_dp);
+
+ limits->min_lane_count = limits->max_lane_count =
+ intel_dp_max_lane_count(intel_dp);
+
+ limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
+ /*
+ * FIXME: If all the streams can't fit into the link with
+ * their current pipe_bpp we should reduce pipe_bpp across
+ * the board until things start to fit. Until then we
+ * limit to <= 8bpc since that's what was hardcoded for all
+ * MST streams previously. This hack should be removed once
+ * we have the proper retry logic in place.
+ */
+ limits->max_bpp = min(crtc_state->pipe_bpp, 24);
+
+ intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
+}
+
static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
@@ -326,28 +355,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
intel_dp_mst_has_audio(conn_state) &&
intel_audio_compute_config(encoder, pipe_config, conn_state);
- /*
- * for MST we always configure max link bw - the spec doesn't
- * seem to suggest we should do otherwise.
- */
- limits.min_rate =
- limits.max_rate = intel_dp_max_link_rate(intel_dp);
-
- limits.min_lane_count =
- limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
-
- limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
- /*
- * FIXME: If all the streams can't fit into the link with
- * their current pipe_bpp we should reduce pipe_bpp across
- * the board until things start to fit. Until then we
- * limit to <= 8bpc since that's what was hardcoded for all
- * MST streams previously. This hack should be removed once
- * we have the proper retry logic in place.
- */
- limits.max_bpp = min(pipe_config->pipe_bpp, 24);
-
- intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
+ intel_dp_mst_compute_config_limits(intel_dp, pipe_config, &limits);
ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
conn_state, &limits);
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread* [Intel-gfx] [PATCH 02/17] drm/i915/dp: Track the pipe and link bpp limits separately
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 01/17] drm/i915/dp: Factor out helpers to compute the link limits Imre Deak
@ 2023-08-17 16:14 ` Imre Deak
2023-08-17 16:27 ` Jani Nikula
2023-08-17 16:14 ` [Intel-gfx] [PATCH 03/17] drm/i915/dp: Skip computing a non-DSC link config if DSC is needed Imre Deak
` (18 subsequent siblings)
20 siblings, 1 reply; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx
A follow-up patch will need to limit the output link bpp both in the
non-DSC and DSC configuration, so track the pipe and link bpp limits
separately in the link_config_limits struct.
Use .4 fixed point format for link bpp matching the 1/16 bpp granularity
in DSC mode and for now keep this limit matching the pipe bpp limit.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 17 +++++++++++------
drivers/gpu/drm/i915/display/intel_dp.h | 9 ++++++++-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +++++++++++------
3 files changed, 30 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 89de444cfc4da..f4952fcfb16e9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1419,7 +1419,7 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
if (intel_dp->compliance.test_data.bpc != 0) {
int bpp = 3 * intel_dp->compliance.test_data.bpc;
- limits->min_bpp = limits->max_bpp = bpp;
+ limits->pipe.min_bpp = limits->pipe.max_bpp = bpp;
pipe_config->dither_force_disable = bpp == 6 * 3;
drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
@@ -1481,7 +1481,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
int mode_rate, link_rate, link_avail;
- for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
+ for (bpp = limits->link.max_bpp >> 4;
+ bpp >= limits->link.min_bpp >> 4;
+ bpp -= 2 * 3) {
int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
mode_rate = intel_dp_link_required(clock, output_bpp);
@@ -1812,9 +1814,9 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
limits->min_lane_count = 1;
limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
- limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
- limits->max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
- respect_downstream_limits);
+ limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
+ limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
+ respect_downstream_limits);
if (intel_dp->use_max_params) {
/*
@@ -1831,10 +1833,13 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
+ limits->link.min_bpp = limits->pipe.min_bpp << 4;
+ limits->link.max_bpp = limits->pipe.max_bpp << 4;
+
drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
"max rate %d max bpp %d pixel clock %iKHz\n",
limits->max_lane_count, limits->max_rate,
- limits->max_bpp, adjusted_mode->crtc_clock);
+ limits->link.max_bpp >> 4, adjusted_mode->crtc_clock);
}
static int
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 22099de3ca458..a1789419c0d19 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -26,7 +26,14 @@ struct intel_encoder;
struct link_config_limits {
int min_rate, max_rate;
int min_lane_count, max_lane_count;
- int min_bpp, max_bpp;
+ struct {
+ /* Uncompressed DSC input or link output bpp in 1 bpp units */
+ int min_bpp, max_bpp;
+ } pipe;
+ struct {
+ /* Compressed or uncompressed link output bpp in 1/16 bpp units */
+ int min_bpp, max_bpp;
+ } link;
};
void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 998d8a186cc6f..1809643538d08 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -156,8 +156,10 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
&crtc_state->hw.adjusted_mode;
int slots = -EINVAL;
- slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, limits->max_bpp,
- limits->min_bpp, limits,
+ slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
+ limits->link.max_bpp >> 4,
+ limits->link.min_bpp >> 4,
+ limits,
conn_state, 2 * 3, false);
if (slots < 0)
@@ -200,8 +202,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
else
dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc);
- max_bpp = min_t(u8, dsc_max_bpc * 3, limits->max_bpp);
- min_bpp = limits->min_bpp;
+ max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp);
+ min_bpp = limits->pipe.min_bpp;
num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
dsc_bpc);
@@ -318,7 +320,7 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
limits->min_lane_count = limits->max_lane_count =
intel_dp_max_lane_count(intel_dp);
- limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
+ limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
/*
* FIXME: If all the streams can't fit into the link with
* their current pipe_bpp we should reduce pipe_bpp across
@@ -327,9 +329,12 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
* MST streams previously. This hack should be removed once
* we have the proper retry logic in place.
*/
- limits->max_bpp = min(crtc_state->pipe_bpp, 24);
+ limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);
intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
+
+ limits->link.min_bpp = limits->pipe.min_bpp << 4;
+ limits->link.max_bpp = limits->pipe.max_bpp << 4;
}
static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Intel-gfx] [PATCH 02/17] drm/i915/dp: Track the pipe and link bpp limits separately
2023-08-17 16:14 ` [Intel-gfx] [PATCH 02/17] drm/i915/dp: Track the pipe and link bpp limits separately Imre Deak
@ 2023-08-17 16:27 ` Jani Nikula
2023-08-18 8:24 ` Kandpal, Suraj
2023-08-18 13:26 ` Imre Deak
0 siblings, 2 replies; 31+ messages in thread
From: Jani Nikula @ 2023-08-17 16:27 UTC (permalink / raw)
To: Imre Deak, intel-gfx
On Thu, 17 Aug 2023, Imre Deak <imre.deak@intel.com> wrote:
> A follow-up patch will need to limit the output link bpp both in the
> non-DSC and DSC configuration, so track the pipe and link bpp limits
> separately in the link_config_limits struct.
>
> Use .4 fixed point format for link bpp matching the 1/16 bpp granularity
> in DSC mode and for now keep this limit matching the pipe bpp limit.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 17 +++++++++++------
> drivers/gpu/drm/i915/display/intel_dp.h | 9 ++++++++-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +++++++++++------
> 3 files changed, 30 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 89de444cfc4da..f4952fcfb16e9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1419,7 +1419,7 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
> if (intel_dp->compliance.test_data.bpc != 0) {
> int bpp = 3 * intel_dp->compliance.test_data.bpc;
>
> - limits->min_bpp = limits->max_bpp = bpp;
> + limits->pipe.min_bpp = limits->pipe.max_bpp = bpp;
> pipe_config->dither_force_disable = bpp == 6 * 3;
>
> drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
> @@ -1481,7 +1481,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
> int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
> int mode_rate, link_rate, link_avail;
>
> - for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
> + for (bpp = limits->link.max_bpp >> 4;
> + bpp >= limits->link.min_bpp >> 4;
I think I'd like to see some helpers for the >> 4 and << 4, to make this
self-documenting code.
to_bpp_int(), to_bpp_x16(), or something along those lines maybe.
With proper variable/member naming, you'd get:
bpp = to_bpp_int(bpp_x16);
bpp_x16 = to_bpp_x16(bpp);
And it would be obvious what's going on.
> + bpp -= 2 * 3) {
> int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
>
> mode_rate = intel_dp_link_required(clock, output_bpp);
> @@ -1812,9 +1814,9 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
> limits->min_lane_count = 1;
> limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
>
> - limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
> - limits->max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
> - respect_downstream_limits);
> + limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
> + limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
> + respect_downstream_limits);
>
> if (intel_dp->use_max_params) {
> /*
> @@ -1831,10 +1833,13 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
>
> intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
>
> + limits->link.min_bpp = limits->pipe.min_bpp << 4;
> + limits->link.max_bpp = limits->pipe.max_bpp << 4;
> +
> drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
> "max rate %d max bpp %d pixel clock %iKHz\n",
> limits->max_lane_count, limits->max_rate,
> - limits->max_bpp, adjusted_mode->crtc_clock);
> + limits->link.max_bpp >> 4, adjusted_mode->crtc_clock);
> }
>
> static int
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 22099de3ca458..a1789419c0d19 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -26,7 +26,14 @@ struct intel_encoder;
> struct link_config_limits {
> int min_rate, max_rate;
> int min_lane_count, max_lane_count;
> - int min_bpp, max_bpp;
> + struct {
> + /* Uncompressed DSC input or link output bpp in 1 bpp units */
> + int min_bpp, max_bpp;
> + } pipe;
> + struct {
> + /* Compressed or uncompressed link output bpp in 1/16 bpp units */
> + int min_bpp, max_bpp;
The 1/16 bpp units is a source of confusion, and I think we should start
denoting them in naming.
min_bpp_x16, max_bpp_x16
> + } link;
> };
>
> void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 998d8a186cc6f..1809643538d08 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -156,8 +156,10 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
> &crtc_state->hw.adjusted_mode;
> int slots = -EINVAL;
>
> - slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, limits->max_bpp,
> - limits->min_bpp, limits,
> + slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
> + limits->link.max_bpp >> 4,
> + limits->link.min_bpp >> 4,
> + limits,
> conn_state, 2 * 3, false);
>
> if (slots < 0)
> @@ -200,8 +202,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> else
> dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc);
>
> - max_bpp = min_t(u8, dsc_max_bpc * 3, limits->max_bpp);
> - min_bpp = limits->min_bpp;
> + max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp);
> + min_bpp = limits->pipe.min_bpp;
>
> num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
> dsc_bpc);
> @@ -318,7 +320,7 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
> limits->min_lane_count = limits->max_lane_count =
> intel_dp_max_lane_count(intel_dp);
>
> - limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
> + limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
> /*
> * FIXME: If all the streams can't fit into the link with
> * their current pipe_bpp we should reduce pipe_bpp across
> @@ -327,9 +329,12 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
> * MST streams previously. This hack should be removed once
> * we have the proper retry logic in place.
> */
> - limits->max_bpp = min(crtc_state->pipe_bpp, 24);
> + limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);
>
> intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
> +
> + limits->link.min_bpp = limits->pipe.min_bpp << 4;
> + limits->link.max_bpp = limits->pipe.max_bpp << 4;
> }
>
> static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [Intel-gfx] [PATCH 02/17] drm/i915/dp: Track the pipe and link bpp limits separately
2023-08-17 16:27 ` Jani Nikula
@ 2023-08-18 8:24 ` Kandpal, Suraj
2023-08-18 14:06 ` Imre Deak
2023-08-18 13:26 ` Imre Deak
1 sibling, 1 reply; 31+ messages in thread
From: Kandpal, Suraj @ 2023-08-18 8:24 UTC (permalink / raw)
To: Jani Nikula, Deak, Imre, intel-gfx@lists.freedesktop.org
>
> On Thu, 17 Aug 2023, Imre Deak <imre.deak@intel.com> wrote:
> > A follow-up patch will need to limit the output link bpp both in the
> > non-DSC and DSC configuration, so track the pipe and link bpp limits
> > separately in the link_config_limits struct.
> >
> > Use .4 fixed point format for link bpp matching the 1/16 bpp
> > granularity in DSC mode and for now keep this limit matching the pipe bpp
> limit.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 17 +++++++++++------
> > drivers/gpu/drm/i915/display/intel_dp.h | 9 ++++++++-
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +++++++++++------
> > 3 files changed, 30 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 89de444cfc4da..f4952fcfb16e9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1419,7 +1419,7 @@ intel_dp_adjust_compliance_config(struct
> intel_dp *intel_dp,
> > if (intel_dp->compliance.test_data.bpc != 0) {
> > int bpp = 3 * intel_dp->compliance.test_data.bpc;
> >
> > - limits->min_bpp = limits->max_bpp = bpp;
> > + limits->pipe.min_bpp = limits->pipe.max_bpp = bpp;
> > pipe_config->dither_force_disable = bpp == 6 * 3;
> >
> > drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n",
> bpp); @@
> > -1481,7 +1481,9 @@ intel_dp_compute_link_config_wide(struct intel_dp
> *intel_dp,
> > int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config,
> conn_state);
> > int mode_rate, link_rate, link_avail;
> >
> > - for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
> > + for (bpp = limits->link.max_bpp >> 4;
> > + bpp >= limits->link.min_bpp >> 4;
>
> I think I'd like to see some helpers for the >> 4 and << 4, to make this self-
> documenting code.
>
> to_bpp_int(), to_bpp_x16(), or something along those lines maybe.
>
> With proper variable/member naming, you'd get:
>
> bpp = to_bpp_int(bpp_x16);
> bpp_x16 = to_bpp_x16(bpp);
>
> And it would be obvious what's going on.
>
> > + bpp -= 2 * 3) {
> > int output_bpp = intel_dp_output_bpp(pipe_config-
> >output_format,
> > bpp);
> >
> > mode_rate = intel_dp_link_required(clock, output_bpp); @@
> -1812,9
> > +1814,9 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
> > limits->min_lane_count = 1;
> > limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
> >
> > - limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
> > - limits->max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
> > - respect_downstream_limits);
> > + limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state-
> >output_format);
> > + limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
> > +
> respect_downstream_limits);
> >
> > if (intel_dp->use_max_params) {
> > /*
> > @@ -1831,10 +1833,13 @@ intel_dp_compute_config_limits(struct
> intel_dp
> > *intel_dp,
> >
> > intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
> >
> > + limits->link.min_bpp = limits->pipe.min_bpp << 4;
> > + limits->link.max_bpp = limits->pipe.max_bpp << 4;
> > +
> > drm_dbg_kms(&i915->drm, "DP link computation with max lane
> count %i "
> > "max rate %d max bpp %d pixel clock %iKHz\n",
> > limits->max_lane_count, limits->max_rate,
> > - limits->max_bpp, adjusted_mode->crtc_clock);
> > + limits->link.max_bpp >> 4, adjusted_mode->crtc_clock);
> > }
> >
> > static int
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> > b/drivers/gpu/drm/i915/display/intel_dp.h
> > index 22099de3ca458..a1789419c0d19 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -26,7 +26,14 @@ struct intel_encoder; struct link_config_limits {
> > int min_rate, max_rate;
> > int min_lane_count, max_lane_count;
> > - int min_bpp, max_bpp;
> > + struct {
> > + /* Uncompressed DSC input or link output bpp in 1 bpp units
> */
> > + int min_bpp, max_bpp;
> > + } pipe;
> > + struct {
> > + /* Compressed or uncompressed link output bpp in 1/16 bpp
> units */
> > + int min_bpp, max_bpp;
>
> The 1/16 bpp units is a source of confusion, and I think we should start
> denoting them in naming.
>
> min_bpp_x16, max_bpp_x16
>
> > + } link;
> > };
Also a small question here do we need to track both pipe and link bpp separately
When we can have the helper mentioned above maybe we can call it
pipe_to_link_bpp
Also if it is really required to track link bpp for dsc and non dsc scenario won't it be
Better to have link_dsc and link_non_dsc structs rather than pipe and link since both
are bpp for link with dsc enablement differentiation.
Regards,
Suraj Kandpal
> >
> > void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int
> > pipe_bpp); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 998d8a186cc6f..1809643538d08 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -156,8 +156,10 @@ static int
> intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
> > &crtc_state->hw.adjusted_mode;
> > int slots = -EINVAL;
> >
> > - slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
> limits->max_bpp,
> > - limits->min_bpp, limits,
> > + slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
> > + limits->link.max_bpp >> 4,
> > + limits->link.min_bpp >> 4,
> > + limits,
> > conn_state, 2 * 3, false);
> >
> > if (slots < 0)
> > @@ -200,8 +202,8 @@ static int
> intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> > else
> > dsc_max_bpc = min_t(u8, 10, conn_state-
> >max_requested_bpc);
> >
> > - max_bpp = min_t(u8, dsc_max_bpc * 3, limits->max_bpp);
> > - min_bpp = limits->min_bpp;
> > + max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp);
> > + min_bpp = limits->pipe.min_bpp;
> >
> > num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp-
> >dsc_dpcd,
> > dsc_bpc);
> > @@ -318,7 +320,7 @@ intel_dp_mst_compute_config_limits(struct
> intel_dp *intel_dp,
> > limits->min_lane_count = limits->max_lane_count =
> > intel_dp_max_lane_count(intel_dp);
> >
> > - limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
> > + limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state-
> >output_format);
> > /*
> > * FIXME: If all the streams can't fit into the link with
> > * their current pipe_bpp we should reduce pipe_bpp across @@ -
> 327,9
> > +329,12 @@ intel_dp_mst_compute_config_limits(struct intel_dp
> *intel_dp,
> > * MST streams previously. This hack should be removed once
> > * we have the proper retry logic in place.
> > */
> > - limits->max_bpp = min(crtc_state->pipe_bpp, 24);
> > + limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);
> >
> > intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
> > +
> > + limits->link.min_bpp = limits->pipe.min_bpp << 4;
> > + limits->link.max_bpp = limits->pipe.max_bpp << 4;
> > }
> >
> > static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [Intel-gfx] [PATCH 02/17] drm/i915/dp: Track the pipe and link bpp limits separately
2023-08-18 8:24 ` Kandpal, Suraj
@ 2023-08-18 14:06 ` Imre Deak
0 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-18 14:06 UTC (permalink / raw)
To: Kandpal, Suraj; +Cc: intel-gfx@lists.freedesktop.org
On Fri, Aug 18, 2023 at 11:24:26AM +0300, Kandpal, Suraj wrote:
> [...]
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> > > b/drivers/gpu/drm/i915/display/intel_dp.h
> > > index 22099de3ca458..a1789419c0d19 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > > @@ -26,7 +26,14 @@ struct intel_encoder; struct link_config_limits {
> > > int min_rate, max_rate;
> > > int min_lane_count, max_lane_count;
> > > - int min_bpp, max_bpp;
> > > + struct {
> > > + /* Uncompressed DSC input or link output bpp in 1 bpp units */
> > > + int min_bpp, max_bpp;
> > > + } pipe;
> > > + struct {
> > > + /* Compressed or uncompressed link output bpp in 1/16 bpp units */
> > > + int min_bpp, max_bpp;
> >
> > The 1/16 bpp units is a source of confusion, and I think we should start
> > denoting them in naming.
> >
> > min_bpp_x16, max_bpp_x16
> >
> > > + } link;
> > > };
>
> Also a small question here do we need to track both pipe and link bpp
> separately When we can have the helper mentioned above maybe we can
> call it pipe_to_link_bpp
>
> Also if it is really required to track link bpp for dsc and non dsc
> scenario won't it be Better to have link_dsc and link_non_dsc structs
> rather than pipe and link since both are bpp for link with dsc
> enablement differentiation.
They are separate things, which can be set independently within their
own valid range. pipe bpp is about the format pixels are handled by the
display engine (pipe) internally, while link bpp is about the format of
pixels on the link.
For instance for DSC a given link bpp (which is limited by the BW on the
link) could be used with different pipe bpp settings (limited by other
platform specific constraints).
>
> Regards,
> Suraj Kandpal
>
>
> > >
> > > void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int
> > > pipe_bpp); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > index 998d8a186cc6f..1809643538d08 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > @@ -156,8 +156,10 @@ static int
> > intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
> > > &crtc_state->hw.adjusted_mode;
> > > int slots = -EINVAL;
> > >
> > > - slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
> > limits->max_bpp,
> > > - limits->min_bpp, limits,
> > > + slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
> > > + limits->link.max_bpp >> 4,
> > > + limits->link.min_bpp >> 4,
> > > + limits,
> > > conn_state, 2 * 3, false);
> > >
> > > if (slots < 0)
> > > @@ -200,8 +202,8 @@ static int
> > intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> > > else
> > > dsc_max_bpc = min_t(u8, 10, conn_state-
> > >max_requested_bpc);
> > >
> > > - max_bpp = min_t(u8, dsc_max_bpc * 3, limits->max_bpp);
> > > - min_bpp = limits->min_bpp;
> > > + max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp);
> > > + min_bpp = limits->pipe.min_bpp;
> > >
> > > num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp-
> > >dsc_dpcd,
> > > dsc_bpc);
> > > @@ -318,7 +320,7 @@ intel_dp_mst_compute_config_limits(struct
> > intel_dp *intel_dp,
> > > limits->min_lane_count = limits->max_lane_count =
> > > intel_dp_max_lane_count(intel_dp);
> > >
> > > - limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
> > > + limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state-
> > >output_format);
> > > /*
> > > * FIXME: If all the streams can't fit into the link with
> > > * their current pipe_bpp we should reduce pipe_bpp across @@ -
> > 327,9
> > > +329,12 @@ intel_dp_mst_compute_config_limits(struct intel_dp
> > *intel_dp,
> > > * MST streams previously. This hack should be removed once
> > > * we have the proper retry logic in place.
> > > */
> > > - limits->max_bpp = min(crtc_state->pipe_bpp, 24);
> > > + limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);
> > >
> > > intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
> > > +
> > > + limits->link.min_bpp = limits->pipe.min_bpp << 4;
> > > + limits->link.max_bpp = limits->pipe.max_bpp << 4;
> > > }
> > >
> > > static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH 02/17] drm/i915/dp: Track the pipe and link bpp limits separately
2023-08-17 16:27 ` Jani Nikula
2023-08-18 8:24 ` Kandpal, Suraj
@ 2023-08-18 13:26 ` Imre Deak
1 sibling, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-18 13:26 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Aug 17, 2023 at 07:27:24PM +0300, Jani Nikula wrote:
> On Thu, 17 Aug 2023, Imre Deak <imre.deak@intel.com> wrote:
> > A follow-up patch will need to limit the output link bpp both in the
> > non-DSC and DSC configuration, so track the pipe and link bpp limits
> > separately in the link_config_limits struct.
> >
> > Use .4 fixed point format for link bpp matching the 1/16 bpp granularity
> > in DSC mode and for now keep this limit matching the pipe bpp limit.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 17 +++++++++++------
> > drivers/gpu/drm/i915/display/intel_dp.h | 9 ++++++++-
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +++++++++++------
> > 3 files changed, 30 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 89de444cfc4da..f4952fcfb16e9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1419,7 +1419,7 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
> > if (intel_dp->compliance.test_data.bpc != 0) {
> > int bpp = 3 * intel_dp->compliance.test_data.bpc;
> >
> > - limits->min_bpp = limits->max_bpp = bpp;
> > + limits->pipe.min_bpp = limits->pipe.max_bpp = bpp;
> > pipe_config->dither_force_disable = bpp == 6 * 3;
> >
> > drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
> > @@ -1481,7 +1481,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
> > int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
> > int mode_rate, link_rate, link_avail;
> >
> > - for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
> > + for (bpp = limits->link.max_bpp >> 4;
> > + bpp >= limits->link.min_bpp >> 4;
>
> I think I'd like to see some helpers for the >> 4 and << 4, to make this
> self-documenting code.
I wondered about more generic fixed point helpers, but didn't find any.
> to_bpp_int(), to_bpp_x16(), or something along those lines maybe.
>
> With proper variable/member naming, you'd get:
>
> bpp = to_bpp_int(bpp_x16);
> bpp_x16 = to_bpp_x16(bpp);
>
> And it would be obvious what's going on.
Yes, makes sense, will add these.
>
> > + bpp -= 2 * 3) {
> > int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
> >
> > mode_rate = intel_dp_link_required(clock, output_bpp);
> > @@ -1812,9 +1814,9 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
> > limits->min_lane_count = 1;
> > limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
> >
> > - limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
> > - limits->max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
> > - respect_downstream_limits);
> > + limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
> > + limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
> > + respect_downstream_limits);
> >
> > if (intel_dp->use_max_params) {
> > /*
> > @@ -1831,10 +1833,13 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
> >
> > intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
> >
> > + limits->link.min_bpp = limits->pipe.min_bpp << 4;
> > + limits->link.max_bpp = limits->pipe.max_bpp << 4;
> > +
> > drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
> > "max rate %d max bpp %d pixel clock %iKHz\n",
> > limits->max_lane_count, limits->max_rate,
> > - limits->max_bpp, adjusted_mode->crtc_clock);
> > + limits->link.max_bpp >> 4, adjusted_mode->crtc_clock);
> > }
> >
> > static int
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> > index 22099de3ca458..a1789419c0d19 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -26,7 +26,14 @@ struct intel_encoder;
> > struct link_config_limits {
> > int min_rate, max_rate;
> > int min_lane_count, max_lane_count;
> > - int min_bpp, max_bpp;
> > + struct {
> > + /* Uncompressed DSC input or link output bpp in 1 bpp units */
> > + int min_bpp, max_bpp;
> > + } pipe;
> > + struct {
> > + /* Compressed or uncompressed link output bpp in 1/16 bpp units */
> > + int min_bpp, max_bpp;
>
> The 1/16 bpp units is a source of confusion, and I think we should start
> denoting them in naming.
>
> min_bpp_x16, max_bpp_x16
Ok, will change these.
>
> > + } link;
> > };
> >
> > void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 998d8a186cc6f..1809643538d08 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -156,8 +156,10 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
> > &crtc_state->hw.adjusted_mode;
> > int slots = -EINVAL;
> >
> > - slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, limits->max_bpp,
> > - limits->min_bpp, limits,
> > + slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
> > + limits->link.max_bpp >> 4,
> > + limits->link.min_bpp >> 4,
> > + limits,
> > conn_state, 2 * 3, false);
> >
> > if (slots < 0)
> > @@ -200,8 +202,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> > else
> > dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc);
> >
> > - max_bpp = min_t(u8, dsc_max_bpc * 3, limits->max_bpp);
> > - min_bpp = limits->min_bpp;
> > + max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp);
> > + min_bpp = limits->pipe.min_bpp;
> >
> > num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
> > dsc_bpc);
> > @@ -318,7 +320,7 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
> > limits->min_lane_count = limits->max_lane_count =
> > intel_dp_max_lane_count(intel_dp);
> >
> > - limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
> > + limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
> > /*
> > * FIXME: If all the streams can't fit into the link with
> > * their current pipe_bpp we should reduce pipe_bpp across
> > @@ -327,9 +329,12 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
> > * MST streams previously. This hack should be removed once
> > * we have the proper retry logic in place.
> > */
> > - limits->max_bpp = min(crtc_state->pipe_bpp, 24);
> > + limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);
> >
> > intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
> > +
> > + limits->link.min_bpp = limits->pipe.min_bpp << 4;
> > + limits->link.max_bpp = limits->pipe.max_bpp << 4;
> > }
> >
> > static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-gfx] [PATCH 03/17] drm/i915/dp: Skip computing a non-DSC link config if DSC is needed
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 01/17] drm/i915/dp: Factor out helpers to compute the link limits Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 02/17] drm/i915/dp: Track the pipe and link bpp limits separately Imre Deak
@ 2023-08-17 16:14 ` Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 04/17] drm/i915/dp: Update the link bpp limits for DSC mode Imre Deak
` (17 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx
Computing the non-DSC mode link config is redundant once it's determined
that DSC will be needed, so skip computing it. In a follow-up patch this
simplifies setting the link limits which are dependent on the DSC vs.
non-DSC mode.
While at it sanitize the debug print about the MST DSC fallback path,
making it similar to the SST DSC one.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 22 ++++++++++++------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 25 +++++++++++++++------
2 files changed, 33 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f4952fcfb16e9..62dc3716c3998 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1855,7 +1855,8 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct link_config_limits limits;
bool joiner_needs_dsc = false;
- int ret;
+ bool dsc_needed;
+ int ret = 0;
intel_dp_compute_config_limits(intel_dp, pipe_config,
respect_downstream_limits, &limits);
@@ -1871,13 +1872,20 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
*/
joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
- /*
- * Optimize for slow and wide for everything, because there are some
- * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
- */
- ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, conn_state, &limits);
+ dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en;
+
+ if (!dsc_needed) {
+ /*
+ * Optimize for slow and wide for everything, because there are some
+ * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
+ */
+ ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
+ conn_state, &limits);
+ if (ret)
+ dsc_needed = true;
+ }
- if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
+ if (dsc_needed) {
drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
str_yes_no(ret), str_yes_no(joiner_needs_dsc),
str_yes_no(intel_dp->force_dsc_en));
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 1809643538d08..68739e46a9edb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -347,7 +347,8 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
struct link_config_limits limits;
- int ret;
+ bool dsc_needed;
+ int ret = 0;
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
@@ -362,15 +363,25 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
intel_dp_mst_compute_config_limits(intel_dp, pipe_config, &limits);
- ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
- conn_state, &limits);
+ dsc_needed = intel_dp->force_dsc_en;
- if (ret == -EDEADLK)
- return ret;
+ if (!dsc_needed) {
+ ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
+ conn_state, &limits);
+
+ if (ret == -EDEADLK)
+ return ret;
+
+ if (ret)
+ dsc_needed = true;
+ }
/* enable compression if the mode doesn't fit available BW */
- drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
- if (ret || intel_dp->force_dsc_en) {
+ if (dsc_needed) {
+ drm_dbg_kms(&dev_priv->drm, "Try DSC (fallback=%s, force=%s)\n",
+ str_yes_no(ret),
+ str_yes_no(intel_dp->force_dsc_en));
+
/*
* Try to get at least some timeslots and then see, if
* we can fit there with DSC.
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread* [Intel-gfx] [PATCH 04/17] drm/i915/dp: Update the link bpp limits for DSC mode
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
` (2 preceding siblings ...)
2023-08-17 16:14 ` [Intel-gfx] [PATCH 03/17] drm/i915/dp: Skip computing a non-DSC link config if DSC is needed Imre Deak
@ 2023-08-17 16:14 ` Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 05/17] drm/i915/dp: Limit the output link bpp in " Imre Deak
` (16 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx
In non-DSC mode the link bpp can be set in 2*3 bpp steps in the pipe bpp
range, while in DSC mode it can be set in 1/16 bpp steps to any value
up to the maximum pipe bpp. Update the limits accordingly in both modes
to prepare for a follow-up patch which may need to reduce the max link
bpp value and starts to check the link bpp limits in DSC mode as well.
While at it add more detail to the link limit debug print and print it
also for DSC mode.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 89 +++++++++++++++++----
drivers/gpu/drm/i915/display/intel_dp.h | 6 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 23 ++++--
3 files changed, 96 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 62dc3716c3998..c4016fd0dc980 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1798,16 +1798,68 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return 0;
}
-static void
+/**
+ * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
+ * @intel_dp: intel DP
+ * @crtc_state: crtc state
+ * @dsc: DSC compression mode
+ * @limits: link configuration limits
+ *
+ * Calculates the output link min, max bpp values in @limits based on the
+ * pipe bpp range, @crtc_state and @dsc mode.
+ *
+ * Returns %true in case of success.
+ */
+bool
+intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ bool dsc,
+ struct link_config_limits *limits)
+{
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+ const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ int max_link_bpp;
+
+ max_link_bpp = limits->pipe.max_bpp << 4;
+
+ if (!dsc) {
+ max_link_bpp = rounddown(max_link_bpp, (2 * 3) << 4);
+
+ if (max_link_bpp < limits->pipe.min_bpp << 4)
+ return false;
+
+ limits->link.min_bpp = limits->pipe.min_bpp << 4;
+ } else {
+ limits->link.min_bpp = 0;
+ }
+
+ limits->link.max_bpp = max_link_bpp;
+
+ drm_dbg_kms(&i915->drm,
+ "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp %d.%04d\n",
+ encoder->base.base.id, encoder->base.name,
+ crtc->base.base.id, crtc->base.name,
+ adjusted_mode->crtc_clock,
+ dsc ? "on" : "off",
+ limits->max_lane_count,
+ limits->max_rate,
+ limits->pipe.max_bpp,
+ limits->link.max_bpp >> 4,
+ (limits->link.max_bpp & 0xf) * 625);
+
+ return true;
+}
+
+static bool
intel_dp_compute_config_limits(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
bool respect_downstream_limits,
+ bool dsc,
struct link_config_limits *limits)
{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
-
limits->min_rate = intel_dp_common_rate(intel_dp, 0);
limits->max_rate = intel_dp_max_link_rate(intel_dp);
@@ -1833,13 +1885,10 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
- limits->link.min_bpp = limits->pipe.min_bpp << 4;
- limits->link.max_bpp = limits->pipe.max_bpp << 4;
-
- drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
- "max rate %d max bpp %d pixel clock %iKHz\n",
- limits->max_lane_count, limits->max_rate,
- limits->link.max_bpp >> 4, adjusted_mode->crtc_clock);
+ return intel_dp_compute_config_link_bpp_limits(intel_dp,
+ crtc_state,
+ dsc,
+ limits);
}
static int
@@ -1858,9 +1907,6 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
bool dsc_needed;
int ret = 0;
- intel_dp_compute_config_limits(intel_dp, pipe_config,
- respect_downstream_limits, &limits);
-
if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
adjusted_mode->crtc_clock))
pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
@@ -1872,7 +1918,11 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
*/
joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
- dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en;
+ dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
+ !intel_dp_compute_config_limits(intel_dp, pipe_config,
+ respect_downstream_limits,
+ false,
+ &limits);
if (!dsc_needed) {
/*
@@ -1889,6 +1939,13 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
str_yes_no(ret), str_yes_no(joiner_needs_dsc),
str_yes_no(intel_dp->force_dsc_en));
+
+ if (!intel_dp_compute_config_limits(intel_dp, pipe_config,
+ respect_downstream_limits,
+ true,
+ &limits))
+ return -EINVAL;
+
ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
conn_state, &limits, 64, true);
if (ret < 0)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index a1789419c0d19..22c18310ae47d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -151,4 +151,10 @@ void intel_dp_phy_test(struct intel_encoder *encoder);
void intel_dp_wait_source_oui(struct intel_dp *intel_dp);
+bool
+intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ bool dsc,
+ struct link_config_limits *limits);
+
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 68739e46a9edb..48c247ddef53a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -305,9 +305,10 @@ static bool intel_dp_mst_has_audio(const struct drm_connector_state *conn_state)
return intel_conn_state->force_audio == HDMI_AUDIO_ON;
}
-static void
+static bool
intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
+ bool dsc,
struct link_config_limits *limits)
{
/*
@@ -333,8 +334,10 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
- limits->link.min_bpp = limits->pipe.min_bpp << 4;
- limits->link.max_bpp = limits->pipe.max_bpp << 4;
+ return intel_dp_compute_config_link_bpp_limits(intel_dp,
+ crtc_state,
+ dsc,
+ limits);
}
static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
@@ -361,9 +364,11 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
intel_dp_mst_has_audio(conn_state) &&
intel_audio_compute_config(encoder, pipe_config, conn_state);
- intel_dp_mst_compute_config_limits(intel_dp, pipe_config, &limits);
-
- dsc_needed = intel_dp->force_dsc_en;
+ dsc_needed = intel_dp->force_dsc_en ||
+ !intel_dp_mst_compute_config_limits(intel_dp,
+ pipe_config,
+ false,
+ &limits);
if (!dsc_needed) {
ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
@@ -382,6 +387,12 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
str_yes_no(ret),
str_yes_no(intel_dp->force_dsc_en));
+ if (!intel_dp_mst_compute_config_limits(intel_dp,
+ pipe_config,
+ true,
+ &limits))
+ return -EINVAL;
+
/*
* Try to get at least some timeslots and then see, if
* we can fit there with DSC.
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread* [Intel-gfx] [PATCH 05/17] drm/i915/dp: Limit the output link bpp in DSC mode
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
` (3 preceding siblings ...)
2023-08-17 16:14 ` [Intel-gfx] [PATCH 04/17] drm/i915/dp: Update the link bpp limits for DSC mode Imre Deak
@ 2023-08-17 16:14 ` Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 06/17] drm/i915: Add helper to modeset a set of pipes Imre Deak
` (15 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx
Limit the output link bpp in DSC mode to the link_config_limits
link.min_bpp .. max_bpp range the same way it's done in non-DSC mode.
Atm, this doesn't make a difference, the link bpp range being
0 .. max pipe bpp, but a follow-up patch will need a way to reduce max
link bpp below its current value.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 +++++++++++-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c4016fd0dc980..b5d38765dde54 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1703,9 +1703,16 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->lane_count = limits->max_lane_count;
if (intel_dp_is_edp(intel_dp)) {
+ u16 dsc_max_output_bpp;
+
+ dsc_max_output_bpp =
+ min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd),
+ limits->link.max_bpp);
+
pipe_config->dsc.compressed_bpp =
- min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
+ min_t(u16, dsc_max_output_bpp >> 4,
pipe_config->pipe_bpp);
+
pipe_config->dsc.slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
@@ -1761,6 +1768,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
* calculation procedure is bit different for MST case.
*/
if (compute_pipe_bpp) {
+ dsc_max_output_bpp = min_t(u16, dsc_max_output_bpp,
+ limits->link.max_bpp);
+
pipe_config->dsc.compressed_bpp = min_t(u16,
dsc_max_output_bpp >> 4,
pipe_config->pipe_bpp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 48c247ddef53a..0dcb9a203dfe7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -230,6 +230,9 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
if (max_bpp > sink_max_bpp)
max_bpp = sink_max_bpp;
+ min_bpp = max(min_bpp, (limits->link.min_bpp + 0xf) >> 4);
+ max_bpp = min(max_bpp, limits->link.max_bpp >> 4);
+
slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_bpp,
min_bpp, limits,
conn_state, 2 * 3, true);
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread* [Intel-gfx] [PATCH 06/17] drm/i915: Add helper to modeset a set of pipes
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
` (4 preceding siblings ...)
2023-08-17 16:14 ` [Intel-gfx] [PATCH 05/17] drm/i915/dp: Limit the output link bpp in " Imre Deak
@ 2023-08-17 16:14 ` Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 07/17] drm/i915: Factor out a helper to check/compute all the CRTC states Imre Deak
` (14 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx
Add intel_modeset_pipes_in_mask() to modeset a provided set of pipes,
used in a follow-up patch.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 12 +++++++++---
drivers/gpu/drm/i915/display/intel_display.h | 2 ++
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 763ab569d8f32..c35e5d7e45a3b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5420,8 +5420,8 @@ intel_verify_planes(struct intel_atomic_state *state)
plane_state->uapi.visible);
}
-int intel_modeset_all_pipes(struct intel_atomic_state *state,
- const char *reason)
+int intel_modeset_pipes_in_mask(struct intel_atomic_state *state,
+ const char *reason, u8 mask)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc *crtc;
@@ -5430,7 +5430,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
* Add all pipes to the state, and force
* a modeset on all the active ones.
*/
- for_each_intel_crtc(&dev_priv->drm, crtc) {
+ for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, mask) {
struct intel_crtc_state *crtc_state;
int ret;
@@ -5469,6 +5469,12 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
return 0;
}
+int intel_modeset_all_pipes(struct intel_atomic_state *state,
+ const char *reason)
+{
+ return intel_modeset_pipes_in_mask(state, reason, -1);
+}
+
/*
* This implements the workaround described in the "notes" section of the mode
* set sequence documentation. When going from no pipes or single pipe to
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 49ac8473b988b..ffbabfc9e1e10 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -515,6 +515,8 @@ void intel_update_watermarks(struct drm_i915_private *i915);
/* modesetting */
int intel_modeset_all_pipes(struct intel_atomic_state *state,
const char *reason);
+int intel_modeset_pipes_in_mask(struct intel_atomic_state *state,
+ const char *reason, u8 pipe_mask);
void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
struct intel_power_domain_mask *old_domains);
void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread* [Intel-gfx] [PATCH 07/17] drm/i915: Factor out a helper to check/compute all the CRTC states
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
` (5 preceding siblings ...)
2023-08-17 16:14 ` [Intel-gfx] [PATCH 06/17] drm/i915: Add helper to modeset a set of pipes Imre Deak
@ 2023-08-17 16:14 ` Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 08/17] drm/i915/fdi: Improve FDI BW sharing between pipe B and C Imre Deak
` (13 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx
Factor out intel_atomic_check_config() to check and compute all the CRTC
states. This will be used by a follow up patch to recompute/check the
state until required by BW limitations between CRTCs.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 78 ++++++++++++--------
1 file changed, 46 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c35e5d7e45a3b..381f68890565c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6177,6 +6177,51 @@ static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
return 0;
}
+static int intel_atomic_check_config(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc *crtc;
+ int ret;
+ int i;
+
+ ret = intel_bigjoiner_add_affected_crtcs(state);
+ if (ret)
+ return ret;
+
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ if (!intel_crtc_needs_modeset(new_crtc_state)) {
+ if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
+ copy_bigjoiner_crtc_state_nomodeset(state, crtc);
+ else
+ intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
+ continue;
+ }
+
+ if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
+ drm_WARN_ON(&i915->drm, new_crtc_state->uapi.enable);
+ continue;
+ }
+
+ ret = intel_crtc_prepare_cleared_state(state, crtc);
+ if (ret)
+ break;
+
+ if (!new_crtc_state->hw.enable)
+ continue;
+
+ ret = intel_modeset_pipe_config(state, crtc);
+ if (ret)
+ break;
+
+ ret = intel_atomic_check_bigjoiner(state, crtc);
+ if (ret)
+ break;
+ }
+
+ return ret;
+}
+
/**
* intel_atomic_check - validate state object
* @dev: drm device
@@ -6221,41 +6266,10 @@ int intel_atomic_check(struct drm_device *dev,
return ret;
}
- ret = intel_bigjoiner_add_affected_crtcs(state);
+ ret = intel_atomic_check_config(state);
if (ret)
goto fail;
- for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
- new_crtc_state, i) {
- if (!intel_crtc_needs_modeset(new_crtc_state)) {
- if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
- copy_bigjoiner_crtc_state_nomodeset(state, crtc);
- else
- intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
- continue;
- }
-
- if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
- drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable);
- continue;
- }
-
- ret = intel_crtc_prepare_cleared_state(state, crtc);
- if (ret)
- goto fail;
-
- if (!new_crtc_state->hw.enable)
- continue;
-
- ret = intel_modeset_pipe_config(state, crtc);
- if (ret)
- goto fail;
-
- ret = intel_atomic_check_bigjoiner(state, crtc);
- if (ret)
- goto fail;
- }
-
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
if (!intel_crtc_needs_modeset(new_crtc_state))
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread* [Intel-gfx] [PATCH 08/17] drm/i915/fdi: Improve FDI BW sharing between pipe B and C
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
` (6 preceding siblings ...)
2023-08-17 16:14 ` [Intel-gfx] [PATCH 07/17] drm/i915: Factor out a helper to check/compute all the CRTC states Imre Deak
@ 2023-08-17 16:14 ` Imre Deak
2023-08-17 16:14 ` Imre Deak
` (12 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx
At the moment modesetting pipe C on IVB will fail if pipe B uses 4 FDI
lanes. Make the BW sharing more dynamic by trying to reduce pipe B's
link bpp in this case, until pipe B uses only up to 2 FDI lanes.
For this instead of the encoder compute config retry loop - which
reduced link bpp only for the encoder's pipe - check the overall BW
limits after all CRTC states have been computed and if the check fails
reduce the maximum link bpp for a selected pipe (for FDI pipe B or C as
required) and recompute all the CRTC states. Retry this sequence until
either the overall BW limit check passes, or further bpp reduction is
not possible (because all pipes/encoders sharing the link BW reached
their minimum link bpp).
This change also prepares for an upcoming patch resolving BW limits in
a similar way on MST links as well.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/g4x_hdmi.c | 5 +-
drivers/gpu/drm/i915/display/intel_atomic.c | 205 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_atomic.h | 8 +
drivers/gpu/drm/i915/display/intel_crt.c | 7 +
drivers/gpu/drm/i915/display/intel_crtc.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 40 ++--
drivers/gpu/drm/i915/display/intel_display.h | 4 +
.../drm/i915/display/intel_display_types.h | 9 +-
drivers/gpu/drm/i915/display/intel_dp.c | 3 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 66 ++++--
drivers/gpu/drm/i915/display/intel_fdi.h | 4 +
drivers/gpu/drm/i915/display/intel_lvds.c | 9 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 9 +-
13 files changed, 326 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 634b14116d9dd..ebbceddc13259 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -133,8 +133,11 @@ static int g4x_hdmi_compute_config(struct intel_encoder *encoder,
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- if (HAS_PCH_SPLIT(i915))
+ if (HAS_PCH_SPLIT(i915)) {
crtc_state->has_pch_encoder = true;
+ if (!intel_atomic_compute_pipe_bpp(crtc_state))
+ return -EINVAL;
+ }
if (IS_G4X(i915))
crtc_state->has_hdmi_sink = g4x_compute_has_hdmi_sink(state, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 7cf51dd8c0567..8e55eb3b2cee0 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -38,6 +38,7 @@
#include "intel_atomic.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
+#include "intel_fdi.h"
#include "intel_global_state.h"
#include "intel_hdcp.h"
#include "intel_psr.h"
@@ -358,3 +359,207 @@ intel_atomic_get_crtc_state(struct drm_atomic_state *state,
return to_intel_crtc_state(crtc_state);
}
+
+/**
+ * intel_atomic_compute_pipe_bpp - compute pipe bpp limited by max link bpp
+ * @crtc_state: the crtc state
+ *
+ * Compute the pipe bpp limited by the CRTC's maximum link bpp. Encoders can
+ * call this function during state computation in the simple case where the
+ * link bpp will always match the pipe bpp. This is the case for all non-DP
+ * encoders, while DP encoders will use a link bpp lower than pipe bpp in case
+ * of DSC compression.
+ *
+ * Returns %true in case of success, %false if pipe bpp would need to be
+ * reduced below its valid range.
+ */
+bool intel_atomic_compute_pipe_bpp(struct intel_crtc_state *crtc_state)
+{
+ int pipe_bpp = min(crtc_state->pipe_bpp,
+ crtc_state->max_link_bpp >> 4);
+
+ pipe_bpp = rounddown(pipe_bpp, 2 * 3);
+
+ if (pipe_bpp < 6 * 3)
+ return false;
+
+ crtc_state->pipe_bpp = pipe_bpp;
+
+ return true;
+}
+
+/**
+ * intel_atomic_reduce_link_bpp - reduce maximum link bpp for a selected pipe
+ * @state: atomic state
+ * @limits: link BW limits
+ * @pipe_mask: mask of pipes to select from
+ * @reason: explanation of why bpp reduction is needed
+ *
+ * Select the pipe from @pipe_mask with the biggest link bpp value and set the
+ * maximum of link bpp in @limits below this value. Modeset the selected pipe,
+ * so that its state will get recomputed.
+ *
+ * This function can be called to resolve a link's BW overallocation by reducing
+ * the link bpp of one pipe on * the link and hence reducing the total link BW.
+ *
+ * Returns
+ * - 0 in case of success
+ * - %-EINVAL if no pipe can further reduce its link bpp
+ * - A negative error code if modesetting the selected pipe failed.
+ */
+int intel_atomic_reduce_link_bpp(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits,
+ u8 pipe_mask,
+ const char *reason)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *crtc_state;
+ enum pipe max_bpp_pipe = INVALID_PIPE;
+ int max_bpp = 0;
+ int i;
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ int pipe_bpp;
+
+ if (!(pipe_mask & BIT(crtc->pipe)))
+ continue;
+
+ if (limits->min_bpp_pipes & BIT(crtc->pipe))
+ continue;
+
+ if (crtc_state->dsc.compression_enable)
+ pipe_bpp = crtc_state->dsc.compressed_bpp;
+ else
+ pipe_bpp = crtc_state->pipe_bpp;
+
+ if (pipe_bpp > max_bpp) {
+ max_bpp = pipe_bpp;
+ max_bpp_pipe = crtc->pipe;
+ }
+ }
+
+ if (max_bpp_pipe == INVALID_PIPE)
+ return -EINVAL;
+
+ limits->max_bpp[max_bpp_pipe] = (max_bpp << 4) - 1;
+
+ return intel_modeset_pipes_in_mask(state, reason,
+ BIT(max_bpp_pipe));
+}
+
+static int intel_atomic_check_link(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits)
+{
+ int ret;
+
+ ret = intel_fdi_atomic_check_link(state, limits);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static bool
+assert_link_limit_change_valid(struct drm_i915_private *i915,
+ const struct intel_link_bw_limits *old_limits,
+ const struct intel_link_bw_limits *new_limits)
+{
+ bool bpps_changed = false;
+ enum pipe pipe;
+
+ for_each_pipe(i915, pipe) {
+ /* The bpp limit can only decrease. */
+ if (drm_WARN_ON(&i915->drm,
+ new_limits->max_bpp[pipe] >
+ old_limits->max_bpp[pipe]))
+ return false;
+
+ if (new_limits->max_bpp[pipe] <
+ old_limits->max_bpp[pipe])
+ bpps_changed = true;
+ }
+
+ if (drm_WARN_ON(&i915->drm,
+ !bpps_changed))
+ return false;
+
+ return true;
+}
+
+static bool
+reset_link_bpp_limit_to_min(struct intel_atomic_state *state,
+ const struct intel_link_bw_limits *old_limits,
+ struct intel_link_bw_limits *new_limits,
+ enum pipe failed_pipe)
+{
+ if (failed_pipe == INVALID_PIPE)
+ return false;
+
+ if (new_limits->min_bpp_pipes & BIT(failed_pipe))
+ return false;
+
+ if (new_limits->max_bpp[failed_pipe] ==
+ old_limits->max_bpp[failed_pipe])
+ return false;
+
+ new_limits->max_bpp[failed_pipe] =
+ old_limits->max_bpp[failed_pipe];
+ new_limits->min_bpp_pipes |= BIT(failed_pipe);
+
+ return true;
+}
+
+/**
+ * intel_atomic_check_config_and_link - compute CRTC configs, resolving any BW limits
+ * @state: atomic state
+ *
+ * Compute the configuration of all CRTCs in @state and resolve any BW
+ * limitations on links shared by these CRTCs.
+ *
+ * Return 0 in case of success, or a negative error code otherwise.
+ */
+int intel_atomic_check_config_and_link(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_link_bw_limits new_limits = {};
+ struct intel_link_bw_limits old_limits;
+ enum pipe pipe;
+ int ret;
+
+ for_each_pipe(i915, pipe)
+ new_limits.max_bpp[pipe] = INT_MAX;
+
+ old_limits = new_limits;
+
+ while (true) {
+ enum pipe failed_pipe;
+
+ ret = intel_atomic_check_config(state, &new_limits,
+ &failed_pipe);
+ if (ret) {
+ if (ret == -EINVAL &&
+ reset_link_bpp_limit_to_min(state,
+ &old_limits,
+ &new_limits,
+ failed_pipe))
+ continue;
+
+ break;
+ }
+
+ old_limits = new_limits;
+
+ ret = intel_atomic_check_link(state, &new_limits);
+ if (ret != -EAGAIN)
+ break;
+
+ if (!assert_link_limit_change_valid(i915,
+ &old_limits,
+ &new_limits)) {
+ ret = -EINVAL;
+ break;
+ }
+ }
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
index e506f6a873447..bbf3595d52c41 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -20,6 +20,7 @@ struct intel_atomic_state;
struct intel_connector;
struct intel_crtc;
struct intel_crtc_state;
+struct intel_link_bw_limits;
int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
const struct drm_connector_state *state,
@@ -52,4 +53,11 @@ struct intel_crtc_state *
intel_atomic_get_crtc_state(struct drm_atomic_state *state,
struct intel_crtc *crtc);
+int intel_atomic_reduce_link_bpp(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits,
+ u8 pipe_mask,
+ const char *reason);
+bool intel_atomic_compute_pipe_bpp(struct intel_crtc_state *crtc_state);
+int intel_atomic_check_config_and_link(struct intel_atomic_state *state);
+
#endif /* __INTEL_ATOMIC_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index f66340b4caf0f..3322080a574e8 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -36,6 +36,7 @@
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_reg.h"
+#include "intel_atomic.h"
#include "intel_connector.h"
#include "intel_crt.h"
#include "intel_crtc.h"
@@ -413,6 +414,9 @@ static int pch_crt_compute_config(struct intel_encoder *encoder,
return -EINVAL;
pipe_config->has_pch_encoder = true;
+ if (!intel_atomic_compute_pipe_bpp(pipe_config))
+ return -EINVAL;
+
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
return 0;
@@ -435,6 +439,9 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
return -EINVAL;
pipe_config->has_pch_encoder = true;
+ if (!intel_atomic_compute_pipe_bpp(pipe_config))
+ return -EINVAL;
+
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
/* LPT FDI RX only supports 8bpc. */
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 182c6dd64f47c..0a701163e2f33 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -175,6 +175,7 @@ void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
crtc_state->hsw_workaround_pipe = INVALID_PIPE;
crtc_state->scaler_state.scaler_id = -1;
crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
+ crtc_state->max_link_bpp = INT_MAX;
}
static struct intel_crtc *intel_crtc_alloc(void)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 381f68890565c..de2152c94c161 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4641,7 +4641,8 @@ intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
static int
intel_modeset_pipe_config(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+ struct intel_crtc *crtc,
+ const struct intel_link_bw_limits *limits)
{
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_crtc_state *crtc_state =
@@ -4650,7 +4651,6 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
struct drm_connector_state *connector_state;
int pipe_src_w, pipe_src_h;
int base_bpp, ret, i;
- bool retry = true;
crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
@@ -4673,6 +4673,17 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
if (ret)
return ret;
+ crtc_state->max_link_bpp = limits->max_bpp[crtc->pipe];
+
+ if (crtc_state->pipe_bpp > crtc_state->max_link_bpp >> 4) {
+ drm_dbg_kms(&i915->drm,
+ "[CRTC:%d:%s] Link bpp limited to %d.%04d\n",
+ crtc->base.base.id, crtc->base.name,
+ crtc_state->max_link_bpp >> 4,
+ (crtc_state->max_link_bpp & 0xf) * 625);
+ crtc_state->bw_constrained = true;
+ }
+
base_bpp = crtc_state->pipe_bpp;
/*
@@ -4714,7 +4725,6 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
crtc_state->output_types |= BIT(encoder->type);
}
-encoder_retry:
/* Ensure the port clock defaults are reset when retrying. */
crtc_state->port_clock = 0;
crtc_state->pixel_multiplier = 1;
@@ -4754,17 +4764,6 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
ret = intel_crtc_compute_config(state, crtc);
if (ret == -EDEADLK)
return ret;
- if (ret == -EAGAIN) {
- if (drm_WARN(&i915->drm, !retry,
- "[CRTC:%d:%s] loop in pipe configuration computation\n",
- crtc->base.base.id, crtc->base.name))
- return -EINVAL;
-
- drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n",
- crtc->base.base.id, crtc->base.name);
- retry = false;
- goto encoder_retry;
- }
if (ret < 0) {
drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
crtc->base.base.id, crtc->base.name, ret);
@@ -6177,7 +6176,9 @@ static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
return 0;
}
-static int intel_atomic_check_config(struct intel_atomic_state *state)
+int intel_atomic_check_config(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits,
+ enum pipe *failed_pipe)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state;
@@ -6185,6 +6186,8 @@ static int intel_atomic_check_config(struct intel_atomic_state *state)
int ret;
int i;
+ *failed_pipe = INVALID_PIPE;
+
ret = intel_bigjoiner_add_affected_crtcs(state);
if (ret)
return ret;
@@ -6210,7 +6213,7 @@ static int intel_atomic_check_config(struct intel_atomic_state *state)
if (!new_crtc_state->hw.enable)
continue;
- ret = intel_modeset_pipe_config(state, crtc);
+ ret = intel_modeset_pipe_config(state, crtc, limits);
if (ret)
break;
@@ -6219,6 +6222,9 @@ static int intel_atomic_check_config(struct intel_atomic_state *state)
break;
}
+ if (ret)
+ *failed_pipe = crtc->pipe;
+
return ret;
}
@@ -6266,7 +6272,7 @@ int intel_atomic_check(struct drm_device *dev,
return ret;
}
- ret = intel_atomic_check_config(state);
+ ret = intel_atomic_check_config_and_link(state);
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index ffbabfc9e1e10..8c3d2eb422567 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -55,6 +55,7 @@ struct intel_digital_port;
struct intel_dp;
struct intel_encoder;
struct intel_initial_plane_config;
+struct intel_link_bw_limits;
struct intel_link_m_n;
struct intel_plane;
struct intel_plane_state;
@@ -391,6 +392,9 @@ enum phy_fia {
(new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);
+int intel_atomic_check_config(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits,
+ enum pipe *failed_pipe);
int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
struct intel_crtc *crtc);
u8 intel_calc_active_pipes(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 731f2ec04d5cd..aa17ac64273a9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -66,6 +66,12 @@ struct intel_tc_port;
* Display related stuff
*/
+struct intel_link_bw_limits {
+ u8 min_bpp_pipes;
+ /* in 1/16 bpp units */
+ int max_bpp[I915_MAX_PIPES];
+};
+
/* these are outputs from the chip - integrated only
external chips are via DVO or SDVO output */
enum intel_output_type {
@@ -1189,7 +1195,8 @@ struct intel_crtc_state {
u32 ctrl, div;
} dsi_pll;
- int pipe_bpp;
+ int max_link_bpp; /* in 1/16 bpp units */
+ int pipe_bpp; /* in 1 bpp units */
struct intel_link_m_n dp_m_n;
/* m2_n2 for eDP downclock */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b5d38765dde54..e85a6f89ca9e3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1833,7 +1833,8 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
int max_link_bpp;
- max_link_bpp = limits->pipe.max_bpp << 4;
+ max_link_bpp = min(crtc_state->max_link_bpp,
+ limits->pipe.max_bpp << 4);
if (!dsc) {
max_link_bpp = rounddown(max_link_bpp, (2 * 3) << 4);
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index e12b46a84fa11..061d2e54786ea 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -129,13 +129,16 @@ static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
}
static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
- struct intel_crtc_state *pipe_config)
+ struct intel_crtc_state *pipe_config,
+ enum pipe *pipe_to_reduce)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_atomic_state *state = pipe_config->uapi.state;
struct intel_crtc *other_crtc;
struct intel_crtc_state *other_crtc_state;
+ *pipe_to_reduce = pipe;
+
drm_dbg_kms(&dev_priv->drm,
"checking fdi config on pipe %c, lanes %i\n",
pipe_name(pipe), pipe_config->fdi_lanes);
@@ -198,6 +201,9 @@ static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
drm_dbg_kms(&dev_priv->drm,
"fdi link B uses too many lanes to enable link C\n");
+
+ *pipe_to_reduce = PIPE_B;
+
return -EINVAL;
}
return 0;
@@ -238,10 +244,8 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *i915 = to_i915(dev);
const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
- int lane, link_bw, fdi_dotclock, ret;
- bool needs_recompute = false;
+ int lane, link_bw, fdi_dotclock;
-retry:
/* FDI is a binary signal running at ~2.7GHz, encoding
* each output octet as 10 bits. The actual frequency
* is stored as a divider into a 100MHz clock, and the
@@ -261,25 +265,51 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
link_bw, &pipe_config->fdi_m_n, false);
- ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
- if (ret == -EDEADLK)
+ return 0;
+}
+
+static int intel_fdi_atomic_check_bw(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config,
+ struct intel_link_bw_limits *limits)
+{
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ enum pipe pipe_to_reduce;
+ int ret;
+
+ ret = ilk_check_fdi_lanes(&i915->drm, crtc->pipe, pipe_config,
+ &pipe_to_reduce);
+ if (ret != -EINVAL)
return ret;
- if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
- pipe_config->pipe_bpp -= 2*3;
- drm_dbg_kms(&i915->drm,
- "fdi link bw constraint, reducing pipe bpp to %i\n",
- pipe_config->pipe_bpp);
- needs_recompute = true;
- pipe_config->bw_constrained = true;
+ ret = intel_atomic_reduce_link_bpp(state, limits,
+ BIT(pipe_to_reduce),
+ "FDI link BW");
- goto retry;
- }
+ return ret ? : -EAGAIN;
+}
+
+int intel_fdi_atomic_check_link(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *crtc_state;
+ int i;
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ int ret;
- if (needs_recompute)
- return -EAGAIN;
+ if (!crtc_state->has_pch_encoder ||
+ !intel_crtc_needs_modeset(crtc_state) ||
+ !crtc_state->hw.enable)
+ continue;
+
+ ret = intel_fdi_atomic_check_bw(state, crtc, crtc_state, limits);
+ if (ret)
+ return ret;
+ }
- return ret;
+ return 0;
}
static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h b/drivers/gpu/drm/i915/display/intel_fdi.h
index 1cdb86172702f..129444c580f27 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.h
+++ b/drivers/gpu/drm/i915/display/intel_fdi.h
@@ -8,14 +8,18 @@
enum pipe;
struct drm_i915_private;
+struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_encoder;
+struct intel_link_bw_limits;
int intel_fdi_link_freq(struct drm_i915_private *i915,
const struct intel_crtc_state *pipe_config);
int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
struct intel_crtc_state *pipe_config);
+int intel_fdi_atomic_check_link(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits);
void intel_fdi_normal_train(struct intel_crtc *crtc);
void ilk_fdi_disable(struct intel_crtc *crtc);
void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 3ace56979b70e..08dcc2d10a2c1 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -425,6 +425,12 @@ static int intel_lvds_compute_config(struct intel_encoder *encoder,
return -EINVAL;
}
+ if (HAS_PCH_SPLIT(i915)) {
+ crtc_state->has_pch_encoder = true;
+ if (!intel_atomic_compute_pipe_bpp(crtc_state))
+ return -EINVAL;
+ }
+
if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
lvds_bpp = 8*3;
else
@@ -453,9 +459,6 @@ static int intel_lvds_compute_config(struct intel_encoder *encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
- if (HAS_PCH_SPLIT(i915))
- crtc_state->has_pch_encoder = true;
-
ret = intel_panel_fitting(crtc_state, conn_state);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 7d25a64698e2f..1c6330151f4d6 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -1352,14 +1352,17 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder,
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
struct drm_display_mode *mode = &pipe_config->hw.mode;
+ if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) {
+ pipe_config->has_pch_encoder = true;
+ if (!intel_atomic_compute_pipe_bpp(pipe_config))
+ return -EINVAL;
+ }
+
DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
pipe_config->pipe_bpp = 8*3;
pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
- if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
- pipe_config->has_pch_encoder = true;
-
/*
* We need to construct preferred input timings based on our
* output timings. To do that, we have to set the output
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread* [Intel-gfx] [PATCH 09/17] drm/dp_mst: Fix fractional bpp scaling in drm_dp_calc_pbn_mode()
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
@ 2023-08-17 16:14 ` Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 02/17] drm/i915/dp: Track the pipe and link bpp limits separately Imre Deak
` (19 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
For fractional bpp values passed to the function in a .4 fixed point
format, the fractional part is currently ignored due to scaling bpp too
early. Fix this by scaling the overhead factor instead and to avoid an
overflow multiplying bpp with the overhead factor instead of the clock
rate.
While at it simplify the formula, and pass the expected fixed point bpp
values in the kunit tests.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 7 ++-----
drivers/gpu/drm/tests/drm_dp_mst_helper_test.c | 8 ++++----
2 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index ed96cfcfa3040..bd0f35a0ea5fb 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -4712,12 +4712,9 @@ int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
* factor in the numerator rather than the denominator to avoid
* integer overflow
*/
+ u32 bpp_m = (dsc ? 64 / 16 : 64) * 1006 * bpp;
- if (dsc)
- return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006),
- 8 * 54 * 1000 * 1000);
-
- return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
+ return DIV_ROUND_UP_ULL(mul_u32_u32(clock, bpp_m),
8 * 54 * 1000 * 1000);
}
EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
index 545beea33e8c7..ea2182815ebe8 100644
--- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
+++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
@@ -40,15 +40,15 @@ static const struct drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases
},
{
.clock = 332880,
- .bpp = 24,
+ .bpp = 24 << 4,
.dsc = true,
- .expected = 50
+ .expected = 1191
},
{
.clock = 324540,
- .bpp = 24,
+ .bpp = 24 << 4,
.dsc = true,
- .expected = 49
+ .expected = 1161
},
};
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 09/17] drm/dp_mst: Fix fractional bpp scaling in drm_dp_calc_pbn_mode()
@ 2023-08-17 16:14 ` Imre Deak
0 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
For fractional bpp values passed to the function in a .4 fixed point
format, the fractional part is currently ignored due to scaling bpp too
early. Fix this by scaling the overhead factor instead and to avoid an
overflow multiplying bpp with the overhead factor instead of the clock
rate.
While at it simplify the formula, and pass the expected fixed point bpp
values in the kunit tests.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 7 ++-----
drivers/gpu/drm/tests/drm_dp_mst_helper_test.c | 8 ++++----
2 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index ed96cfcfa3040..bd0f35a0ea5fb 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -4712,12 +4712,9 @@ int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
* factor in the numerator rather than the denominator to avoid
* integer overflow
*/
+ u32 bpp_m = (dsc ? 64 / 16 : 64) * 1006 * bpp;
- if (dsc)
- return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006),
- 8 * 54 * 1000 * 1000);
-
- return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
+ return DIV_ROUND_UP_ULL(mul_u32_u32(clock, bpp_m),
8 * 54 * 1000 * 1000);
}
EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
index 545beea33e8c7..ea2182815ebe8 100644
--- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
+++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
@@ -40,15 +40,15 @@ static const struct drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases
},
{
.clock = 332880,
- .bpp = 24,
+ .bpp = 24 << 4,
.dsc = true,
- .expected = 50
+ .expected = 1191
},
{
.clock = 324540,
- .bpp = 24,
+ .bpp = 24 << 4,
.dsc = true,
- .expected = 49
+ .expected = 1161
},
};
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [PATCH 10/17] drm/dp_mst: Add a way to calculate PBN values with FEC overhead
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
@ 2023-08-17 16:14 ` Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 02/17] drm/i915/dp: Track the pipe and link bpp limits separately Imre Deak
` (19 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx; +Cc: Alex Deucher, Harry Wentland, dri-devel, Wayne Lin
Add a way for drivers to calculate the MST PBN values with FEC overhead.
This is required by 8b/10b links both for DSC and non-DSC (the latter
needed if there are both DSC and non-DSC streams on the same MST link).
Also add kunit test cases for PBN values calculated with FEC overhead.
Cc: Lyude Paul <lyude@redhat.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Wayne Lin <wayne.lin@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
drivers/gpu/drm/display/drm_dp_mst_topology.c | 18 +++++++++++----
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++--
drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
.../gpu/drm/tests/drm_dp_mst_helper_test.c | 23 ++++++++++++++++++-
include/drm/display/drm_dp_mst_helper.h | 2 +-
7 files changed, 42 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 4d3d6009838c7..c34ee22b2e7b2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6782,7 +6782,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
max_bpc);
bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
clock = adjusted_mode->clock;
- dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
+ dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false, false);
}
dm_new_connector_state->vcpi_slots =
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 57230661132bd..9acfdefc792d6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1636,7 +1636,7 @@ enum dc_status dm_dp_mst_is_port_support_mode(
} else {
/* check if mode could be supported within full_pbn */
bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
- pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
+ pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false, false);
if (pbn > aconnector->mst_output_port->full_pbn)
return DC_FAIL_BANDWIDTH_VALIDATE;
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index bd0f35a0ea5fb..e26f1b7f5a701 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -4693,26 +4693,34 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
* @clock: dot clock for the mode
* @bpp: bpp for the mode.
* @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel
+ * @fec: FEC overhead.
*
* This uses the formula in the spec to calculate the PBN value for a mode.
*/
-int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
+int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc, bool fec)
{
/*
- * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
+ * Overheads:
+ * - SSC downspread and ref clock variation margin:
+ * 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
+ * - FEC symbol insertions:
+ * 2.4% as per spec, factor is 1.024
+ *
* The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
* common multiplier to render an integer PBN for all link rate/lane
* counts combinations
* calculate
- * peak_kbps *= (1006/1000)
+ * peak_kbps *= (1006/1000) without FEC, or
+ * peak_kbps *= (1030/1000) with FEC
* peak_kbps *= (64/54)
- * peak_kbps *= 8 convert to bytes
+ * peak_kbps /= 8 convert to bytes
*
* If the bpp is in units of 1/16, further divide by 16. Put this
* factor in the numerator rather than the denominator to avoid
* integer overflow
*/
- u32 bpp_m = (dsc ? 64 / 16 : 64) * 1006 * bpp;
+ u32 overhead = fec ? 1030 : 1006;
+ u32 bpp_m = (dsc ? 64 / 16 : 64) * overhead * bpp;
return DIV_ROUND_UP_ULL(mul_u32_u32(clock, bpp_m),
8 * 54 * 1000 * 1000);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 0dcb9a203dfe7..b22e0cbdb7d56 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -110,7 +110,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
dsc ? bpp << 4 : bpp,
- dsc);
+ dsc,
+ false);
slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
connector->port,
@@ -975,7 +976,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
return ret;
if (mode_rate > max_rate || mode->clock > max_dotclk ||
- drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) {
+ drm_dp_calc_pbn_mode(mode->clock, min_bpp, false, false) > port->full_pbn) {
*status = MODE_CLOCK_HIGH;
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 4e7c9c353c511..d71c28e458107 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -967,7 +967,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
asyh->or.bpc = connector->display_info.bpc;
asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
- false);
+ false, false);
}
mst_state = drm_atomic_get_mst_topology_state(state, &mstm->mgr);
diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
index ea2182815ebe8..3c0c0ffd5f9f5 100644
--- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
+++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
@@ -16,6 +16,7 @@ struct drm_dp_mst_calc_pbn_mode_test {
const int clock;
const int bpp;
const bool dsc;
+ const bool fec;
const int expected;
};
@@ -24,39 +25,59 @@ static const struct drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases
.clock = 154000,
.bpp = 30,
.dsc = false,
+ .fec = false,
.expected = 689
},
{
.clock = 234000,
.bpp = 30,
.dsc = false,
+ .fec = false,
.expected = 1047
},
{
.clock = 297000,
.bpp = 24,
.dsc = false,
+ .fec = false,
.expected = 1063
},
{
.clock = 332880,
.bpp = 24 << 4,
.dsc = true,
+ .fec = false,
.expected = 1191
},
{
.clock = 324540,
.bpp = 24 << 4,
.dsc = true,
+ .fec = false,
.expected = 1161
},
+ {
+ .clock = 324540,
+ .bpp = 24 << 4,
+ .dsc = true,
+ .fec = true,
+ .expected = 1189
+ },
+ {
+ .clock = 324540,
+ .bpp = 24,
+ .dsc = false,
+ .fec = true,
+ .expected = 1189
+ },
};
static void drm_test_dp_mst_calc_pbn_mode(struct kunit *test)
{
const struct drm_dp_mst_calc_pbn_mode_test *params = test->param_value;
- KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp, params->dsc),
+ KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp,
+ params->dsc, params->fec),
params->expected);
}
diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
index ed5c9660563c4..0953b7b16a51b 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -832,7 +832,7 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector,
int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
int link_rate, int link_lane_count);
-int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
+int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc, bool fec);
void drm_dp_mst_update_slots(struct drm_dp_mst_topology_state *mst_state, uint8_t link_encoding_cap);
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 10/17] drm/dp_mst: Add a way to calculate PBN values with FEC overhead
@ 2023-08-17 16:14 ` Imre Deak
0 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx; +Cc: Alex Deucher, dri-devel, Wayne Lin
Add a way for drivers to calculate the MST PBN values with FEC overhead.
This is required by 8b/10b links both for DSC and non-DSC (the latter
needed if there are both DSC and non-DSC streams on the same MST link).
Also add kunit test cases for PBN values calculated with FEC overhead.
Cc: Lyude Paul <lyude@redhat.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Wayne Lin <wayne.lin@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
drivers/gpu/drm/display/drm_dp_mst_topology.c | 18 +++++++++++----
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++--
drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
.../gpu/drm/tests/drm_dp_mst_helper_test.c | 23 ++++++++++++++++++-
include/drm/display/drm_dp_mst_helper.h | 2 +-
7 files changed, 42 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 4d3d6009838c7..c34ee22b2e7b2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6782,7 +6782,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
max_bpc);
bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
clock = adjusted_mode->clock;
- dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
+ dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false, false);
}
dm_new_connector_state->vcpi_slots =
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 57230661132bd..9acfdefc792d6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1636,7 +1636,7 @@ enum dc_status dm_dp_mst_is_port_support_mode(
} else {
/* check if mode could be supported within full_pbn */
bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
- pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
+ pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false, false);
if (pbn > aconnector->mst_output_port->full_pbn)
return DC_FAIL_BANDWIDTH_VALIDATE;
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index bd0f35a0ea5fb..e26f1b7f5a701 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -4693,26 +4693,34 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
* @clock: dot clock for the mode
* @bpp: bpp for the mode.
* @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel
+ * @fec: FEC overhead.
*
* This uses the formula in the spec to calculate the PBN value for a mode.
*/
-int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
+int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc, bool fec)
{
/*
- * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
+ * Overheads:
+ * - SSC downspread and ref clock variation margin:
+ * 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
+ * - FEC symbol insertions:
+ * 2.4% as per spec, factor is 1.024
+ *
* The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
* common multiplier to render an integer PBN for all link rate/lane
* counts combinations
* calculate
- * peak_kbps *= (1006/1000)
+ * peak_kbps *= (1006/1000) without FEC, or
+ * peak_kbps *= (1030/1000) with FEC
* peak_kbps *= (64/54)
- * peak_kbps *= 8 convert to bytes
+ * peak_kbps /= 8 convert to bytes
*
* If the bpp is in units of 1/16, further divide by 16. Put this
* factor in the numerator rather than the denominator to avoid
* integer overflow
*/
- u32 bpp_m = (dsc ? 64 / 16 : 64) * 1006 * bpp;
+ u32 overhead = fec ? 1030 : 1006;
+ u32 bpp_m = (dsc ? 64 / 16 : 64) * overhead * bpp;
return DIV_ROUND_UP_ULL(mul_u32_u32(clock, bpp_m),
8 * 54 * 1000 * 1000);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 0dcb9a203dfe7..b22e0cbdb7d56 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -110,7 +110,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
dsc ? bpp << 4 : bpp,
- dsc);
+ dsc,
+ false);
slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
connector->port,
@@ -975,7 +976,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
return ret;
if (mode_rate > max_rate || mode->clock > max_dotclk ||
- drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) {
+ drm_dp_calc_pbn_mode(mode->clock, min_bpp, false, false) > port->full_pbn) {
*status = MODE_CLOCK_HIGH;
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 4e7c9c353c511..d71c28e458107 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -967,7 +967,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
asyh->or.bpc = connector->display_info.bpc;
asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
- false);
+ false, false);
}
mst_state = drm_atomic_get_mst_topology_state(state, &mstm->mgr);
diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
index ea2182815ebe8..3c0c0ffd5f9f5 100644
--- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
+++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
@@ -16,6 +16,7 @@ struct drm_dp_mst_calc_pbn_mode_test {
const int clock;
const int bpp;
const bool dsc;
+ const bool fec;
const int expected;
};
@@ -24,39 +25,59 @@ static const struct drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases
.clock = 154000,
.bpp = 30,
.dsc = false,
+ .fec = false,
.expected = 689
},
{
.clock = 234000,
.bpp = 30,
.dsc = false,
+ .fec = false,
.expected = 1047
},
{
.clock = 297000,
.bpp = 24,
.dsc = false,
+ .fec = false,
.expected = 1063
},
{
.clock = 332880,
.bpp = 24 << 4,
.dsc = true,
+ .fec = false,
.expected = 1191
},
{
.clock = 324540,
.bpp = 24 << 4,
.dsc = true,
+ .fec = false,
.expected = 1161
},
+ {
+ .clock = 324540,
+ .bpp = 24 << 4,
+ .dsc = true,
+ .fec = true,
+ .expected = 1189
+ },
+ {
+ .clock = 324540,
+ .bpp = 24,
+ .dsc = false,
+ .fec = true,
+ .expected = 1189
+ },
};
static void drm_test_dp_mst_calc_pbn_mode(struct kunit *test)
{
const struct drm_dp_mst_calc_pbn_mode_test *params = test->param_value;
- KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp, params->dsc),
+ KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp,
+ params->dsc, params->fec),
params->expected);
}
diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
index ed5c9660563c4..0953b7b16a51b 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -832,7 +832,7 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector,
int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
int link_rate, int link_lane_count);
-int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
+int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc, bool fec);
void drm_dp_mst_update_slots(struct drm_dp_mst_topology_state *mst_state, uint8_t link_encoding_cap);
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [PATCH 11/17] drm/dp_mst: Add helper to determine if an MST port is downstream of another port
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
@ 2023-08-17 16:14 ` Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 02/17] drm/i915/dp: Track the pipe and link bpp limits separately Imre Deak
` (19 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Add drm_dp_mst_port_downstream_of_parent() required by the i915
driver in a follow-up patch to resolve a BW overallocation of MST
streams going through a given MST port.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 52 +++++++++++++++++++
include/drm/display/drm_dp_mst_helper.h | 3 ++
2 files changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index e26f1b7f5a701..ced9ae36a9177 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5105,6 +5105,58 @@ static bool drm_dp_mst_port_downstream_of_branch(struct drm_dp_mst_port *port,
return false;
}
+static bool
+drm_dp_mst_port_downstream_of_parent_locked(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_mst_port *parent)
+{
+ if (!mgr->mst_primary)
+ return false;
+
+ port = drm_dp_mst_topology_get_port_validated_locked(mgr->mst_primary,
+ port);
+ if (!port)
+ return false;
+
+ if (!parent)
+ return true;
+
+ parent = drm_dp_mst_topology_get_port_validated_locked(mgr->mst_primary,
+ parent);
+ if (!parent)
+ return false;
+
+ if (!parent->mstb)
+ return false;
+
+ return drm_dp_mst_port_downstream_of_branch(port, parent->mstb);
+}
+
+/**
+ * drm_dp_mst_port_downstream_of_parent - check if a port is downstream of a parent port
+ * @mgr: MST topology manager
+ * @port: the port being looked up
+ * @parent: the parent port
+ *
+ * The function returns %true if @port is downstream of @parent. If @parent is
+ * %NULL - denoting the root port - the function returns %true if @port is in
+ * @mgr's topology.
+ */
+bool
+drm_dp_mst_port_downstream_of_parent(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_mst_port *parent)
+{
+ bool ret;
+
+ mutex_lock(&mgr->lock);
+ ret = drm_dp_mst_port_downstream_of_parent_locked(mgr, port, parent);
+ mutex_unlock(&mgr->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(drm_dp_mst_port_downstream_of_parent);
+
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
struct drm_dp_mst_topology_state *state);
diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
index 0953b7b16a51b..097c4204ffae4 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -879,6 +879,9 @@ drm_atomic_get_new_mst_topology_state(struct drm_atomic_state *state,
struct drm_dp_mst_atomic_payload *
drm_atomic_get_mst_payload_state(struct drm_dp_mst_topology_state *state,
struct drm_dp_mst_port *port);
+bool drm_dp_mst_port_downstream_of_parent(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_mst_port *parent);
int __must_check
drm_dp_atomic_find_time_slots(struct drm_atomic_state *state,
struct drm_dp_mst_topology_mgr *mgr,
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 11/17] drm/dp_mst: Add helper to determine if an MST port is downstream of another port
@ 2023-08-17 16:14 ` Imre Deak
0 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Add drm_dp_mst_port_downstream_of_parent() required by the i915
driver in a follow-up patch to resolve a BW overallocation of MST
streams going through a given MST port.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 52 +++++++++++++++++++
include/drm/display/drm_dp_mst_helper.h | 3 ++
2 files changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index e26f1b7f5a701..ced9ae36a9177 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5105,6 +5105,58 @@ static bool drm_dp_mst_port_downstream_of_branch(struct drm_dp_mst_port *port,
return false;
}
+static bool
+drm_dp_mst_port_downstream_of_parent_locked(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_mst_port *parent)
+{
+ if (!mgr->mst_primary)
+ return false;
+
+ port = drm_dp_mst_topology_get_port_validated_locked(mgr->mst_primary,
+ port);
+ if (!port)
+ return false;
+
+ if (!parent)
+ return true;
+
+ parent = drm_dp_mst_topology_get_port_validated_locked(mgr->mst_primary,
+ parent);
+ if (!parent)
+ return false;
+
+ if (!parent->mstb)
+ return false;
+
+ return drm_dp_mst_port_downstream_of_branch(port, parent->mstb);
+}
+
+/**
+ * drm_dp_mst_port_downstream_of_parent - check if a port is downstream of a parent port
+ * @mgr: MST topology manager
+ * @port: the port being looked up
+ * @parent: the parent port
+ *
+ * The function returns %true if @port is downstream of @parent. If @parent is
+ * %NULL - denoting the root port - the function returns %true if @port is in
+ * @mgr's topology.
+ */
+bool
+drm_dp_mst_port_downstream_of_parent(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_mst_port *parent)
+{
+ bool ret;
+
+ mutex_lock(&mgr->lock);
+ ret = drm_dp_mst_port_downstream_of_parent_locked(mgr, port, parent);
+ mutex_unlock(&mgr->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(drm_dp_mst_port_downstream_of_parent);
+
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
struct drm_dp_mst_topology_state *state);
diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
index 0953b7b16a51b..097c4204ffae4 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -879,6 +879,9 @@ drm_atomic_get_new_mst_topology_state(struct drm_atomic_state *state,
struct drm_dp_mst_atomic_payload *
drm_atomic_get_mst_payload_state(struct drm_dp_mst_topology_state *state,
struct drm_dp_mst_port *port);
+bool drm_dp_mst_port_downstream_of_parent(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_mst_port *parent);
int __must_check
drm_dp_atomic_find_time_slots(struct drm_atomic_state *state,
struct drm_dp_mst_topology_mgr *mgr,
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [PATCH 12/17] drm/dp_mst: Factor out a helper to check the atomic state of a topology manager
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
@ 2023-08-17 16:14 ` Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 02/17] drm/i915/dp: Track the pipe and link bpp limits separately Imre Deak
` (19 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Factor out a helper to check the atomic state for one MST topology
manager, returning the MST port where the BW limit check has failed.
This will be used in a follow-up patch by the i915 driver to improve the
BW sharing between MST streams.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 94 +++++++++++++++----
include/drm/display/drm_dp_mst_helper.h | 4 +
2 files changed, 79 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index ced9ae36a9177..a32da72bb05c5 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5159,11 +5159,13 @@ EXPORT_SYMBOL(drm_dp_mst_port_downstream_of_parent);
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
- struct drm_dp_mst_topology_state *state);
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port);
static int
drm_dp_mst_atomic_check_mstb_bw_limit(struct drm_dp_mst_branch *mstb,
- struct drm_dp_mst_topology_state *state)
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port)
{
struct drm_dp_mst_atomic_payload *payload;
struct drm_dp_mst_port *port;
@@ -5192,7 +5194,7 @@ drm_dp_mst_atomic_check_mstb_bw_limit(struct drm_dp_mst_branch *mstb,
drm_dbg_atomic(mstb->mgr->dev, "[MSTB:%p] Checking bandwidth limits\n", mstb);
list_for_each_entry(port, &mstb->ports, next) {
- ret = drm_dp_mst_atomic_check_port_bw_limit(port, state);
+ ret = drm_dp_mst_atomic_check_port_bw_limit(port, state, failing_port);
if (ret < 0)
return ret;
@@ -5204,7 +5206,8 @@ drm_dp_mst_atomic_check_mstb_bw_limit(struct drm_dp_mst_branch *mstb,
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
- struct drm_dp_mst_topology_state *state)
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port)
{
struct drm_dp_mst_atomic_payload *payload;
int pbn_used = 0;
@@ -5225,13 +5228,15 @@ drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
drm_dbg_atomic(port->mgr->dev,
"[MSTB:%p] [MST PORT:%p] no BW available for the port\n",
port->parent, port);
+ *failing_port = port;
return -EINVAL;
}
pbn_used = payload->pbn;
} else {
pbn_used = drm_dp_mst_atomic_check_mstb_bw_limit(port->mstb,
- state);
+ state,
+ failing_port);
if (pbn_used <= 0)
return pbn_used;
}
@@ -5240,6 +5245,7 @@ drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
drm_dbg_atomic(port->mgr->dev,
"[MSTB:%p] [MST PORT:%p] required PBN of %d exceeds port limit of %d\n",
port->parent, port, pbn_used, port->full_pbn);
+ *failing_port = port;
return -ENOSPC;
}
@@ -5417,20 +5423,80 @@ int drm_dp_mst_atomic_enable_dsc(struct drm_atomic_state *state,
}
EXPORT_SYMBOL(drm_dp_mst_atomic_enable_dsc);
+/**
+ * drm_dp_mst_atomic_check_mgr - Check the atomic state of an MST topology manager
+ * @state: The global atomic state
+ * @mgr: Manager to check
+ * @mst_state: The MST atomic state for @mgr
+ * @failing_port: Returns the port with a BW limitation
+ *
+ * Checks the given MST manager's topology state for an atomic update to ensure
+ * that it's valid. This includes checking whether there's enough bandwidth to
+ * support the new timeslot allocations in the atomic update.
+ *
+ * Any atomic drivers supporting DP MST must make sure to call this or
+ * the drm_dp_mst_atomic_check() function after checking the rest of their state
+ * in their &drm_mode_config_funcs.atomic_check() callback.
+ *
+ * See also:
+ * drm_dp_mst_atomic_check()
+ * drm_dp_atomic_find_time_slots()
+ * drm_dp_atomic_release_time_slots()
+ *
+ * Returns:
+ *
+ * 0 if the new state is valid
+ * %-ENOSPC, if the new state is invalid, because of BW limitation
+ * @failing_port is set to:
+ * - The non-root port where a BW limit check failed
+ * The returned port pointer is valid until at least
+ * one payload downstream of it exists.
+ * - %NULL if the BW limit check failed at the root port
+ * %-EINVAL, if the new state is invalid, because the root port has too many
+ * payloads.
+ */
+int drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_topology_state *mst_state,
+ struct drm_dp_mst_port **failing_port)
+{
+ int ret;
+
+ *failing_port = NULL;
+
+ if (!mgr->mst_state)
+ return 0;
+
+ ret = drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
+ if (ret)
+ return ret;
+
+ mutex_lock(&mgr->lock);
+ ret = drm_dp_mst_atomic_check_mstb_bw_limit(mgr->mst_primary,
+ mst_state,
+ failing_port);
+ mutex_unlock(&mgr->lock);
+
+ return ret < 0 ? ret : 0;
+}
+EXPORT_SYMBOL(drm_dp_mst_atomic_check_mgr);
+
/**
* drm_dp_mst_atomic_check - Check that the new state of an MST topology in an
* atomic update is valid
* @state: Pointer to the new &struct drm_dp_mst_topology_state
*
* Checks the given topology state for an atomic update to ensure that it's
- * valid. This includes checking whether there's enough bandwidth to support
- * the new timeslot allocations in the atomic update.
+ * valid, calling drm_dp_mst_atomic_check_mgr() for all MST manager in the
+ * atomic state. This includes checking whether there's enough bandwidth to
+ * support the new timeslot allocations in the atomic update.
*
* Any atomic drivers supporting DP MST must make sure to call this after
* checking the rest of their state in their
* &drm_mode_config_funcs.atomic_check() callback.
*
* See also:
+ * drm_dp_mst_atomic_check_mgr()
* drm_dp_atomic_find_time_slots()
* drm_dp_atomic_release_time_slots()
*
@@ -5445,21 +5511,11 @@ int drm_dp_mst_atomic_check(struct drm_atomic_state *state)
int i, ret = 0;
for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
- if (!mgr->mst_state)
- continue;
+ struct drm_dp_mst_port *tmp_port;
- ret = drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
+ ret = drm_dp_mst_atomic_check_mgr(state, mgr, mst_state, &tmp_port);
if (ret)
break;
-
- mutex_lock(&mgr->lock);
- ret = drm_dp_mst_atomic_check_mstb_bw_limit(mgr->mst_primary,
- mst_state);
- mutex_unlock(&mgr->lock);
- if (ret < 0)
- break;
- else
- ret = 0;
}
return ret;
diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
index 097c4204ffae4..0bbc9b0178f9b 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -903,6 +903,10 @@ int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr,
int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_port *port,
struct drm_dp_query_stream_enc_status_ack_reply *status);
+int __must_check drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_topology_state *mst_state,
+ struct drm_dp_mst_port **failing_port);
int __must_check drm_dp_mst_atomic_check(struct drm_atomic_state *state);
int __must_check drm_dp_mst_root_conn_atomic_check(struct drm_connector_state *new_conn_state,
struct drm_dp_mst_topology_mgr *mgr);
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 12/17] drm/dp_mst: Factor out a helper to check the atomic state of a topology manager
@ 2023-08-17 16:14 ` Imre Deak
0 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Factor out a helper to check the atomic state for one MST topology
manager, returning the MST port where the BW limit check has failed.
This will be used in a follow-up patch by the i915 driver to improve the
BW sharing between MST streams.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 94 +++++++++++++++----
include/drm/display/drm_dp_mst_helper.h | 4 +
2 files changed, 79 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index ced9ae36a9177..a32da72bb05c5 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5159,11 +5159,13 @@ EXPORT_SYMBOL(drm_dp_mst_port_downstream_of_parent);
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
- struct drm_dp_mst_topology_state *state);
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port);
static int
drm_dp_mst_atomic_check_mstb_bw_limit(struct drm_dp_mst_branch *mstb,
- struct drm_dp_mst_topology_state *state)
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port)
{
struct drm_dp_mst_atomic_payload *payload;
struct drm_dp_mst_port *port;
@@ -5192,7 +5194,7 @@ drm_dp_mst_atomic_check_mstb_bw_limit(struct drm_dp_mst_branch *mstb,
drm_dbg_atomic(mstb->mgr->dev, "[MSTB:%p] Checking bandwidth limits\n", mstb);
list_for_each_entry(port, &mstb->ports, next) {
- ret = drm_dp_mst_atomic_check_port_bw_limit(port, state);
+ ret = drm_dp_mst_atomic_check_port_bw_limit(port, state, failing_port);
if (ret < 0)
return ret;
@@ -5204,7 +5206,8 @@ drm_dp_mst_atomic_check_mstb_bw_limit(struct drm_dp_mst_branch *mstb,
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
- struct drm_dp_mst_topology_state *state)
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port)
{
struct drm_dp_mst_atomic_payload *payload;
int pbn_used = 0;
@@ -5225,13 +5228,15 @@ drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
drm_dbg_atomic(port->mgr->dev,
"[MSTB:%p] [MST PORT:%p] no BW available for the port\n",
port->parent, port);
+ *failing_port = port;
return -EINVAL;
}
pbn_used = payload->pbn;
} else {
pbn_used = drm_dp_mst_atomic_check_mstb_bw_limit(port->mstb,
- state);
+ state,
+ failing_port);
if (pbn_used <= 0)
return pbn_used;
}
@@ -5240,6 +5245,7 @@ drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
drm_dbg_atomic(port->mgr->dev,
"[MSTB:%p] [MST PORT:%p] required PBN of %d exceeds port limit of %d\n",
port->parent, port, pbn_used, port->full_pbn);
+ *failing_port = port;
return -ENOSPC;
}
@@ -5417,20 +5423,80 @@ int drm_dp_mst_atomic_enable_dsc(struct drm_atomic_state *state,
}
EXPORT_SYMBOL(drm_dp_mst_atomic_enable_dsc);
+/**
+ * drm_dp_mst_atomic_check_mgr - Check the atomic state of an MST topology manager
+ * @state: The global atomic state
+ * @mgr: Manager to check
+ * @mst_state: The MST atomic state for @mgr
+ * @failing_port: Returns the port with a BW limitation
+ *
+ * Checks the given MST manager's topology state for an atomic update to ensure
+ * that it's valid. This includes checking whether there's enough bandwidth to
+ * support the new timeslot allocations in the atomic update.
+ *
+ * Any atomic drivers supporting DP MST must make sure to call this or
+ * the drm_dp_mst_atomic_check() function after checking the rest of their state
+ * in their &drm_mode_config_funcs.atomic_check() callback.
+ *
+ * See also:
+ * drm_dp_mst_atomic_check()
+ * drm_dp_atomic_find_time_slots()
+ * drm_dp_atomic_release_time_slots()
+ *
+ * Returns:
+ *
+ * 0 if the new state is valid
+ * %-ENOSPC, if the new state is invalid, because of BW limitation
+ * @failing_port is set to:
+ * - The non-root port where a BW limit check failed
+ * The returned port pointer is valid until at least
+ * one payload downstream of it exists.
+ * - %NULL if the BW limit check failed at the root port
+ * %-EINVAL, if the new state is invalid, because the root port has too many
+ * payloads.
+ */
+int drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_topology_state *mst_state,
+ struct drm_dp_mst_port **failing_port)
+{
+ int ret;
+
+ *failing_port = NULL;
+
+ if (!mgr->mst_state)
+ return 0;
+
+ ret = drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
+ if (ret)
+ return ret;
+
+ mutex_lock(&mgr->lock);
+ ret = drm_dp_mst_atomic_check_mstb_bw_limit(mgr->mst_primary,
+ mst_state,
+ failing_port);
+ mutex_unlock(&mgr->lock);
+
+ return ret < 0 ? ret : 0;
+}
+EXPORT_SYMBOL(drm_dp_mst_atomic_check_mgr);
+
/**
* drm_dp_mst_atomic_check - Check that the new state of an MST topology in an
* atomic update is valid
* @state: Pointer to the new &struct drm_dp_mst_topology_state
*
* Checks the given topology state for an atomic update to ensure that it's
- * valid. This includes checking whether there's enough bandwidth to support
- * the new timeslot allocations in the atomic update.
+ * valid, calling drm_dp_mst_atomic_check_mgr() for all MST manager in the
+ * atomic state. This includes checking whether there's enough bandwidth to
+ * support the new timeslot allocations in the atomic update.
*
* Any atomic drivers supporting DP MST must make sure to call this after
* checking the rest of their state in their
* &drm_mode_config_funcs.atomic_check() callback.
*
* See also:
+ * drm_dp_mst_atomic_check_mgr()
* drm_dp_atomic_find_time_slots()
* drm_dp_atomic_release_time_slots()
*
@@ -5445,21 +5511,11 @@ int drm_dp_mst_atomic_check(struct drm_atomic_state *state)
int i, ret = 0;
for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
- if (!mgr->mst_state)
- continue;
+ struct drm_dp_mst_port *tmp_port;
- ret = drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
+ ret = drm_dp_mst_atomic_check_mgr(state, mgr, mst_state, &tmp_port);
if (ret)
break;
-
- mutex_lock(&mgr->lock);
- ret = drm_dp_mst_atomic_check_mstb_bw_limit(mgr->mst_primary,
- mst_state);
- mutex_unlock(&mgr->lock);
- if (ret < 0)
- break;
- else
- ret = 0;
}
return ret;
diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
index 097c4204ffae4..0bbc9b0178f9b 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -903,6 +903,10 @@ int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr,
int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_port *port,
struct drm_dp_query_stream_enc_status_ack_reply *status);
+int __must_check drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_topology_state *mst_state,
+ struct drm_dp_mst_port **failing_port);
int __must_check drm_dp_mst_atomic_check(struct drm_atomic_state *state);
int __must_check drm_dp_mst_root_conn_atomic_check(struct drm_connector_state *new_conn_state,
struct drm_dp_mst_topology_mgr *mgr);
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [PATCH 13/17] drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
@ 2023-08-17 16:14 ` Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 02/17] drm/i915/dp: Track the pipe and link bpp limits separately Imre Deak
` (19 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
drm_dp_mst_atomic_check_mgr() should check for BW limitation starting
from sink ports continuing towards the root port, so that drivers can
use the @failing_port returned to resolve a BW overallocation in an
ideal way. For instance from streams A,B,C in a topology A,B going
through @failing_port and C not going through it, a BW overallocation of
A,B due to a limit of the port must be resolved first before considering
the limits of other ports closer to the root port. This way can avoid
reducing the BW of stream C unnecessarily due to a BW limit closer to the
root port.
Based on the above swap the order of the BW check for the root port and
the check for all the ports downstream of it (the latter going through
the topology already in the sink->root port direction).
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index a32da72bb05c5..12a13885145d3 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5449,9 +5449,13 @@ EXPORT_SYMBOL(drm_dp_mst_atomic_enable_dsc);
* %-ENOSPC, if the new state is invalid, because of BW limitation
* @failing_port is set to:
* - The non-root port where a BW limit check failed
+ * with all the ports downstream of @failing_port passing
+ * the BW limit check.
* The returned port pointer is valid until at least
* one payload downstream of it exists.
* - %NULL if the BW limit check failed at the root port
+ * with all the ports downstream of the root port passing
+ * the BW limit check.
* %-EINVAL, if the new state is invalid, because the root port has too many
* payloads.
*/
@@ -5467,17 +5471,16 @@ int drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state,
if (!mgr->mst_state)
return 0;
- ret = drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
- if (ret)
- return ret;
-
mutex_lock(&mgr->lock);
ret = drm_dp_mst_atomic_check_mstb_bw_limit(mgr->mst_primary,
mst_state,
failing_port);
mutex_unlock(&mgr->lock);
- return ret < 0 ? ret : 0;
+ if (ret < 0)
+ return ret;
+
+ return drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
}
EXPORT_SYMBOL(drm_dp_mst_atomic_check_mgr);
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 13/17] drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations
@ 2023-08-17 16:14 ` Imre Deak
0 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
drm_dp_mst_atomic_check_mgr() should check for BW limitation starting
from sink ports continuing towards the root port, so that drivers can
use the @failing_port returned to resolve a BW overallocation in an
ideal way. For instance from streams A,B,C in a topology A,B going
through @failing_port and C not going through it, a BW overallocation of
A,B due to a limit of the port must be resolved first before considering
the limits of other ports closer to the root port. This way can avoid
reducing the BW of stream C unnecessarily due to a BW limit closer to the
root port.
Based on the above swap the order of the BW check for the root port and
the check for all the ports downstream of it (the latter going through
the topology already in the sink->root port direction).
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index a32da72bb05c5..12a13885145d3 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5449,9 +5449,13 @@ EXPORT_SYMBOL(drm_dp_mst_atomic_enable_dsc);
* %-ENOSPC, if the new state is invalid, because of BW limitation
* @failing_port is set to:
* - The non-root port where a BW limit check failed
+ * with all the ports downstream of @failing_port passing
+ * the BW limit check.
* The returned port pointer is valid until at least
* one payload downstream of it exists.
* - %NULL if the BW limit check failed at the root port
+ * with all the ports downstream of the root port passing
+ * the BW limit check.
* %-EINVAL, if the new state is invalid, because the root port has too many
* payloads.
*/
@@ -5467,17 +5471,16 @@ int drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state,
if (!mgr->mst_state)
return 0;
- ret = drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
- if (ret)
- return ret;
-
mutex_lock(&mgr->lock);
ret = drm_dp_mst_atomic_check_mstb_bw_limit(mgr->mst_primary,
mst_state,
failing_port);
mutex_unlock(&mgr->lock);
- return ret < 0 ? ret : 0;
+ if (ret < 0)
+ return ret;
+
+ return drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
}
EXPORT_SYMBOL(drm_dp_mst_atomic_check_mgr);
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [PATCH 14/17] drm/i915/dp_mst: Fix PBN calculation with FEC overhead
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
` (12 preceding siblings ...)
2023-08-17 16:14 ` Imre Deak
@ 2023-08-17 16:14 ` Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 15/17] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms Imre Deak
` (6 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx
On 8b/10b MST links the PBN value for DSC streams must be calculated
accounting for the FEC overhead. The same applies to 8b/10b non-DSC
streams if there is another DSC stream on the same link. Fix up the PBN
calculation accordingly.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index b22e0cbdb7d56..4fe10d7256630 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -111,7 +111,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
dsc ? bpp << 4 : bpp,
dsc,
- false);
+ (dsc || crtc_state->fec_enable) &&
+ !intel_dp_is_uhbr(crtc_state));
slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
connector->port,
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread* [Intel-gfx] [PATCH 15/17] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
` (13 preceding siblings ...)
2023-08-17 16:14 ` [Intel-gfx] [PATCH 14/17] drm/i915/dp_mst: Fix PBN calculation with FEC overhead Imre Deak
@ 2023-08-17 16:14 ` Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 16/17] drm/i915/dp_mst: Improve BW sharing between MST streams Imre Deak
` (5 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx
If an MST stream is modeset, its state must be checked along all the
other streams on the same MST link, for instance to resolve a BW
overallocation of a non-sink MST port or to make sure that the FEC is
enabled/disabled the same way for all these streams.
To prepare for that this patch adds all the stream CRTCs to the atomic
state and marks them for modeset similarly to tgl+ platforms. (If the
state computation doesn't change the state the CRTC is switched back to
fastset mode.)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 4fe10d7256630..b53254473e0d9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -499,9 +499,6 @@ intel_dp_mst_atomic_master_trans_check(struct intel_connector *connector,
struct intel_connector *connector_iter;
int ret = 0;
- if (DISPLAY_VER(dev_priv) < 12)
- return 0;
-
if (!intel_connector_needs_modeset(state, &connector->base))
return 0;
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread* [Intel-gfx] [PATCH 16/17] drm/i915/dp_mst: Improve BW sharing between MST streams
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
` (14 preceding siblings ...)
2023-08-17 16:14 ` [Intel-gfx] [PATCH 15/17] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms Imre Deak
@ 2023-08-17 16:14 ` Imre Deak
2023-08-17 16:14 ` [Intel-gfx] [PATCH 17/17] drm/i915/dp_mst: Check BW limitations only when all streams are computed Imre Deak
` (4 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx
At the moment modesetting a stream CRTC will fail if the stream's BW
along with the current BW of all the other streams on the same MST link
is above the total BW of the MST link. Make the BW sharing more dynamic
by trying to reduce the link bpp of one or more streams on the MST link
in this case.
When selecting a stream to reduce the BW for, take into account which
link segment in the MST topology ran out of BW and which streams go
through this link segment. For instance with A,B,C streams in the same
MST topology A and B may share the BW of a link segment downstream of a
branch device, stream C not downstream of the branch device, hence not
affecting this BW. If this link segment's BW runs out one or both of
stream A/B's BW will be reduced until their total BW is within limits.
While reducing the link bpp for a given stream DSC may need to be
enabled for it, which requires FEC on the whole MST link. Check for this
condition and recompute the state for all streams taking the FEC
overhead into account (on 8b/10b links).
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 14 ++-
drivers/gpu/drm/i915/display/intel_display.c | 5 +-
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 13 ++-
drivers/gpu/drm/i915/display/intel_dp.h | 2 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 105 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp_mst.h | 3 +
7 files changed, 133 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 8e55eb3b2cee0..9c6bd522c43af 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -38,6 +38,7 @@
#include "intel_atomic.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
+#include "intel_dp_mst.h"
#include "intel_fdi.h"
#include "intel_global_state.h"
#include "intel_hdcp.h"
@@ -456,7 +457,7 @@ static int intel_atomic_check_link(struct intel_atomic_state *state,
if (ret)
return ret;
- return 0;
+ return intel_dp_mst_atomic_check_link(state, limits);
}
static bool
@@ -467,6 +468,12 @@ assert_link_limit_change_valid(struct drm_i915_private *i915,
bool bpps_changed = false;
enum pipe pipe;
+ /* FEC can't be forced off after it was forced on. */
+ if (drm_WARN_ON(&i915->drm,
+ (old_limits->force_fec_pipes & new_limits->force_fec_pipes) !=
+ old_limits->force_fec_pipes))
+ return false;
+
for_each_pipe(i915, pipe) {
/* The bpp limit can only decrease. */
if (drm_WARN_ON(&i915->drm,
@@ -479,8 +486,11 @@ assert_link_limit_change_valid(struct drm_i915_private *i915,
bpps_changed = true;
}
+ /* At least one limit must change. */
if (drm_WARN_ON(&i915->drm,
- !bpps_changed))
+ !bpps_changed &&
+ new_limits->force_fec_pipes ==
+ old_limits->force_fec_pipes))
return false;
return true;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index de2152c94c161..60180ba4b9981 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4673,6 +4673,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
if (ret)
return ret;
+ crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);
crtc_state->max_link_bpp = limits->max_bpp[crtc->pipe];
if (crtc_state->pipe_bpp > crtc_state->max_link_bpp >> 4) {
@@ -6351,10 +6352,6 @@ int intel_atomic_check(struct drm_device *dev,
goto fail;
}
- ret = drm_dp_mst_atomic_check(&state->base);
- if (ret)
- goto fail;
-
ret = intel_atomic_check_planes(state);
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index aa17ac64273a9..227a549b553b7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -67,6 +67,7 @@ struct intel_tc_port;
*/
struct intel_link_bw_limits {
+ u8 force_fec_pipes;
u8 min_bpp_pipes;
/* in 1/16 bpp units */
int max_bpp[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e85a6f89ca9e3..407b2f24aca80 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1318,8 +1318,8 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
return false;
}
-static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
- const struct intel_crtc_state *pipe_config)
+bool intel_dp_supports_fec(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *pipe_config)
{
return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
drm_dp_sink_supports_fec(intel_dp->fec_capable);
@@ -1667,8 +1667,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
int pipe_bpp;
int ret;
- pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
- intel_dp_supports_fec(intel_dp, pipe_config);
+ pipe_config->fec_enable = pipe_config->fec_enable ||
+ (!intel_dp_is_edp(intel_dp) &&
+ intel_dp_supports_fec(intel_dp, pipe_config));
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
@@ -1918,6 +1919,10 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
bool dsc_needed;
int ret = 0;
+ if (pipe_config->fec_enable &&
+ !intel_dp_supports_fec(intel_dp, pipe_config))
+ return -EINVAL;
+
if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
adjusted_mode->crtc_clock))
pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 22c18310ae47d..3ada941547bf9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -131,6 +131,8 @@ static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
return ~((1 << lane_count) - 1) & 0xf;
}
+bool intel_dp_supports_fec(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *pipe_config);
u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index b53254473e0d9..686ce61e16f8d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -358,6 +358,10 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
bool dsc_needed;
int ret = 0;
+ if (pipe_config->fec_enable &&
+ !intel_dp_supports_fec(intel_dp, pipe_config))
+ return -EINVAL;
+
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
@@ -469,6 +473,107 @@ intel_dp_mst_transcoder_mask(struct intel_atomic_state *state,
return transcoders;
}
+static u8 get_pipes_downstream_of_mst_port(struct intel_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mst_mgr,
+ struct drm_dp_mst_port *parent_port)
+{
+ const struct intel_digital_connector_state *conn_state;
+ struct intel_connector *connector;
+ u8 mask = 0;
+ int i;
+
+ for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
+ if (!conn_state->base.crtc)
+ continue;
+
+ if (&connector->mst_port->mst_mgr != mst_mgr)
+ continue;
+
+ if (connector->port != parent_port &&
+ !drm_dp_mst_port_downstream_of_parent(mst_mgr,
+ connector->port,
+ parent_port))
+ continue;
+
+ mask |= BIT(to_intel_crtc(conn_state->base.crtc)->pipe);
+ }
+
+ return mask;
+}
+
+static int intel_dp_mst_check_fec_change(struct intel_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mst_mgr,
+ struct intel_link_bw_limits *limits)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+ u8 mst_pipe_mask;
+ u8 fec_pipe_mask = 0;
+ int ret;
+
+ mst_pipe_mask = get_pipes_downstream_of_mst_port(state, mst_mgr, NULL);
+
+ for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mst_pipe_mask) {
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (crtc_state->fec_enable)
+ fec_pipe_mask |= BIT(crtc->pipe);
+ }
+
+ if (!fec_pipe_mask || mst_pipe_mask == fec_pipe_mask)
+ return 0;
+
+ limits->force_fec_pipes |= mst_pipe_mask;
+ ret = intel_modeset_pipes_in_mask(state, "MST FEC",
+ mst_pipe_mask);
+
+ return ret ? : -EAGAIN;
+}
+
+static int intel_dp_mst_check_bw(struct intel_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mst_mgr,
+ struct drm_dp_mst_topology_state *mst_state,
+ struct intel_link_bw_limits *limits)
+{
+ struct drm_dp_mst_port *mst_port;
+ u8 mst_port_pipes;
+ int ret;
+
+ ret = drm_dp_mst_atomic_check_mgr(&state->base, mst_mgr, mst_state, &mst_port);
+ if (ret != -ENOSPC)
+ return ret;
+
+ mst_port_pipes = get_pipes_downstream_of_mst_port(state, mst_mgr, mst_port);
+
+ ret = intel_atomic_reduce_link_bpp(state, limits,
+ mst_port_pipes, "MST link BW");
+
+ return ret ? : -EAGAIN;
+}
+
+int intel_dp_mst_atomic_check_link(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits)
+{
+ struct drm_dp_mst_topology_mgr *mgr;
+ struct drm_dp_mst_topology_state *mst_state;
+ int ret;
+ int i;
+
+ for_each_new_mst_mgr_in_state(&state->base, mgr, mst_state, i) {
+ ret = intel_dp_mst_check_fec_change(state, mgr, limits);
+ if (ret)
+ return ret;
+
+ ret = intel_dp_mst_check_bw(state, mgr, mst_state,
+ limits);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h
index f1815bb722672..4e836b9ac6061 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h
@@ -13,6 +13,7 @@ struct intel_crtc;
struct intel_crtc_state;
struct intel_digital_port;
struct intel_dp;
+struct intel_link_bw_limits;
int intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_id);
void intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port);
@@ -22,5 +23,7 @@ bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state);
bool intel_dp_mst_source_support(struct intel_dp *intel_dp);
int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state,
struct intel_crtc *crtc);
+int intel_dp_mst_atomic_check_link(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits);
#endif /* __INTEL_DP_MST_H__ */
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread* [Intel-gfx] [PATCH 17/17] drm/i915/dp_mst: Check BW limitations only when all streams are computed
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
` (15 preceding siblings ...)
2023-08-17 16:14 ` [Intel-gfx] [PATCH 16/17] drm/i915/dp_mst: Improve BW sharing between MST streams Imre Deak
@ 2023-08-17 16:14 ` Imre Deak
2023-08-18 1:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on shared display links Patchwork
` (3 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2023-08-17 16:14 UTC (permalink / raw)
To: intel-gfx
After the previous patch the BW limits on the whole MST topology will be
checked after computing the state for all the streams in the topology.
Accordingly remove the check during the stream's encoder compute config
step, to prevent failing an atomic commit due to a BW limit, if this can
be resolved only by reducing the BW of other streams on the same MST
link.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 686ce61e16f8d..35a9bccd68d9b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -120,15 +120,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
if (slots == -EDEADLK)
return slots;
- if (slots >= 0) {
- ret = drm_dp_mst_atomic_check(state);
- /*
- * If we got slots >= 0 and we can fit those based on check
- * then we can exit the loop. Otherwise keep trying.
- */
- if (!ret)
- break;
- }
+ if (slots >= 0)
+ break;
}
/* We failed to find a proper bpp/timeslots, return error */
--
2.37.2
^ permalink raw reply related [flat|nested] 31+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on shared display links
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
` (16 preceding siblings ...)
2023-08-17 16:14 ` [Intel-gfx] [PATCH 17/17] drm/i915/dp_mst: Check BW limitations only when all streams are computed Imre Deak
@ 2023-08-18 1:33 ` Patchwork
2023-08-18 1:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2023-08-18 1:33 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Improve BW management on shared display links
URL : https://patchwork.freedesktop.org/series/122589/
State : warning
== Summary ==
Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
^ permalink raw reply [flat|nested] 31+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Improve BW management on shared display links
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
` (17 preceding siblings ...)
2023-08-18 1:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on shared display links Patchwork
@ 2023-08-18 1:33 ` Patchwork
2023-08-18 1:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-08-19 2:20 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
20 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2023-08-18 1:33 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Improve BW management on shared display links
URL : https://patchwork.freedesktop.org/series/122589/
State : warning
== Summary ==
Error: dim sparse failed
/home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
^ permalink raw reply [flat|nested] 31+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Improve BW management on shared display links
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
` (18 preceding siblings ...)
2023-08-18 1:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-08-18 1:49 ` Patchwork
2023-08-19 2:20 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
20 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2023-08-18 1:49 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5534 bytes --]
== Series Details ==
Series: drm/i915: Improve BW management on shared display links
URL : https://patchwork.freedesktop.org/series/122589/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13534 -> Patchwork_122589v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/index.html
Participating hosts (39 -> 38)
------------------------------
Additional (1): fi-kbl-soraka
Missing (2): fi-snb-2520m fi-pnv-d510
Known issues
------------
Here are the changes found in Patchwork_122589v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s0@smem:
- bat-jsl-3: [PASS][1] -> [ABORT][2] ([i915#5122])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/bat-jsl-3/igt@gem_exec_suspend@basic-s0@smem.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/bat-jsl-3/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][5] ([i915#5334] / [i915#7872])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][6] ([i915#1886] / [i915#7913])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-jsl-3: [PASS][7] -> [FAIL][8] ([fdo#103375])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/bat-jsl-3/igt@i915_suspend@basic-s3-without-i915.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/bat-jsl-3/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271]) +8 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/fi-kbl-soraka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
#### Possible fixes ####
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [DMESG-WARN][10] ([i915#7699]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/bat-dg2-11/igt@i915_selftest@live@migrate.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/bat-dg2-11/igt@i915_selftest@live@migrate.html
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
Build changes
-------------
* Linux: CI_DRM_13534 -> Patchwork_122589v1
CI-20190529: 20190529
CI_DRM_13534: 2c5542cb377b2e9e15c1f84a6e78a3d6fca47ea0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7443: 953448dbf2e63918a8eced9707f65fc0a19a9c85 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_122589v1: 2c5542cb377b2e9e15c1f84a6e78a3d6fca47ea0 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
8069a55b8868 drm/i915/dp_mst: Check BW limitations only when all streams are computed
800890e956a2 drm/i915/dp_mst: Improve BW sharing between MST streams
b9f1572b49fe drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms
665d48335aab drm/i915/dp_mst: Fix PBN calculation with FEC overhead
54bfdbc5f57c drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations
1c549d40f2fa drm/dp_mst: Factor out a helper to check the atomic state of a topology manager
2a9aec3381b1 drm/dp_mst: Add helper to determine if an MST port is downstream of another port
13020ea3d646 drm/dp_mst: Add a way to calculate PBN values with FEC overhead
46faa49e6bb9 drm/dp_mst: Fix fractional bpp scaling in drm_dp_calc_pbn_mode()
bfbf761d450f drm/i915/fdi: Improve FDI BW sharing between pipe B and C
924e8e5a72aa drm/i915: Factor out a helper to check/compute all the CRTC states
a5bd9fb2d19c drm/i915: Add helper to modeset a set of pipes
0c20239cc145 drm/i915/dp: Limit the output link bpp in DSC mode
c176068a0c48 drm/i915/dp: Update the link bpp limits for DSC mode
453e785e3f91 drm/i915/dp: Skip computing a non-DSC link config if DSC is needed
a524caa1992f drm/i915/dp: Track the pipe and link bpp limits separately
d9abbb5a4074 drm/i915/dp: Factor out helpers to compute the link limits
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/index.html
[-- Attachment #2: Type: text/html, Size: 6551 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Improve BW management on shared display links
2023-08-17 16:14 [Intel-gfx] [PATCH 00/17] drm/i915: Improve BW management on shared display links Imre Deak
` (19 preceding siblings ...)
2023-08-18 1:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-08-19 2:20 ` Patchwork
20 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2023-08-19 2:20 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 53157 bytes --]
== Series Details ==
Series: drm/i915: Improve BW management on shared display links
URL : https://patchwork.freedesktop.org/series/122589/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13534_full -> Patchwork_122589v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_122589v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_122589v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/index.html
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_122589v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rc6_residency@rc6-idle@rcs0:
- shard-snb: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-snb1/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-snb2/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
* igt@kms_plane_lowres@tiling-x@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [ABORT][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-rkl-7/igt@kms_plane_lowres@tiling-x@pipe-a-hdmi-a-1.html
Known issues
------------
Here are the changes found in Patchwork_122589v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@object-reloc-purge-cache:
- shard-mtlp: NOTRUN -> [SKIP][4] ([i915#8411])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@api_intel_bb@object-reloc-purge-cache.html
* igt@device_reset@cold-reset-bound:
- shard-mtlp: NOTRUN -> [SKIP][5] ([i915#7701])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@device_reset@cold-reset-bound.html
* igt@drm_fdinfo@busy-check-all@ccs0:
- shard-mtlp: NOTRUN -> [SKIP][6] ([i915#8414]) +5 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@drm_fdinfo@busy-check-all@ccs0.html
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [PASS][7] -> [FAIL][8] ([i915#7742])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-rkl-7/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@drm_fdinfo@virtual-busy-all:
- shard-dg2: NOTRUN -> [SKIP][9] ([i915#8414])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@drm_fdinfo@virtual-busy-all.html
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-snb: NOTRUN -> [DMESG-WARN][10] ([i915#8841]) +4 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-snb4/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_ctx_isolation@preservation-s3@vcs1:
- shard-dg2: [PASS][11] -> [FAIL][12] ([fdo#103375])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-dg2-6/igt@gem_ctx_isolation@preservation-s3@vcs1.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-11/igt@gem_ctx_isolation@preservation-s3@vcs1.html
* igt@gem_ctx_persistence@heartbeat-hang:
- shard-dg2: NOTRUN -> [SKIP][13] ([i915#8555])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@gem_ctx_persistence@heartbeat-hang.html
* igt@gem_ctx_persistence@processes:
- shard-snb: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1099]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-snb1/igt@gem_ctx_persistence@processes.html
* igt@gem_eio@reset-stress:
- shard-snb: NOTRUN -> [FAIL][15] ([i915#8898])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-snb1/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@sliced:
- shard-mtlp: NOTRUN -> [SKIP][16] ([i915#4812])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@gem_exec_balancer@sliced.html
* igt@gem_exec_capture@pi@ccs0:
- shard-mtlp: [PASS][17] -> [FAIL][18] ([i915#7765])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-mtlp-4/igt@gem_exec_capture@pi@ccs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@gem_exec_capture@pi@ccs0.html
* igt@gem_exec_capture@pi@rcs0:
- shard-mtlp: [PASS][19] -> [FAIL][20] ([i915#4475])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-mtlp-4/igt@gem_exec_capture@pi@rcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@gem_exec_capture@pi@rcs0.html
* igt@gem_exec_capture@pi@vcs1:
- shard-mtlp: [PASS][21] -> [FAIL][22] ([i915#4475] / [i915#7765])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-mtlp-4/igt@gem_exec_capture@pi@vcs1.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@gem_exec_capture@pi@vcs1.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-rkl: [PASS][23] -> [FAIL][24] ([i915#2842])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-rkl-2/igt@gem_exec_fair@basic-none@vecs0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-rkl-7/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl: [PASS][25] -> [FAIL][26] ([i915#2842])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-apl1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-apl2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [PASS][27] -> [FAIL][28] ([i915#2842])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-glk2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-glk4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fence@parallel@vcs0:
- shard-mtlp: NOTRUN -> [DMESG-FAIL][29] ([i915#9121])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-4/igt@gem_exec_fence@parallel@vcs0.html
* igt@gem_exec_fence@parallel@vecs0:
- shard-mtlp: NOTRUN -> [FAIL][30] ([i915#8957]) +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-4/igt@gem_exec_fence@parallel@vecs0.html
* igt@gem_exec_fence@submit67:
- shard-dg2: NOTRUN -> [SKIP][31] ([i915#4812])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@gem_exec_fence@submit67.html
* igt@gem_exec_flush@basic-wb-rw-before-default:
- shard-dg2: NOTRUN -> [SKIP][32] ([i915#3539] / [i915#4852]) +3 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@gem_exec_flush@basic-wb-rw-before-default.html
* igt@gem_exec_reloc@basic-cpu-wc-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][33] ([i915#3281]) +5 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@gem_exec_reloc@basic-cpu-wc-noreloc.html
* igt@gem_exec_reloc@basic-gtt-cpu-active:
- shard-dg2: NOTRUN -> [SKIP][34] ([i915#3281]) +6 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@gem_exec_reloc@basic-gtt-cpu-active.html
* igt@gem_fence_thrash@bo-copy:
- shard-dg2: NOTRUN -> [SKIP][35] ([i915#4860]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@gem_fence_thrash@bo-copy.html
* igt@gem_lmem_swapping@heavy-random:
- shard-mtlp: NOTRUN -> [SKIP][36] ([i915#4613]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-5/igt@gem_lmem_swapping@heavy-random.html
* igt@gem_media_vme:
- shard-dg2: NOTRUN -> [SKIP][37] ([i915#284])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-11/igt@gem_media_vme.html
* igt@gem_mmap_gtt@big-bo-tiledy:
- shard-mtlp: NOTRUN -> [SKIP][38] ([i915#4077]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@gem_mmap_gtt@big-bo-tiledy.html
* igt@gem_mmap_wc@bad-offset:
- shard-mtlp: NOTRUN -> [SKIP][39] ([i915#4083])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@gem_mmap_wc@bad-offset.html
* igt@gem_mmap_wc@close:
- shard-dg2: NOTRUN -> [SKIP][40] ([i915#4083]) +5 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-11/igt@gem_mmap_wc@close.html
* igt@gem_partial_pwrite_pread@writes-after-reads-display:
- shard-mtlp: NOTRUN -> [SKIP][41] ([i915#3282])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
* igt@gem_pwrite@basic-random:
- shard-dg2: NOTRUN -> [SKIP][42] ([i915#3282]) +7 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-11/igt@gem_pwrite@basic-random.html
* igt@gem_pxp@create-regular-context-1:
- shard-mtlp: NOTRUN -> [SKIP][43] ([i915#4270])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@gem_pxp@create-regular-context-1.html
* igt@gem_pxp@verify-pxp-stale-ctx-execution:
- shard-dg2: NOTRUN -> [SKIP][44] ([i915#4270]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@gem_pxp@verify-pxp-stale-ctx-execution.html
* igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs:
- shard-mtlp: NOTRUN -> [SKIP][45] ([i915#8428])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs.html
* igt@gem_render_copy@yf-tiled-ccs-to-y-tiled:
- shard-dg2: NOTRUN -> [SKIP][46] ([i915#5190]) +7 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-11/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled.html
* igt@gem_tiled_pread_basic:
- shard-mtlp: NOTRUN -> [SKIP][47] ([i915#4079])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@gem_tiled_pread_basic.html
* igt@gem_userptr_blits@access-control:
- shard-dg2: NOTRUN -> [SKIP][48] ([i915#3297])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@gem_userptr_blits@access-control.html
* igt@gem_userptr_blits@map-fixed-invalidate:
- shard-dg2: NOTRUN -> [SKIP][49] ([i915#3297] / [i915#4880])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@gem_userptr_blits@map-fixed-invalidate.html
* igt@gen3_render_tiledx_blits:
- shard-dg2: NOTRUN -> [SKIP][50] ([fdo#109289]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@gen3_render_tiledx_blits.html
* igt@gen7_exec_parse@basic-rejected:
- shard-mtlp: NOTRUN -> [SKIP][51] ([fdo#109289])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@gen7_exec_parse@basic-rejected.html
* igt@gen9_exec_parse@allowed-single:
- shard-dg2: NOTRUN -> [SKIP][52] ([i915#2856]) +2 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@gen9_exec_parse@allowed-single.html
* igt@i915_fb_tiling:
- shard-dg2: NOTRUN -> [SKIP][53] ([i915#4881])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@i915_fb_tiling.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg2: [PASS][54] -> [DMESG-WARN][55] ([i915#7061] / [i915#8617])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-dg2-11/igt@i915_module_load@reload-with-fault-injection.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-1/igt@i915_module_load@reload-with-fault-injection.html
- shard-snb: [PASS][56] -> [ABORT][57] ([i915#4528] / [i915#8668])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-snb4/igt@i915_module_load@reload-with-fault-injection.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-snb4/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pipe_stress@stress-xrgb8888-untiled:
- shard-mtlp: [PASS][58] -> [FAIL][59] ([i915#8691])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-mtlp-8/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-4/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
* igt@i915_pm_backlight@fade-with-dpms:
- shard-dg2: NOTRUN -> [SKIP][60] ([i915#5354] / [i915#7561])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-11/igt@i915_pm_backlight@fade-with-dpms.html
* igt@i915_pm_freq_mult@media-freq@gt1:
- shard-mtlp: NOTRUN -> [SKIP][61] ([i915#6590]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@i915_pm_freq_mult@media-freq@gt1.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- shard-dg1: [PASS][62] -> [SKIP][63] ([i915#1937])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-dg1-19/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg1-17/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-dg1: [PASS][64] -> [SKIP][65] ([i915#1397])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-dg1-17/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg1-19/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- shard-rkl: [PASS][66] -> [SKIP][67] ([i915#1397]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-rkl-2/igt@i915_pm_rpm@dpms-non-lpsp.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-rkl-7/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@i915_pm_rpm@fences-dpms:
- shard-dg2: NOTRUN -> [SKIP][68] ([i915#4077]) +6 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-11/igt@i915_pm_rpm@fences-dpms.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-dg2: [PASS][69] -> [SKIP][70] ([i915#1397])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-dg2-10/igt@i915_pm_rpm@modeset-lpsp-stress.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-11/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-mtlp: NOTRUN -> [SKIP][71] ([fdo#109293])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@i915_pm_rpm@pc8-residency:
- shard-dg2: NOTRUN -> [SKIP][72] ([fdo#109506])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@i915_pm_rpm@pc8-residency.html
* igt@i915_pm_rps@min-max-config-idle:
- shard-dg2: NOTRUN -> [SKIP][73] ([i915#6621])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@i915_pm_rps@min-max-config-idle.html
* igt@i915_pm_rps@thresholds-park@gt1:
- shard-mtlp: NOTRUN -> [SKIP][74] ([i915#8925]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@i915_pm_rps@thresholds-park@gt1.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1:
- shard-mtlp: [PASS][75] -> [FAIL][76] ([i915#2521])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-mtlp-2/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-5/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
* igt@kms_async_flips@crc@pipe-b-hdmi-a-1:
- shard-dg2: NOTRUN -> [FAIL][77] ([i915#8247]) +3 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-10/igt@kms_async_flips@crc@pipe-b-hdmi-a-1.html
- shard-rkl: NOTRUN -> [FAIL][78] ([i915#8247]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-rkl-7/igt@kms_async_flips@crc@pipe-b-hdmi-a-1.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-snb: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#1769])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-snb4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][80] ([fdo#111614]) +2 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@linear-16bpp-rotate-270:
- shard-mtlp: NOTRUN -> [SKIP][81] ([fdo#111614]) +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@kms_big_fb@linear-16bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-mtlp: [PASS][82] -> [FAIL][83] ([i915#3743])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-mtlp-4/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
- shard-mtlp: NOTRUN -> [SKIP][84] ([fdo#111615]) +2 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- shard-dg2: NOTRUN -> [SKIP][85] ([i915#4538] / [i915#5190]) +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-mtlp: NOTRUN -> [SKIP][86] ([i915#3886] / [i915#6095])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-dg2: NOTRUN -> [SKIP][87] ([i915#3689] / [i915#3886] / [i915#5354]) +3 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-rotation-90-yf_tiled_ccs:
- shard-dg2: NOTRUN -> [SKIP][88] ([i915#3689] / [i915#5354]) +13 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_ccs@pipe-b-bad-rotation-90-yf_tiled_ccs.html
* igt@kms_ccs@pipe-d-bad-pixel-format-4_tiled_dg2_mc_ccs:
- shard-mtlp: NOTRUN -> [SKIP][89] ([i915#6095]) +4 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@kms_ccs@pipe-d-bad-pixel-format-4_tiled_dg2_mc_ccs.html
* igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][90] ([i915#4087]) +3 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-1/igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3.html
* igt@kms_chamelium_color@ctm-green-to-red:
- shard-dg2: NOTRUN -> [SKIP][91] ([fdo#111827]) +2 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_chamelium_color@ctm-green-to-red.html
* igt@kms_chamelium_color@degamma:
- shard-mtlp: NOTRUN -> [SKIP][92] ([fdo#111827])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@kms_chamelium_color@degamma.html
* igt@kms_chamelium_frames@dp-crc-single:
- shard-mtlp: NOTRUN -> [SKIP][93] ([i915#7828])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@kms_chamelium_frames@dp-crc-single.html
* igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
- shard-dg2: NOTRUN -> [SKIP][94] ([i915#7828]) +5 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html
* igt@kms_content_protection@atomic-dpms:
- shard-dg2: NOTRUN -> [SKIP][95] ([i915#7118]) +2 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-1/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@content_type_change:
- shard-mtlp: NOTRUN -> [SKIP][96] ([i915#6944])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@kms_content_protection@content_type_change.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-dg2: NOTRUN -> [SKIP][97] ([i915#3299])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@type1:
- shard-dg2: NOTRUN -> [SKIP][98] ([i915#7118] / [i915#7162])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-mtlp: NOTRUN -> [SKIP][99] ([i915#3359]) +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-random-32x32:
- shard-mtlp: NOTRUN -> [SKIP][100] ([i915#8814])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@kms_cursor_crc@cursor-random-32x32.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
- shard-mtlp: NOTRUN -> [SKIP][101] ([i915#3546])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
- shard-dg2: NOTRUN -> [SKIP][102] ([fdo#109274] / [fdo#111767] / [i915#5354])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-legacy:
- shard-dg2: NOTRUN -> [SKIP][103] ([fdo#109274] / [i915#5354]) +3 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-11/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][104] ([i915#3804])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-rkl-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][105] ([i915#3637])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][106] ([fdo#111767] / [i915#3637])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
- shard-snb: NOTRUN -> [SKIP][107] ([fdo#109271] / [fdo#111767])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-snb2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-panning:
- shard-dg2: NOTRUN -> [SKIP][108] ([fdo#109274]) +4 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_flip@2x-flip-vs-panning.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][109] ([i915#8810])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][110] ([i915#2672]) +2 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][111] ([i915#2672])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
- shard-dg2: [PASS][112] -> [FAIL][113] ([i915#6880]) +1 similar issue
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt:
- shard-dg2: NOTRUN -> [SKIP][114] ([i915#5354]) +33 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt:
- shard-tglu: NOTRUN -> [SKIP][115] ([fdo#109280])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-tglu-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][116] ([i915#8708]) +10 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][117] ([i915#8708]) +2 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
- shard-mtlp: NOTRUN -> [SKIP][118] ([i915#1825]) +4 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
- shard-dg2: NOTRUN -> [SKIP][119] ([i915#3458]) +13 similar issues
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc:
- shard-tglu: NOTRUN -> [SKIP][120] ([fdo#110189])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-tglu-2/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html
* igt@kms_getfb@getfb-reject-ccs:
- shard-dg2: NOTRUN -> [SKIP][121] ([i915#6118])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_getfb@getfb-reject-ccs.html
* igt@kms_plane@pixel-format-source-clamping@pipe-b-planes:
- shard-mtlp: [PASS][122] -> [FAIL][123] ([i915#1623])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-mtlp-3/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-2/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
- shard-dg1: NOTRUN -> [FAIL][124] ([i915#8292])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg1-19/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][125] ([i915#5176]) +3 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][126] ([i915#5176]) +7 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-6/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][127] ([i915#5235]) +5 similar issues
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-rkl-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][128] ([i915#5235]) +3 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg1-16/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-hdmi-a-4.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][129] ([i915#5235]) +27 similar issues
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3.html
* igt@kms_prime@basic-crc-vgem:
- shard-dg2: NOTRUN -> [SKIP][130] ([i915#6524] / [i915#6805])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_prime@basic-crc-vgem.html
* igt@kms_prime@d3hot:
- shard-mtlp: NOTRUN -> [SKIP][131] ([i915#6524])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@kms_prime@d3hot.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-dg2: NOTRUN -> [SKIP][132] ([i915#658])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr@primary_mmap_cpu:
- shard-dg2: NOTRUN -> [SKIP][133] ([i915#1072]) +4 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_psr@primary_mmap_cpu.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-dg2: NOTRUN -> [SKIP][134] ([i915#5461] / [i915#658])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-dg2: NOTRUN -> [SKIP][135] ([i915#4235] / [i915#5190]) +1 similar issue
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_selftest@drm_cmdline:
- shard-snb: NOTRUN -> [SKIP][136] ([fdo#109271] / [i915#8661])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-snb5/igt@kms_selftest@drm_cmdline.html
* igt@kms_selftest@drm_plane:
- shard-dg2: NOTRUN -> [SKIP][137] ([i915#8661]) +1 similar issue
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_selftest@drm_plane.html
* igt@kms_vblank@pipe-c-query-busy-hang:
- shard-snb: NOTRUN -> [SKIP][138] ([fdo#109271]) +250 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-snb5/igt@kms_vblank@pipe-c-query-busy-hang.html
* igt@kms_vrr@flip-basic:
- shard-dg2: NOTRUN -> [SKIP][139] ([i915#3555]) +2 similar issues
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@kms_vrr@flip-basic.html
* igt@perf_pmu@most-busy-idle-check-all@rcs0:
- shard-dg2: NOTRUN -> [FAIL][140] ([i915#5234])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
* igt@prime_vgem@basic-fence-read:
- shard-dg2: NOTRUN -> [SKIP][141] ([i915#3291] / [i915#3708]) +1 similar issue
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@prime_vgem@basic-fence-read.html
* igt@tools_test@sysfs_l3_parity:
- shard-dg2: NOTRUN -> [SKIP][142] ([i915#4818])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@tools_test@sysfs_l3_parity.html
* igt@v3d/v3d_submit_cl@bad-perfmon:
- shard-mtlp: NOTRUN -> [SKIP][143] ([i915#2575]) +2 similar issues
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@v3d/v3d_submit_cl@bad-perfmon.html
* igt@v3d/v3d_submit_csd@bad-extension:
- shard-dg2: NOTRUN -> [SKIP][144] ([i915#2575]) +5 similar issues
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-11/igt@v3d/v3d_submit_csd@bad-extension.html
* igt@vc4/vc4_perfmon@get-values-invalid-perfmon:
- shard-mtlp: NOTRUN -> [SKIP][145] ([i915#7711])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@vc4/vc4_perfmon@get-values-invalid-perfmon.html
* igt@vc4/vc4_wait_bo@unused-bo-1ns:
- shard-dg2: NOTRUN -> [SKIP][146] ([i915#7711]) +6 similar issues
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@vc4/vc4_wait_bo@unused-bo-1ns.html
#### Possible fixes ####
* igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0:
- shard-dg2: [INCOMPLETE][147] ([i915#7297] / [i915#8011]) -> [PASS][148]
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-dg2-6/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-12/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglu: [FAIL][149] ([i915#6268]) -> [PASS][150]
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-tglu-8/igt@gem_ctx_exec@basic-nohangcheck.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-tglu-3/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_exec_capture@pi@bcs0:
- shard-mtlp: [FAIL][151] ([i915#4475] / [i915#7765]) -> [PASS][152]
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-mtlp-4/igt@gem_exec_capture@pi@bcs0.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@gem_exec_capture@pi@bcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-rkl: [FAIL][153] ([i915#2842]) -> [PASS][154]
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-rkl-7/igt@gem_exec_fair@basic-none-share@rcs0.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-rkl-2/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_suspend@basic-s4-devices@smem:
- shard-tglu: [ABORT][155] ([i915#7975] / [i915#8213]) -> [PASS][156]
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-tglu-10/igt@gem_exec_suspend@basic-s4-devices@smem.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-tglu-2/igt@gem_exec_suspend@basic-s4-devices@smem.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg1: [TIMEOUT][157] ([i915#5493]) -> [PASS][158]
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg1-17/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-rkl: [SKIP][159] ([i915#1397]) -> [PASS][160] +1 similar issue
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-rkl-2/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-rkl-7/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- shard-dg2: [SKIP][161] ([i915#1397]) -> [PASS][162] +2 similar issues
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-dg2-12/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-1/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
* igt@i915_selftest@live@requests:
- shard-mtlp: [ABORT][163] ([i915#7920]) -> [PASS][164]
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-mtlp-4/igt@i915_selftest@live@requests.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-8/igt@i915_selftest@live@requests.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-vga-1:
- shard-snb: [FAIL][165] ([i915#2521]) -> [PASS][166]
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-snb4/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-vga-1.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-snb2/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-vga-1.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-mtlp: [FAIL][167] ([i915#3743]) -> [PASS][168]
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-mtlp-8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-5/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [FAIL][169] ([i915#2346]) -> [PASS][170]
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-mtlp: [FAIL][171] ([i915#4767]) -> [PASS][172]
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-mtlp-1/igt@kms_fbcon_fbt@fbc-suspend.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-1/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a1:
- shard-glk: [FAIL][173] ([i915#2122]) -> [PASS][174]
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-glk6/igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a1.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-glk5/igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt:
- shard-dg2: [FAIL][175] ([i915#6880]) -> [PASS][176] +1 similar issue
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_plane@pixel-format@pipe-b-planes:
- shard-mtlp: [FAIL][177] ([i915#1623]) -> [PASS][178]
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-mtlp-8/igt@kms_plane@pixel-format@pipe-b-planes.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-5/igt@kms_plane@pixel-format@pipe-b-planes.html
* igt@prime_busy@hang@rcs0:
- shard-snb: [ABORT][179] ([i915#8865]) -> [PASS][180]
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-snb7/igt@prime_busy@hang@rcs0.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-snb1/igt@prime_busy@hang@rcs0.html
#### Warnings ####
* igt@gem_exec_fence@parallel@bcs0:
- shard-mtlp: [TIMEOUT][181] -> [DMESG-FAIL][182] ([i915#8962] / [i915#9121])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-mtlp-4/igt@gem_exec_fence@parallel@bcs0.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-4/igt@gem_exec_fence@parallel@bcs0.html
* igt@gem_exec_suspend@basic-s0@smem:
- shard-snb: [DMESG-WARN][183] ([i915#8841]) -> [DMESG-FAIL][184] ([fdo#103375])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-snb4/igt@gem_exec_suspend@basic-s0@smem.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-snb7/igt@gem_exec_suspend@basic-s0@smem.html
* igt@kms_async_flips@crc@pipe-a-edp-1:
- shard-mtlp: [DMESG-FAIL][185] ([i915#1982] / [i915#8561]) -> [DMESG-FAIL][186] ([i915#8561])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-mtlp-8/igt@kms_async_flips@crc@pipe-a-edp-1.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-mtlp-4/igt@kms_async_flips@crc@pipe-a-edp-1.html
* igt@kms_content_protection@mei_interface:
- shard-dg2: [SKIP][187] ([i915#7118]) -> [SKIP][188] ([i915#7118] / [i915#7162])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-dg2-6/igt@kms_content_protection@mei_interface.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg2-11/igt@kms_content_protection@mei_interface.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][189] ([i915#4070] / [i915#4816]) -> [SKIP][190] ([i915#4816])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-rkl-2/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_psr@primary_page_flip:
- shard-dg1: [SKIP][191] ([i915#1072]) -> [SKIP][192] ([i915#1072] / [i915#4078])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-dg1-14/igt@kms_psr@primary_page_flip.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/shard-dg1-18/igt@kms_psr@primary_page_flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1623]: https://gitlab.freedesktop.org/drm/intel/issues/1623
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4475]: https://gitlab.freedesktop.org/drm/intel/issues/4475
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5234]: https://gitlab.freedesktop.org/drm/intel/issues/5234
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6118]: https://gitlab.freedesktop.org/drm/intel/issues/6118
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#7061]: https://gitlab.freedesktop.org/drm/intel/issues/7061
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
[i915#7297]: https://gitlab.freedesktop.org/drm/intel/issues/7297
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7765]: https://gitlab.freedesktop.org/drm/intel/issues/7765
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8561]: https://gitlab.freedesktop.org/drm/intel/issues/8561
[i915#8617]: https://gitlab.freedesktop.org/drm/intel/issues/8617
[i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#8691]: https://gitlab.freedesktop.org/drm/intel/issues/8691
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
[i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#8865]: https://gitlab.freedesktop.org/drm/intel/issues/8865
[i915#8898]: https://gitlab.freedesktop.org/drm/intel/issues/8898
[i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
[i915#8957]: https://gitlab.freedesktop.org/drm/intel/issues/8957
[i915#8962]: https://gitlab.freedesktop.org/drm/intel/issues/8962
[i915#9121]: https://gitlab.freedesktop.org/drm/intel/issues/9121
Build changes
-------------
* Linux: CI_DRM_13534 -> Patchwork_122589v1
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_13534: 2c5542cb377b2e9e15c1f84a6e78a3d6fca47ea0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7443: 953448dbf2e63918a8eced9707f65fc0a19a9c85 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_122589v1: 2c5542cb377b2e9e15c1f84a6e78a3d6fca47ea0 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v1/index.html
[-- Attachment #2: Type: text/html, Size: 61918 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread