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From: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
To: "Belgaumkar, Vinay" <vinay.belgaumkar@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915/pmu: Use common freq functions with sysfs
Date: Wed, 08 Mar 2023 19:53:21 -0800	[thread overview]
Message-ID: <87fsaemvgu.wl-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <8b4e02e6-35a0-5262-5f85-5671f4d287b4@intel.com>

On Tue, 07 Mar 2023 22:12:49 -0800, Belgaumkar, Vinay wrote:
>

Hi Vinay,

> On 3/7/2023 9:33 PM, Ashutosh Dixit wrote:
> > Using common freq functions with sysfs in PMU (but without taking
> > forcewake) solves the following issues (a) missing support for MTL (b)
>
> For the requested_freq, we read it only if actual_freq is zero below
> (meaning, GT is in C6). So then what is the point of reading it without a
> force wake? It will also be zero, correct?

Yes agreed. I had tested this and you do see values for requested freq
which look correct even when actual freq is 0 even without taking
forcewake. That is why I ended up writing Patch 2/3.

However what I missed is what you pointed out that 0xa008 is a shadowed
register which cannot be read without taking forcewake. It is probably
returning the last value which was written to the shadowed write register.

As a result I have dropped the "drm/i915/rps: Expose
get_requested_frequency_fw for PMU" patch in v2 of this series.

Thanks.
--
Ashutosh

WARNING: multiple messages have this Message-ID (diff)
From: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
To: "Belgaumkar, Vinay" <vinay.belgaumkar@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
	intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH 3/3] drm/i915/pmu: Use common freq functions with sysfs
Date: Wed, 08 Mar 2023 19:53:21 -0800	[thread overview]
Message-ID: <87fsaemvgu.wl-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <8b4e02e6-35a0-5262-5f85-5671f4d287b4@intel.com>

On Tue, 07 Mar 2023 22:12:49 -0800, Belgaumkar, Vinay wrote:
>

Hi Vinay,

> On 3/7/2023 9:33 PM, Ashutosh Dixit wrote:
> > Using common freq functions with sysfs in PMU (but without taking
> > forcewake) solves the following issues (a) missing support for MTL (b)
>
> For the requested_freq, we read it only if actual_freq is zero below
> (meaning, GT is in C6). So then what is the point of reading it without a
> force wake? It will also be zero, correct?

Yes agreed. I had tested this and you do see values for requested freq
which look correct even when actual freq is 0 even without taking
forcewake. That is why I ended up writing Patch 2/3.

However what I missed is what you pointed out that 0xa008 is a shadowed
register which cannot be read without taking forcewake. It is probably
returning the last value which was written to the shadowed write register.

As a result I have dropped the "drm/i915/rps: Expose
get_requested_frequency_fw for PMU" patch in v2 of this series.

Thanks.
--
Ashutosh

  reply	other threads:[~2023-03-09  3:53 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-08  5:33 [Intel-gfx] [PATCH 0/3] drm/i915/pmu: Use common freq functions with sysfs Ashutosh Dixit
2023-03-08  5:33 ` Ashutosh Dixit
2023-03-08  5:33 ` [Intel-gfx] [PATCH 1/3] drm/i915/rps: Expose read_actual_frequency_fw for PMU Ashutosh Dixit
2023-03-08  5:33   ` Ashutosh Dixit
2023-03-08  5:33 ` [Intel-gfx] [PATCH 2/3] drm/i915/rps: Expose get_requested_frequency_fw " Ashutosh Dixit
2023-03-08  5:33   ` Ashutosh Dixit
2023-03-08  5:33 ` [Intel-gfx] [PATCH 3/3] drm/i915/pmu: Use common freq functions with sysfs Ashutosh Dixit
2023-03-08  5:33   ` Ashutosh Dixit
2023-03-08  6:12   ` [Intel-gfx] " Belgaumkar, Vinay
2023-03-08  6:12     ` Belgaumkar, Vinay
2023-03-09  3:53     ` Dixit, Ashutosh [this message]
2023-03-09  3:53       ` Dixit, Ashutosh
2023-03-08  6:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2023-03-09 18:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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