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From: Thomas Gleixner <tglx@linutronix.de>
To: Adrian Hunter <adrian.hunter@intel.com>,
	Peter Zijlstra <peterz@infradead.org>
Cc: "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	"virtualization@lists.linux-foundation.org"
	<virtualization@lists.linux-foundation.org>,
	H Peter Anvin <hpa@zytor.com>, Jiri Olsa <jolsa@redhat.com>,
	"Hall, Christopher S" <christopher.s.hall@intel.com>,
	"sthemmin@microsoft.com" <sthemmin@microsoft.com>,
	"x86@kernel.org" <x86@kernel.org>,
	"pv-drivers@vmware.com" <pv-drivers@vmware.com>,
	Ingo Molnar <mingo@redhat.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Leo Yan <leo.yan@linaro.org>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Borislav Petkov <bp@alien8.de>,
	"jgross@suse.com" <jgross@suse.com>,
	Mathieu Poirier <mathieu.poirier@linaro.org>,
	"seanjc@google.com" <seanjc@google.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"Andrew.Cooper3@citrix.com" <Andrew.Cooper3@citrix.com>,
	"pbonzini@redhat.com" <pbonzini@redhat.com>
Subject: Re: [PATCH V2 03/11] perf/x86: Add support for TSC in nanoseconds as a perf event clock
Date: Mon, 25 Apr 2022 19:05:58 +0200	[thread overview]
Message-ID: <87fsm114ax.ffs@tglx> (raw)
In-Reply-To: <ff1e190a-95e6-e2a6-dc01-a46f7ffd2162@intel.com>

On Mon, Apr 25 2022 at 16:15, Adrian Hunter wrote:
> On 25/04/22 12:32, Thomas Gleixner wrote:
>> It's hillarious, that we still cling to this pvclock abomination, while
>> we happily expose TSC deadline timer to the guest. TSC virt scaling was
>> implemented in hardware for a reason.
>
> So you are talking about changing VMX TCS Offset on every VM-Entry to try to hide
> the time jumps when the VM is scheduled out?  Or neglect that and just let the time
> jumps happen?
>
> If changing VMX TCS Offset, how can TSC be kept consistent between each VCPU i.e.
> wouldn't that mean each VCPU has to have the same VMX TSC Offset?

Obviously so. That's the only thing which makes sense, no?

Thanks,

        tglx
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WARNING: multiple messages have this Message-ID (diff)
From: Thomas Gleixner <tglx@linutronix.de>
To: Adrian Hunter <adrian.hunter@intel.com>,
	Peter Zijlstra <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Jiri Olsa <jolsa@redhat.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	"x86@kernel.org" <x86@kernel.org>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	H Peter Anvin <hpa@zytor.com>,
	Mathieu Poirier <mathieu.poirier@linaro.org>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Leo Yan <leo.yan@linaro.org>, "jgross@suse.com" <jgross@suse.com>,
	"sdeep@vmware.com" <sdeep@vmware.com>,
	"pv-drivers@vmware.com" <pv-drivers@vmware.com>,
	"pbonzini@redhat.com" <pbonzini@redhat.com>,
	"seanjc@google.com" <seanjc@google.com>,
	"kys@microsoft.com" <kys@microsoft.com>,
	"sthemmin@microsoft.com" <sthemmin@microsoft.com>,
	"virtualization@lists.linux-foundation.org" 
	<virtualization@lists.linux-foundation.org>,
	"Andrew.Cooper3@citrix.com" <Andrew.Cooper3@citrix.com>,
	"Hall, Christopher S" <christopher.s.hall@intel.com>
Subject: Re: [PATCH V2 03/11] perf/x86: Add support for TSC in nanoseconds as a perf event clock
Date: Mon, 25 Apr 2022 19:05:58 +0200	[thread overview]
Message-ID: <87fsm114ax.ffs@tglx> (raw)
In-Reply-To: <ff1e190a-95e6-e2a6-dc01-a46f7ffd2162@intel.com>

On Mon, Apr 25 2022 at 16:15, Adrian Hunter wrote:
> On 25/04/22 12:32, Thomas Gleixner wrote:
>> It's hillarious, that we still cling to this pvclock abomination, while
>> we happily expose TSC deadline timer to the guest. TSC virt scaling was
>> implemented in hardware for a reason.
>
> So you are talking about changing VMX TCS Offset on every VM-Entry to try to hide
> the time jumps when the VM is scheduled out?  Or neglect that and just let the time
> jumps happen?
>
> If changing VMX TCS Offset, how can TSC be kept consistent between each VCPU i.e.
> wouldn't that mean each VCPU has to have the same VMX TSC Offset?

Obviously so. That's the only thing which makes sense, no?

Thanks,

        tglx

  reply	other threads:[~2022-04-25 17:06 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-14 11:09 [PATCH V2 00/11] perf intel-pt: Add perf event clocks to better support VM tracing Adrian Hunter
2022-02-14 11:09 ` [PATCH V2 01/11] perf/x86: Fix native_perf_sched_clock_from_tsc() with __sched_clock_offset Adrian Hunter
2022-02-14 11:09 ` [PATCH V2 02/11] perf/x86: Add support for TSC as a perf event clock Adrian Hunter
2022-03-04 12:30   ` Peter Zijlstra
2022-03-04 13:03     ` Adrian Hunter
2022-03-04 12:32   ` Peter Zijlstra
2022-03-04 17:51     ` Thomas Gleixner
2022-03-04 12:33   ` Peter Zijlstra
2022-03-04 12:41     ` Adrian Hunter
2022-02-14 11:09 ` [PATCH V2 03/11] perf/x86: Add support for TSC in nanoseconds " Adrian Hunter
2022-03-04 13:41   ` Peter Zijlstra
2022-03-04 18:27     ` Adrian Hunter
2022-03-07  9:50       ` Peter Zijlstra
2022-03-07  9:50         ` Peter Zijlstra
2022-03-07 10:06         ` Juergen Gross via Virtualization
2022-03-07 10:06           ` Juergen Gross
2022-03-07 10:38           ` Peter Zijlstra
2022-03-07 10:38             ` Peter Zijlstra
2022-03-07 10:58             ` Juergen Gross via Virtualization
2022-03-07 10:58               ` Juergen Gross
2022-03-07 12:36         ` Adrian Hunter
2022-03-07 14:42           ` Peter Zijlstra
2022-03-07 14:42             ` Peter Zijlstra
2022-03-08 14:23             ` Adrian Hunter
2022-03-08 21:06               ` Hall, Christopher S
2022-03-14 11:50                 ` Adrian Hunter
2022-04-25  5:30                   ` Adrian Hunter
2022-04-25  9:32                     ` Thomas Gleixner
2022-04-25  9:32                       ` Thomas Gleixner
2022-04-25 13:15                       ` Adrian Hunter
2022-04-25 17:05                         ` Thomas Gleixner [this message]
2022-04-25 17:05                           ` Thomas Gleixner
2022-04-26  6:51                           ` Adrian Hunter
2022-04-27 23:10                             ` Thomas Gleixner
2022-04-27 23:10                               ` Thomas Gleixner
2022-05-16  7:20                               ` Adrian Hunter
2022-02-14 11:09 ` [PATCH V2 04/11] perf tools: Add new perf clock IDs Adrian Hunter
2022-02-14 11:09 ` [PATCH V2 05/11] perf tools: Add API probes for new " Adrian Hunter
2022-02-14 11:09 ` [PATCH V2 06/11] perf tools: Add new clock IDs to "perf time to TSC" test Adrian Hunter
2022-02-14 11:09 ` [PATCH V2 07/11] perf tools: Add perf_read_tsc_conv_for_clockid() Adrian Hunter
2022-02-14 11:09 ` [PATCH V2 08/11] perf intel-pt: Add support for new clock IDs Adrian Hunter
2022-02-14 11:09 ` [PATCH V2 09/11] perf intel-pt: Use CLOCK_PERF_HW_CLOCK_NS by default Adrian Hunter
2022-02-14 11:09 ` [PATCH V2 10/11] perf intel-pt: Add config variables for timing parameters Adrian Hunter
2022-02-14 11:09 ` [PATCH V2 11/11] perf intel-pt: Add documentation for new clock IDs Adrian Hunter
2022-02-21  6:54 ` [PATCH V2 00/11] perf intel-pt: Add perf event clocks to better support VM tracing Adrian Hunter
2022-03-01 11:06   ` Adrian Hunter

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