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From: Marc Zyngier <maz@kernel.org>
To: Hector Martin <marcan@marcan.st>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh+dt@kernel.org>, Sven Peter <sven@svenpeter.dev>,
	Alyssa Rosenzweig <alyssa@rosenzweig.io>,
	Mark Kettenis <mark.kettenis@xs4all.nl>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v2 3/7] irqchip/apple-aic: Add Fast IPI support
Date: Mon, 07 Mar 2022 11:35:14 +0000	[thread overview]
Message-ID: <87fsnu0zd9.wl-maz@kernel.org> (raw)
In-Reply-To: <d0e2a08e-79d6-03e8-09a2-bb634fa3c23c@marcan.st>

On Sun, 27 Feb 2022 15:33:54 +0000,
Hector Martin <marcan@marcan.st> wrote:
> 
> On 25/02/2022 23.39, Marc Zyngier wrote:
> > On Thu, 24 Feb 2022 13:07:37 +0000,
> >>  		if (!(pending & irq_bit) &&
> >> -		    (atomic_read(per_cpu_ptr(&aic_vipi_enable, cpu)) & irq_bit))
> >> -			send |= AIC_IPI_SEND_CPU(cpu);
> >> +		    (atomic_read(per_cpu_ptr(&aic_vipi_enable, cpu)) & irq_bit)) {
> >> +			if (static_branch_likely(&use_fast_ipi))
> >> +				aic_ipi_send_fast(cpu);
> > 
> > OK, this is suffering from the same issue that GICv3 has, which is
> > that memory barriers don't provide order against sysregs. You need a
> > DSB for that, which is a pain. Something like this:
> 
> Doesn't the control flow here guarantee the ordering? atomic_read() must
> complete before the sysreg is written since there is a control flow
> dependency, and the prior atomic/barrier dance ensures that read is
> ordered properly with everything that comes before it.

Yes, you're right. Mixing memory ordering and control dependency hurts
my head badly, but hey, why not.

	M.

-- 
Without deviation from the norm, progress is not possible.

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WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Hector Martin <marcan@marcan.st>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh+dt@kernel.org>, Sven Peter <sven@svenpeter.dev>,
	Alyssa Rosenzweig <alyssa@rosenzweig.io>,
	Mark Kettenis <mark.kettenis@xs4all.nl>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v2 3/7] irqchip/apple-aic: Add Fast IPI support
Date: Mon, 07 Mar 2022 11:35:14 +0000	[thread overview]
Message-ID: <87fsnu0zd9.wl-maz@kernel.org> (raw)
In-Reply-To: <d0e2a08e-79d6-03e8-09a2-bb634fa3c23c@marcan.st>

On Sun, 27 Feb 2022 15:33:54 +0000,
Hector Martin <marcan@marcan.st> wrote:
> 
> On 25/02/2022 23.39, Marc Zyngier wrote:
> > On Thu, 24 Feb 2022 13:07:37 +0000,
> >>  		if (!(pending & irq_bit) &&
> >> -		    (atomic_read(per_cpu_ptr(&aic_vipi_enable, cpu)) & irq_bit))
> >> -			send |= AIC_IPI_SEND_CPU(cpu);
> >> +		    (atomic_read(per_cpu_ptr(&aic_vipi_enable, cpu)) & irq_bit)) {
> >> +			if (static_branch_likely(&use_fast_ipi))
> >> +				aic_ipi_send_fast(cpu);
> > 
> > OK, this is suffering from the same issue that GICv3 has, which is
> > that memory barriers don't provide order against sysregs. You need a
> > DSB for that, which is a pain. Something like this:
> 
> Doesn't the control flow here guarantee the ordering? atomic_read() must
> complete before the sysreg is written since there is a control flow
> dependency, and the prior atomic/barrier dance ensures that read is
> ordered properly with everything that comes before it.

Yes, you're right. Mixing memory ordering and control dependency hurts
my head badly, but hey, why not.

	M.

-- 
Without deviation from the norm, progress is not possible.

  reply	other threads:[~2022-03-07 11:36 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-24 13:07 [PATCH v2 0/7] irqchip/apple-aic: Add support for AICv2 Hector Martin
2022-02-24 13:07 ` Hector Martin
2022-02-24 13:07 ` [PATCH v2 1/7] PCI: apple: Change MSI handling to handle 4-cell AIC fwspec form Hector Martin
2022-02-24 13:07   ` Hector Martin
2022-02-24 13:07 ` [PATCH v2 2/7] dt-bindings: interrupt-controller: apple, aic2: New binding for AICv2 Hector Martin
2022-02-24 13:07   ` [PATCH v2 2/7] dt-bindings: interrupt-controller: apple,aic2: " Hector Martin
2022-02-25 20:19   ` Rob Herring
2022-02-25 20:19     ` Rob Herring
2022-02-25 21:58     ` [PATCH v2 2/7] dt-bindings: interrupt-controller: apple, aic2: " Hector Martin
2022-02-25 21:58       ` [PATCH v2 2/7] dt-bindings: interrupt-controller: apple,aic2: " Hector Martin
2022-03-07 11:35       ` [PATCH v2 2/7] dt-bindings: interrupt-controller: apple, aic2: " Marc Zyngier
2022-03-07 11:35         ` [PATCH v2 2/7] dt-bindings: interrupt-controller: apple,aic2: " Marc Zyngier
2022-02-24 13:07 ` [PATCH v2 3/7] irqchip/apple-aic: Add Fast IPI support Hector Martin
2022-02-24 13:07   ` Hector Martin
2022-02-25 14:39   ` Marc Zyngier
2022-02-25 14:39     ` Marc Zyngier
2022-02-27 15:33     ` Hector Martin
2022-02-27 15:33       ` Hector Martin
2022-03-07 11:35       ` Marc Zyngier [this message]
2022-03-07 11:35         ` Marc Zyngier
2022-02-24 13:07 ` [PATCH v2 4/7] irqchip/apple-aic: Switch to irq_domain_create_tree and sparse hwirqs Hector Martin
2022-02-24 13:07   ` Hector Martin
2022-02-24 13:07 ` [PATCH v2 5/7] irqchip/apple-aic: Dynamically compute register offsets Hector Martin
2022-02-24 13:07   ` Hector Martin
2022-02-24 13:07 ` [PATCH v2 6/7] irqchip/apple-aic: Support multiple dies Hector Martin
2022-02-24 13:07   ` Hector Martin
2022-02-24 13:07 ` [PATCH v2 7/7] irqchip/apple-aic: Add support for AICv2 Hector Martin
2022-02-24 13:07   ` Hector Martin
2022-02-25 15:27   ` Marc Zyngier
2022-02-25 15:27     ` Marc Zyngier
2022-02-25 22:05     ` Hector Martin
2022-02-25 22:05       ` Hector Martin
2022-02-24 18:26 ` [PATCH v2 0/7] " Mark Rutland
2022-02-24 18:26   ` Mark Rutland
2022-02-24 19:06   ` Marc Zyngier
2022-02-24 19:06     ` Marc Zyngier
2022-02-25  4:27     ` Hector Martin
2022-02-25  4:27       ` Hector Martin

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