From: Felipe Balbi <balbi@kernel.org>
Cc: tony@atomide.com, Joao.Pinto@synopsys.com,
sergei.shtylyov@cogentembedded.com, peter.chen@freescale.com,
jun.li@freescale.com, grygorii.strashko@ti.com,
yoshihiro.shimoda.uh@renesas.com, nsekhar@ti.com,
linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-omap@vger.kernel.org, Roger Quadros <rogerq@ti.com>
Subject: Re: [PATCH v7 1/4] usb: dwc3: core.h: add some register definitions
Date: Mon, 20 Jun 2016 12:28:14 +0300 [thread overview]
Message-ID: <87fus8qkep.fsf@linux.intel.com> (raw)
In-Reply-To: <1465564650-27516-2-git-send-email-rogerq@ti.com>
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Hi,
Roger Quadros <rogerq@ti.com> writes:
> Add OTG and GHWPARAMS6 register definitions
>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
> drivers/usb/dwc3/core.h | 84 ++++++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 83 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 8fb6361..32bb7531 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -197,6 +197,15 @@
> #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
> #define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
>
> +/* Global Status Register */
> +#define DWC3_GSTS_OTG_IP BIT(10)
> +#define DWC3_GSTS_BC_IP BIT(9)
> +#define DWC3_GSTS_ADP_IP BIT(8)
> +#define DWC3_GSTS_HOST_IP BIT(7)
> +#define DWC3_GSTS_DEVICE_IP BIT(6)
> +#define DWC3_GSTS_CSR_TIMEOUT BIT(5)
> +#define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4)
> +
> /* Global USB2 PHY Configuration Register */
> #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
> #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
> @@ -269,7 +278,12 @@
> #define DWC3_MAX_HIBER_SCRATCHBUFS 15
>
> /* Global HWPARAMS6 Register */
> -#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
> +#define DWC3_GHWPARAMS6_BCSUPPORT BIT(14)
> +#define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13)
> +#define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12)
> +#define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11)
> +#define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10)
> +#define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
Keep consistency, we don't use BIT() here.
--
balbi
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WARNING: multiple messages have this Message-ID (diff)
From: Felipe Balbi <balbi@kernel.org>
To: Roger Quadros <rogerq@ti.com>
Cc: tony@atomide.com, Joao.Pinto@synopsys.com,
sergei.shtylyov@cogentembedded.com, peter.chen@freescale.com,
jun.li@freescale.com, grygorii.strashko@ti.com,
yoshihiro.shimoda.uh@renesas.com, nsekhar@ti.com,
linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-omap@vger.kernel.org, Roger Quadros <rogerq@ti.com>
Subject: Re: [PATCH v7 1/4] usb: dwc3: core.h: add some register definitions
Date: Mon, 20 Jun 2016 12:28:14 +0300 [thread overview]
Message-ID: <87fus8qkep.fsf@linux.intel.com> (raw)
In-Reply-To: <1465564650-27516-2-git-send-email-rogerq@ti.com>
[-- Attachment #1: Type: text/plain, Size: 1533 bytes --]
Hi,
Roger Quadros <rogerq@ti.com> writes:
> Add OTG and GHWPARAMS6 register definitions
>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
> drivers/usb/dwc3/core.h | 84 ++++++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 83 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 8fb6361..32bb7531 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -197,6 +197,15 @@
> #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
> #define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
>
> +/* Global Status Register */
> +#define DWC3_GSTS_OTG_IP BIT(10)
> +#define DWC3_GSTS_BC_IP BIT(9)
> +#define DWC3_GSTS_ADP_IP BIT(8)
> +#define DWC3_GSTS_HOST_IP BIT(7)
> +#define DWC3_GSTS_DEVICE_IP BIT(6)
> +#define DWC3_GSTS_CSR_TIMEOUT BIT(5)
> +#define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4)
> +
> /* Global USB2 PHY Configuration Register */
> #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
> #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
> @@ -269,7 +278,12 @@
> #define DWC3_MAX_HIBER_SCRATCHBUFS 15
>
> /* Global HWPARAMS6 Register */
> -#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
> +#define DWC3_GHWPARAMS6_BCSUPPORT BIT(14)
> +#define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13)
> +#define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12)
> +#define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11)
> +#define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10)
> +#define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
Keep consistency, we don't use BIT() here.
--
balbi
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next prev parent reply other threads:[~2016-06-20 9:28 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-10 13:17 [PATCH v7 0/4] usb: dwc3: dual-role support Roger Quadros
2016-06-10 13:17 ` Roger Quadros
2016-06-10 13:17 ` [PATCH v7 1/4] usb: dwc3: core.h: add some register definitions Roger Quadros
2016-06-10 13:17 ` Roger Quadros
2016-06-20 9:28 ` Felipe Balbi [this message]
2016-06-20 9:28 ` Felipe Balbi
[not found] ` <87fus8qkep.fsf-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2016-06-20 11:53 ` Roger Quadros
2016-06-20 11:53 ` Roger Quadros
2016-06-20 12:04 ` Felipe Balbi
2016-06-10 13:17 ` [PATCH v7 2/4] usb: dwc3: add dual-role support Roger Quadros
2016-06-10 13:17 ` Roger Quadros
[not found] ` <1465564650-27516-3-git-send-email-rogerq-l0cyMroinI0@public.gmane.org>
2016-06-12 9:11 ` Peter Chen
2016-06-12 9:11 ` Peter Chen
2016-06-13 7:09 ` Roger Quadros
2016-06-13 7:09 ` Roger Quadros
[not found] ` <575E5C21.8040103-l0cyMroinI0@public.gmane.org>
2016-06-13 8:25 ` Roger Quadros
2016-06-13 8:25 ` Roger Quadros
2016-06-10 13:17 ` [PATCH v7 3/4] ARM: dts: dra7*-evm: Enable dual-role for usb1 Roger Quadros
2016-06-10 13:17 ` Roger Quadros
2016-06-10 13:17 ` [PATCH v7 4/4] ARM: dts: am43xx: Enable dual-role on USB1 Roger Quadros
2016-06-10 13:17 ` Roger Quadros
2016-06-10 13:26 ` [PATCH v7 0/4] usb: dwc3: dual-role support Roger Quadros
2016-06-10 13:26 ` Roger Quadros
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