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From: Ed L Cashin <ecashin@uga.edu>
To: sparclinux@vger.kernel.org
Subject: Re: TLB miss handler code
Date: Wed, 21 Jan 2004 16:43:20 +0000	[thread overview]
Message-ID: <87fze96ymv.fsf@uga.edu> (raw)
In-Reply-To: <Pine.GSO.4.43.0401191315430.13707-100000@gatekeeper.ececs.uc.edu>

Nawab Ali <alin@ececs.uc.edu> writes:

> Hi Ed,
> Thanx for pointing out the file. I checked out the do_sparc64_fault
> function in arch/sparc64/mm/fault.c (2.6.0).
>
> This is the code snippet I found.
> if ((fault_code & FAULT_CODE_ITLB) && (fault_code & FAULT_CODE_DTLB))
> 	BUG();

That case is a bug, so it's not what you're looking for.  The test
checks whether the fault code says that it's a dTLB *and* an iTLB
miss, which doesn't make any sense.

You're interested in the non-buggy case.  In 2.6.0-test11, I can
follow that the call sequence: do_sparc64_fault calls
mm/memory.c:handle_mm_fault which calls handle_pte_fault.  Eventually
update_mmu_cache and the assembly __update_mmu_cache are called.

arch/sparc64/mm/ultra.S has the actual code that fills the TLBs.  All
you have to do is decide where in that path it makes sense for you to
add your code.  Maybe about the time update_mmu_cache is called.

-- 
--Ed L Cashin            |   PGP public key:
  ecashin@uga.edu        |   http://noserose.net/e/pgp/


  parent reply	other threads:[~2004-01-21 16:43 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2004-01-19 18:23 TLB miss handler code Nawab Ali
2004-01-19 21:27 ` Ed L Cashin
2004-01-20 23:46 ` Ben Collins
2004-01-21  0:33 ` Nawab Ali
2004-01-21 16:41 ` David S. Miller
2004-01-21 16:43 ` Ed L Cashin [this message]
2004-01-21 17:21 ` Ed L Cashin
2004-01-21 21:34 ` David S. Miller
2004-01-21 22:11 ` Ed L Cashin
2004-01-21 23:14 ` Nawab Ali
2004-01-22  1:52 ` David S. Miller
2004-01-22  2:15 ` Ed L Cashin
2004-01-22  2:16 ` David S. Miller
2004-01-22  5:01 ` Ed L Cashin
2004-01-22  5:24 ` Ed L Cashin

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