Re: [PATCH 1/3] target/arm/tcg: define cortex-m85 cpu

["Alex Bennée" <alex.bennee@linaro.org>]

Torbjörn SVENSSON <torbjorn.svensson@foss.st.com> writes:

Can you mention the TRM in the commit:

  https://developer.arm.com/documentation/101924/0100/

> Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
> ---
>  target/arm/tcg/cpu-v7m.c | 40 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
>
> diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
> index dc249ce1f1..5cfda232cd 100644
> --- a/target/arm/tcg/cpu-v7m.c
> +++ b/target/arm/tcg/cpu-v7m.c
> @@ -237,6 +237,44 @@ static void cortex_m55_initfn(Object *obj)
>      cpu->ctr = 0x8303c003;
>  }
>  
> +static void cortex_m85_initfn(Object *obj)
> +{
> +    ARMCPU *cpu = ARM_CPU(obj);
> +    ARMISARegisters *isar = &cpu->isar;
> +
> +    set_feature(&cpu->env, ARM_FEATURE_V8);
> +    set_feature(&cpu->env, ARM_FEATURE_V8_1M);
> +    set_feature(&cpu->env, ARM_FEATURE_M);
> +    set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
> +    set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
> +    set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
> +    cpu->midr = 0x411fd230; /* r1p0 */
> +    cpu->revidr = 0;
> +    cpu->pmsav7_dregion = 16;
> +    cpu->sau_sregion = 8;
> +    /* These are the MVFR* values for the FPU + full MVE configuration */
> +    cpu->isar.mvfr0 = 0x10110221;
> +    cpu->isar.mvfr1 = 0x12100211;
> +    cpu->isar.mvfr2 = 0x00000040;
> +    SET_IDREG(isar, ID_PFR0, 0x20000030);
> +    SET_IDREG(isar, ID_PFR1, 0x00000230);
> +    SET_IDREG(isar, ID_DFR0, 0x10200000);
> +    SET_IDREG(isar, ID_AFR0, 0x00000000);
> +    SET_IDREG(isar, ID_MMFR0, 0x00111040);
> +    SET_IDREG(isar, ID_MMFR1, 0x00000000);
> +    SET_IDREG(isar, ID_MMFR2, 0x01000000);
> +    SET_IDREG(isar, ID_MMFR3, 0x00000011);
> +    SET_IDREG(isar, ID_ISAR0, 0x01103110);
> +    SET_IDREG(isar, ID_ISAR1, 0x02212000);
> +    SET_IDREG(isar, ID_ISAR2, 0x20232232);
> +    SET_IDREG(isar, ID_ISAR3, 0x01111131);
> +    SET_IDREG(isar, ID_ISAR4, 0x01310132);
> +    SET_IDREG(isar, ID_ISAR5, 0x00000000);

The TRM specifies this as 0x00100000 and you set this to in 3/3 to:

  SET_IDREG(isar, ID_ISAR5, 0x00200000); /* PACBTI=implementation defined */

which isn't one of the available config options. We'd rather not present
a CPU that can't exist.

With that said for A-profile we do offer the control knob of
pauth-impdef (which is the default for -cpu max). We could add similar
logic to aarch64_cpu_pauth_finalize to cpu32 to allow the user to
actively tune their emulation speed.

> +    SET_IDREG(isar, ID_ISAR6, 0x00000000);
> +    SET_IDREG(isar, CLIDR, 0x00000000); /* caches not implemented */
> +    cpu->ctr = 0x8303c003;
> +}
> +
>  static const TCGCPUOps arm_v7m_tcg_ops = {
>      /* ARM processors have a weak memory model */
>      .guest_default_memory_order = 0,
> @@ -290,6 +328,8 @@ static const ARMCPUInfo arm_v7m_cpus[] = {
>                               .class_init = arm_v7m_class_init },
>      { .name = "cortex-m55",  .initfn = cortex_m55_initfn,
>                               .class_init = arm_v7m_class_init },
> +    { .name = "cortex-m85",  .initfn = cortex_m85_initfn,
> +                             .class_init = arm_v7m_class_init },
>  };
>  
>  static void arm_v7m_cpu_register_types(void)

-- 
Alex Bennée
Virtualisation Tech Lead @ Linaro