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* [PATCH] drm/i915: Flush the CSB pointer reset
@ 2019-04-12 11:01 Chris Wilson
  2019-04-12 12:22 ` Mika Kuoppala
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Chris Wilson @ 2019-04-12 11:01 UTC (permalink / raw)
  To: intel-gfx

The HW resets it CSB tail pointer on resetting the engine. Most of the
time. In case it doesn't (and for system resume) we write the expected
value anyway. For extra paranoia, flush the write before we invalidate
the cacheline.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3cb788a223ef..4e0a351bfbca 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1866,6 +1866,7 @@ static void reset_csb_pointers(struct intel_engine_execlists *execlists)
 	 */
 	execlists->csb_head = reset_value;
 	WRITE_ONCE(*execlists->csb_write, reset_value);
+	wmb(); /* Make sure this is visible to HW (paranoia?) */
 
 	invalidate_csb_entries(&execlists->csb_status[0],
 			       &execlists->csb_status[reset_value]);
-- 
2.20.1

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^ permalink raw reply related	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2019-04-12 16:30 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-04-12 11:01 [PATCH] drm/i915: Flush the CSB pointer reset Chris Wilson
2019-04-12 12:22 ` Mika Kuoppala
2019-04-12 12:28   ` Chris Wilson
2019-04-12 12:42     ` Mika Kuoppala
2019-04-12 14:32 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-04-12 16:30 ` ✓ Fi.CI.IGT: " Patchwork

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