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From: "Alex Bennée" <alex.bennee@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org,
	Michael Davidsaver <mdavidsaver@gmail.com>,
	Liviu Ionescu <ilg@livius.net>
Subject: Re: [PATCH 6/9] armv7m: Escalate exceptions to HardFault if necessary
Date: Wed, 15 Feb 2017 14:15:49 +0000	[thread overview]
Message-ID: <87h93vv8tm.fsf@linaro.org> (raw)
In-Reply-To: <1486065742-28639-7-git-send-email-peter.maydell@linaro.org>


Peter Maydell <peter.maydell@linaro.org> writes:

> From: Michael Davidsaver <mdavidsaver@gmail.com>
>
> The v7M exception architecture requires that if a synchronous
> exception cannot be taken immediately (because it is disabled
> or at too low a priority) then it should be escalated to
> HardFault (and the HardFault exception is then taken).
> Implement this escalation logic.
>
> Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
> [PMM: extracted from another patch]
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

> ---
>  hw/intc/armv7m_nvic.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++
>  target/arm/helper.c   |  2 --
>  2 files changed, 53 insertions(+), 2 deletions(-)
>
> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
> index 3d77cbf..2eaac3d 100644
> --- a/hw/intc/armv7m_nvic.c
> +++ b/hw/intc/armv7m_nvic.c
> @@ -334,6 +334,59 @@ void armv7m_nvic_set_pending(void *opaque, int irq)
>
>      vec = &s->vectors[irq];
>      trace_nvic_set_pending(irq, vec->enabled, vec->prio);
> +
> +
> +    if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) {
> +        /* If a synchronous exception is pending then it may be
> +         * escalated to HardFault if:
> +         *  * it is equal or lower priority to current execution
> +         *  * it is disabled
> +         * (ie we need to take it immediately but we can't do so).
> +         * Asynchronous exceptions (and interrupts) simply remain pending.
> +         *
> +         * For QEMU, we don't have any imprecise (asynchronous) faults,
> +         * so we can assume that PREFETCH_ABORT and DATA_ABORT are always
> +         * synchronous.
> +         * Debug exceptions are awkward because only Debug exceptions
> +         * resulting from the BKPT instruction should be escalated,
> +         * but we don't currently implement any Debug exceptions other
> +         * than those that result from BKPT, so we treat all debug exceptions
> +         * as needing escalation.
> +         *
> +         * This all means we can identify whether to escalate based only on
> +         * the exception number and don't (yet) need the caller to explicitly
> +         * tell us whether this exception is synchronous or not.
> +         */
> +        int running = nvic_exec_prio(s);
> +        bool escalate = false;
> +
> +        if (vec->prio >= running) {
> +            trace_nvic_escalate_prio(irq, vec->prio, running);
> +            escalate = true;
> +        } else if (!vec->enabled) {
> +            trace_nvic_escalate_disabled(irq);
> +            escalate = true;
> +        }
> +
> +        if (escalate) {
> +            if (running < 0) {
> +                /* We want to escalate to HardFault but we can't take a
> +                 * synchronous HardFault at this point either. This is a
> +                 * Lockup condition due to a guest bug. We don't model
> +                 * Lockup, so report via cpu_abort() instead.
> +                 */
> +                cpu_abort(&s->cpu->parent_obj,
> +                          "Lockup: can't escalate %d to HardFault "
> +                          "(current priority %d)\n", irq, running);
> +            }
> +
> +            /* We can do the escalation, so we take HardFault instead */
> +            irq = ARMV7M_EXCP_HARD;
> +            vec = &s->vectors[irq];
> +            s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
> +        }
> +    }
> +
>      if (!vec->pending) {
>          vec->pending = 1;
>          nvic_irq_update(s);
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index c23df1b..6c86eac 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -6067,8 +6067,6 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
>
>      /* For exceptions we just mark as pending on the NVIC, and let that
>         handle it.  */
> -    /* TODO: Need to escalate if the current priority is higher than the
> -       one we're raising.  */
>      switch (cs->exception_index) {
>      case EXCP_UDEF:
>          armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);


--
Alex Bennée

WARNING: multiple messages have this Message-ID (diff)
From: "Alex Bennée" <alex.bennee@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org,
	Michael Davidsaver <mdavidsaver@gmail.com>,
	Liviu Ionescu <ilg@livius.net>
Subject: Re: [Qemu-devel] [PATCH 6/9] armv7m: Escalate exceptions to HardFault if necessary
Date: Wed, 15 Feb 2017 14:15:49 +0000	[thread overview]
Message-ID: <87h93vv8tm.fsf@linaro.org> (raw)
In-Reply-To: <1486065742-28639-7-git-send-email-peter.maydell@linaro.org>


Peter Maydell <peter.maydell@linaro.org> writes:

> From: Michael Davidsaver <mdavidsaver@gmail.com>
>
> The v7M exception architecture requires that if a synchronous
> exception cannot be taken immediately (because it is disabled
> or at too low a priority) then it should be escalated to
> HardFault (and the HardFault exception is then taken).
> Implement this escalation logic.
>
> Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
> [PMM: extracted from another patch]
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

> ---
>  hw/intc/armv7m_nvic.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++
>  target/arm/helper.c   |  2 --
>  2 files changed, 53 insertions(+), 2 deletions(-)
>
> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
> index 3d77cbf..2eaac3d 100644
> --- a/hw/intc/armv7m_nvic.c
> +++ b/hw/intc/armv7m_nvic.c
> @@ -334,6 +334,59 @@ void armv7m_nvic_set_pending(void *opaque, int irq)
>
>      vec = &s->vectors[irq];
>      trace_nvic_set_pending(irq, vec->enabled, vec->prio);
> +
> +
> +    if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) {
> +        /* If a synchronous exception is pending then it may be
> +         * escalated to HardFault if:
> +         *  * it is equal or lower priority to current execution
> +         *  * it is disabled
> +         * (ie we need to take it immediately but we can't do so).
> +         * Asynchronous exceptions (and interrupts) simply remain pending.
> +         *
> +         * For QEMU, we don't have any imprecise (asynchronous) faults,
> +         * so we can assume that PREFETCH_ABORT and DATA_ABORT are always
> +         * synchronous.
> +         * Debug exceptions are awkward because only Debug exceptions
> +         * resulting from the BKPT instruction should be escalated,
> +         * but we don't currently implement any Debug exceptions other
> +         * than those that result from BKPT, so we treat all debug exceptions
> +         * as needing escalation.
> +         *
> +         * This all means we can identify whether to escalate based only on
> +         * the exception number and don't (yet) need the caller to explicitly
> +         * tell us whether this exception is synchronous or not.
> +         */
> +        int running = nvic_exec_prio(s);
> +        bool escalate = false;
> +
> +        if (vec->prio >= running) {
> +            trace_nvic_escalate_prio(irq, vec->prio, running);
> +            escalate = true;
> +        } else if (!vec->enabled) {
> +            trace_nvic_escalate_disabled(irq);
> +            escalate = true;
> +        }
> +
> +        if (escalate) {
> +            if (running < 0) {
> +                /* We want to escalate to HardFault but we can't take a
> +                 * synchronous HardFault at this point either. This is a
> +                 * Lockup condition due to a guest bug. We don't model
> +                 * Lockup, so report via cpu_abort() instead.
> +                 */
> +                cpu_abort(&s->cpu->parent_obj,
> +                          "Lockup: can't escalate %d to HardFault "
> +                          "(current priority %d)\n", irq, running);
> +            }
> +
> +            /* We can do the escalation, so we take HardFault instead */
> +            irq = ARMV7M_EXCP_HARD;
> +            vec = &s->vectors[irq];
> +            s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
> +        }
> +    }
> +
>      if (!vec->pending) {
>          vec->pending = 1;
>          nvic_irq_update(s);
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index c23df1b..6c86eac 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -6067,8 +6067,6 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
>
>      /* For exceptions we just mark as pending on the NVIC, and let that
>         handle it.  */
> -    /* TODO: Need to escalate if the current priority is higher than the
> -       one we're raising.  */
>      switch (cs->exception_index) {
>      case EXCP_UDEF:
>          armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);


--
Alex Bennée

  reply	other threads:[~2017-02-15 14:15 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-02 20:02 [PATCH 0/9] Rewrite NVIC to not depend on the GIC Peter Maydell
2017-02-02 20:02 ` [Qemu-devel] " Peter Maydell
2017-02-02 20:02 ` [PATCH 1/9] armv7m: Rename nvic_state to NVICState Peter Maydell
2017-02-02 20:02   ` [Qemu-devel] " Peter Maydell
2017-02-10 14:23   ` Philippe Mathieu-Daudé
2017-02-14 17:00   ` Alex Bennée
2017-02-14 17:00     ` [Qemu-devel] " Alex Bennée
2017-02-02 20:02 ` [PATCH 2/9] armv7m: Implement reading and writing of PRIGROUP Peter Maydell
2017-02-02 20:02   ` [Qemu-devel] " Peter Maydell
2017-02-10 14:27   ` Philippe Mathieu-Daudé
2017-02-14 17:08   ` Alex Bennée
2017-02-14 17:08     ` [Qemu-devel] " Alex Bennée
2017-02-02 20:02 ` [PATCH 3/9] armv7m: Rewrite NVIC to not use any GIC code Peter Maydell
2017-02-02 20:02   ` [Qemu-devel] " Peter Maydell
2017-02-15 12:46   ` Alex Bennée
2017-02-15 12:46     ` [Qemu-devel] " Alex Bennée
2017-02-15 13:34     ` Peter Maydell
2017-02-15 13:34       ` [Qemu-devel] " Peter Maydell
2017-02-15 14:14       ` Alex Bennée
2017-02-15 14:14         ` [Qemu-devel] " Alex Bennée
2017-02-15 14:27         ` Peter Maydell
2017-02-15 14:27           ` [Qemu-devel] " Peter Maydell
2017-02-15 14:51           ` Alex Bennée
2017-02-15 14:51             ` [Qemu-devel] " Alex Bennée
2017-02-16 14:11       ` Peter Maydell
2017-02-16 14:11         ` [Qemu-devel] " Peter Maydell
2017-02-18 17:45         ` Michael Davidsaver
2017-02-18 17:45           ` [Qemu-devel] " Michael Davidsaver
2017-02-18 18:38           ` Peter Maydell
2017-02-18 18:38             ` [Qemu-devel] " Peter Maydell
2017-02-19 18:10             ` Michael Davidsaver
2017-02-19 18:10               ` [Qemu-devel] " Michael Davidsaver
2017-02-16 16:12       ` Peter Maydell
2017-02-16 16:12         ` [Qemu-devel] " Peter Maydell
2017-02-02 20:02 ` [PATCH 4/9] armv7m: Fix condition check for taking exceptions Peter Maydell
2017-02-02 20:02   ` [Qemu-devel] " Peter Maydell
2017-02-15 12:48   ` Alex Bennée
2017-02-15 12:48     ` [Qemu-devel] " Alex Bennée
2017-02-02 20:02 ` [PATCH 5/9] arm: gic: Remove references to NVIC Peter Maydell
2017-02-02 20:02   ` [Qemu-devel] " Peter Maydell
2017-02-15 12:49   ` Alex Bennée
2017-02-15 12:49     ` [Qemu-devel] " Alex Bennée
2017-04-17  3:11   ` Philippe Mathieu-Daudé
2017-02-02 20:02 ` [PATCH 6/9] armv7m: Escalate exceptions to HardFault if necessary Peter Maydell
2017-02-02 20:02   ` [Qemu-devel] " Peter Maydell
2017-02-15 14:15   ` Alex Bennée [this message]
2017-02-15 14:15     ` Alex Bennée
2017-02-02 20:02 ` [PATCH 7/9] armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value Peter Maydell
2017-02-02 20:02   ` [Qemu-devel] " Peter Maydell
2017-02-15 14:16   ` Alex Bennée
2017-02-15 14:16     ` [Qemu-devel] " Alex Bennée
2017-02-02 20:02 ` [PATCH 8/9] armv7m: Simpler and faster exception start Peter Maydell
2017-02-02 20:02   ` [Qemu-devel] " Peter Maydell
2017-02-15 14:18   ` Alex Bennée
2017-02-15 14:18     ` [Qemu-devel] " Alex Bennée
2017-02-02 20:02 ` [PATCH 9/9] armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE Peter Maydell
2017-02-02 20:02   ` [Qemu-devel] " Peter Maydell
2017-02-10 14:31   ` Philippe Mathieu-Daudé
2017-02-15 14:19   ` Alex Bennée
2017-02-15 14:19     ` [Qemu-devel] " Alex Bennée
2017-02-10 14:05 ` [Qemu-arm] [PATCH 0/9] Rewrite NVIC to not depend on the GIC Peter Maydell
2017-02-10 14:05   ` [Qemu-devel] " Peter Maydell

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