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* [PATCH] drm/i915/display: program DBUF_CTL tracker state service to 0x8
@ 2024-12-16 12:45 Ravi Kumar Vodapalli
  2024-12-16 13:14 ` Jani Nikula
  0 siblings, 1 reply; 3+ messages in thread
From: Ravi Kumar Vodapalli @ 2024-12-16 12:45 UTC (permalink / raw)
  To: intel-gfx
  Cc: balasubramani.vivekanandan, matthew.d.roper, lucas.demarchi,
	gustavo.sousa, clinton.a.taylor, matthew.s.atwood,
	dnyaneshwar.bhadane, haridhar.kalvala, shekhar.chauhan

Program Tracker state service(DBUF_CTL Register) for TGLLP, SVL,
RYF, DG1, ACM, ACMPLUS, RKLC, RKLGM, ADLS platforms to 0x8 which
is not the default value.

Bspec: 49213
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 34465d56def0..d9ba48b68979 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1126,7 +1126,9 @@ static void gen12_dbuf_slices_config(struct intel_display *display)
 {
 	enum dbuf_slice slice;
 
-	if (display->platform.alderlake_p)
+	if (display->platform.alderlake_p || display->platform.dg2 ||
+	    display->platform.alderlake_p_raptorlake_p ||
+	    DISPLAY_VER(display) >= 14)
 		return;
 
 	for_each_dbuf_slice(display, slice)
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 3+ messages in thread
* [PATCH] drm/i915/display: program DBUF_CTL tracker state service to 0x8
@ 2024-12-16 16:32 Ravi Kumar Vodapalli
  0 siblings, 0 replies; 3+ messages in thread
From: Ravi Kumar Vodapalli @ 2024-12-16 16:32 UTC (permalink / raw)
  To: intel-gfx
  Cc: balasubramani.vivekanandan, matthew.d.roper, lucas.demarchi,
	gustavo.sousa, clinton.a.taylor, matthew.s.atwood,
	dnyaneshwar.bhadane, haridhar.kalvala, shekhar.chauhan

While display initialization along with MBUS credits programming
DBUF_CTL register is also programmed, as a part of it the tracker
state service field is also set to 0x8 value when default value is
other than 0x8. so, for TGLLP, SVL, RYF, DG1, ACM, ACMPLUS, RKLC,
RKLGM and ADLS platforms default value is not 0x8, hence set to 0x8.
For remaining platforms the default value is already 0x8 so no need
to program them.

Bspec: 49213
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 34465d56def0..d9ba48b68979 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1126,7 +1126,9 @@ static void gen12_dbuf_slices_config(struct intel_display *display)
 {
 	enum dbuf_slice slice;
 
-	if (display->platform.alderlake_p)
+	if (display->platform.alderlake_p || display->platform.dg2 ||
+	    display->platform.alderlake_p_raptorlake_p ||
+	    DISPLAY_VER(display) >= 14)
 		return;
 
 	for_each_dbuf_slice(display, slice)
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2024-12-16 16:34 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2024-12-16 12:45 [PATCH] drm/i915/display: program DBUF_CTL tracker state service to 0x8 Ravi Kumar Vodapalli
2024-12-16 13:14 ` Jani Nikula
  -- strict thread matches above, loose matches on Subject: below --
2024-12-16 16:32 Ravi Kumar Vodapalli

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