* [PATCH 2/4] arm64: dts: agilex5: add gmac nodes
2024-10-30 12:10 [PATCH 0/4] ARM64: dts: intel: agilex5: add nodes and new board Steffen Trumtrar
2024-10-30 12:10 ` [PATCH 1/4] arm64: dts: agilex5: add gpio0 Steffen Trumtrar
@ 2024-10-30 12:10 ` Steffen Trumtrar
2024-10-30 12:10 ` [PATCH 3/4] dt-bindings: intel: add agilex5-based Arrow AXE5-Eagle Steffen Trumtrar
` (2 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Steffen Trumtrar @ 2024-10-30 12:10 UTC (permalink / raw)
To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-kernel, netdev, linux-clk, kernel,
Steffen Trumtrar
The Agilex5 provides three Synopsys XGMAC ethernet cores, that can be
used to transmit and receive data at 10M/100M/1G/2.5G over ethernet
connections and enables support for Time Sensitive Networking (TSN)
applications.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 321 +++++++++++++++++++++++++
1 file changed, 321 insertions(+)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 57c28e284cccdb99ede6cea2bc0e8dd8aaf47fe9..761d970f8de59e08275edf15a9c890ba3bb1404c 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -141,6 +141,327 @@ soc: soc@0 {
device_type = "soc";
interrupt-parent = <&intc>;
+ gmac0: ethernet@10810000 {
+ compatible = "altr,socfpga-stmmac-a10-s10",
+ "snps,dwxgmac-2.10",
+ "snps,dwxgmac";
+ reg = <0x10810000 0x3500>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ max-frame-size = <3800>;
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <64>;
+ rx-fifo-depth = <16384>;
+ tx-fifo-depth = <32768>;
+ resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
+ reset-names = "stmmaceth", "stmmaceth-ocp";
+ clocks = <&clkmgr AGILEX5_EMAC0_CLK>,
+ <&clkmgr AGILEX5_EMAC_PTP_CLK>;
+ clock-names = "stmmaceth", "ptp_ref";
+ snps,axi-config = <&stmmac_axi_emac0_setup>;
+ snps,mtl-rx-config = <&mtl_rx_emac0_setup>;
+ snps,mtl-tx-config = <&mtl_tx_emac0_setup>;
+ altr,sysmgr-syscon = <&sysmgr 0x44 0>;
+ status = "disabled";
+
+ stmmac_axi_emac0_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <31>;
+ snps,rd_osr_lmt = <31>;
+ snps,blen = <0 0 0 32 16 8 4>;
+ };
+
+ mtl_rx_emac0_setup: rx-queues-config {
+ snps,rx-queues-to-use = <8>;
+ snps,rx-sched-sp;
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+ queue1 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x1>;
+ };
+ queue2 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x2>;
+ };
+ queue3 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x3>;
+ };
+ queue4 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x4>;
+ };
+ queue5 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x5>;
+ };
+ queue6 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x6>;
+ };
+ queue7 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x7>;
+ };
+ };
+
+ mtl_tx_emac0_setup: tx-queues-config {
+ snps,tx-queues-to-use = <8>;
+ snps,tx-sched-wrr;
+ queue0 {
+ snps,weight = <0x9>;
+ snps,dcb-algorithm;
+ };
+ queue1 {
+ snps,weight = <0x0A>;
+ snps,dcb-algorithm;
+ };
+ queue2 {
+ snps,weight = <0x0B>;
+ snps,dcb-algorithm;
+ };
+ queue3 {
+ snps,weight = <0x0C>;
+ snps,dcb-algorithm;
+ };
+ queue4 {
+ snps,weight = <0x0D>;
+ snps,dcb-algorithm;
+ };
+ queue5 {
+ snps,weight = <0x0E>;
+ snps,dcb-algorithm;
+ };
+ queue6 {
+ snps,weight = <0x0F>;
+ snps,dcb-algorithm;
+ snps,tbs-enable;
+ };
+ queue7 {
+ snps,weight = <0x10>;
+ snps,dcb-algorithm;
+ snps,tbs-enable;
+ };
+ };
+ };
+
+ gmac1: ethernet@10820000 {
+ compatible = "altr,socfpga-stmmac-a10-s10",
+ "snps,dwxgmac-2.10",
+ "snps,dwxgmac";
+ reg = <0x10820000 0x3500>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ max-frame-size = <3800>;
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <64>;
+ rx-fifo-depth = <16384>;
+ tx-fifo-depth = <32768>;
+ resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
+ reset-names = "stmmaceth", "stmmaceth-ocp";
+ clocks = <&clkmgr AGILEX5_EMAC1_CLK>,
+ <&clkmgr AGILEX5_EMAC_PTP_CLK>;
+ clock-names = "stmmaceth", "ptp_ref";
+ snps,axi-config = <&stmmac_axi_emac1_setup>;
+ snps,mtl-rx-config = <&mtl_rx_emac1_setup>;
+ snps,mtl-tx-config = <&mtl_tx_emac1_setup>;
+ altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+ status = "disabled";
+
+ stmmac_axi_emac1_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <31>;
+ snps,rd_osr_lmt = <31>;
+ snps,blen = <0 0 0 32 16 8 4>;
+ };
+
+ mtl_rx_emac1_setup: rx-queues-config {
+ snps,rx-queues-to-use = <8>;
+ snps,rx-sched-sp;
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+ queue1 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x1>;
+ };
+ queue2 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x2>;
+ };
+ queue3 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x3>;
+ };
+ queue4 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x4>;
+ };
+ queue5 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x5>;
+ };
+ queue6 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x6>;
+ };
+ queue7 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x7>;
+ };
+ };
+
+ mtl_tx_emac1_setup: tx-queues-config {
+ snps,tx-queues-to-use = <8>;
+ snps,tx-sched-wrr;
+ queue0 {
+ snps,weight = <0x9>;
+ snps,dcb-algorithm;
+ };
+ queue1 {
+ snps,weight = <0x0A>;
+ snps,dcb-algorithm;
+ };
+ queue2 {
+ snps,weight = <0x0B>;
+ snps,dcb-algorithm;
+ };
+ queue3 {
+ snps,weight = <0x0C>;
+ snps,dcb-algorithm;
+ };
+ queue4 {
+ snps,weight = <0x0D>;
+ snps,dcb-algorithm;
+ };
+ queue5 {
+ snps,weight = <0x0E>;
+ snps,dcb-algorithm;
+ };
+ queue6 {
+ snps,weight = <0x0F>;
+ snps,dcb-algorithm;
+ snps,tbs-enable;
+ };
+ queue7 {
+ snps,weight = <0x10>;
+ snps,dcb-algorithm;
+ snps,tbs-enable;
+ };
+ };
+ };
+
+ gmac2: ethernet@10830000 {
+ compatible = "altr,socfpga-stmmac-a10-s10",
+ "snps,dwxgmac-2.10",
+ "snps,dwxgmac";
+ reg = <0x10830000 0x3500>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ max-frame-size = <3800>;
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <64>;
+ rx-fifo-depth = <16384>;
+ tx-fifo-depth = <32768>;
+ resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
+ reset-names = "stmmaceth", "stmmaceth-ocp";
+ clocks = <&clkmgr AGILEX5_EMAC2_CLK>,
+ <&clkmgr AGILEX5_EMAC_PTP_CLK>;
+ clock-names = "stmmaceth", "ptp_ref";
+ snps,axi-config = <&stmmac_axi_emac2_setup>;
+ snps,mtl-rx-config = <&mtl_rx_emac2_setup>;
+ snps,mtl-tx-config = <&mtl_tx_emac2_setup>;
+ altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
+ status = "disabled";
+
+ stmmac_axi_emac2_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <31>;
+ snps,rd_osr_lmt = <31>;
+ snps,blen = <0 0 0 32 16 8 4>;
+ };
+
+ mtl_rx_emac2_setup: rx-queues-config {
+ snps,rx-queues-to-use = <8>;
+ snps,rx-sched-sp;
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+ queue1 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x1>;
+ };
+ queue2 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x2>;
+ };
+ queue3 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x3>;
+ };
+ queue4 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x4>;
+ };
+ queue5 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x5>;
+ };
+ queue6 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x6>;
+ };
+ queue7 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x7>;
+ };
+ };
+
+ mtl_tx_emac2_setup: tx-queues-config {
+ snps,tx-queues-to-use = <8>;
+ snps,tx-sched-wrr;
+ queue0 {
+ snps,weight = <0x9>;
+ snps,dcb-algorithm;
+ };
+ queue1 {
+ snps,weight = <0x0A>;
+ snps,dcb-algorithm;
+ };
+ queue2 {
+ snps,weight = <0x0B>;
+ snps,dcb-algorithm;
+ };
+ queue3 {
+ snps,weight = <0x0C>;
+ snps,dcb-algorithm;
+ };
+ queue4 {
+ snps,weight = <0x0D>;
+ snps,dcb-algorithm;
+ };
+ queue5 {
+ snps,weight = <0x0E>;
+ snps,dcb-algorithm;
+ };
+ queue6 {
+ snps,weight = <0x0F>;
+ snps,dcb-algorithm;
+ snps,tbs-enable;
+ };
+ queue7 {
+ snps,weight = <0x10>;
+ snps,dcb-algorithm;
+ snps,tbs-enable;
+ };
+ };
+ };
+
clkmgr: clock-controller@10d10000 {
compatible = "intel,agilex5-clkmgr";
reg = <0x10d10000 0x1000>;
--
2.46.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 4/4] arm64: dts: agilex5: initial support for Arrow AXE5-Eagle
2024-10-30 12:10 [PATCH 0/4] ARM64: dts: intel: agilex5: add nodes and new board Steffen Trumtrar
` (2 preceding siblings ...)
2024-10-30 12:10 ` [PATCH 3/4] dt-bindings: intel: add agilex5-based Arrow AXE5-Eagle Steffen Trumtrar
@ 2024-10-30 12:10 ` Steffen Trumtrar
2024-10-30 13:41 ` Andrew Lunn
2024-10-30 14:00 ` Krzysztof Kozlowski
2024-10-30 17:04 ` [PATCH 0/4] ARM64: dts: intel: agilex5: add nodes and new board Rob Herring (Arm)
4 siblings, 2 replies; 11+ messages in thread
From: Steffen Trumtrar @ 2024-10-30 12:10 UTC (permalink / raw)
To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-kernel, netdev, linux-clk, kernel,
Steffen Trumtrar
The Arrow AXE5-Eagle is an Intel Agilex5 SoCFPGA based board with:
- 1x PCIe Gen4.0 edge connector
- 4-port USB HUB
- 2x 1Gb Ethernet
- microSD
- HDMI output
- 2x 10Gb SFP+ cages
As most devices aren't supported mainline yet, this is only the initial
support for the board.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm64/boot/dts/intel/Makefile | 1 +
.../boot/dts/intel/socfpga_agilex5_axe5_eagle.dts | 146 +++++++++++++++++++++
2 files changed, 147 insertions(+)
diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
index d39cfb723f5b6674a821dfdafb21b12668bb1e0e..3e87d548c532b1a9e38f4489c037c5c4db3a50b8 100644
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -3,5 +3,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
socfpga_agilex_socdk.dtb \
socfpga_agilex_socdk_nand.dtb \
socfpga_agilex5_socdk.dtb \
+ socfpga_agilex5_axe5_eagle.dtb \
socfpga_n5x_socdk.dtb
dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dts
new file mode 100644
index 0000000000000000000000000000000000000000..bd5bd8f680c9ade49ac174108beed6828c5a925d
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dts
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024, Arrow Electronics, Inc.
+ */
+#include "socfpga_agilex5.dtsi"
+
+/ {
+ model = "SoCFPGA Agilex5 Arrow AXE5-Eagle";
+ compatible = "arrow,socfpga-agilex5-axe5-eagle", "intel,socfpga-agilex";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ hps0 {
+ label = "hps_led0";
+ gpios = <&porta 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ hps1 {
+ label = "hps_led1";
+ gpios = <&porta 7 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ hps_sw0 {
+ label = "hps_sw0";
+ gpios = <&porta 10 0>;
+ linux,input-type = <5>; /* EV_SW */
+ linux,code = <0x0>;
+ };
+
+ hps_sw1 {
+ label = "hps_sw1";
+ gpios = <&porta 1 0>;
+ linux,input-type = <5>; /* EV_SW */
+ linux,code = <0x0>;
+ };
+
+ hps_pb0 {
+ label = "hps_pb0";
+ gpios = <&porta 8 1>;
+ linux,code = <187>; /* KEY_F17 */
+ };
+
+ hps_pb1 {
+ label = "hps_pb1";
+ gpios = <&porta 9 1>;
+ linux,code = <188>; /* KEY_F18 */
+ };
+ };
+
+ vdd: regulator-vdd {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-supply";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vdd_3_3: regulator-vdd {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+};
+
+&gmac2 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <&emac2_phy0>;
+
+ max-frame-size = <9000>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ emac2_phy0: ethernet-phy@1 {
+ reg = <0x1>;
+ adi,rx-internal-delay-ps = <2000>;
+ adi,tx-internal-delay-ps = <2000>;
+ };
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ tca9544@70 {
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ status = "okay";
+ };
+};
+
+&osc1 {
+ clock-frequency = <25000000>;
+};
+
+&qspi {
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,mt25qu02g", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+
+ m25p,fast-read;
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <2>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
--
2.46.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 0/4] ARM64: dts: intel: agilex5: add nodes and new board
2024-10-30 12:10 [PATCH 0/4] ARM64: dts: intel: agilex5: add nodes and new board Steffen Trumtrar
` (3 preceding siblings ...)
2024-10-30 12:10 ` [PATCH 4/4] arm64: dts: agilex5: initial support for " Steffen Trumtrar
@ 2024-10-30 17:04 ` Rob Herring (Arm)
4 siblings, 0 replies; 11+ messages in thread
From: Rob Herring (Arm) @ 2024-10-30 17:04 UTC (permalink / raw)
To: Steffen Trumtrar
Cc: netdev, Richard Cochran, Michael Turquette, Conor Dooley,
Krzysztof Kozlowski, linux-kernel, linux-clk, Dinh Nguyen,
Stephen Boyd, kernel, devicetree
On Wed, 30 Oct 2024 13:10:11 +0100, Steffen Trumtrar wrote:
> This series adds the gpio0 and gmac nodes to the socfpga_agilex5.dtsi.
>
> An initial devicetree for a new board (Arrow AXE5-Eagle) is also added.
> Currently only QSPI and network are functional as all other hardware
> currently lacks mainline support.
>
> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
> ---
> Steffen Trumtrar (4):
> arm64: dts: agilex5: add gpio0
> arm64: dts: agilex5: add gmac nodes
> dt-bindings: intel: add agilex5-based Arrow AXE5-Eagle
> arm64: dts: agilex5: initial support for Arrow AXE5-Eagle
>
> .../devicetree/bindings/arm/intel,socfpga.yaml | 1 +
> arch/arm64/boot/dts/intel/Makefile | 1 +
> arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 341 +++++++++++++++++++++
> .../boot/dts/intel/socfpga_agilex5_axe5_eagle.dts | 146 +++++++++
> 4 files changed, 489 insertions(+)
> ---
> base-commit: 9852d85ec9d492ebef56dc5f229416c925758edc
> change-id: 20241030-v6-12-topic-socfpga-agilex5-90fd3d8f980c
>
> Best regards,
> --
> Steffen Trumtrar <s.trumtrar@pengutronix.de>
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y intel/socfpga_agilex5_axe5_eagle.dtb' for 20241030-v6-12-topic-socfpga-agilex5-v1-0-b2b67780e60e@pengutronix.de:
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: /: compatible: 'oneOf' conditional failed, one must be fixed:
'arrow,socfpga-agilex5-axe5-eagle' is not one of ['intel,n5x-socdk', 'intel,socfpga-agilex-n6000', 'intel,socfpga-agilex-socdk']
'intel,socfpga-agilex5' was expected
from schema $id: http://devicetree.org/schemas/arm/intel,socfpga.yaml#
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: ethernet@10810000: reset-names: 'oneOf' conditional failed, one must be fixed:
['stmmaceth', 'stmmaceth-ocp'] is too long
'ahb' was expected
from schema $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: ethernet@10810000: tx-queues-config:queue6: 'snps,tbs-enable' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: ethernet@10810000: tx-queues-config:queue7: 'snps,tbs-enable' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: /soc@0/ethernet@10810000: failed to match any schema with compatible: ['altr,socfpga-stmmac-a10-s10', 'snps,dwxgmac-2.10', 'snps,dwxgmac']
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: ethernet@10820000: reset-names: 'oneOf' conditional failed, one must be fixed:
['stmmaceth', 'stmmaceth-ocp'] is too long
'ahb' was expected
from schema $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: ethernet@10820000: tx-queues-config:queue6: 'snps,tbs-enable' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: ethernet@10820000: tx-queues-config:queue7: 'snps,tbs-enable' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: /soc@0/ethernet@10820000: failed to match any schema with compatible: ['altr,socfpga-stmmac-a10-s10', 'snps,dwxgmac-2.10', 'snps,dwxgmac']
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: ethernet@10830000: reset-names: 'oneOf' conditional failed, one must be fixed:
['stmmaceth', 'stmmaceth-ocp'] is too long
'ahb' was expected
from schema $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: ethernet@10830000: tx-queues-config:queue6: 'snps,tbs-enable' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: ethernet@10830000: tx-queues-config:queue7: 'snps,tbs-enable' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: /soc@0/ethernet@10830000: failed to match any schema with compatible: ['altr,socfpga-stmmac-a10-s10', 'snps,dwxgmac-2.10', 'snps,dwxgmac']
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: tca9544@70: $nodename:0: 'tca9544@70' does not match '^(i2c-?)?mux'
from schema $id: http://devicetree.org/schemas/i2c/i2c-mux-pca954x.yaml#
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: tca9544@70: Unevaluated properties are not allowed ('#address-cells', '#size-cells' were unexpected)
from schema $id: http://devicetree.org/schemas/i2c/i2c-mux-pca954x.yaml#
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: /soc@0/nand-controller@10b80000: failed to match any schema with compatible: ['cdns,hp-nfc']
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: /soc@0/sysmgr@10d12000: failed to match any schema with compatible: ['altr,sys-mgr-s10', 'altr,sys-mgr']
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: /soc@0/sysmgr@10d12000: failed to match any schema with compatible: ['altr,sys-mgr-s10', 'altr,sys-mgr']
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: flash@0: Unevaluated properties are not allowed ('cdns,block-size', 'cdns,page-size' were unexpected)
from schema $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: leds: 'hps0', 'hps1' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/leds/leds-gpio.yaml#
arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dtb: gpio-keys: 'hps_pb0', 'hps_pb1', 'hps_sw0', 'hps_sw1' do not match any of the regexes: '^(button|event|key|switch|(button|event|key|switch)-[a-z0-9-]+|[a-z0-9-]+-(button|event|key|switch))$', 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/input/gpio-keys.yaml#
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