From: Marc Zyngier <maz@kernel.org>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Shuah Khan <shuah@kernel.org>,
linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org,
kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v14 3/5] KVM: arm64: Manage GCS access and registers for guests
Date: Sat, 05 Oct 2024 12:34:20 +0100 [thread overview]
Message-ID: <87iku6vl4z.wl-maz@kernel.org> (raw)
In-Reply-To: <20241005-arm64-gcs-v14-3-59060cd6092b@kernel.org>
On Sat, 05 Oct 2024 11:37:30 +0100,
Mark Brown <broonie@kernel.org> wrote:
>
> GCS introduces a number of system registers for EL1 and EL0, on systems
> with GCS we need to context switch them and expose them to VMMs to allow
> guests to use GCS.
>
> In order to allow guests to use GCS we also need to configure
> HCRX_EL2.GCSEn, if this is not set GCS instructions will be noops and
> CHKFEAT will report GCS as disabled. Also enable fine grained traps for
> access to the GCS registers by guests which do not have the feature
> enabled.
>
> In order to allow userspace to control availability of the feature to
> guests we enable writability for only ID_AA64PFR1_EL1.GCS, this is a
> deliberately conservative choice to avoid errors due to oversights.
> Further fields should be made writable in future.
It appears I have accidentally dropped the branch fixing
ID_AA64PFR1_EL1. I'll make sure this goes in as quickly as possible.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/arm64/include/asm/kvm_host.h | 12 ++++++++++++
> arch/arm64/include/asm/vncr_mapping.h | 2 ++
> arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 31 ++++++++++++++++++++++++++++++
> arch/arm64/kvm/sys_regs.c | 31 +++++++++++++++++++++++++++++-
> 4 files changed, 75 insertions(+), 1 deletion(-)
>
[...]
> @@ -4716,6 +4737,14 @@ void kvm_calculate_traps(struct kvm_vcpu *vcpu)
> kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPOR_EL1 |
> HFGxTR_EL2_nPOR_EL0);
>
> + if (!kvm_has_gcs(kvm)) {
> + kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nGCS_EL0 |
> + HFGxTR_EL2_nGCS_EL1);
> + kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_nGCSEPP |
> + HFGITR_EL2_nGCSSTR_EL1 |
> + HFGITR_EL2_nGCSPUSHM_EL1);
Where is the handling of traps resulting of HFGITR_EL2.nGCSSTR_EL1?
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2024-10-05 11:34 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-05 10:37 [PATCH v14 0/5] KVM: arm64: Provide guest support for GCS Mark Brown
2024-10-05 10:37 ` [PATCH v14 1/5] KVM: arm64: Expose S1PIE to guests Mark Brown
2024-10-05 10:37 ` [PATCH v14 2/5] arm64/gcs: Ensure FGTs for EL1 GCS instructions are disabled Mark Brown
2024-10-05 10:37 ` [PATCH v14 3/5] KVM: arm64: Manage GCS access and registers for guests Mark Brown
2024-10-05 11:34 ` Marc Zyngier [this message]
2024-10-05 13:08 ` Mark Brown
2024-10-05 13:18 ` Marc Zyngier
2024-10-05 13:48 ` Mark Brown
2024-10-05 14:02 ` Marc Zyngier
2024-10-05 14:26 ` Mark Brown
2024-10-05 14:33 ` Marc Zyngier
2024-10-05 10:37 ` [PATCH v14 4/5] KVM: arm64: Set PSTATE.EXLOCK when entering an exception Mark Brown
2024-10-05 12:36 ` Marc Zyngier
2024-10-05 14:14 ` Mark Brown
2024-10-05 16:35 ` Marc Zyngier
2024-10-05 10:37 ` [PATCH v14 5/5] KVM: selftests: arm64: Add GCS registers to get-reg-list Mark Brown
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