[RFC 0/4] DP link training failure fallback

[RFC 0/4] DP link training failure fallback

[Arun R Murthy]

The series depicts a working skeleton of the fallback sequence in case
on DP link training failure.
The fallback is currently implemented for DP2.0 only, on similar basis
DP1.4 fallback will come up in the same patch series.
A hotplug event was trigerred in the existing fallback sequence. This
has been removed. On fallback only the link rate and the lane count is
changed for which user need not be notified.
As part of the fallback, the link rate and lane count has to be changed
and these parameters are in intel_crtc_state struct which is passed as
const. The same variables link_rate and lane_count is available in
intel_dp structure. It would be more meaningful to use these for the dp
link training and fallback as well.
As part of cleanup the lane_count in intel_crtc_state structure has to
be removed and the port_clock will have to be used only in crtc
configuration. These changes will be included in this patch series.

Arun R Murthy (4):
  drm/i915/display/dp: Add DP fallback on LT
  drm/i915/display/dp: Dont send hotplug event on LT failure
  drm/i915/dp: use link rate and lane count in intel_dp struct
  drm/i915/display/dp: On LT failure retry LT

 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  16 +--
 drivers/gpu/drm/i915/display/intel_ddi.c      |  31 ++++--
 .../drm/i915/display/intel_ddi_buf_trans.c    |   7 +-
 drivers/gpu/drm/i915/display/intel_dp.c       | 100 +++++++++++++++---
 drivers/gpu/drm/i915/display/intel_dp.h       |   2 +-
 .../drm/i915/display/intel_dp_link_training.c |  86 +++++++--------
 .../drm/i915/display/intel_dp_link_training.h |   2 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |  29 ++---
 8 files changed, 184 insertions(+), 89 deletions(-)

-- 
2.25.1

[RFC 1/4] drm/i915/display/dp: Add DP fallback on LT

[Arun R Murthy]

Fallback mandates on DP link training failure. This patch just covers
the DP2.0 fallback sequence.

TODO: Need to implement the DP1.4 fallback.

Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 92 ++++++++++++++++++++++---
 1 file changed, 82 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 10ec231acd98..82d354a6b0cd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -104,6 +104,50 @@ static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
  */
 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 
+/* DL Link Rates */
+#define UHBR20		2000000
+#define UHBR13P5	1350000
+#define UHBR10		1000000
+#define HBR3		810000
+#define HBR2		540000
+#define HBR		270000
+#define RBR		162000
+
+/* DP Lane Count */
+#define LANE_COUNT_4	4
+#define LANE_COUNT_2	2
+#define LANE_COUNT_1	1
+
+/* DP2.0 fallback values */
+struct dp_fallback {
+	u32 link_rate;
+	u8 lane_count;
+};
+
+struct dp_fallback dp2dot0_fallback[] = {
+	{UHBR20, LANE_COUNT_4},
+	{UHBR13P5, LANE_COUNT_4},
+	{UHBR20, LANE_COUNT_2},
+	{UHBR10, LANE_COUNT_4},
+	{UHBR13P5, LANE_COUNT_2},
+	{HBR3, LANE_COUNT_4},
+	{UHBR20, LANE_COUNT_1},
+	{UHBR10, LANE_COUNT_2},
+	{HBR2, LANE_COUNT_4},
+	{UHBR13P5, LANE_COUNT_1},
+	{HBR3, LANE_COUNT_2},
+	{UHBR10, LANE_COUNT_1},
+	{HBR2, LANE_COUNT_2},
+	{HBR, LANE_COUNT_4},
+	{HBR3, LANE_COUNT_1},
+	{RBR, LANE_COUNT_4},
+	{HBR2, LANE_COUNT_1},
+	{HBR, LANE_COUNT_2},
+	{RBR, LANE_COUNT_2},
+	{HBR, LANE_COUNT_1},
+	{RBR, LANE_COUNT_1},
+};
+
 /**
  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  * @intel_dp: DP struct
@@ -299,6 +343,19 @@ static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 				       intel_dp->num_common_rates, max_rate);
 }
 
+static bool intel_dp_link_rate_supported(struct intel_dp *intel_dp, u32 link_rate)
+{
+	u8 i;
+
+	for (i = 0; i < ARRAY_SIZE(intel_dp->common_rates); i++) {
+		if (intel_dp->common_rates[i] == link_rate)
+			return true;
+		else
+			continue;
+	}
+	return false;
+}
+
 static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
 {
 	if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
@@ -671,15 +728,6 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 	int index;
 
-	/*
-	 * TODO: Enable fallback on MST links once MST link compute can handle
-	 * the fallback params.
-	 */
-	if (intel_dp->is_mst) {
-		drm_err(&i915->drm, "Link Training Unsuccessful\n");
-		return -1;
-	}
-
 	if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
 		drm_dbg_kms(&i915->drm,
 			    "Retrying Link training for eDP with max parameters\n");
@@ -687,6 +735,31 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 		return 0;
 	}
 
+	/* DP fallback values */
+	if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
+		for(index = 0; index < ARRAY_SIZE(dp2dot0_fallback); index++) {
+			if (link_rate == dp2dot0_fallback[index].link_rate &&
+				lane_count == dp2dot0_fallback[index].lane_count) {
+				for(index += 1; index < ARRAY_SIZE(dp2dot0_fallback); index++) {
+					if (intel_dp_link_rate_supported(intel_dp,
+							dp2dot0_fallback[index].link_rate)) {
+						intel_dp_set_link_params(intel_dp,
+								      dp2dot0_fallback[index].link_rate,
+								      dp2dot0_fallback[index].lane_count);
+						drm_dbg_kms(&i915->drm,
+							    "Retrying Link training with link rate %d and lane count %d\n",
+							    dp2dot0_fallback[index].link_rate,
+							    dp2dot0_fallback[index].lane_count);
+						return 0;
+					}
+				}
+			}
+		}
+		/* Report failure and fail link training */
+		drm_err(&i915->drm, "Link Training Unsuccessful\n");
+		return -1;
+	}
+
 	index = intel_dp_rate_index(intel_dp->common_rates,
 				    intel_dp->num_common_rates,
 				    link_rate);
@@ -716,7 +789,6 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 		drm_err(&i915->drm, "Link Training Unsuccessful\n");
 		return -1;
 	}
-
 	return 0;
 }
 
-- 
2.25.1

Re: [RFC 1/4] drm/i915/display/dp: Add DP fallback on LT

[Almahallawy, Khaled]

On Tue, 2024-02-06 at 16:17 +0530, Arun R Murthy wrote:
> Fallback mandates on DP link training failure. This patch just covers
> the DP2.0 fallback sequence.
> 
> TODO: Need to implement the DP1.4 fallback.
> 
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 92 ++++++++++++++++++++++-
> --
>  1 file changed, 82 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 10ec231acd98..82d354a6b0cd 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -104,6 +104,50 @@ static const u8 valid_dsc_bpp[] = {6, 8, 10, 12,
> 15};
>   */
>  static const u8 valid_dsc_slicecount[] = {1, 2, 4};
>  
> +/* DL Link Rates */
> +#define UHBR20		2000000
> +#define UHBR13P5	1350000

Do we have 13.5G support?
Plz check Specs:55726 Note 6

Thanks
Khaled

> +#define UHBR10		1000000
> +#define HBR3		810000
> +#define HBR2		540000
> +#define HBR		270000
> +#define RBR		162000
> +
> +/* DP Lane Count */
> +#define LANE_COUNT_4	4
> +#define LANE_COUNT_2	2
> +#define LANE_COUNT_1	1
> +
> +/* DP2.0 fallback values */
> +struct dp_fallback {
> +	u32 link_rate;
> +	u8 lane_count;
> +};
> +
> +struct dp_fallback dp2dot0_fallback[] = {
> +	{UHBR20, LANE_COUNT_4},
> +	{UHBR13P5, LANE_COUNT_4},
> +	{UHBR20, LANE_COUNT_2},
> +	{UHBR10, LANE_COUNT_4},
> +	{UHBR13P5, LANE_COUNT_2},
> +	{HBR3, LANE_COUNT_4},
> +	{UHBR20, LANE_COUNT_1},
> +	{UHBR10, LANE_COUNT_2},
> +	{HBR2, LANE_COUNT_4},
> +	{UHBR13P5, LANE_COUNT_1},
> +	{HBR3, LANE_COUNT_2},
> +	{UHBR10, LANE_COUNT_1},
> +	{HBR2, LANE_COUNT_2},
> +	{HBR, LANE_COUNT_4},
> +	{HBR3, LANE_COUNT_1},
> +	{RBR, LANE_COUNT_4},
> +	{HBR2, LANE_COUNT_1},
> +	{HBR, LANE_COUNT_2},
> +	{RBR, LANE_COUNT_2},
> +	{HBR, LANE_COUNT_1},
> +	{RBR, LANE_COUNT_1},
> +};
> +
>  /**
>   * intel_dp_is_edp - is the given port attached to an eDP panel
> (either CPU or PCH)
>   * @intel_dp: DP struct
> @@ -299,6 +343,19 @@ static int intel_dp_common_len_rate_limit(const
> struct intel_dp *intel_dp,
>  				       intel_dp->num_common_rates,
> max_rate);
>  }
>  
> +static bool intel_dp_link_rate_supported(struct intel_dp *intel_dp,
> u32 link_rate)
> +{
> +	u8 i;
> +
> +	for (i = 0; i < ARRAY_SIZE(intel_dp->common_rates); i++) {
> +		if (intel_dp->common_rates[i] == link_rate)
> +			return true;
> +		else
> +			continue;
> +	}
> +	return false;
> +}
> +
>  static int intel_dp_common_rate(struct intel_dp *intel_dp, int
> index)
>  {
>  	if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
> @@ -671,15 +728,6 @@ int
> intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>  	int index;
>  
> -	/*
> -	 * TODO: Enable fallback on MST links once MST link compute can
> handle
> -	 * the fallback params.
> -	 */
> -	if (intel_dp->is_mst) {
> -		drm_err(&i915->drm, "Link Training Unsuccessful\n");
> -		return -1;
> -	}
> -
>  	if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
>  		drm_dbg_kms(&i915->drm,
>  			    "Retrying Link training for eDP with max
> parameters\n");
> @@ -687,6 +735,31 @@ int
> intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
>  		return 0;
>  	}
>  
> +	/* DP fallback values */
> +	if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] &
> DP_CAP_ANSI_128B132B) {
> +		for(index = 0; index < ARRAY_SIZE(dp2dot0_fallback);
> index++) {
> +			if (link_rate ==
> dp2dot0_fallback[index].link_rate &&
> +				lane_count ==
> dp2dot0_fallback[index].lane_count) {
> +				for(index += 1; index <
> ARRAY_SIZE(dp2dot0_fallback); index++) {
> +					if
> (intel_dp_link_rate_supported(intel_dp,
> +							dp2dot0_fallbac
> k[index].link_rate)) {
> +						intel_dp_set_link_param
> s(intel_dp,
> +								      d
> p2dot0_fallback[index].link_rate,
> +								      d
> p2dot0_fallback[index].lane_count);
> +						drm_dbg_kms(&i915->drm,
> +							    "Retrying
> Link training with link rate %d and lane count %d\n",
> +							    dp2dot0_fal
> lback[index].link_rate,
> +							    dp2dot0_fal
> lback[index].lane_count);
> +						return 0;
> +					}
> +				}
> +			}
> +		}
> +		/* Report failure and fail link training */
> +		drm_err(&i915->drm, "Link Training Unsuccessful\n");
> +		return -1;
> +	}
> +
>  	index = intel_dp_rate_index(intel_dp->common_rates,
>  				    intel_dp->num_common_rates,
>  				    link_rate);
> @@ -716,7 +789,6 @@ int
> intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
>  		drm_err(&i915->drm, "Link Training Unsuccessful\n");
>  		return -1;
>  	}
> -
>  	return 0;
>  }
>  

RE: [RFC 1/4] drm/i915/display/dp: Add DP fallback on LT

[Murthy, Arun R]

> -----Original Message-----
> From: Almahallawy, Khaled <khaled.almahallawy@intel.com>
> Sent: Wednesday, February 7, 2024 4:11 AM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; Deak, Imre <imre.deak@intel.com>; Syrjala, Ville
> <ville.syrjala@intel.com>
> Subject: Re: [RFC 1/4] drm/i915/display/dp: Add DP fallback on LT
> 
> On Tue, 2024-02-06 at 16:17 +0530, Arun R Murthy wrote:
> > Fallback mandates on DP link training failure. This patch just covers
> > the DP2.0 fallback sequence.
> >
> > TODO: Need to implement the DP1.4 fallback.
> >
> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 92 ++++++++++++++++++++++-
> > --
> >  1 file changed, 82 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 10ec231acd98..82d354a6b0cd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -104,6 +104,50 @@ static const u8 valid_dsc_bpp[] = {6, 8, 10, 12,
> > 15};
> >   */
> >  static const u8 valid_dsc_slicecount[] = {1, 2, 4};
> >
> > +/* DL Link Rates */
> > +#define UHBR20		2000000
> > +#define UHBR13P5	1350000
> 
> Do we have 13.5G support?
> Plz check Specs:55726 Note 6
> 
Long back had posted a patch to remove UHBR13.5(https://patchwork.freedesktop.org/series/119555/), but was rejected. Hence added this.

Thanks and Regards,
Arun R Murthy
--------------------

> Thanks
> Khaled
> 
> > +#define UHBR10		1000000
> > +#define HBR3		810000
> > +#define HBR2		540000
> > +#define HBR		270000
> > +#define RBR		162000
> > +
> > +/* DP Lane Count */
> > +#define LANE_COUNT_4	4
> > +#define LANE_COUNT_2	2
> > +#define LANE_COUNT_1	1
> > +
> > +/* DP2.0 fallback values */
> > +struct dp_fallback {
> > +	u32 link_rate;
> > +	u8 lane_count;
> > +};
> > +
> > +struct dp_fallback dp2dot0_fallback[] = {
> > +	{UHBR20, LANE_COUNT_4},
> > +	{UHBR13P5, LANE_COUNT_4},
> > +	{UHBR20, LANE_COUNT_2},
> > +	{UHBR10, LANE_COUNT_4},
> > +	{UHBR13P5, LANE_COUNT_2},
> > +	{HBR3, LANE_COUNT_4},
> > +	{UHBR20, LANE_COUNT_1},
> > +	{UHBR10, LANE_COUNT_2},
> > +	{HBR2, LANE_COUNT_4},
> > +	{UHBR13P5, LANE_COUNT_1},
> > +	{HBR3, LANE_COUNT_2},
> > +	{UHBR10, LANE_COUNT_1},
> > +	{HBR2, LANE_COUNT_2},
> > +	{HBR, LANE_COUNT_4},
> > +	{HBR3, LANE_COUNT_1},
> > +	{RBR, LANE_COUNT_4},
> > +	{HBR2, LANE_COUNT_1},
> > +	{HBR, LANE_COUNT_2},
> > +	{RBR, LANE_COUNT_2},
> > +	{HBR, LANE_COUNT_1},
> > +	{RBR, LANE_COUNT_1},
> > +};
> > +
> >  /**
> >   * intel_dp_is_edp - is the given port attached to an eDP panel
> > (either CPU or PCH)
> >   * @intel_dp: DP struct
> > @@ -299,6 +343,19 @@ static int intel_dp_common_len_rate_limit(const
> > struct intel_dp *intel_dp,
> >  				       intel_dp->num_common_rates, max_rate);
> }
> >
> > +static bool intel_dp_link_rate_supported(struct intel_dp *intel_dp,
> > u32 link_rate)
> > +{
> > +	u8 i;
> > +
> > +	for (i = 0; i < ARRAY_SIZE(intel_dp->common_rates); i++) {
> > +		if (intel_dp->common_rates[i] == link_rate)
> > +			return true;
> > +		else
> > +			continue;
> > +	}
> > +	return false;
> > +}
> > +
> >  static int intel_dp_common_rate(struct intel_dp *intel_dp, int
> > index)
> >  {
> >  	if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
> > @@ -671,15 +728,6 @@ int
> > intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
> >  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> >  	int index;
> >
> > -	/*
> > -	 * TODO: Enable fallback on MST links once MST link compute can
> > handle
> > -	 * the fallback params.
> > -	 */
> > -	if (intel_dp->is_mst) {
> > -		drm_err(&i915->drm, "Link Training Unsuccessful\n");
> > -		return -1;
> > -	}
> > -
> >  	if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
> >  		drm_dbg_kms(&i915->drm,
> >  			    "Retrying Link training for eDP with max
> parameters\n"); @@
> > -687,6 +735,31 @@ int intel_dp_get_link_train_fallback_values(struct
> > intel_dp *intel_dp,
> >  		return 0;
> >  	}
> >
> > +	/* DP fallback values */
> > +	if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] &
> > DP_CAP_ANSI_128B132B) {
> > +		for(index = 0; index < ARRAY_SIZE(dp2dot0_fallback);
> > index++) {
> > +			if (link_rate ==
> > dp2dot0_fallback[index].link_rate &&
> > +				lane_count ==
> > dp2dot0_fallback[index].lane_count) {
> > +				for(index += 1; index <
> > ARRAY_SIZE(dp2dot0_fallback); index++) {
> > +					if
> > (intel_dp_link_rate_supported(intel_dp,
> > +							dp2dot0_fallbac
> > k[index].link_rate)) {
> > +						intel_dp_set_link_param
> > s(intel_dp,
> > +								      d
> > p2dot0_fallback[index].link_rate,
> > +								      d
> > p2dot0_fallback[index].lane_count);
> > +						drm_dbg_kms(&i915->drm,
> > +							    "Retrying
> > Link training with link rate %d and lane count %d\n",
> > +							    dp2dot0_fal
> > lback[index].link_rate,
> > +							    dp2dot0_fal
> > lback[index].lane_count);
> > +						return 0;
> > +					}
> > +				}
> > +			}
> > +		}
> > +		/* Report failure and fail link training */
> > +		drm_err(&i915->drm, "Link Training Unsuccessful\n");
> > +		return -1;
> > +	}
> > +
> >  	index = intel_dp_rate_index(intel_dp->common_rates,
> >  				    intel_dp->num_common_rates,
> >  				    link_rate);
> > @@ -716,7 +789,6 @@ int
> > intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
> >  		drm_err(&i915->drm, "Link Training Unsuccessful\n");
> >  		return -1;
> >  	}
> > -
> >  	return 0;
> >  }
> >

Re: [RFC 1/4] drm/i915/display/dp: Add DP fallback on LT

[Jani Nikula]

On Tue, 06 Feb 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> Fallback mandates on DP link training failure. This patch just covers
> the DP2.0 fallback sequence.
>
> TODO: Need to implement the DP1.4 fallback.
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 92 ++++++++++++++++++++++---
>  1 file changed, 82 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 10ec231acd98..82d354a6b0cd 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -104,6 +104,50 @@ static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
>   */
>  static const u8 valid_dsc_slicecount[] = {1, 2, 4};
>  
> +/* DL Link Rates */
> +#define UHBR20		2000000
> +#define UHBR13P5	1350000
> +#define UHBR10		1000000
> +#define HBR3		810000
> +#define HBR2		540000
> +#define HBR		270000
> +#define RBR		162000
> +
> +/* DP Lane Count */
> +#define LANE_COUNT_4	4
> +#define LANE_COUNT_2	2
> +#define LANE_COUNT_1	1
> +
> +/* DP2.0 fallback values */
> +struct dp_fallback {
> +	u32 link_rate;
> +	u8 lane_count;
> +};
> +
> +struct dp_fallback dp2dot0_fallback[] = {
> +	{UHBR20, LANE_COUNT_4},
> +	{UHBR13P5, LANE_COUNT_4},
> +	{UHBR20, LANE_COUNT_2},
> +	{UHBR10, LANE_COUNT_4},
> +	{UHBR13P5, LANE_COUNT_2},
> +	{HBR3, LANE_COUNT_4},
> +	{UHBR20, LANE_COUNT_1},
> +	{UHBR10, LANE_COUNT_2},
> +	{HBR2, LANE_COUNT_4},
> +	{UHBR13P5, LANE_COUNT_1},
> +	{HBR3, LANE_COUNT_2},
> +	{UHBR10, LANE_COUNT_1},
> +	{HBR2, LANE_COUNT_2},
> +	{HBR, LANE_COUNT_4},
> +	{HBR3, LANE_COUNT_1},
> +	{RBR, LANE_COUNT_4},
> +	{HBR2, LANE_COUNT_1},
> +	{HBR, LANE_COUNT_2},
> +	{RBR, LANE_COUNT_2},
> +	{HBR, LANE_COUNT_1},
> +	{RBR, LANE_COUNT_1},
> +};
> +
>  /**
>   * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
>   * @intel_dp: DP struct
> @@ -299,6 +343,19 @@ static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
>  				       intel_dp->num_common_rates, max_rate);
>  }
>  
> +static bool intel_dp_link_rate_supported(struct intel_dp *intel_dp, u32 link_rate)
> +{
> +	u8 i;
> +
> +	for (i = 0; i < ARRAY_SIZE(intel_dp->common_rates); i++) {
> +		if (intel_dp->common_rates[i] == link_rate)
> +			return true;
> +		else
> +			continue;
> +	}
> +	return false;
> +}
> +
>  static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
>  {
>  	if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
> @@ -671,15 +728,6 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>  	int index;
>  
> -	/*
> -	 * TODO: Enable fallback on MST links once MST link compute can handle
> -	 * the fallback params.
> -	 */
> -	if (intel_dp->is_mst) {
> -		drm_err(&i915->drm, "Link Training Unsuccessful\n");
> -		return -1;
> -	}
> -

By removing this, the claim is both 8b/10b and 128b/132b DP MST link
training fallbacks work...

>  	if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
>  		drm_dbg_kms(&i915->drm,
>  			    "Retrying Link training for eDP with max parameters\n");
> @@ -687,6 +735,31 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
>  		return 0;
>  	}
>  
> +	/* DP fallback values */
> +	if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {

...but this only addresses 128b/132b, and the 8b/10b MST drops to the
existing SST fallback path.

And with the current code, DP_CAP_ANSI_128B132B does not decide whether
we use DP MST or not. So this will also cover 8b/10b fallback for
displays that support 128b/132b but have DP_MSTM_CAP == 0.

> +		for(index = 0; index < ARRAY_SIZE(dp2dot0_fallback); index++) {
> +			if (link_rate == dp2dot0_fallback[index].link_rate &&
> +				lane_count == dp2dot0_fallback[index].lane_count) {
> +				for(index += 1; index < ARRAY_SIZE(dp2dot0_fallback); index++) {

I honestly do not understand the double looping here, and how index is
managed.

> +					if (intel_dp_link_rate_supported(intel_dp,
> +							dp2dot0_fallback[index].link_rate)) {
> +						intel_dp_set_link_params(intel_dp,
> +								      dp2dot0_fallback[index].link_rate,
> +								      dp2dot0_fallback[index].lane_count);

intel_dp_set_link_params() is supposed to be called in the DP encoder
(pre-)enable paths to set the link rates. If you do it here, the
subsequent enable will just overwrite whatever you did here.

The mechanism in this function should be to to adjust
intel_dp->max_link_rate and intel_dp->max_link_lane_count, and then the
caller will send an uevent to have the userspace do everything again,
but with reduced max values.

This is all very convoluted. And I admit the existing code is also
complex, but this makes it *much* harder to understand.

BR,
Jani.

> +						drm_dbg_kms(&i915->drm,
> +							    "Retrying Link training with link rate %d and lane count %d\n",
> +							    dp2dot0_fallback[index].link_rate,
> +							    dp2dot0_fallback[index].lane_count);
> +						return 0;
> +					}
> +				}
> +			}
> +		}
> +		/* Report failure and fail link training */
> +		drm_err(&i915->drm, "Link Training Unsuccessful\n");
> +		return -1;
> +	}
> +
>  	index = intel_dp_rate_index(intel_dp->common_rates,
>  				    intel_dp->num_common_rates,
>  				    link_rate);
> @@ -716,7 +789,6 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
>  		drm_err(&i915->drm, "Link Training Unsuccessful\n");
>  		return -1;
>  	}
> -
>  	return 0;
>  }

-- 
Jani Nikula, Intel

RE: [RFC 1/4] drm/i915/display/dp: Add DP fallback on LT

[Murthy, Arun R]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, February 13, 2024 11:41 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Deak, Imre <imre.deak@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>
> Subject: Re: [RFC 1/4] drm/i915/display/dp: Add DP fallback on LT
> 
> On Tue, 06 Feb 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> > Fallback mandates on DP link training failure. This patch just covers
> > the DP2.0 fallback sequence.
> >
> > TODO: Need to implement the DP1.4 fallback.
> >
> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 92
> > ++++++++++++++++++++++---
> >  1 file changed, 82 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 10ec231acd98..82d354a6b0cd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -104,6 +104,50 @@ static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
> >   */
> >  static const u8 valid_dsc_slicecount[] = {1, 2, 4};
> >
> > +/* DL Link Rates */
> > +#define UHBR20		2000000
> > +#define UHBR13P5	1350000
> > +#define UHBR10		1000000
> > +#define HBR3		810000
> > +#define HBR2		540000
> > +#define HBR		270000
> > +#define RBR		162000
> > +
> > +/* DP Lane Count */
> > +#define LANE_COUNT_4	4
> > +#define LANE_COUNT_2	2
> > +#define LANE_COUNT_1	1
> > +
> > +/* DP2.0 fallback values */
> > +struct dp_fallback {
> > +	u32 link_rate;
> > +	u8 lane_count;
> > +};
> > +
> > +struct dp_fallback dp2dot0_fallback[] = {
> > +	{UHBR20, LANE_COUNT_4},
> > +	{UHBR13P5, LANE_COUNT_4},
> > +	{UHBR20, LANE_COUNT_2},
> > +	{UHBR10, LANE_COUNT_4},
> > +	{UHBR13P5, LANE_COUNT_2},
> > +	{HBR3, LANE_COUNT_4},
> > +	{UHBR20, LANE_COUNT_1},
> > +	{UHBR10, LANE_COUNT_2},
> > +	{HBR2, LANE_COUNT_4},
> > +	{UHBR13P5, LANE_COUNT_1},
> > +	{HBR3, LANE_COUNT_2},
> > +	{UHBR10, LANE_COUNT_1},
> > +	{HBR2, LANE_COUNT_2},
> > +	{HBR, LANE_COUNT_4},
> > +	{HBR3, LANE_COUNT_1},
> > +	{RBR, LANE_COUNT_4},
> > +	{HBR2, LANE_COUNT_1},
> > +	{HBR, LANE_COUNT_2},
> > +	{RBR, LANE_COUNT_2},
> > +	{HBR, LANE_COUNT_1},
> > +	{RBR, LANE_COUNT_1},
> > +};
> > +
> >  /**
> >   * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or
> PCH)
> >   * @intel_dp: DP struct
> > @@ -299,6 +343,19 @@ static int intel_dp_common_len_rate_limit(const
> struct intel_dp *intel_dp,
> >  				       intel_dp->num_common_rates, max_rate);
> }
> >
> > +static bool intel_dp_link_rate_supported(struct intel_dp *intel_dp,
> > +u32 link_rate) {
> > +	u8 i;
> > +
> > +	for (i = 0; i < ARRAY_SIZE(intel_dp->common_rates); i++) {
> > +		if (intel_dp->common_rates[i] == link_rate)
> > +			return true;
> > +		else
> > +			continue;
> > +	}
> > +	return false;
> > +}
> > +
> >  static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
> > {
> >  	if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
> > @@ -671,15 +728,6 @@ int intel_dp_get_link_train_fallback_values(struct
> intel_dp *intel_dp,
> >  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> >  	int index;
> >
> > -	/*
> > -	 * TODO: Enable fallback on MST links once MST link compute can
> handle
> > -	 * the fallback params.
> > -	 */
> > -	if (intel_dp->is_mst) {
> > -		drm_err(&i915->drm, "Link Training Unsuccessful\n");
> > -		return -1;
> > -	}
> > -
> 
> By removing this, the claim is both 8b/10b and 128b/132b DP MST link training
> fallbacks work...
Yes! This series focuses on the fallback mandates mentioned in DP2.1 spec and doesn't fallback from MST to SST or vicecersa.
Hence if it is MST the fallback will be within MST and if its SST the fallback will be within SST.

> 
> >  	if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
> >  		drm_dbg_kms(&i915->drm,
> >  			    "Retrying Link training for eDP with max
> parameters\n"); @@
> > -687,6 +735,31 @@ int intel_dp_get_link_train_fallback_values(struct
> intel_dp *intel_dp,
> >  		return 0;
> >  	}
> >
> > +	/* DP fallback values */
> > +	if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] &
> > +DP_CAP_ANSI_128B132B) {
> 
> ...but this only addresses 128b/132b, and the 8b/10b MST drops to the existing
> SST fallback path.
Yes! As said above this fallback is based on fallback mandates mentioned in DP2.1 spec in Table 3.31 and Figure 3-52 which focuses on reducing the link rate/lance count and nothing to with MST/SST

> 
> And with the current code, DP_CAP_ANSI_128B132B does not decide whether
> we use DP MST or not. So this will also cover 8b/10b fallback for displays that
> support 128b/132b but have DP_MSTM_CAP == 0.

Yes, the series doent depend on MST and SST and doest fallback from MST to SST or viceversa.

> 
> > +		for(index = 0; index < ARRAY_SIZE(dp2dot0_fallback); index++)
> {
> > +			if (link_rate == dp2dot0_fallback[index].link_rate &&
> > +				lane_count ==
> dp2dot0_fallback[index].lane_count) {
> > +				for(index += 1; index <
> ARRAY_SIZE(dp2dot0_fallback); index++) {
> 
> I honestly do not understand the double looping here, and how index is
> managed.
The first loop is to find the present link rate and lane count in the fallback table. Once we find this, we will have to traverse from that index below to get the next fallback link rate and lane count. The second loop is now to traverse from this index to see the supported link rate and lane count.
For ex: if the link rate is 10Gbps and lane count is 4. First loop is to find this in the fallback table, index would be 3. Then next loop is to traverse from this index 3 to find the fallback values. This would essentially be UHBR13P5 lane count 2. But MTL doesn' support this. Hence will have to move index by 1 to get UHBR10 lane count 2. This second loop will be used for this purpose.

> 
> > +					if
> (intel_dp_link_rate_supported(intel_dp,
> > +
> 	dp2dot0_fallback[index].link_rate)) {
> > +
> 	intel_dp_set_link_params(intel_dp,
> > +
> dp2dot0_fallback[index].link_rate,
> > +
> dp2dot0_fallback[index].lane_count);
> 
> intel_dp_set_link_params() is supposed to be called in the DP encoder (pre-
> )enable paths to set the link rates. If you do it here, the subsequent enable will
> just overwrite whatever you did here.
This is taken care of so as to not override and retain this fallback value.

> 
> The mechanism in this function should be to to adjust intel_dp->max_link_rate
> and intel_dp->max_link_lane_count, and then the caller will send an uevent to
> have the userspace do everything again, but with reduced max values.
> 
If falling back within UHBR rate, so with a mode that supports the new fallback link rate then we don't essentially have to send uevent to user and new modeset may not be required.
For Ex: the link rate is 20Gbps with mode 6k, Link training fails. So with the new fallback linkrate falling within UHBR need not do a modeset. Only if the fallback link rate falls to HBR rate for which 6k is not supported, only then uevent will be sent to user.

> This is all very convoluted. And I admit the existing code is also complex, but
> this makes it *much* harder to understand.
> 
Hopefully upon cleaning up some redundant code and re-arranging this implementation with a formal patch traversing the fallback code might become a little simple.

Thanks and Regards,
Arun R Murthy
--------------------
> BR,
> Jani.
> 
> > +						drm_dbg_kms(&i915->drm,
> > +							    "Retrying Link
> training with link rate %d and lane count %d\n",
> > +
> dp2dot0_fallback[index].link_rate,
> > +
> dp2dot0_fallback[index].lane_count);
> > +						return 0;
> > +					}
> > +				}
> > +			}
> > +		}
> > +		/* Report failure and fail link training */
> > +		drm_err(&i915->drm, "Link Training Unsuccessful\n");
> > +		return -1;
> > +	}
> > +
> >  	index = intel_dp_rate_index(intel_dp->common_rates,
> >  				    intel_dp->num_common_rates,
> >  				    link_rate);
> > @@ -716,7 +789,6 @@ int intel_dp_get_link_train_fallback_values(struct
> intel_dp *intel_dp,
> >  		drm_err(&i915->drm, "Link Training Unsuccessful\n");
> >  		return -1;
> >  	}
> > -
> >  	return 0;
> >  }
> 
> --
> Jani Nikula, Intel

RE: [RFC 1/4] drm/i915/display/dp: Add DP fallback on LT

[Jani Nikula]

On Wed, 14 Feb 2024, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani <jani.nikula@intel.com>
>> Sent: Tuesday, February 13, 2024 11:41 PM
>> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-gfx@lists.freedesktop.org
>> Cc: Deak, Imre <imre.deak@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
>> Shankar, Uma <uma.shankar@intel.com>; Murthy, Arun R
>> <arun.r.murthy@intel.com>
>> Subject: Re: [RFC 1/4] drm/i915/display/dp: Add DP fallback on LT
>>
>> On Tue, 06 Feb 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
>> > Fallback mandates on DP link training failure. This patch just covers
>> > the DP2.0 fallback sequence.
>> >
>> > TODO: Need to implement the DP1.4 fallback.
>> >
>> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_dp.c | 92
>> > ++++++++++++++++++++++---
>> >  1 file changed, 82 insertions(+), 10 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> > b/drivers/gpu/drm/i915/display/intel_dp.c
>> > index 10ec231acd98..82d354a6b0cd 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> > @@ -104,6 +104,50 @@ static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
>> >   */
>> >  static const u8 valid_dsc_slicecount[] = {1, 2, 4};
>> >
>> > +/* DL Link Rates */
>> > +#define UHBR20             2000000
>> > +#define UHBR13P5   1350000
>> > +#define UHBR10             1000000
>> > +#define HBR3               810000
>> > +#define HBR2               540000
>> > +#define HBR                270000
>> > +#define RBR                162000
>> > +
>> > +/* DP Lane Count */
>> > +#define LANE_COUNT_4       4
>> > +#define LANE_COUNT_2       2
>> > +#define LANE_COUNT_1       1
>> > +
>> > +/* DP2.0 fallback values */
>> > +struct dp_fallback {
>> > +   u32 link_rate;
>> > +   u8 lane_count;
>> > +};
>> > +
>> > +struct dp_fallback dp2dot0_fallback[] = {
>> > +   {UHBR20, LANE_COUNT_4},
>> > +   {UHBR13P5, LANE_COUNT_4},
>> > +   {UHBR20, LANE_COUNT_2},
>> > +   {UHBR10, LANE_COUNT_4},
>> > +   {UHBR13P5, LANE_COUNT_2},
>> > +   {HBR3, LANE_COUNT_4},
>> > +   {UHBR20, LANE_COUNT_1},
>> > +   {UHBR10, LANE_COUNT_2},
>> > +   {HBR2, LANE_COUNT_4},
>> > +   {UHBR13P5, LANE_COUNT_1},
>> > +   {HBR3, LANE_COUNT_2},
>> > +   {UHBR10, LANE_COUNT_1},
>> > +   {HBR2, LANE_COUNT_2},
>> > +   {HBR, LANE_COUNT_4},
>> > +   {HBR3, LANE_COUNT_1},
>> > +   {RBR, LANE_COUNT_4},
>> > +   {HBR2, LANE_COUNT_1},
>> > +   {HBR, LANE_COUNT_2},
>> > +   {RBR, LANE_COUNT_2},
>> > +   {HBR, LANE_COUNT_1},
>> > +   {RBR, LANE_COUNT_1},
>> > +};
>> > +
>> >  /**
>> >   * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or
>> PCH)
>> >   * @intel_dp: DP struct
>> > @@ -299,6 +343,19 @@ static int intel_dp_common_len_rate_limit(const
>> struct intel_dp *intel_dp,
>> >                                    intel_dp->num_common_rates, max_rate);
>> }
>> >
>> > +static bool intel_dp_link_rate_supported(struct intel_dp *intel_dp,
>> > +u32 link_rate) {
>> > +   u8 i;
>> > +
>> > +   for (i = 0; i < ARRAY_SIZE(intel_dp->common_rates); i++) {
>> > +           if (intel_dp->common_rates[i] == link_rate)
>> > +                   return true;
>> > +           else
>> > +                   continue;
>> > +   }
>> > +   return false;
>> > +}
>> > +
>> >  static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
>> > {
>> >     if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
>> > @@ -671,15 +728,6 @@ int intel_dp_get_link_train_fallback_values(struct
>> intel_dp *intel_dp,
>> >     struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>> >     int index;
>> >
>> > -   /*
>> > -    * TODO: Enable fallback on MST links once MST link compute can
>> handle
>> > -    * the fallback params.
>> > -    */
>> > -   if (intel_dp->is_mst) {
>> > -           drm_err(&i915->drm, "Link Training Unsuccessful\n");
>> > -           return -1;
>> > -   }
>> > -
>>
>> By removing this, the claim is both 8b/10b and 128b/132b DP MST link training
>> fallbacks work...
> Yes! This series focuses on the fallback mandates mentioned in DP2.1 spec and doesn't fallback from MST to SST or vicecersa.
> Hence if it is MST the fallback will be within MST and if its SST the fallback will be within SST.
>
>>
>> >     if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
>> >             drm_dbg_kms(&i915->drm,
>> >                         "Retrying Link training for eDP with max
>> parameters\n"); @@
>> > -687,6 +735,31 @@ int intel_dp_get_link_train_fallback_values(struct
>> intel_dp *intel_dp,
>> >             return 0;
>> >     }
>> >
>> > +   /* DP fallback values */
>> > +   if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] &
>> > +DP_CAP_ANSI_128B132B) {
>>
>> ...but this only addresses 128b/132b, and the 8b/10b MST drops to the existing
>> SST fallback path.
> Yes! As said above this fallback is based on fallback mandates mentioned in DP2.1 spec in Table 3.31 and Figure 3-52 which focuses on reducing the link rate/lance count and nothing to with MST/SST
>
>>
>> And with the current code, DP_CAP_ANSI_128B132B does not decide whether
>> we use DP MST or not. So this will also cover 8b/10b fallback for displays that
>> support 128b/132b but have DP_MSTM_CAP == 0.
>
> Yes, the series doent depend on MST and SST and doest fallback from MST to SST or viceversa.

What I'm saying is, this changes the way 8b/10b link training fallback
is handled.

First, it starts handling 8b/10b MST link training fallback.

Second, it changes the way 8b/10b *and* 128b/132b *and* SST *and* MST
link training fallback is handled for all displays that support
128b/132b channel coding.

That's *wildly* too much in one patch.

It also duplicates the existing code in the same function, with a
different mechanism. We don't want to have two different ways to do
this, and of all things based on sink's 128b/132b cap. Just one.

>
>>
>> > +           for(index = 0; index < ARRAY_SIZE(dp2dot0_fallback); index++)
>> {
>> > +                   if (link_rate == dp2dot0_fallback[index].link_rate &&
>> > +                           lane_count ==
>> dp2dot0_fallback[index].lane_count) {
>> > +                           for(index += 1; index <
>> ARRAY_SIZE(dp2dot0_fallback); index++) {
>>
>> I honestly do not understand the double looping here, and how index is
>> managed.
> The first loop is to find the present link rate and lane count in the fallback table. Once we find this, we will have to traverse from that index below to get the next fallback link rate and lane count. The second loop is now to traverse from this index to see the supported link rate and lane count.
> For ex: if the link rate is 10Gbps and lane count is 4. First loop is to find this in the fallback table, index would be 3. Then next loop is to traverse from this index 3 to find the fallback values. This would essentially be UHBR13P5 lane count 2. But MTL doesn' support this. Hence will have to move index by 1 to get UHBR10 lane count 2. This second loop will be used for this purpose.

Needs abstractions i.e. more functions instead of trying to make it all
happen in one loop.

>
>>
>> > +                                   if
>> (intel_dp_link_rate_supported(intel_dp,
>> > +
>>       dp2dot0_fallback[index].link_rate)) {
>> > +
>>       intel_dp_set_link_params(intel_dp,
>> > +
>> dp2dot0_fallback[index].link_rate,
>> > +
>> dp2dot0_fallback[index].lane_count);
>>
>> intel_dp_set_link_params() is supposed to be called in the DP encoder (pre-
>> )enable paths to set the link rates. If you do it here, the subsequent enable will
>> just overwrite whatever you did here.
> This is taken care of so as to not override and retain this fallback value.

I don't understand.

>
>>
>> The mechanism in this function should be to to adjust intel_dp->max_link_rate
>> and intel_dp->max_link_lane_count, and then the caller will send an uevent to
>> have the userspace do everything again, but with reduced max values.
>>
> If falling back within UHBR rate, so with a mode that supports the new fallback link rate then we don't essentially have to send uevent to user and new modeset may not be required.
> For Ex: the link rate is 20Gbps with mode 6k, Link training fails. So with the new fallback linkrate falling within UHBR need not do a modeset. Only if the fallback link rate falls to HBR rate for which 6k is not supported, only then uevent will be sent to user.

For SST paths we'll always choose the optimal link parameters, and the
mode will not fit if we have to reduce the parameters. And as I just
explained, your changes impact SST paths as well.

For MST we'll start with max parameters, so yeah there's a possibility
we could reduce the link parameters without having to reduce the
mode. However, I'm inclined to always go through userspace here, using
the same tested paths for link training failures. This will also give
userspace some form of transparency into what is going on, and why an
additional MST stream might not fit when it should.

>> This is all very convoluted. And I admit the existing code is also complex, but
>> this makes it *much* harder to understand.
>>
> Hopefully upon cleaning up some redundant code and re-arranging this implementation with a formal patch traversing the fallback code might become a little simple.

If we want to use a list for the parameters, I think the first step
should be to modify the existing code to use the list. No additional
changes, no functional changes.

BR,
Jani.

>
> Thanks and Regards,
> Arun R Murthy
> --------------------
>> BR,
>> Jani.
>>
>> > +                                           drm_dbg_kms(&i915->drm,
>> > +                                                       "Retrying Link
>> training with link rate %d and lane count %d\n",
>> > +
>> dp2dot0_fallback[index].link_rate,
>> > +
>> dp2dot0_fallback[index].lane_count);
>> > +                                           return 0;
>> > +                                   }
>> > +                           }
>> > +                   }
>> > +           }
>> > +           /* Report failure and fail link training */
>> > +           drm_err(&i915->drm, "Link Training Unsuccessful\n");
>> > +           return -1;
>> > +   }
>> > +
>> >     index = intel_dp_rate_index(intel_dp->common_rates,
>> >                                 intel_dp->num_common_rates,
>> >                                 link_rate);
>> > @@ -716,7 +789,6 @@ int intel_dp_get_link_train_fallback_values(struct
>> intel_dp *intel_dp,
>> >             drm_err(&i915->drm, "Link Training Unsuccessful\n");
>> >             return -1;
>> >     }
>> > -
>> >     return 0;
>> >  }
>>
>> --
>> Jani Nikula, Intel

-- 
Jani Nikula, Intel

RE: [RFC 1/4] drm/i915/display/dp: Add DP fallback on LT

[Murthy, Arun R]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Wednesday, February 14, 2024 4:54 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Deak, Imre <imre.deak@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>
> Subject: RE: [RFC 1/4] drm/i915/display/dp: Add DP fallback on LT
> 
> On Wed, 14 Feb 2024, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> >> -----Original Message-----
> >> From: Nikula, Jani <jani.nikula@intel.com>
> >> Sent: Tuesday, February 13, 2024 11:41 PM
> >> To: Murthy, Arun R <arun.r.murthy@intel.com>;
> >> intel-gfx@lists.freedesktop.org
> >> Cc: Deak, Imre <imre.deak@intel.com>; Syrjala, Ville
> >> <ville.syrjala@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> >> Murthy, Arun R <arun.r.murthy@intel.com>
> >> Subject: Re: [RFC 1/4] drm/i915/display/dp: Add DP fallback on LT
> >>
> >> On Tue, 06 Feb 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> >> > Fallback mandates on DP link training failure. This patch just
> >> > covers the DP2.0 fallback sequence.
> >> >
> >> > TODO: Need to implement the DP1.4 fallback.
> >> >
> >> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/display/intel_dp.c | 92
> >> > ++++++++++++++++++++++---
> >> >  1 file changed, 82 insertions(+), 10 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> >> > b/drivers/gpu/drm/i915/display/intel_dp.c
> >> > index 10ec231acd98..82d354a6b0cd 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> > @@ -104,6 +104,50 @@ static const u8 valid_dsc_bpp[] = {6, 8, 10, 12,
> 15};
> >> >   */
> >> >  static const u8 valid_dsc_slicecount[] = {1, 2, 4};
> >> >
> >> > +/* DL Link Rates */
> >> > +#define UHBR20             2000000
> >> > +#define UHBR13P5   1350000
> >> > +#define UHBR10             1000000
> >> > +#define HBR3               810000
> >> > +#define HBR2               540000
> >> > +#define HBR                270000
> >> > +#define RBR                162000
> >> > +
> >> > +/* DP Lane Count */
> >> > +#define LANE_COUNT_4       4
> >> > +#define LANE_COUNT_2       2
> >> > +#define LANE_COUNT_1       1
> >> > +
> >> > +/* DP2.0 fallback values */
> >> > +struct dp_fallback {
> >> > +   u32 link_rate;
> >> > +   u8 lane_count;
> >> > +};
> >> > +
> >> > +struct dp_fallback dp2dot0_fallback[] = {
> >> > +   {UHBR20, LANE_COUNT_4},
> >> > +   {UHBR13P5, LANE_COUNT_4},
> >> > +   {UHBR20, LANE_COUNT_2},
> >> > +   {UHBR10, LANE_COUNT_4},
> >> > +   {UHBR13P5, LANE_COUNT_2},
> >> > +   {HBR3, LANE_COUNT_4},
> >> > +   {UHBR20, LANE_COUNT_1},
> >> > +   {UHBR10, LANE_COUNT_2},
> >> > +   {HBR2, LANE_COUNT_4},
> >> > +   {UHBR13P5, LANE_COUNT_1},
> >> > +   {HBR3, LANE_COUNT_2},
> >> > +   {UHBR10, LANE_COUNT_1},
> >> > +   {HBR2, LANE_COUNT_2},
> >> > +   {HBR, LANE_COUNT_4},
> >> > +   {HBR3, LANE_COUNT_1},
> >> > +   {RBR, LANE_COUNT_4},
> >> > +   {HBR2, LANE_COUNT_1},
> >> > +   {HBR, LANE_COUNT_2},
> >> > +   {RBR, LANE_COUNT_2},
> >> > +   {HBR, LANE_COUNT_1},
> >> > +   {RBR, LANE_COUNT_1},
> >> > +};
> >> > +
> >> >  /**
> >> >   * intel_dp_is_edp - is the given port attached to an eDP panel
> >> > (either CPU or
> >> PCH)
> >> >   * @intel_dp: DP struct
> >> > @@ -299,6 +343,19 @@ static int
> >> > intel_dp_common_len_rate_limit(const
> >> struct intel_dp *intel_dp,
> >> >                                    intel_dp->num_common_rates,
> >> > max_rate);
> >> }
> >> >
> >> > +static bool intel_dp_link_rate_supported(struct intel_dp
> >> > +*intel_dp,
> >> > +u32 link_rate) {
> >> > +   u8 i;
> >> > +
> >> > +   for (i = 0; i < ARRAY_SIZE(intel_dp->common_rates); i++) {
> >> > +           if (intel_dp->common_rates[i] == link_rate)
> >> > +                   return true;
> >> > +           else
> >> > +                   continue;
> >> > +   }
> >> > +   return false;
> >> > +}
> >> > +
> >> >  static int intel_dp_common_rate(struct intel_dp *intel_dp, int
> >> > index) {
> >> >     if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
> >> > @@ -671,15 +728,6 @@ int
> >> > intel_dp_get_link_train_fallback_values(struct
> >> intel_dp *intel_dp,
> >> >     struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> >> >     int index;
> >> >
> >> > -   /*
> >> > -    * TODO: Enable fallback on MST links once MST link compute can
> >> handle
> >> > -    * the fallback params.
> >> > -    */
> >> > -   if (intel_dp->is_mst) {
> >> > -           drm_err(&i915->drm, "Link Training Unsuccessful\n");
> >> > -           return -1;
> >> > -   }
> >> > -
> >>
> >> By removing this, the claim is both 8b/10b and 128b/132b DP MST link
> >> training fallbacks work...
> > Yes! This series focuses on the fallback mandates mentioned in DP2.1 spec and
> doesn't fallback from MST to SST or vicecersa.
> > Hence if it is MST the fallback will be within MST and if its SST the fallback
> will be within SST.
> >
> >>
> >> >     if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
> >> >             drm_dbg_kms(&i915->drm,
> >> >                         "Retrying Link training for eDP with max
> >> parameters\n"); @@
> >> > -687,6 +735,31 @@ int
> >> > intel_dp_get_link_train_fallback_values(struct
> >> intel_dp *intel_dp,
> >> >             return 0;
> >> >     }
> >> >
> >> > +   /* DP fallback values */
> >> > +   if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] &
> >> > +DP_CAP_ANSI_128B132B) {
> >>
> >> ...but this only addresses 128b/132b, and the 8b/10b MST drops to the
> >> existing SST fallback path.
> > Yes! As said above this fallback is based on fallback mandates
> > mentioned in DP2.1 spec in Table 3.31 and Figure 3-52 which focuses on
> > reducing the link rate/lance count and nothing to with MST/SST
> >
> >>
> >> And with the current code, DP_CAP_ANSI_128B132B does not decide
> >> whether we use DP MST or not. So this will also cover 8b/10b fallback
> >> for displays that support 128b/132b but have DP_MSTM_CAP == 0.
> >
> > Yes, the series doent depend on MST and SST and doest fallback from MST to
> SST or viceversa.
> 
> What I'm saying is, this changes the way 8b/10b link training fallback is
> handled.
> 
The first loop has a if condition for 128/132b and is executed only if its 128/132b and if not falls to the existing code. i.e 8/10b link training fallback sequence.

> First, it starts handling 8b/10b MST link training fallback.
> 
As far as I see, at the entry of this function 128/132b is checked and link training fallback values for this obtained and if not link training fallback values for 8/10b is obtained. Have taken care as to not modify the existing 8/10b fallback.

> Second, it changes the way 8b/10b *and* 128b/132b *and* SST *and* MST link
> training fallback is handled for all displays that support 128b/132b channel
> coding.
> 
MST/SST configuration and then the link training happens. This link training by writing to dpcd registers is done over here by sending certain patterns. The fallback in this RFC is done only in this small link training sequence. On failure the handler doesn't return back instead retry from starting of link training is done. MST/SST configuration is not touched upon, if any required for this as part of fallback can be taken up in the next step.
This RFC is aiming to achieve fallback for the link training sequence only.

> That's *wildly* too much in one patch.
> 
Will surely break this into multiple patches based on the functionality.

> It also duplicates the existing code in the same function, with a different
> mechanism. We don't want to have two different ways to do this, and of all
> things based on sink's 128b/132b cap. Just one.
> 

The way for obtaining link training fallback values for 128/132b is done and the same code will be utilized for 8/10b as well but with a different table.
If the RFC is approved then will work on getting this done in a cleaner and optimized way.

> >
> >>
> >> > +           for(index = 0; index < ARRAY_SIZE(dp2dot0_fallback);
> >> > + index++)
> >> {
> >> > +                   if (link_rate == dp2dot0_fallback[index].link_rate &&
> >> > +                           lane_count ==
> >> dp2dot0_fallback[index].lane_count) {
> >> > +                           for(index += 1; index <
> >> ARRAY_SIZE(dp2dot0_fallback); index++) {
> >>
> >> I honestly do not understand the double looping here, and how index
> >> is managed.
> > The first loop is to find the present link rate and lane count in the fallback
> table. Once we find this, we will have to traverse from that index below to get
> the next fallback link rate and lane count. The second loop is now to traverse
> from this index to see the supported link rate and lane count.
> > For ex: if the link rate is 10Gbps and lane count is 4. First loop is to find this in
> the fallback table, index would be 3. Then next loop is to traverse from this
> index 3 to find the fallback values. This would essentially be UHBR13P5 lane
> count 2. But MTL doesn' support this. Hence will have to move index by 1 to get
> UHBR10 lane count 2. This second loop will be used for this purpose.
> 
> Needs abstractions i.e. more functions instead of trying to make it all happen in
> one loop.

Sure will work on this and will float the patch.

> 
> >
> >>
> >> > +                                   if
> >> (intel_dp_link_rate_supported(intel_dp,
> >> > +
> >>       dp2dot0_fallback[index].link_rate)) {
> >> > +
> >>       intel_dp_set_link_params(intel_dp,
> >> > +
> >> dp2dot0_fallback[index].link_rate,
> >> > +
> >> dp2dot0_fallback[index].lane_count);
> >>
> >> intel_dp_set_link_params() is supposed to be called in the DP encoder
> >> (pre- )enable paths to set the link rates. If you do it here, the
> >> subsequent enable will just overwrite whatever you did here.
> > This is taken care of so as to not override and retain this fallback value.
> 
> I don't understand.
> 
With the existing code the driver sends uevent and a new modeset along with dp_init is done and the values will be overwritten. In this RFC we don't send uevent for all the fallback values instead re-iterate only the link training part without touching the dp enable sequence.

> >
> >>
> >> The mechanism in this function should be to to adjust
> >> intel_dp->max_link_rate and intel_dp->max_link_lane_count, and then
> >> the caller will send an uevent to have the userspace do everything again, but
> with reduced max values.
> >>
> > If falling back within UHBR rate, so with a mode that supports the new
> fallback link rate then we don't essentially have to send uevent to user and new
> modeset may not be required.
> > For Ex: the link rate is 20Gbps with mode 6k, Link training fails. So with the
> new fallback linkrate falling within UHBR need not do a modeset. Only if the
> fallback link rate falls to HBR rate for which 6k is not supported, only then
> uevent will be sent to user.
> 
> For SST paths we'll always choose the optimal link parameters, and the mode
> will not fit if we have to reduce the parameters. And as I just explained, your
> changes impact SST paths as well.
> 
> For MST we'll start with max parameters, so yeah there's a possibility we could
> reduce the link parameters without having to reduce the mode. However, I'm
> inclined to always go through userspace here, using the same tested paths for
> link training failures. This will also give userspace some form of transparency
> into what is going on, and why an additional MST stream might not fit when it
> should.
> 
> >> This is all very convoluted. And I admit the existing code is also
> >> complex, but this makes it *much* harder to understand.
> >>
> > Hopefully upon cleaning up some redundant code and re-arranging this
> implementation with a formal patch traversing the fallback code might become
> a little simple.
> 
> If we want to use a list for the parameters, I think the first step should be to
> modify the existing code to use the list. No additional changes, no functional
> changes.
> 
Sure will ensure that would be the first patch in this series before touching upon anything on the 128/132b fallback.

Thanks and Regards,
Arun R Murthy
-------------------

> BR,
> Jani.
> 
> >
> > Thanks and Regards,
> > Arun R Murthy
> > --------------------
> >> BR,
> >> Jani.
> >>
> >> > +                                           drm_dbg_kms(&i915->drm,
> >> > +                                                       "Retrying
> >> > + Link
> >> training with link rate %d and lane count %d\n",
> >> > +
> >> dp2dot0_fallback[index].link_rate,
> >> > +
> >> dp2dot0_fallback[index].lane_count);
> >> > +                                           return 0;
> >> > +                                   }
> >> > +                           }
> >> > +                   }
> >> > +           }
> >> > +           /* Report failure and fail link training */
> >> > +           drm_err(&i915->drm, "Link Training Unsuccessful\n");
> >> > +           return -1;
> >> > +   }
> >> > +
> >> >     index = intel_dp_rate_index(intel_dp->common_rates,
> >> >                                 intel_dp->num_common_rates,
> >> >                                 link_rate); @@ -716,7 +789,6 @@ int
> >> > intel_dp_get_link_train_fallback_values(struct
> >> intel_dp *intel_dp,
> >> >             drm_err(&i915->drm, "Link Training Unsuccessful\n");
> >> >             return -1;
> >> >     }
> >> > -
> >> >     return 0;
> >> >  }
> >>
> >> --
> >> Jani Nikula, Intel
> 
> --
> Jani Nikula, Intel

RE: [RFC 1/4] drm/i915/display/dp: Add DP fallback on LT

[Jani Nikula]

On Wed, 14 Feb 2024, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> >> And with the current code, DP_CAP_ANSI_128B132B does not decide
>> >> whether we use DP MST or not. So this will also cover 8b/10b fallback
>> >> for displays that support 128b/132b but have DP_MSTM_CAP == 0.
>> >
>> > Yes, the series doent depend on MST and SST and doest fallback from MST to
>> SST or viceversa.
>>
>> What I'm saying is, this changes the way 8b/10b link training fallback is
>> handled.
>>
> The first loop has a if condition for 128/132b and is executed only if its 128/132b and if not falls to the existing code. i.e 8/10b link training fallback sequence.

You check for sink 128b/132b capability. Please take the time to
consider what this means. I've tried to explain this a few times now.

>> First, it starts handling 8b/10b MST link training fallback.
>>
> As far as I see, at the entry of this function 128/132b is checked and link training fallback values for this obtained and if not link training fallback values for 8/10b is obtained. Have taken care as to not modify the existing 8/10b fallback.

Same as above.

>> Second, it changes the way 8b/10b *and* 128b/132b *and* SST *and* MST link
>> training fallback is handled for all displays that support 128b/132b channel
>> coding.
>>
> MST/SST configuration and then the link training happens. This link training by writing to dpcd registers is done over here by sending certain patterns. The fallback in this RFC is done only in this small link training sequence. On failure the handler doesn't return back instead retry from starting of link training is done. MST/SST configuration is not touched upon, if any required for this as part of fallback can be taken up in the next step.
> This RFC is aiming to achieve fallback for the link training sequence only.

To be clear, I don't want to change the way link training failure
fallback is handled in general. It should go via userspace. Please let's
just not go there, at all. Changing it does not help us right now, it
just adds another complication, and another code path to test.

But regardless of that, I don't think you rightly appreciate what
implications your changes actually have. The code does not do what you
claim it does. I don't know what else to say.

>> >> intel_dp_set_link_params() is supposed to be called in the DP encoder
>> >> (pre- )enable paths to set the link rates. If you do it here, the
>> >> subsequent enable will just overwrite whatever you did here.
>> > This is taken care of so as to not override and retain this fallback value.
>>
>> I don't understand.
>>
> With the existing code the driver sends uevent and a new modeset along with dp_init is done and the values will be overwritten. In this RFC we don't send uevent for all the fallback values instead re-iterate only the link training part without touching the dp enable sequence.

I any patch series, no matter what you're working on, each patch in the
series must stand on its own merits. Patches can't depend on something
that may or may not be done later in subsequent patches.

BR,
Jani.

-- 
Jani Nikula, Intel

Re: [RFC 1/4] drm/i915/display/dp: Add DP fallback on LT

[Ville Syrjälä]

On Wed, Feb 14, 2024 at 01:23:42PM +0200, Jani Nikula wrote:
> On Wed, 14 Feb 2024, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> >> -----Original Message-----
> >> From: Nikula, Jani <jani.nikula@intel.com>
> >> Sent: Tuesday, February 13, 2024 11:41 PM
> >> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-gfx@lists.freedesktop.org
> >> Cc: Deak, Imre <imre.deak@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
> >> Shankar, Uma <uma.shankar@intel.com>; Murthy, Arun R
> >> <arun.r.murthy@intel.com>
> >> Subject: Re: [RFC 1/4] drm/i915/display/dp: Add DP fallback on LT
> >>
> >> On Tue, 06 Feb 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> >> > Fallback mandates on DP link training failure. This patch just covers
> >> > the DP2.0 fallback sequence.
> >> >
> >> > TODO: Need to implement the DP1.4 fallback.
> >> >
> >> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/display/intel_dp.c | 92
> >> > ++++++++++++++++++++++---
> >> >  1 file changed, 82 insertions(+), 10 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> >> > b/drivers/gpu/drm/i915/display/intel_dp.c
> >> > index 10ec231acd98..82d354a6b0cd 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> > @@ -104,6 +104,50 @@ static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
> >> >   */
> >> >  static const u8 valid_dsc_slicecount[] = {1, 2, 4};
> >> >
> >> > +/* DL Link Rates */
> >> > +#define UHBR20             2000000
> >> > +#define UHBR13P5   1350000
> >> > +#define UHBR10             1000000
> >> > +#define HBR3               810000
> >> > +#define HBR2               540000
> >> > +#define HBR                270000
> >> > +#define RBR                162000
> >> > +
> >> > +/* DP Lane Count */
> >> > +#define LANE_COUNT_4       4
> >> > +#define LANE_COUNT_2       2
> >> > +#define LANE_COUNT_1       1
> >> > +
> >> > +/* DP2.0 fallback values */
> >> > +struct dp_fallback {
> >> > +   u32 link_rate;
> >> > +   u8 lane_count;
> >> > +};
> >> > +
> >> > +struct dp_fallback dp2dot0_fallback[] = {
> >> > +   {UHBR20, LANE_COUNT_4},
> >> > +   {UHBR13P5, LANE_COUNT_4},
> >> > +   {UHBR20, LANE_COUNT_2},
> >> > +   {UHBR10, LANE_COUNT_4},
> >> > +   {UHBR13P5, LANE_COUNT_2},
> >> > +   {HBR3, LANE_COUNT_4},
> >> > +   {UHBR20, LANE_COUNT_1},
> >> > +   {UHBR10, LANE_COUNT_2},
> >> > +   {HBR2, LANE_COUNT_4},
> >> > +   {UHBR13P5, LANE_COUNT_1},
> >> > +   {HBR3, LANE_COUNT_2},
> >> > +   {UHBR10, LANE_COUNT_1},
> >> > +   {HBR2, LANE_COUNT_2},
> >> > +   {HBR, LANE_COUNT_4},
> >> > +   {HBR3, LANE_COUNT_1},
> >> > +   {RBR, LANE_COUNT_4},
> >> > +   {HBR2, LANE_COUNT_1},
> >> > +   {HBR, LANE_COUNT_2},
> >> > +   {RBR, LANE_COUNT_2},
> >> > +   {HBR, LANE_COUNT_1},
> >> > +   {RBR, LANE_COUNT_1},
> >> > +};
> >> > +
> >> >  /**
> >> >   * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or
> >> PCH)
> >> >   * @intel_dp: DP struct
> >> > @@ -299,6 +343,19 @@ static int intel_dp_common_len_rate_limit(const
> >> struct intel_dp *intel_dp,
> >> >                                    intel_dp->num_common_rates, max_rate);
> >> }
> >> >
> >> > +static bool intel_dp_link_rate_supported(struct intel_dp *intel_dp,
> >> > +u32 link_rate) {
> >> > +   u8 i;
> >> > +
> >> > +   for (i = 0; i < ARRAY_SIZE(intel_dp->common_rates); i++) {
> >> > +           if (intel_dp->common_rates[i] == link_rate)
> >> > +                   return true;
> >> > +           else
> >> > +                   continue;
> >> > +   }
> >> > +   return false;
> >> > +}
> >> > +
> >> >  static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
> >> > {
> >> >     if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
> >> > @@ -671,15 +728,6 @@ int intel_dp_get_link_train_fallback_values(struct
> >> intel_dp *intel_dp,
> >> >     struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> >> >     int index;
> >> >
> >> > -   /*
> >> > -    * TODO: Enable fallback on MST links once MST link compute can
> >> handle
> >> > -    * the fallback params.
> >> > -    */
> >> > -   if (intel_dp->is_mst) {
> >> > -           drm_err(&i915->drm, "Link Training Unsuccessful\n");
> >> > -           return -1;
> >> > -   }
> >> > -
> >>
> >> By removing this, the claim is both 8b/10b and 128b/132b DP MST link training
> >> fallbacks work...
> > Yes! This series focuses on the fallback mandates mentioned in DP2.1 spec and doesn't fallback from MST to SST or vicecersa.
> > Hence if it is MST the fallback will be within MST and if its SST the fallback will be within SST.
> >
> >>
> >> >     if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
> >> >             drm_dbg_kms(&i915->drm,
> >> >                         "Retrying Link training for eDP with max
> >> parameters\n"); @@
> >> > -687,6 +735,31 @@ int intel_dp_get_link_train_fallback_values(struct
> >> intel_dp *intel_dp,
> >> >             return 0;
> >> >     }
> >> >
> >> > +   /* DP fallback values */
> >> > +   if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] &
> >> > +DP_CAP_ANSI_128B132B) {
> >>
> >> ...but this only addresses 128b/132b, and the 8b/10b MST drops to the existing
> >> SST fallback path.
> > Yes! As said above this fallback is based on fallback mandates mentioned in DP2.1 spec in Table 3.31 and Figure 3-52 which focuses on reducing the link rate/lance count and nothing to with MST/SST
> >
> >>
> >> And with the current code, DP_CAP_ANSI_128B132B does not decide whether
> >> we use DP MST or not. So this will also cover 8b/10b fallback for displays that
> >> support 128b/132b but have DP_MSTM_CAP == 0.
> >
> > Yes, the series doent depend on MST and SST and doest fallback from MST to SST or viceversa.
> 
> What I'm saying is, this changes the way 8b/10b link training fallback
> is handled.
> 
> First, it starts handling 8b/10b MST link training fallback.
> 
> Second, it changes the way 8b/10b *and* 128b/132b *and* SST *and* MST
> link training fallback is handled for all displays that support
> 128b/132b channel coding.
> 
> That's *wildly* too much in one patch.
> 
> It also duplicates the existing code in the same function, with a
> different mechanism. We don't want to have two different ways to do
> this, and of all things based on sink's 128b/132b cap. Just one.
> 
> >
> >>
> >> > +           for(index = 0; index < ARRAY_SIZE(dp2dot0_fallback); index++)
> >> {
> >> > +                   if (link_rate == dp2dot0_fallback[index].link_rate &&
> >> > +                           lane_count ==
> >> dp2dot0_fallback[index].lane_count) {
> >> > +                           for(index += 1; index <
> >> ARRAY_SIZE(dp2dot0_fallback); index++) {
> >>
> >> I honestly do not understand the double looping here, and how index is
> >> managed.
> > The first loop is to find the present link rate and lane count in the fallback table. Once we find this, we will have to traverse from that index below to get the next fallback link rate and lane count. The second loop is now to traverse from this index to see the supported link rate and lane count.
> > For ex: if the link rate is 10Gbps and lane count is 4. First loop is to find this in the fallback table, index would be 3. Then next loop is to traverse from this index 3 to find the fallback values. This would essentially be UHBR13P5 lane count 2. But MTL doesn' support this. Hence will have to move index by 1 to get UHBR10 lane count 2. This second loop will be used for this purpose.
> 
> Needs abstractions i.e. more functions instead of trying to make it all
> happen in one loop.
> 
> >
> >>
> >> > +                                   if
> >> (intel_dp_link_rate_supported(intel_dp,
> >> > +
> >>       dp2dot0_fallback[index].link_rate)) {
> >> > +
> >>       intel_dp_set_link_params(intel_dp,
> >> > +
> >> dp2dot0_fallback[index].link_rate,
> >> > +
> >> dp2dot0_fallback[index].lane_count);
> >>
> >> intel_dp_set_link_params() is supposed to be called in the DP encoder (pre-
> >> )enable paths to set the link rates. If you do it here, the subsequent enable will
> >> just overwrite whatever you did here.
> > This is taken care of so as to not override and retain this fallback value.
> 
> I don't understand.
> 
> >
> >>
> >> The mechanism in this function should be to to adjust intel_dp->max_link_rate
> >> and intel_dp->max_link_lane_count, and then the caller will send an uevent to
> >> have the userspace do everything again, but with reduced max values.
> >>
> > If falling back within UHBR rate, so with a mode that supports the new fallback link rate then we don't essentially have to send uevent to user and new modeset may not be required.
> > For Ex: the link rate is 20Gbps with mode 6k, Link training fails. So with the new fallback linkrate falling within UHBR need not do a modeset. Only if the fallback link rate falls to HBR rate for which 6k is not supported, only then uevent will be sent to user.
> 
> For SST paths we'll always choose the optimal link parameters, and the
> mode will not fit if we have to reduce the parameters. And as I just
> explained, your changes impact SST paths as well.
> 
> For MST we'll start with max parameters, so yeah there's a possibility
> we could reduce the link parameters without having to reduce the
> mode. However, I'm inclined to always go through userspace here, using
> the same tested paths for link training failures. This will also give
> userspace some form of transparency into what is going on, and why an
> additional MST stream might not fit when it should.

Sudden loss of link -> try a blind retrain:

   This is rather sketchy as we don't go through the full modeset
   sequence. Probably should replace this by either just always
   punting to userspace, or by just doing a proper atomic commit with
   the current parameters from a work. I'm not sure all userspace/fb-helper
   handle everything correctly so might still want to keep this in kernel...

If link training fails then reduce link parms and punt to userspace:

   This could in theory also try a blind modeset in kernel first and
   if that fails then punt to userspace. Again the concern might be
   that not all userspace is perhaps very good, but I might be wrong
   about that.

Anyways all of that is kinda orthogonal stuff to just getting MST
to reduce its link rate. For that I think we should just need:
 a) remove the MST check from the fallback stuff
 b) handle all the MST connectors on the same link in the retry work

-- 
Ville Syrjälä
Intel

[RFC 2/4] drm/i915/display/dp: Dont send hotplug event on LT failure

[Arun R Murthy]

On link training failure fallback sequence a hotpplu event was sent to
the user, but this is not requried as we are not changing the mode and
instead only changing the link rate and lane count. User has no
dependency with these parameters.

Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 1abfafbbfa75..242cb08e9fc4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1074,8 +1074,6 @@ intel_dp_link_train_phy(struct intel_dp *intel_dp,
 static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
 						     const struct intel_crtc_state *crtc_state)
 {
-	struct intel_connector *intel_connector = intel_dp->attached_connector;
-	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 
 	if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) {
 		lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n");
@@ -1092,8 +1090,7 @@ static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
 		return;
 	}
 
-	/* Schedule a Hotplug Uevent to userspace to start modeset */
-	queue_work(i915->unordered_wq, &intel_connector->modeset_retry_work);
+	/* TODO: Re-visit, sending hotplug is not required. No need to notify user as we are not changing the mode */
 }
 
 /* Perform the link training on all LTTPRs and the DPRX on a link. */
-- 
2.25.1

Re: [RFC 2/4] drm/i915/display/dp: Dont send hotplug event on LT failure

[Jani Nikula]

On Tue, 06 Feb 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> On link training failure fallback sequence a hotpplu event was sent to
> the user, but this is not requried as we are not changing the mode and
> instead only changing the link rate and lane count. User has no
> dependency with these parameters.
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_link_training.c | 5 +----
>  1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 1abfafbbfa75..242cb08e9fc4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -1074,8 +1074,6 @@ intel_dp_link_train_phy(struct intel_dp *intel_dp,
>  static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
>  						     const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_connector *intel_connector = intel_dp->attached_connector;
> -	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>  
>  	if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) {
>  		lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n");
> @@ -1092,8 +1090,7 @@ static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
>  		return;
>  	}
>  
> -	/* Schedule a Hotplug Uevent to userspace to start modeset */
> -	queue_work(i915->unordered_wq, &intel_connector->modeset_retry_work);
> +	/* TODO: Re-visit, sending hotplug is not required. No need to notify user as we are not changing the mode */

Yeah, we're not changing the mode, we're asking the userspace to change
the mode.

BR,
Jani.

>  }
>  
>  /* Perform the link training on all LTTPRs and the DPRX on a link. */

-- 
Jani Nikula, Intel

RE: [RFC 2/4] drm/i915/display/dp: Dont send hotplug event on LT failure

[Murthy, Arun R]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, February 6, 2024 5:10 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Deak, Imre <imre.deak@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>
> Subject: Re: [RFC 2/4] drm/i915/display/dp: Dont send hotplug event on LT
> failure
> 
> On Tue, 06 Feb 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> > On link training failure fallback sequence a hotpplu event was sent to
> > the user, but this is not requried as we are not changing the mode and
> > instead only changing the link rate and lane count. User has no
> > dependency with these parameters.
> >
> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp_link_training.c | 5 +----
> >  1 file changed, 1 insertion(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index 1abfafbbfa75..242cb08e9fc4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -1074,8 +1074,6 @@ intel_dp_link_train_phy(struct intel_dp
> > *intel_dp,  static void intel_dp_schedule_fallback_link_training(struct intel_dp
> *intel_dp,
> >  						     const struct intel_crtc_state
> *crtc_state)  {
> > -	struct intel_connector *intel_connector = intel_dp-
> >attached_connector;
> > -	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> >
> >  	if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) {
> >  		lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on
> disconnected
> > sink.\n"); @@ -1092,8 +1090,7 @@ static void
> intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
> >  		return;
> >  	}
> >
> > -	/* Schedule a Hotplug Uevent to userspace to start modeset */
> > -	queue_work(i915->unordered_wq, &intel_connector-
> >modeset_retry_work);
> > +	/* TODO: Re-visit, sending hotplug is not required. No need to
> > +notify user as we are not changing the mode */
> 
> Yeah, we're not changing the mode, we're asking the userspace to change the
> mode.
As far as I see mode change is not necessity. Link rate and lane count change is internal to KMD.

Thanks and Regards,
Arun R Murthy
--------------------
> 
> BR,
> Jani.
> 
> >  }
> >
> >  /* Perform the link training on all LTTPRs and the DPRX on a link. */
> 
> --
> Jani Nikula, Intel

Re: [RFC 2/4] drm/i915/display/dp: Dont send hotplug event on LT failure

[Almahallawy, Khaled]

On Tue, 2024-02-06 at 15:06 +0000, Murthy, Arun R wrote:
> > -----Original Message-----
> > From: Nikula, Jani <jani.nikula@intel.com>
> > Sent: Tuesday, February 6, 2024 5:10 PM
> > To: Murthy, Arun R <arun.r.murthy@intel.com>; 
> > intel-gfx@lists.freedesktop.org
> > Cc: Deak, Imre <imre.deak@intel.com>; Syrjala, Ville <
> > ville.syrjala@intel.com>;
> > Shankar, Uma <uma.shankar@intel.com>; Murthy, Arun R
> > <arun.r.murthy@intel.com>
> > Subject: Re: [RFC 2/4] drm/i915/display/dp: Dont send hotplug event
> > on LT
> > failure
> > 
> > On Tue, 06 Feb 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> > > On link training failure fallback sequence a hotpplu event was
> > > sent to
> > > the user, but this is not requried as we are not changing the
> > > mode and
> > > instead only changing the link rate and lane count. User has no
> > > dependency with these parameters.
> > > 
> > > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dp_link_training.c | 5 +----
> > >  1 file changed, 1 insertion(+), 4 deletions(-)
> > > 
> > > diff --git
> > > a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > index 1abfafbbfa75..242cb08e9fc4 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > @@ -1074,8 +1074,6 @@ intel_dp_link_train_phy(struct intel_dp
> > > *intel_dp,  static void
> > > intel_dp_schedule_fallback_link_training(struct intel_dp
> > *intel_dp,
> > >  						     const struct
> > > intel_crtc_state
> > *crtc_state)  {
> > > -	struct intel_connector *intel_connector = intel_dp-
> > > attached_connector;
> > > -	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > > 
> > >  	if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)-
> > > >base)) {
> > >  		lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on
> > disconnected
> > > sink.\n"); @@ -1092,8 +1090,7 @@ static void
> > intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
> > >  		return;
> > >  	}
> > > 
> > > -	/* Schedule a Hotplug Uevent to userspace to start modeset */
> > > -	queue_work(i915->unordered_wq, &intel_connector-
> > > modeset_retry_work);
> > > +	/* TODO: Re-visit, sending hotplug is not required. No need to
> > > +notify user as we are not changing the mode */
> > 
> > Yeah, we're not changing the mode, we're asking the userspace to
> > change the
> > mode.
> As far as I see mode change is not necessity. Link rate and lane
> count change is internal to KMD.

Userspace may need to reprobe again in order to ensure that the resolution/refresh rate still fits within the bandwidth provided by LR/LC.
Also I believe this part works with DP1.4 LT fallback when we tested
recently.

Thanks
Khaled
> 
> Thanks and Regards,
> Arun R Murthy
> --------------------
> > BR,
> > Jani.
> > 
> > >  }
> > > 
> > >  /* Perform the link training on all LTTPRs and the DPRX on a
> > > link. */
> > 
> > --
> > Jani Nikula, Intel

RE: [RFC 2/4] drm/i915/display/dp: Dont send hotplug event on LT failure

[Murthy, Arun R]

> -----Original Message-----
> From: Almahallawy, Khaled <khaled.almahallawy@intel.com>
> Sent: Wednesday, February 7, 2024 11:58 AM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Deak, Imre
> <imre.deak@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>
> Subject: Re: [RFC 2/4] drm/i915/display/dp: Dont send hotplug event on LT
> failure
> 
> On Tue, 2024-02-06 at 15:06 +0000, Murthy, Arun R wrote:
> > > -----Original Message-----
> > > From: Nikula, Jani <jani.nikula@intel.com>
> > > Sent: Tuesday, February 6, 2024 5:10 PM
> > > To: Murthy, Arun R <arun.r.murthy@intel.com>;
> > > intel-gfx@lists.freedesktop.org
> > > Cc: Deak, Imre <imre.deak@intel.com>; Syrjala, Ville <
> > > ville.syrjala@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> > > Murthy, Arun R <arun.r.murthy@intel.com>
> > > Subject: Re: [RFC 2/4] drm/i915/display/dp: Dont send hotplug event
> > > on LT failure
> > >
> > > On Tue, 06 Feb 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> > > > On link training failure fallback sequence a hotpplu event was
> > > > sent to the user, but this is not requried as we are not changing
> > > > the mode and instead only changing the link rate and lane count.
> > > > User has no dependency with these parameters.
> > > >
> > > > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_dp_link_training.c | 5 +----
> > > >  1 file changed, 1 insertion(+), 4 deletions(-)
> > > >
> > > > diff --git
> > > > a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > > index 1abfafbbfa75..242cb08e9fc4 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > > @@ -1074,8 +1074,6 @@ intel_dp_link_train_phy(struct intel_dp
> > > > *intel_dp,  static void
> > > > intel_dp_schedule_fallback_link_training(struct intel_dp
> > > *intel_dp,
> > > >  						     const struct
> > > > intel_crtc_state
> > > *crtc_state)  {
> > > > -	struct intel_connector *intel_connector = intel_dp-
> > > > attached_connector;
> > > > -	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > > >
> > > >  	if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)-
> > > > >base)) {
> > > >  		lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on
> > > disconnected
> > > > sink.\n"); @@ -1092,8 +1090,7 @@ static void
> > > intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
> > > >  		return;
> > > >  	}
> > > >
> > > > -	/* Schedule a Hotplug Uevent to userspace to start modeset */
> > > > -	queue_work(i915->unordered_wq, &intel_connector-
> > > > modeset_retry_work);
> > > > +	/* TODO: Re-visit, sending hotplug is not required. No need to
> > > > +notify user as we are not changing the mode */
> > >
> > > Yeah, we're not changing the mode, we're asking the userspace to
> > > change the mode.
> > As far as I see mode change is not necessity. Link rate and lane count
> > change is internal to KMD.
> 
> Userspace may need to reprobe again in order to ensure that the
> resolution/refresh rate still fits within the bandwidth provided by LR/LC.
> Also I believe this part works with DP1.4 LT fallback when we tested recently.
> 
That's right, I missed it. The case when we are shifting from UHBR to HBR rate, we might have to check for the mode support and if not then trigger hotplug.
A table with link rate and the max supported resolutions helps for this, for a new resolution based on the fallback if the current mode fits in then proceed else trigger hotplug.

Will take this change in my patch series.

Thanks and Regards,
Arun R Murthy
-------------------

> Thanks
> Khaled
> >
> > Thanks and Regards,
> > Arun R Murthy
> > --------------------
> > > BR,
> > > Jani.
> > >
> > > >  }
> > > >
> > > >  /* Perform the link training on all LTTPRs and the DPRX on a
> > > > link. */
> > >
> > > --
> > > Jani Nikula, Intel

[RFC 3/4] drm/i915/dp: use link rate and lane count in intel_dp struct

[Arun R Murthy]

The link rate and lane count are now part of the intel_crtc_state
structure. These two parameters are nothing to do with the crtc and are
more confined to DP.

TODO: Need to still seperate out the use of link rate and port clock
which is in intel_dp and intel_crtc_state structure.

Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 16 ++--
 drivers/gpu/drm/i915/display/intel_ddi.c      | 21 ++---
 .../drm/i915/display/intel_ddi_buf_trans.c    |  7 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |  8 +-
 drivers/gpu/drm/i915/display/intel_dp.h       |  2 +-
 .../drm/i915/display/intel_dp_link_training.c | 81 ++++++++++---------
 .../drm/i915/display/intel_dp_link_training.h |  2 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 29 ++++---
 8 files changed, 92 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 288a00e083c8..cde8f26ba26b 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -414,6 +414,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	const struct intel_ddi_buf_trans *trans;
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	enum phy phy = intel_port_to_phy(i915, encoder->port);
 	u8 owned_lane_mask;
 	intel_wakeref_t wakeref;
@@ -446,7 +447,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
 			      MB_WRITE_COMMITTED);
 	}
 
-	for (ln = 0; ln < crtc_state->lane_count; ln++) {
+	for (ln = 0; ln < intel_dp->lane_count; ln++) {
 		int level = intel_ddi_level(encoder, crtc_state, ln);
 		int lane = ln / 2;
 		int tx = ln % 2;
@@ -2327,10 +2328,11 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
 				  const struct intel_crtc_state *crtc_state,
 				  struct intel_encoder *encoder)
 {
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	const struct intel_c20pll_state *pll_state = &crtc_state->cx0pll_state.c20;
 	bool dp = false;
-	int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
-	u32 clock = crtc_state->port_clock;
+	int lane = intel_dp->lane_count > 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
+	u32 clock = intel_dp->link_rate;
 	bool cntx;
 	int i;
 
@@ -2455,6 +2457,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
 					 const struct intel_crtc_state *crtc_state,
 					 bool lane_reversal)
 {
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	u32 val = 0;
 
@@ -2475,7 +2478,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
 
 	/* TODO: HDMI FRL */
 	/* DP2.0 10G and 20G rates enable MPLLA*/
-	if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000)
+	if (intel_dp->link_rate == 1000000 || intel_dp->link_rate == 2000000)
 		val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;
 	else
 		val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
@@ -2705,6 +2708,7 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
 				const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	enum phy phy = intel_port_to_phy(i915, encoder->port);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
@@ -2744,7 +2748,7 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
 	 * 6. Program the enabled and disabled owned PHY lane
 	 * transmitters over message bus
 	 */
-	intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count, lane_reversal);
+	intel_cx0_program_phy_lane(i915, encoder, intel_dp->lane_count, lane_reversal);
 
 	/*
 	 * 7. Follow the Display Voltage Frequency Switching - Sequence
@@ -2756,7 +2760,7 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
 	 * clock frequency.
 	 */
 	intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
-		       crtc_state->port_clock);
+		       intel_dp->link_rate);
 
 	/*
 	 * 9. Set PORT_CLOCK_CTL register PCLK PLL Request
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index bea441590204..ed7620e7f763 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -334,18 +334,18 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
 
 	/* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
 	intel_dp->DP = dig_port->saved_port_bits |
-		DDI_PORT_WIDTH(crtc_state->lane_count) |
+		DDI_PORT_WIDTH(intel_dp->lane_count) |
 		DDI_BUF_TRANS_SELECT(0);
 
 	if (DISPLAY_VER(i915) >= 14) {
-		if (intel_dp_is_uhbr(crtc_state))
+		if (intel_dp_is_uhbr(intel_dp))
 			intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
 		else
 			intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
 	}
 
 	if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
-		intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
+		intel_dp->DP |= ddi_buf_phy_link_rate(intel_dp->link_rate);
 		if (!intel_tc_port_in_tbt_alt_mode(dig_port))
 			intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
 	}
@@ -456,10 +456,11 @@ intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder,
 				const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	u32 val = 0;
 
-	if (intel_dp_is_uhbr(crtc_state))
+	if (intel_dp_is_uhbr(intel_dp))
 		val = TRANS_DP2_128B132B_CHANNEL_CODING;
 
 	intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val);
@@ -477,6 +478,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	enum pipe pipe = crtc->pipe;
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	enum port port = encoder->port;
@@ -552,11 +554,11 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
 		temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
 		temp |= (crtc_state->fdi_lanes - 1) << 1;
 	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
-		if (intel_dp_is_uhbr(crtc_state))
+		if (intel_dp_is_uhbr(intel_dp))
 			temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
 		else
 			temp |= TRANS_DDI_MODE_SELECT_DP_MST;
-		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
+		temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
 
 		if (DISPLAY_VER(dev_priv) >= 12) {
 			enum transcoder master;
@@ -1414,7 +1416,7 @@ static int intel_ddi_dp_level(struct intel_dp *intel_dp,
 {
 	u8 train_set = intel_dp->train_set[lane];
 
-	if (intel_dp_is_uhbr(crtc_state)) {
+	if (intel_dp_is_uhbr(intel_dp)) {
 		return train_set & DP_TX_FFE_PRESET_VALUE_MASK;
 	} else {
 		u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
@@ -2456,15 +2458,16 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	enum port port = encoder->port;
 	u32 val;
 
 	val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port));
 	val &= ~XELPDP_PORT_WIDTH_MASK;
-	val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count));
+	val |= XELPDP_PORT_WIDTH(mtl_get_port_width(intel_dp->lane_count));
 
 	val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK;
-	if (intel_dp_is_uhbr(crtc_state))
+	if (intel_dp_is_uhbr(intel_dp))
 		val |= XELPDP_PORT_BUF_PORT_DATA_40BIT;
 	else
 		val |= XELPDP_PORT_BUF_PORT_DATA_10BIT;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index de809e2d9cac..e490bffd3e49 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1679,8 +1679,10 @@ dg2_get_snps_buf_trans(struct intel_encoder *encoder,
 		       const struct intel_crtc_state *crtc_state,
 		       int *n_entries)
 {
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
 	if (intel_crtc_has_dp_encoder(crtc_state) &&
-	    intel_dp_is_uhbr(crtc_state))
+	    intel_dp_is_uhbr(intel_dp))
 		return intel_get_buf_trans(&dg2_snps_trans_uhbr, n_entries);
 	else
 		return intel_get_buf_trans(&dg2_snps_trans, n_entries);
@@ -1692,9 +1694,10 @@ mtl_get_cx0_buf_trans(struct intel_encoder *encoder,
 		      int *n_entries)
 {
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	enum phy phy = intel_port_to_phy(i915, encoder->port);
 
-	if (intel_crtc_has_dp_encoder(crtc_state) && crtc_state->port_clock >= 1000000)
+	if (intel_crtc_has_dp_encoder(crtc_state) && intel_dp_is_uhbr(intel_dp))
 		return intel_get_buf_trans(&mtl_c20_trans_uhbr, n_entries);
 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && !(intel_is_c10phy(i915, phy)))
 		return intel_get_buf_trans(&mtl_c20_trans_hdmi, n_entries);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 82d354a6b0cd..ba3c8201c0ef 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -167,9 +167,9 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 
 /* Is link rate UHBR and thus 128b/132b? */
-bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
+bool intel_dp_is_uhbr(struct intel_dp *intel_dp)
 {
-	return drm_dp_is_uhbr_rate(crtc_state->port_clock);
+	return drm_dp_is_uhbr_rate(intel_dp->link_rate);
 }
 
 /**
@@ -2901,12 +2901,14 @@ intel_dp_audio_compute_config(struct intel_encoder *encoder,
 			      struct intel_crtc_state *pipe_config,
 			      struct drm_connector_state *conn_state)
 {
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
 	pipe_config->has_audio =
 		intel_dp_has_audio(encoder, pipe_config, conn_state) &&
 		intel_audio_compute_config(encoder, pipe_config, conn_state);
 
 	pipe_config->sdp_split_enable = pipe_config->has_audio &&
-					intel_dp_is_uhbr(pipe_config);
+					intel_dp_is_uhbr(intel_dp);
 }
 
 int
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 530cc97bc42f..cc93c244a2f9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -80,7 +80,7 @@ void intel_dp_audio_compute_config(struct intel_encoder *encoder,
 				   struct drm_connector_state *conn_state);
 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);
 bool intel_dp_is_edp(struct intel_dp *intel_dp);
-bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
+bool intel_dp_is_uhbr(struct intel_dp *intel_dp);
 int intel_dp_link_symbol_size(int rate);
 int intel_dp_link_symbol_clock(int rate);
 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 242cb08e9fc4..eb25b59a4eb3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -355,7 +355,7 @@ static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp,
 		v = drm_dp_get_adjust_request_voltage(link_status, lane);
 		p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
 	} else {
-		for (lane = 0; lane < crtc_state->lane_count; lane++) {
+		for (lane = 0; lane < intel_dp->lane_count; lane++) {
 			v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
 			p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
 		}
@@ -380,7 +380,7 @@ static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,
 					 const u8 link_status[DP_LINK_STATUS_SIZE],
 					 int lane)
 {
-	if (intel_dp_is_uhbr(crtc_state))
+	if (intel_dp_is_uhbr(intel_dp))
 		return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp, crtc_state,
 							      dp_phy, link_status, lane);
 	else
@@ -419,18 +419,18 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 {
 	int lane;
 
-	if (intel_dp_is_uhbr(crtc_state)) {
+	if (intel_dp_is_uhbr(intel_dp)) {
 		lt_dbg(intel_dp, dp_phy,
 		       "128b/132b, lanes: %d, "
 		       "TX FFE request: " TRAIN_REQ_FMT "\n",
-		       crtc_state->lane_count,
+		       intel_dp->lane_count,
 		       TRAIN_REQ_TX_FFE_ARGS(link_status));
 	} else {
 		lt_dbg(intel_dp, dp_phy,
 		       "8b/10b, lanes: %d, "
 		       "vswing request: " TRAIN_REQ_FMT ", "
 		       "pre-emphasis request: " TRAIN_REQ_FMT "\n",
-		       crtc_state->lane_count,
+		       intel_dp->lane_count,
 		       TRAIN_REQ_VSWING_ARGS(link_status),
 		       TRAIN_REQ_PREEMPH_ARGS(link_status));
 	}
@@ -464,7 +464,7 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
 
 	buf[0] = dp_train_pat;
 	/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
-	memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
+	memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
 	len = crtc_state->lane_count + 1;
 
 	return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
@@ -531,18 +531,18 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 
-	if (intel_dp_is_uhbr(crtc_state)) {
+	if (intel_dp_is_uhbr(intel_dp)){
 		lt_dbg(intel_dp, dp_phy,
 		       "128b/132b, lanes: %d, "
 		       "TX FFE presets: " TRAIN_SET_FMT "\n",
-		       crtc_state->lane_count,
+		       intel_dp->lane_count,
 		       TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set));
 	} else {
 		lt_dbg(intel_dp, dp_phy,
 		       "8b/10b, lanes: %d, "
 		       "vswing levels: " TRAIN_SET_FMT ", "
 		       "pre-emphasis levels: " TRAIN_SET_FMT "\n",
-		       crtc_state->lane_count,
+		       intel_dp->lane_count,
 		       TRAIN_SET_VSWING_ARGS(intel_dp->train_set),
 		       TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set));
 	}
@@ -575,9 +575,9 @@ intel_dp_update_link_train(struct intel_dp *intel_dp,
 	intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
 
 	ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
-				intel_dp->train_set, crtc_state->lane_count);
+				intel_dp->train_set, intel_dp->lane_count);
 
-	return ret == crtc_state->lane_count;
+	return ret == intel_dp->lane_count;
 }
 
 /* 128b/132b */
@@ -618,10 +618,10 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
 {
 	int lane;
 
-	for (lane = 0; lane < crtc_state->lane_count; lane++) {
+	for (lane = 0; lane < intel_dp->lane_count; lane++) {
 		u8 train_set_lane = intel_dp->train_set[lane];
 
-		if (intel_dp_is_uhbr(crtc_state)) {
+		if (intel_dp_is_uhbr(intel_dp)) {
 			if (!intel_dp_lane_max_tx_ffe_reached(train_set_lane))
 				return false;
 		} else {
@@ -640,7 +640,7 @@ intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
 	u8 link_config[2];
 
 	link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
-	link_config[1] = intel_dp_is_uhbr(crtc_state) ?
+	link_config[1] = intel_dp_is_uhbr(intel_dp) ?
 			 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
 	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
 }
@@ -650,7 +650,7 @@ intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
 			    const struct intel_crtc_state *crtc_state,
 			    u8 link_bw, u8 rate_select)
 {
-	u8 lane_count = crtc_state->lane_count;
+	u8 lane_count = intel_dp->lane_count;
 
 	if (crtc_state->enhanced_framing)
 		lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
@@ -689,7 +689,7 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
 	if (intel_dp->prepare_link_retrain)
 		intel_dp->prepare_link_retrain(intel_dp, crtc_state);
 
-	intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
+	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
 			      &link_bw, &rate_select);
 
 	/*
@@ -730,16 +730,16 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
 	return true;
 }
 
-static bool intel_dp_adjust_request_changed(const struct intel_crtc_state *crtc_state,
+static bool intel_dp_adjust_request_changed(struct intel_dp *intel_dp,
 					    const u8 old_link_status[DP_LINK_STATUS_SIZE],
 					    const u8 new_link_status[DP_LINK_STATUS_SIZE])
 {
 	int lane;
 
-	for (lane = 0; lane < crtc_state->lane_count; lane++) {
+	for (lane = 0; lane < intel_dp->lane_count; lane++) {
 		u8 old, new;
 
-		if (intel_dp_is_uhbr(crtc_state)) {
+		if (intel_dp_is_uhbr(intel_dp)) {
 			old = drm_dp_get_adjust_tx_ffe_preset(old_link_status, lane);
 			new = drm_dp_get_adjust_tx_ffe_preset(new_link_status, lane);
 		} else {
@@ -783,7 +783,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
 
 	delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux,
 						    intel_dp->dpcd, dp_phy,
-						    intel_dp_is_uhbr(crtc_state));
+						    intel_dp_is_uhbr(intel_dp));
 
 	/* clock recovery */
 	if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,
@@ -816,7 +816,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
 			return false;
 		}
 
-		if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
+		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
 			lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n");
 			return true;
 		}
@@ -841,7 +841,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
 			return false;
 		}
 
-		if (!intel_dp_adjust_request_changed(crtc_state, old_link_status, link_status))
+		if (!intel_dp_adjust_request_changed(intel_dp, old_link_status, link_status))
 			++voltage_tries;
 		else
 			voltage_tries = 1;
@@ -872,7 +872,7 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
 	bool source_tps3, sink_tps3, source_tps4, sink_tps4;
 
 	/* UHBR+ use separate 128b/132b TPS2 */
-	if (intel_dp_is_uhbr(crtc_state))
+	if (intel_dp_is_uhbr(intel_dp))
 		return DP_TRAINING_PATTERN_2;
 
 	/*
@@ -886,7 +886,7 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
 		    drm_dp_tps4_supported(intel_dp->dpcd);
 	if (source_tps4 && sink_tps4) {
 		return DP_TRAINING_PATTERN_4;
-	} else if (crtc_state->port_clock == 810000) {
+	} else if (intel_dp->link_rate == 810000) {
 		if (!source_tps4)
 			lt_dbg(intel_dp, dp_phy,
 			       "8.1 Gbps link rate without source TPS4 support\n");
@@ -904,7 +904,7 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
 		    drm_dp_tps3_supported(intel_dp->dpcd);
 	if (source_tps3 && sink_tps3) {
 		return  DP_TRAINING_PATTERN_3;
-	} else if (crtc_state->port_clock >= 540000) {
+	} else if (intel_dp->link_rate >= 540000) {
 		if (!source_tps3)
 			lt_dbg(intel_dp, dp_phy,
 			       ">=5.4/6.48 Gbps link rate without source TPS3 support\n");
@@ -934,7 +934,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
 
 	delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux,
 						intel_dp->dpcd, dp_phy,
-						intel_dp_is_uhbr(crtc_state));
+						intel_dp_is_uhbr(intel_dp));
 
 	training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy);
 	/* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
@@ -959,7 +959,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
 
 		/* Make sure clock is still ok */
 		if (!drm_dp_clock_recovery_ok(link_status,
-					      crtc_state->lane_count)) {
+					      intel_dp->lane_count)) {
 			intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
 			lt_dbg(intel_dp, dp_phy,
 			       "Clock recovery check failed, cannot continue channel equalization\n");
@@ -967,7 +967,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
 		}
 
 		if (drm_dp_channel_eq_ok(link_status,
-					 crtc_state->lane_count)) {
+					 intel_dp->lane_count)) {
 			channel_eq = true;
 			lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP Training successful\n");
 			break;
@@ -1041,7 +1041,7 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp,
 	intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,
 					       DP_TRAINING_PATTERN_DISABLE);
 
-	if (intel_dp_is_uhbr(crtc_state) &&
+	if (intel_dp_is_uhbr(intel_dp) &&
 	    wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) {
 		lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n");
 	}
@@ -1066,7 +1066,7 @@ intel_dp_link_train_phy(struct intel_dp *intel_dp,
 	lt_dbg(intel_dp, dp_phy,
 	       "Link Training %s at link rate = %d, lane count = %d\n",
 	       ret ? "passed" : "failed",
-	       crtc_state->port_clock, crtc_state->lane_count);
+	       intel_dp->link_rate, intel_dp->lane_count);
 
 	return ret;
 }
@@ -1085,8 +1085,8 @@ static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
 		       "Link Training failed with HOBL active, not enabling it from now on\n");
 		intel_dp->hobl_failed = true;
 	} else if (intel_dp_get_link_train_fallback_values(intel_dp,
-							   crtc_state->port_clock,
-							   crtc_state->lane_count)) {
+							   intel_dp->link_rate,
+							   intel_dp->lane_count)) {
 		return;
 	}
 
@@ -1192,7 +1192,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
 			return false;
 		}
 
-		if (drm_dp_128b132b_lane_channel_eq_done(link_status, crtc_state->lane_count)) {
+		if (drm_dp_128b132b_lane_channel_eq_done(link_status, intel_dp->lane_count)) {
 			lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq done\n");
 			break;
 		}
@@ -1287,7 +1287,7 @@ intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp,
 
 		if (drm_dp_128b132b_eq_interlane_align_done(link_status) &&
 		    drm_dp_128b132b_cds_interlane_align_done(link_status) &&
-		    drm_dp_128b132b_lane_symbol_locked(link_status, crtc_state->lane_count)) {
+		    drm_dp_128b132b_lane_symbol_locked(link_status, intel_dp->lane_count)) {
 			lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n");
 			break;
 		}
@@ -1330,7 +1330,7 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
 	lt_dbg(intel_dp, DP_PHY_DPRX,
 	       "128b/132b Link Training %s at link rate = %d, lane count = %d\n",
 	       passed ? "passed" : "failed",
-	       crtc_state->port_clock, crtc_state->lane_count);
+	       intel_dp->link_rate, intel_dp->lane_count);
 
 	return passed;
 }
@@ -1344,8 +1344,9 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
  * retraining with reduced link rate/lane parameters if the link training
  * fails.
  * After calling this function intel_dp_stop_link_train() must be called.
+ * Return: Link trained status success/failure.
  */
-void intel_dp_start_link_train(struct intel_dp *intel_dp,
+bool intel_dp_start_link_train(struct intel_dp *intel_dp,
 			       const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -1363,7 +1364,7 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
 
 	intel_dp_prepare_link_train(intel_dp, crtc_state);
 
-	if (intel_dp_is_uhbr(crtc_state))
+	if (intel_dp_is_uhbr(intel_dp))
 		passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count);
 	else
 		passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count);
@@ -1382,11 +1383,13 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
 	 */
 	if (!passed && i915->display.hotplug.ignore_long_hpd) {
 		lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n");
-		return;
+		return true;
 	}
 
 	if (!passed)
 		intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
+
+	return passed;
 }
 
 void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
@@ -1398,7 +1401,7 @@ void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
 	 * Default value of bit 31 is '0' hence discarding the write
 	 * TODO: Corrective actions on SDP corruption yet to be defined
 	 */
-	if (!intel_dp_is_uhbr(crtc_state))
+	if (!intel_dp_is_uhbr(intel_dp))
 		return;
 
 	/* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 2c8f2775891b..601f7e80476e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -24,7 +24,7 @@ void intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
 void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
 				const struct intel_crtc_state *crtc_state,
 				enum drm_dp_phy dp_phy);
-void intel_dp_start_link_train(struct intel_dp *intel_dp,
+bool intel_dp_start_link_train(struct intel_dp *intel_dp,
 			       const struct intel_crtc_state *crtc_state);
 void intel_dp_stop_link_train(struct intel_dp *intel_dp,
 			      const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 5fa25a5a36b5..27994a3b568c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -52,13 +52,13 @@
 
 static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp,
 					  const struct drm_display_mode *adjusted_mode,
-					  struct intel_crtc_state *crtc_state,
+					  struct intel_dp *intel_dp,
 					  bool dsc)
 {
-	if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) {
+	if (intel_dp_is_uhbr(intel_dp) && DISPLAY_VER(i915) < 14 && dsc) {
 		int output_bpp = bpp;
 		/* DisplayPort 2 128b/132b, bits per lane is always 32 */
-		int symbol_clock = crtc_state->port_clock / 32;
+		int symbol_clock = intel_dp->link_rate / 32;
 
 		if (output_bpp * adjusted_mode->crtc_clock >=
 		    symbol_clock * 72) {
@@ -71,7 +71,8 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp
 	return 0;
 }
 
-static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
+static int intel_dp_mst_bw_overhead(struct intel_dp *intel_dp,
+				    const struct intel_crtc_state *crtc_state,
 				    const struct intel_connector *connector,
 				    bool ssc, bool dsc, int bpp_x16)
 {
@@ -81,7 +82,7 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
 	int dsc_slice_count = 0;
 	int overhead;
 
-	flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0;
+	flags |= intel_dp_is_uhbr(intel_dp) ? DRM_DP_BW_OVERHEAD_UHBR : 0;
 	flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
 	flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
 
@@ -170,12 +171,12 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
 		if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))
 			return -EINVAL;
 
-		crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
+		crtc_state->fec_enable = !intel_dp_is_uhbr(intel_dp);
 	}
 
 	mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
-						      crtc_state->port_clock,
-						      crtc_state->lane_count);
+						      intel_dp->link_rate,
+						      intel_dp->lane_count);
 
 	drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n",
 		    min_bpp, max_bpp);
@@ -188,16 +189,18 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
 
 		drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
 
-		ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, crtc_state, dsc);
+		ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, intel_dp, dsc);
 		if (ret)
 			continue;
 
 		link_bpp_x16 = to_bpp_x16(dsc ? bpp :
 					  intel_dp_output_bpp(crtc_state->output_format, bpp));
 
-		local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,
+		local_bw_overhead = intel_dp_mst_bw_overhead(intel_dp,
+							     crtc_state, connector,
 							     false, dsc, link_bpp_x16);
-		remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,
+		remote_bw_overhead = intel_dp_mst_bw_overhead(intel_dp,
+							      crtc_state, connector,
 							      true, dsc, link_bpp_x16);
 
 		intel_dp_mst_compute_m_n(crtc_state, connector,
@@ -368,7 +371,7 @@ static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
 	struct intel_dp *intel_dp = &intel_mst->primary->dp;
 	struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
 	struct drm_dp_mst_topology_state *topology_state;
-	u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?
+	u8 link_coding_cap = intel_dp_is_uhbr(intel_dp) ?
 		DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;
 
 	topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr);
@@ -1123,7 +1126,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
 
 	drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
 
-	if (intel_dp_is_uhbr(pipe_config)) {
+	if (intel_dp_is_uhbr(intel_dp)) {
 		const struct drm_display_mode *adjusted_mode =
 			&pipe_config->hw.adjusted_mode;
 		u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
-- 
2.25.1

Re: [RFC 3/4] drm/i915/dp: use link rate and lane count in intel_dp struct

[Jani Nikula]

On Tue, 06 Feb 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> The link rate and lane count are now part of the intel_crtc_state
> structure. These two parameters are nothing to do with the crtc and are
> more confined to DP.

As said offline, the parameters were specifically added to crtc state
for both atomic and the state checker.

No go.


BR,
Jani.

>
> TODO: Need to still seperate out the use of link rate and port clock
> which is in intel_dp and intel_crtc_state structure.
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 16 ++--
>  drivers/gpu/drm/i915/display/intel_ddi.c      | 21 ++---
>  .../drm/i915/display/intel_ddi_buf_trans.c    |  7 +-
>  drivers/gpu/drm/i915/display/intel_dp.c       |  8 +-
>  drivers/gpu/drm/i915/display/intel_dp.h       |  2 +-
>  .../drm/i915/display/intel_dp_link_training.c | 81 ++++++++++---------
>  .../drm/i915/display/intel_dp_link_training.h |  2 +-
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   | 29 ++++---
>  8 files changed, 92 insertions(+), 74 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 288a00e083c8..cde8f26ba26b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -414,6 +414,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	const struct intel_ddi_buf_trans *trans;
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	enum phy phy = intel_port_to_phy(i915, encoder->port);
>  	u8 owned_lane_mask;
>  	intel_wakeref_t wakeref;
> @@ -446,7 +447,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
>  			      MB_WRITE_COMMITTED);
>  	}
>  
> -	for (ln = 0; ln < crtc_state->lane_count; ln++) {
> +	for (ln = 0; ln < intel_dp->lane_count; ln++) {
>  		int level = intel_ddi_level(encoder, crtc_state, ln);
>  		int lane = ln / 2;
>  		int tx = ln % 2;
> @@ -2327,10 +2328,11 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
>  				  const struct intel_crtc_state *crtc_state,
>  				  struct intel_encoder *encoder)
>  {
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	const struct intel_c20pll_state *pll_state = &crtc_state->cx0pll_state.c20;
>  	bool dp = false;
> -	int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
> -	u32 clock = crtc_state->port_clock;
> +	int lane = intel_dp->lane_count > 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
> +	u32 clock = intel_dp->link_rate;
>  	bool cntx;
>  	int i;
>  
> @@ -2455,6 +2457,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
>  					 const struct intel_crtc_state *crtc_state,
>  					 bool lane_reversal)
>  {
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	u32 val = 0;
>  
> @@ -2475,7 +2478,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
>  
>  	/* TODO: HDMI FRL */
>  	/* DP2.0 10G and 20G rates enable MPLLA*/
> -	if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000)
> +	if (intel_dp->link_rate == 1000000 || intel_dp->link_rate == 2000000)
>  		val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;
>  	else
>  		val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
> @@ -2705,6 +2708,7 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
>  				const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	enum phy phy = intel_port_to_phy(i915, encoder->port);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> @@ -2744,7 +2748,7 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
>  	 * 6. Program the enabled and disabled owned PHY lane
>  	 * transmitters over message bus
>  	 */
> -	intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count, lane_reversal);
> +	intel_cx0_program_phy_lane(i915, encoder, intel_dp->lane_count, lane_reversal);
>  
>  	/*
>  	 * 7. Follow the Display Voltage Frequency Switching - Sequence
> @@ -2756,7 +2760,7 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
>  	 * clock frequency.
>  	 */
>  	intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
> -		       crtc_state->port_clock);
> +		       intel_dp->link_rate);
>  
>  	/*
>  	 * 9. Set PORT_CLOCK_CTL register PCLK PLL Request
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index bea441590204..ed7620e7f763 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -334,18 +334,18 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
>  
>  	/* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
>  	intel_dp->DP = dig_port->saved_port_bits |
> -		DDI_PORT_WIDTH(crtc_state->lane_count) |
> +		DDI_PORT_WIDTH(intel_dp->lane_count) |
>  		DDI_BUF_TRANS_SELECT(0);
>  
>  	if (DISPLAY_VER(i915) >= 14) {
> -		if (intel_dp_is_uhbr(crtc_state))
> +		if (intel_dp_is_uhbr(intel_dp))
>  			intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
>  		else
>  			intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
>  	}
>  
>  	if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
> -		intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
> +		intel_dp->DP |= ddi_buf_phy_link_rate(intel_dp->link_rate);
>  		if (!intel_tc_port_in_tbt_alt_mode(dig_port))
>  			intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
>  	}
> @@ -456,10 +456,11 @@ intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder,
>  				const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	u32 val = 0;
>  
> -	if (intel_dp_is_uhbr(crtc_state))
> +	if (intel_dp_is_uhbr(intel_dp))
>  		val = TRANS_DP2_128B132B_CHANNEL_CODING;
>  
>  	intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val);
> @@ -477,6 +478,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	enum pipe pipe = crtc->pipe;
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	enum port port = encoder->port;
> @@ -552,11 +554,11 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
>  		temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
>  		temp |= (crtc_state->fdi_lanes - 1) << 1;
>  	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
> -		if (intel_dp_is_uhbr(crtc_state))
> +		if (intel_dp_is_uhbr(intel_dp))
>  			temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
>  		else
>  			temp |= TRANS_DDI_MODE_SELECT_DP_MST;
> -		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
> +		temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
>  
>  		if (DISPLAY_VER(dev_priv) >= 12) {
>  			enum transcoder master;
> @@ -1414,7 +1416,7 @@ static int intel_ddi_dp_level(struct intel_dp *intel_dp,
>  {
>  	u8 train_set = intel_dp->train_set[lane];
>  
> -	if (intel_dp_is_uhbr(crtc_state)) {
> +	if (intel_dp_is_uhbr(intel_dp)) {
>  		return train_set & DP_TX_FFE_PRESET_VALUE_MASK;
>  	} else {
>  		u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> @@ -2456,15 +2458,16 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	enum port port = encoder->port;
>  	u32 val;
>  
>  	val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port));
>  	val &= ~XELPDP_PORT_WIDTH_MASK;
> -	val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count));
> +	val |= XELPDP_PORT_WIDTH(mtl_get_port_width(intel_dp->lane_count));
>  
>  	val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK;
> -	if (intel_dp_is_uhbr(crtc_state))
> +	if (intel_dp_is_uhbr(intel_dp))
>  		val |= XELPDP_PORT_BUF_PORT_DATA_40BIT;
>  	else
>  		val |= XELPDP_PORT_BUF_PORT_DATA_10BIT;
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index de809e2d9cac..e490bffd3e49 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -1679,8 +1679,10 @@ dg2_get_snps_buf_trans(struct intel_encoder *encoder,
>  		       const struct intel_crtc_state *crtc_state,
>  		       int *n_entries)
>  {
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
>  	if (intel_crtc_has_dp_encoder(crtc_state) &&
> -	    intel_dp_is_uhbr(crtc_state))
> +	    intel_dp_is_uhbr(intel_dp))
>  		return intel_get_buf_trans(&dg2_snps_trans_uhbr, n_entries);
>  	else
>  		return intel_get_buf_trans(&dg2_snps_trans, n_entries);
> @@ -1692,9 +1694,10 @@ mtl_get_cx0_buf_trans(struct intel_encoder *encoder,
>  		      int *n_entries)
>  {
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	enum phy phy = intel_port_to_phy(i915, encoder->port);
>  
> -	if (intel_crtc_has_dp_encoder(crtc_state) && crtc_state->port_clock >= 1000000)
> +	if (intel_crtc_has_dp_encoder(crtc_state) && intel_dp_is_uhbr(intel_dp))
>  		return intel_get_buf_trans(&mtl_c20_trans_uhbr, n_entries);
>  	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && !(intel_is_c10phy(i915, phy)))
>  		return intel_get_buf_trans(&mtl_c20_trans_hdmi, n_entries);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 82d354a6b0cd..ba3c8201c0ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -167,9 +167,9 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
>  static void intel_dp_unset_edid(struct intel_dp *intel_dp);
>  
>  /* Is link rate UHBR and thus 128b/132b? */
> -bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
> +bool intel_dp_is_uhbr(struct intel_dp *intel_dp)
>  {
> -	return drm_dp_is_uhbr_rate(crtc_state->port_clock);
> +	return drm_dp_is_uhbr_rate(intel_dp->link_rate);
>  }
>  
>  /**
> @@ -2901,12 +2901,14 @@ intel_dp_audio_compute_config(struct intel_encoder *encoder,
>  			      struct intel_crtc_state *pipe_config,
>  			      struct drm_connector_state *conn_state)
>  {
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
>  	pipe_config->has_audio =
>  		intel_dp_has_audio(encoder, pipe_config, conn_state) &&
>  		intel_audio_compute_config(encoder, pipe_config, conn_state);
>  
>  	pipe_config->sdp_split_enable = pipe_config->has_audio &&
> -					intel_dp_is_uhbr(pipe_config);
> +					intel_dp_is_uhbr(intel_dp);
>  }
>  
>  int
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 530cc97bc42f..cc93c244a2f9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -80,7 +80,7 @@ void intel_dp_audio_compute_config(struct intel_encoder *encoder,
>  				   struct drm_connector_state *conn_state);
>  bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);
>  bool intel_dp_is_edp(struct intel_dp *intel_dp);
> -bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
> +bool intel_dp_is_uhbr(struct intel_dp *intel_dp);
>  int intel_dp_link_symbol_size(int rate);
>  int intel_dp_link_symbol_clock(int rate);
>  bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 242cb08e9fc4..eb25b59a4eb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -355,7 +355,7 @@ static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp,
>  		v = drm_dp_get_adjust_request_voltage(link_status, lane);
>  		p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
>  	} else {
> -		for (lane = 0; lane < crtc_state->lane_count; lane++) {
> +		for (lane = 0; lane < intel_dp->lane_count; lane++) {
>  			v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
>  			p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
>  		}
> @@ -380,7 +380,7 @@ static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,
>  					 const u8 link_status[DP_LINK_STATUS_SIZE],
>  					 int lane)
>  {
> -	if (intel_dp_is_uhbr(crtc_state))
> +	if (intel_dp_is_uhbr(intel_dp))
>  		return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp, crtc_state,
>  							      dp_phy, link_status, lane);
>  	else
> @@ -419,18 +419,18 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp,
>  {
>  	int lane;
>  
> -	if (intel_dp_is_uhbr(crtc_state)) {
> +	if (intel_dp_is_uhbr(intel_dp)) {
>  		lt_dbg(intel_dp, dp_phy,
>  		       "128b/132b, lanes: %d, "
>  		       "TX FFE request: " TRAIN_REQ_FMT "\n",
> -		       crtc_state->lane_count,
> +		       intel_dp->lane_count,
>  		       TRAIN_REQ_TX_FFE_ARGS(link_status));
>  	} else {
>  		lt_dbg(intel_dp, dp_phy,
>  		       "8b/10b, lanes: %d, "
>  		       "vswing request: " TRAIN_REQ_FMT ", "
>  		       "pre-emphasis request: " TRAIN_REQ_FMT "\n",
> -		       crtc_state->lane_count,
> +		       intel_dp->lane_count,
>  		       TRAIN_REQ_VSWING_ARGS(link_status),
>  		       TRAIN_REQ_PREEMPH_ARGS(link_status));
>  	}
> @@ -464,7 +464,7 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
>  
>  	buf[0] = dp_train_pat;
>  	/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
> -	memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
> +	memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
>  	len = crtc_state->lane_count + 1;
>  
>  	return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
> @@ -531,18 +531,18 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
>  {
>  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>  
> -	if (intel_dp_is_uhbr(crtc_state)) {
> +	if (intel_dp_is_uhbr(intel_dp)){
>  		lt_dbg(intel_dp, dp_phy,
>  		       "128b/132b, lanes: %d, "
>  		       "TX FFE presets: " TRAIN_SET_FMT "\n",
> -		       crtc_state->lane_count,
> +		       intel_dp->lane_count,
>  		       TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set));
>  	} else {
>  		lt_dbg(intel_dp, dp_phy,
>  		       "8b/10b, lanes: %d, "
>  		       "vswing levels: " TRAIN_SET_FMT ", "
>  		       "pre-emphasis levels: " TRAIN_SET_FMT "\n",
> -		       crtc_state->lane_count,
> +		       intel_dp->lane_count,
>  		       TRAIN_SET_VSWING_ARGS(intel_dp->train_set),
>  		       TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set));
>  	}
> @@ -575,9 +575,9 @@ intel_dp_update_link_train(struct intel_dp *intel_dp,
>  	intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
>  
>  	ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
> -				intel_dp->train_set, crtc_state->lane_count);
> +				intel_dp->train_set, intel_dp->lane_count);
>  
> -	return ret == crtc_state->lane_count;
> +	return ret == intel_dp->lane_count;
>  }
>  
>  /* 128b/132b */
> @@ -618,10 +618,10 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
>  {
>  	int lane;
>  
> -	for (lane = 0; lane < crtc_state->lane_count; lane++) {
> +	for (lane = 0; lane < intel_dp->lane_count; lane++) {
>  		u8 train_set_lane = intel_dp->train_set[lane];
>  
> -		if (intel_dp_is_uhbr(crtc_state)) {
> +		if (intel_dp_is_uhbr(intel_dp)) {
>  			if (!intel_dp_lane_max_tx_ffe_reached(train_set_lane))
>  				return false;
>  		} else {
> @@ -640,7 +640,7 @@ intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
>  	u8 link_config[2];
>  
>  	link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> -	link_config[1] = intel_dp_is_uhbr(crtc_state) ?
> +	link_config[1] = intel_dp_is_uhbr(intel_dp) ?
>  			 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
>  	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
>  }
> @@ -650,7 +650,7 @@ intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
>  			    const struct intel_crtc_state *crtc_state,
>  			    u8 link_bw, u8 rate_select)
>  {
> -	u8 lane_count = crtc_state->lane_count;
> +	u8 lane_count = intel_dp->lane_count;
>  
>  	if (crtc_state->enhanced_framing)
>  		lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> @@ -689,7 +689,7 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
>  	if (intel_dp->prepare_link_retrain)
>  		intel_dp->prepare_link_retrain(intel_dp, crtc_state);
>  
> -	intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
> +	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
>  			      &link_bw, &rate_select);
>  
>  	/*
> @@ -730,16 +730,16 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
>  	return true;
>  }
>  
> -static bool intel_dp_adjust_request_changed(const struct intel_crtc_state *crtc_state,
> +static bool intel_dp_adjust_request_changed(struct intel_dp *intel_dp,
>  					    const u8 old_link_status[DP_LINK_STATUS_SIZE],
>  					    const u8 new_link_status[DP_LINK_STATUS_SIZE])
>  {
>  	int lane;
>  
> -	for (lane = 0; lane < crtc_state->lane_count; lane++) {
> +	for (lane = 0; lane < intel_dp->lane_count; lane++) {
>  		u8 old, new;
>  
> -		if (intel_dp_is_uhbr(crtc_state)) {
> +		if (intel_dp_is_uhbr(intel_dp)) {
>  			old = drm_dp_get_adjust_tx_ffe_preset(old_link_status, lane);
>  			new = drm_dp_get_adjust_tx_ffe_preset(new_link_status, lane);
>  		} else {
> @@ -783,7 +783,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
>  
>  	delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux,
>  						    intel_dp->dpcd, dp_phy,
> -						    intel_dp_is_uhbr(crtc_state));
> +						    intel_dp_is_uhbr(intel_dp));
>  
>  	/* clock recovery */
>  	if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,
> @@ -816,7 +816,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
>  			return false;
>  		}
>  
> -		if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
> +		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
>  			lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n");
>  			return true;
>  		}
> @@ -841,7 +841,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
>  			return false;
>  		}
>  
> -		if (!intel_dp_adjust_request_changed(crtc_state, old_link_status, link_status))
> +		if (!intel_dp_adjust_request_changed(intel_dp, old_link_status, link_status))
>  			++voltage_tries;
>  		else
>  			voltage_tries = 1;
> @@ -872,7 +872,7 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
>  	bool source_tps3, sink_tps3, source_tps4, sink_tps4;
>  
>  	/* UHBR+ use separate 128b/132b TPS2 */
> -	if (intel_dp_is_uhbr(crtc_state))
> +	if (intel_dp_is_uhbr(intel_dp))
>  		return DP_TRAINING_PATTERN_2;
>  
>  	/*
> @@ -886,7 +886,7 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
>  		    drm_dp_tps4_supported(intel_dp->dpcd);
>  	if (source_tps4 && sink_tps4) {
>  		return DP_TRAINING_PATTERN_4;
> -	} else if (crtc_state->port_clock == 810000) {
> +	} else if (intel_dp->link_rate == 810000) {
>  		if (!source_tps4)
>  			lt_dbg(intel_dp, dp_phy,
>  			       "8.1 Gbps link rate without source TPS4 support\n");
> @@ -904,7 +904,7 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
>  		    drm_dp_tps3_supported(intel_dp->dpcd);
>  	if (source_tps3 && sink_tps3) {
>  		return  DP_TRAINING_PATTERN_3;
> -	} else if (crtc_state->port_clock >= 540000) {
> +	} else if (intel_dp->link_rate >= 540000) {
>  		if (!source_tps3)
>  			lt_dbg(intel_dp, dp_phy,
>  			       ">=5.4/6.48 Gbps link rate without source TPS3 support\n");
> @@ -934,7 +934,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
>  
>  	delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux,
>  						intel_dp->dpcd, dp_phy,
> -						intel_dp_is_uhbr(crtc_state));
> +						intel_dp_is_uhbr(intel_dp));
>  
>  	training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy);
>  	/* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
> @@ -959,7 +959,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
>  
>  		/* Make sure clock is still ok */
>  		if (!drm_dp_clock_recovery_ok(link_status,
> -					      crtc_state->lane_count)) {
> +					      intel_dp->lane_count)) {
>  			intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
>  			lt_dbg(intel_dp, dp_phy,
>  			       "Clock recovery check failed, cannot continue channel equalization\n");
> @@ -967,7 +967,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
>  		}
>  
>  		if (drm_dp_channel_eq_ok(link_status,
> -					 crtc_state->lane_count)) {
> +					 intel_dp->lane_count)) {
>  			channel_eq = true;
>  			lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP Training successful\n");
>  			break;
> @@ -1041,7 +1041,7 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp,
>  	intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,
>  					       DP_TRAINING_PATTERN_DISABLE);
>  
> -	if (intel_dp_is_uhbr(crtc_state) &&
> +	if (intel_dp_is_uhbr(intel_dp) &&
>  	    wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) {
>  		lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n");
>  	}
> @@ -1066,7 +1066,7 @@ intel_dp_link_train_phy(struct intel_dp *intel_dp,
>  	lt_dbg(intel_dp, dp_phy,
>  	       "Link Training %s at link rate = %d, lane count = %d\n",
>  	       ret ? "passed" : "failed",
> -	       crtc_state->port_clock, crtc_state->lane_count);
> +	       intel_dp->link_rate, intel_dp->lane_count);
>  
>  	return ret;
>  }
> @@ -1085,8 +1085,8 @@ static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
>  		       "Link Training failed with HOBL active, not enabling it from now on\n");
>  		intel_dp->hobl_failed = true;
>  	} else if (intel_dp_get_link_train_fallback_values(intel_dp,
> -							   crtc_state->port_clock,
> -							   crtc_state->lane_count)) {
> +							   intel_dp->link_rate,
> +							   intel_dp->lane_count)) {
>  		return;
>  	}
>  
> @@ -1192,7 +1192,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
>  			return false;
>  		}
>  
> -		if (drm_dp_128b132b_lane_channel_eq_done(link_status, crtc_state->lane_count)) {
> +		if (drm_dp_128b132b_lane_channel_eq_done(link_status, intel_dp->lane_count)) {
>  			lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq done\n");
>  			break;
>  		}
> @@ -1287,7 +1287,7 @@ intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp,
>  
>  		if (drm_dp_128b132b_eq_interlane_align_done(link_status) &&
>  		    drm_dp_128b132b_cds_interlane_align_done(link_status) &&
> -		    drm_dp_128b132b_lane_symbol_locked(link_status, crtc_state->lane_count)) {
> +		    drm_dp_128b132b_lane_symbol_locked(link_status, intel_dp->lane_count)) {
>  			lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n");
>  			break;
>  		}
> @@ -1330,7 +1330,7 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
>  	lt_dbg(intel_dp, DP_PHY_DPRX,
>  	       "128b/132b Link Training %s at link rate = %d, lane count = %d\n",
>  	       passed ? "passed" : "failed",
> -	       crtc_state->port_clock, crtc_state->lane_count);
> +	       intel_dp->link_rate, intel_dp->lane_count);
>  
>  	return passed;
>  }
> @@ -1344,8 +1344,9 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
>   * retraining with reduced link rate/lane parameters if the link training
>   * fails.
>   * After calling this function intel_dp_stop_link_train() must be called.
> + * Return: Link trained status success/failure.
>   */
> -void intel_dp_start_link_train(struct intel_dp *intel_dp,
> +bool intel_dp_start_link_train(struct intel_dp *intel_dp,
>  			       const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> @@ -1363,7 +1364,7 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
>  
>  	intel_dp_prepare_link_train(intel_dp, crtc_state);
>  
> -	if (intel_dp_is_uhbr(crtc_state))
> +	if (intel_dp_is_uhbr(intel_dp))
>  		passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count);
>  	else
>  		passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count);
> @@ -1382,11 +1383,13 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
>  	 */
>  	if (!passed && i915->display.hotplug.ignore_long_hpd) {
>  		lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n");
> -		return;
> +		return true;
>  	}
>  
>  	if (!passed)
>  		intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
> +
> +	return passed;
>  }
>  
>  void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
> @@ -1398,7 +1401,7 @@ void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
>  	 * Default value of bit 31 is '0' hence discarding the write
>  	 * TODO: Corrective actions on SDP corruption yet to be defined
>  	 */
> -	if (!intel_dp_is_uhbr(crtc_state))
> +	if (!intel_dp_is_uhbr(intel_dp))
>  		return;
>  
>  	/* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> index 2c8f2775891b..601f7e80476e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> @@ -24,7 +24,7 @@ void intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
>  void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
>  				const struct intel_crtc_state *crtc_state,
>  				enum drm_dp_phy dp_phy);
> -void intel_dp_start_link_train(struct intel_dp *intel_dp,
> +bool intel_dp_start_link_train(struct intel_dp *intel_dp,
>  			       const struct intel_crtc_state *crtc_state);
>  void intel_dp_stop_link_train(struct intel_dp *intel_dp,
>  			      const struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 5fa25a5a36b5..27994a3b568c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -52,13 +52,13 @@
>  
>  static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp,
>  					  const struct drm_display_mode *adjusted_mode,
> -					  struct intel_crtc_state *crtc_state,
> +					  struct intel_dp *intel_dp,
>  					  bool dsc)
>  {
> -	if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) {
> +	if (intel_dp_is_uhbr(intel_dp) && DISPLAY_VER(i915) < 14 && dsc) {
>  		int output_bpp = bpp;
>  		/* DisplayPort 2 128b/132b, bits per lane is always 32 */
> -		int symbol_clock = crtc_state->port_clock / 32;
> +		int symbol_clock = intel_dp->link_rate / 32;
>  
>  		if (output_bpp * adjusted_mode->crtc_clock >=
>  		    symbol_clock * 72) {
> @@ -71,7 +71,8 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp
>  	return 0;
>  }
>  
> -static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
> +static int intel_dp_mst_bw_overhead(struct intel_dp *intel_dp,
> +				    const struct intel_crtc_state *crtc_state,
>  				    const struct intel_connector *connector,
>  				    bool ssc, bool dsc, int bpp_x16)
>  {
> @@ -81,7 +82,7 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
>  	int dsc_slice_count = 0;
>  	int overhead;
>  
> -	flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0;
> +	flags |= intel_dp_is_uhbr(intel_dp) ? DRM_DP_BW_OVERHEAD_UHBR : 0;
>  	flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
>  	flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
>  
> @@ -170,12 +171,12 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
>  		if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))
>  			return -EINVAL;
>  
> -		crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
> +		crtc_state->fec_enable = !intel_dp_is_uhbr(intel_dp);
>  	}
>  
>  	mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
> -						      crtc_state->port_clock,
> -						      crtc_state->lane_count);
> +						      intel_dp->link_rate,
> +						      intel_dp->lane_count);
>  
>  	drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n",
>  		    min_bpp, max_bpp);
> @@ -188,16 +189,18 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
>  
>  		drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
>  
> -		ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, crtc_state, dsc);
> +		ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, intel_dp, dsc);
>  		if (ret)
>  			continue;
>  
>  		link_bpp_x16 = to_bpp_x16(dsc ? bpp :
>  					  intel_dp_output_bpp(crtc_state->output_format, bpp));
>  
> -		local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,
> +		local_bw_overhead = intel_dp_mst_bw_overhead(intel_dp,
> +							     crtc_state, connector,
>  							     false, dsc, link_bpp_x16);
> -		remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,
> +		remote_bw_overhead = intel_dp_mst_bw_overhead(intel_dp,
> +							      crtc_state, connector,
>  							      true, dsc, link_bpp_x16);
>  
>  		intel_dp_mst_compute_m_n(crtc_state, connector,
> @@ -368,7 +371,7 @@ static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
>  	struct intel_dp *intel_dp = &intel_mst->primary->dp;
>  	struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
>  	struct drm_dp_mst_topology_state *topology_state;
> -	u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?
> +	u8 link_coding_cap = intel_dp_is_uhbr(intel_dp) ?
>  		DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;
>  
>  	topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr);
> @@ -1123,7 +1126,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
>  
>  	drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
>  
> -	if (intel_dp_is_uhbr(pipe_config)) {
> +	if (intel_dp_is_uhbr(intel_dp)) {
>  		const struct drm_display_mode *adjusted_mode =
>  			&pipe_config->hw.adjusted_mode;
>  		u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);

-- 
Jani Nikula, Intel

RE: [RFC 3/4] drm/i915/dp: use link rate and lane count in intel_dp struct

[Murthy, Arun R]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, February 13, 2024 11:43 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Deak, Imre <imre.deak@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>
> Subject: Re: [RFC 3/4] drm/i915/dp: use link rate and lane count in intel_dp
> struct
> 
> On Tue, 06 Feb 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> > The link rate and lane count are now part of the intel_crtc_state
> > structure. These two parameters are nothing to do with the crtc and
> > are more confined to DP.
> 
> As said offline, the parameters were specifically added to crtc state for both
> atomic and the state checker.
> 
I am a bit lost as to from where we need this in atomic and state checker for link rate and lane count as none of these parameters are coming from user nor does it change in modeset. On driver init the link rate and lane count value is fetched from the table and thereafter its constant, but used in many places for configuration/calculation purpose for which the same in intel_dp struct would do.

On link training failure, the link rate and lane count tends to change and new value is initialized in intel_dp struct.

Thanks and Regards,
Arun R Murthy
--------------------

> No go.
> 
> 
> BR,
> Jani.
> 
> >
> > TODO: Need to still seperate out the use of link rate and port clock
> > which is in intel_dp and intel_crtc_state structure.
> >
> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 16 ++--
> >  drivers/gpu/drm/i915/display/intel_ddi.c      | 21 ++---
> >  .../drm/i915/display/intel_ddi_buf_trans.c    |  7 +-
> >  drivers/gpu/drm/i915/display/intel_dp.c       |  8 +-
> >  drivers/gpu/drm/i915/display/intel_dp.h       |  2 +-
> >  .../drm/i915/display/intel_dp_link_training.c | 81
> > ++++++++++---------  .../drm/i915/display/intel_dp_link_training.h |  2 +-
> >  drivers/gpu/drm/i915/display/intel_dp_mst.c   | 29 ++++---
> >  8 files changed, 92 insertions(+), 74 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index 288a00e083c8..cde8f26ba26b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -414,6 +414,7 @@ void intel_cx0_phy_set_signal_levels(struct
> > intel_encoder *encoder,  {
> >  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> >  	const struct intel_ddi_buf_trans *trans;
> > +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >  	enum phy phy = intel_port_to_phy(i915, encoder->port);
> >  	u8 owned_lane_mask;
> >  	intel_wakeref_t wakeref;
> > @@ -446,7 +447,7 @@ void intel_cx0_phy_set_signal_levels(struct
> intel_encoder *encoder,
> >  			      MB_WRITE_COMMITTED);
> >  	}
> >
> > -	for (ln = 0; ln < crtc_state->lane_count; ln++) {
> > +	for (ln = 0; ln < intel_dp->lane_count; ln++) {
> >  		int level = intel_ddi_level(encoder, crtc_state, ln);
> >  		int lane = ln / 2;
> >  		int tx = ln % 2;
> > @@ -2327,10 +2328,11 @@ static void intel_c20_pll_program(struct
> drm_i915_private *i915,
> >  				  const struct intel_crtc_state *crtc_state,
> >  				  struct intel_encoder *encoder)
> >  {
> > +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >  	const struct intel_c20pll_state *pll_state = &crtc_state-
> >cx0pll_state.c20;
> >  	bool dp = false;
> > -	int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES :
> INTEL_CX0_LANE0;
> > -	u32 clock = crtc_state->port_clock;
> > +	int lane = intel_dp->lane_count > 2 ? INTEL_CX0_BOTH_LANES :
> INTEL_CX0_LANE0;
> > +	u32 clock = intel_dp->link_rate;
> >  	bool cntx;
> >  	int i;
> >
> > @@ -2455,6 +2457,7 @@ static void intel_program_port_clock_ctl(struct
> intel_encoder *encoder,
> >  					 const struct intel_crtc_state
> *crtc_state,
> >  					 bool lane_reversal)
> >  {
> > +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> >  	u32 val = 0;
> >
> > @@ -2475,7 +2478,7 @@ static void intel_program_port_clock_ctl(struct
> > intel_encoder *encoder,
> >
> >  	/* TODO: HDMI FRL */
> >  	/* DP2.0 10G and 20G rates enable MPLLA*/
> > -	if (crtc_state->port_clock == 1000000 || crtc_state->port_clock ==
> 2000000)
> > +	if (intel_dp->link_rate == 1000000 || intel_dp->link_rate ==
> > +2000000)
> >  		val |= crtc_state->cx0pll_state.ssc_enabled ?
> XELPDP_SSC_ENABLE_PLLA : 0;
> >  	else
> >  		val |= crtc_state->cx0pll_state.ssc_enabled ?
> > XELPDP_SSC_ENABLE_PLLB : 0; @@ -2705,6 +2708,7 @@ static void
> intel_cx0pll_enable(struct intel_encoder *encoder,
> >  				const struct intel_crtc_state *crtc_state)  {
> >  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >  	enum phy phy = intel_port_to_phy(i915, encoder->port);
> >  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> >  	bool lane_reversal = dig_port->saved_port_bits &
> > DDI_BUF_PORT_REVERSAL; @@ -2744,7 +2748,7 @@ static void
> intel_cx0pll_enable(struct intel_encoder *encoder,
> >  	 * 6. Program the enabled and disabled owned PHY lane
> >  	 * transmitters over message bus
> >  	 */
> > -	intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count,
> lane_reversal);
> > +	intel_cx0_program_phy_lane(i915, encoder, intel_dp->lane_count,
> > +lane_reversal);
> >
> >  	/*
> >  	 * 7. Follow the Display Voltage Frequency Switching - Sequence @@
> > -2756,7 +2760,7 @@ static void intel_cx0pll_enable(struct intel_encoder
> *encoder,
> >  	 * clock frequency.
> >  	 */
> >  	intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
> > -		       crtc_state->port_clock);
> > +		       intel_dp->link_rate);
> >
> >  	/*
> >  	 * 9. Set PORT_CLOCK_CTL register PCLK PLL Request diff --git
> > a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index bea441590204..ed7620e7f763 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -334,18 +334,18 @@ static void intel_ddi_init_dp_buf_reg(struct
> > intel_encoder *encoder,
> >
> >  	/* DDI_BUF_CTL_ENABLE will be set by
> intel_ddi_prepare_link_retrain() later */
> >  	intel_dp->DP = dig_port->saved_port_bits |
> > -		DDI_PORT_WIDTH(crtc_state->lane_count) |
> > +		DDI_PORT_WIDTH(intel_dp->lane_count) |
> >  		DDI_BUF_TRANS_SELECT(0);
> >
> >  	if (DISPLAY_VER(i915) >= 14) {
> > -		if (intel_dp_is_uhbr(crtc_state))
> > +		if (intel_dp_is_uhbr(intel_dp))
> >  			intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
> >  		else
> >  			intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
> >  	}
> >
> >  	if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
> > -		intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
> > +		intel_dp->DP |= ddi_buf_phy_link_rate(intel_dp->link_rate);
> >  		if (!intel_tc_port_in_tbt_alt_mode(dig_port))
> >  			intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> >  	}
> > @@ -456,10 +456,11 @@ intel_ddi_config_transcoder_dp2(struct
> intel_encoder *encoder,
> >  				const struct intel_crtc_state *crtc_state)  {
> >  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >  	u32 val = 0;
> >
> > -	if (intel_dp_is_uhbr(crtc_state))
> > +	if (intel_dp_is_uhbr(intel_dp))
> >  		val = TRANS_DP2_128B132B_CHANNEL_CODING;
> >
> >  	intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); @@ -
> 477,6
> > +478,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder
> > *encoder,  {
> >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >  	enum pipe pipe = crtc->pipe;
> >  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >  	enum port port = encoder->port;
> > @@ -552,11 +554,11 @@ intel_ddi_transcoder_func_reg_val_get(struct
> intel_encoder *encoder,
> >  		temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
> >  		temp |= (crtc_state->fdi_lanes - 1) << 1;
> >  	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
> > -		if (intel_dp_is_uhbr(crtc_state))
> > +		if (intel_dp_is_uhbr(intel_dp))
> >  			temp |=
> TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
> >  		else
> >  			temp |= TRANS_DDI_MODE_SELECT_DP_MST;
> > -		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
> > +		temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
> >
> >  		if (DISPLAY_VER(dev_priv) >= 12) {
> >  			enum transcoder master;
> > @@ -1414,7 +1416,7 @@ static int intel_ddi_dp_level(struct intel_dp
> > *intel_dp,  {
> >  	u8 train_set = intel_dp->train_set[lane];
> >
> > -	if (intel_dp_is_uhbr(crtc_state)) {
> > +	if (intel_dp_is_uhbr(intel_dp)) {
> >  		return train_set & DP_TX_FFE_PRESET_VALUE_MASK;
> >  	} else {
> >  		u8 signal_levels = train_set &
> (DP_TRAIN_VOLTAGE_SWING_MASK | @@
> > -2456,15 +2458,16 @@ static void mtl_port_buf_ctl_program(struct
> > intel_encoder *encoder,  {
> >  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> >  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >  	enum port port = encoder->port;
> >  	u32 val;
> >
> >  	val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port));
> >  	val &= ~XELPDP_PORT_WIDTH_MASK;
> > -	val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state-
> >lane_count));
> > +	val |= XELPDP_PORT_WIDTH(mtl_get_port_width(intel_dp-
> >lane_count));
> >
> >  	val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK;
> > -	if (intel_dp_is_uhbr(crtc_state))
> > +	if (intel_dp_is_uhbr(intel_dp))
> >  		val |= XELPDP_PORT_BUF_PORT_DATA_40BIT;
> >  	else
> >  		val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; diff --git
> > a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> > b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> > index de809e2d9cac..e490bffd3e49 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> > @@ -1679,8 +1679,10 @@ dg2_get_snps_buf_trans(struct intel_encoder
> *encoder,
> >  		       const struct intel_crtc_state *crtc_state,
> >  		       int *n_entries)
> >  {
> > +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +
> >  	if (intel_crtc_has_dp_encoder(crtc_state) &&
> > -	    intel_dp_is_uhbr(crtc_state))
> > +	    intel_dp_is_uhbr(intel_dp))
> >  		return intel_get_buf_trans(&dg2_snps_trans_uhbr, n_entries);
> >  	else
> >  		return intel_get_buf_trans(&dg2_snps_trans, n_entries); @@ -
> 1692,9
> > +1694,10 @@ mtl_get_cx0_buf_trans(struct intel_encoder *encoder,
> >  		      int *n_entries)
> >  {
> >  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >  	enum phy phy = intel_port_to_phy(i915, encoder->port);
> >
> > -	if (intel_crtc_has_dp_encoder(crtc_state) && crtc_state->port_clock >=
> 1000000)
> > +	if (intel_crtc_has_dp_encoder(crtc_state) &&
> > +intel_dp_is_uhbr(intel_dp))
> >  		return intel_get_buf_trans(&mtl_c20_trans_uhbr, n_entries);
> >  	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> !(intel_is_c10phy(i915, phy)))
> >  		return intel_get_buf_trans(&mtl_c20_trans_hdmi, n_entries);
> diff
> > --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 82d354a6b0cd..ba3c8201c0ef 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -167,9 +167,9 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
> > static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> >
> >  /* Is link rate UHBR and thus 128b/132b? */ -bool
> > intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
> > +bool intel_dp_is_uhbr(struct intel_dp *intel_dp)
> >  {
> > -	return drm_dp_is_uhbr_rate(crtc_state->port_clock);
> > +	return drm_dp_is_uhbr_rate(intel_dp->link_rate);
> >  }
> >
> >  /**
> > @@ -2901,12 +2901,14 @@ intel_dp_audio_compute_config(struct
> intel_encoder *encoder,
> >  			      struct intel_crtc_state *pipe_config,
> >  			      struct drm_connector_state *conn_state)  {
> > +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +
> >  	pipe_config->has_audio =
> >  		intel_dp_has_audio(encoder, pipe_config, conn_state) &&
> >  		intel_audio_compute_config(encoder, pipe_config, conn_state);
> >
> >  	pipe_config->sdp_split_enable = pipe_config->has_audio &&
> > -					intel_dp_is_uhbr(pipe_config);
> > +					intel_dp_is_uhbr(intel_dp);
> >  }
> >
> >  int
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> > b/drivers/gpu/drm/i915/display/intel_dp.h
> > index 530cc97bc42f..cc93c244a2f9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -80,7 +80,7 @@ void intel_dp_audio_compute_config(struct
> intel_encoder *encoder,
> >  				   struct drm_connector_state *conn_state);
> bool
> > intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);  bool
> > intel_dp_is_edp(struct intel_dp *intel_dp); -bool
> > intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
> > +bool intel_dp_is_uhbr(struct intel_dp *intel_dp);
> >  int intel_dp_link_symbol_size(int rate);  int
> > intel_dp_link_symbol_clock(int rate);  bool
> > intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port
> > port); diff --git
> > a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index 242cb08e9fc4..eb25b59a4eb3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -355,7 +355,7 @@ static u8
> intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp,
> >  		v = drm_dp_get_adjust_request_voltage(link_status, lane);
> >  		p = drm_dp_get_adjust_request_pre_emphasis(link_status,
> lane);
> >  	} else {
> > -		for (lane = 0; lane < crtc_state->lane_count; lane++) {
> > +		for (lane = 0; lane < intel_dp->lane_count; lane++) {
> >  			v = max(v,
> drm_dp_get_adjust_request_voltage(link_status, lane));
> >  			p = max(p,
> drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
> >  		}
> > @@ -380,7 +380,7 @@ static u8 intel_dp_get_lane_adjust_train(struct
> intel_dp *intel_dp,
> >  					 const u8
> link_status[DP_LINK_STATUS_SIZE],
> >  					 int lane)
> >  {
> > -	if (intel_dp_is_uhbr(crtc_state))
> > +	if (intel_dp_is_uhbr(intel_dp))
> >  		return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp,
> crtc_state,
> >  							      dp_phy,
> link_status, lane);
> >  	else
> > @@ -419,18 +419,18 @@ intel_dp_get_adjust_train(struct intel_dp
> > *intel_dp,  {
> >  	int lane;
> >
> > -	if (intel_dp_is_uhbr(crtc_state)) {
> > +	if (intel_dp_is_uhbr(intel_dp)) {
> >  		lt_dbg(intel_dp, dp_phy,
> >  		       "128b/132b, lanes: %d, "
> >  		       "TX FFE request: " TRAIN_REQ_FMT "\n",
> > -		       crtc_state->lane_count,
> > +		       intel_dp->lane_count,
> >  		       TRAIN_REQ_TX_FFE_ARGS(link_status));
> >  	} else {
> >  		lt_dbg(intel_dp, dp_phy,
> >  		       "8b/10b, lanes: %d, "
> >  		       "vswing request: " TRAIN_REQ_FMT ", "
> >  		       "pre-emphasis request: " TRAIN_REQ_FMT "\n",
> > -		       crtc_state->lane_count,
> > +		       intel_dp->lane_count,
> >  		       TRAIN_REQ_VSWING_ARGS(link_status),
> >  		       TRAIN_REQ_PREEMPH_ARGS(link_status));
> >  	}
> > @@ -464,7 +464,7 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
> >
> >  	buf[0] = dp_train_pat;
> >  	/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
> > -	memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
> > +	memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
> >  	len = crtc_state->lane_count + 1;
> >
> >  	return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len; @@
> > -531,18 +531,18 @@ void intel_dp_set_signal_levels(struct intel_dp
> > *intel_dp,  {
> >  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> >
> > -	if (intel_dp_is_uhbr(crtc_state)) {
> > +	if (intel_dp_is_uhbr(intel_dp)){
> >  		lt_dbg(intel_dp, dp_phy,
> >  		       "128b/132b, lanes: %d, "
> >  		       "TX FFE presets: " TRAIN_SET_FMT "\n",
> > -		       crtc_state->lane_count,
> > +		       intel_dp->lane_count,
> >  		       TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set));
> >  	} else {
> >  		lt_dbg(intel_dp, dp_phy,
> >  		       "8b/10b, lanes: %d, "
> >  		       "vswing levels: " TRAIN_SET_FMT ", "
> >  		       "pre-emphasis levels: " TRAIN_SET_FMT "\n",
> > -		       crtc_state->lane_count,
> > +		       intel_dp->lane_count,
> >  		       TRAIN_SET_VSWING_ARGS(intel_dp->train_set),
> >  		       TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set));
> >  	}
> > @@ -575,9 +575,9 @@ intel_dp_update_link_train(struct intel_dp *intel_dp,
> >  	intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
> >
> >  	ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
> > -				intel_dp->train_set, crtc_state->lane_count);
> > +				intel_dp->train_set, intel_dp->lane_count);
> >
> > -	return ret == crtc_state->lane_count;
> > +	return ret == intel_dp->lane_count;
> >  }
> >
> >  /* 128b/132b */
> > @@ -618,10 +618,10 @@ static bool
> > intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,  {
> >  	int lane;
> >
> > -	for (lane = 0; lane < crtc_state->lane_count; lane++) {
> > +	for (lane = 0; lane < intel_dp->lane_count; lane++) {
> >  		u8 train_set_lane = intel_dp->train_set[lane];
> >
> > -		if (intel_dp_is_uhbr(crtc_state)) {
> > +		if (intel_dp_is_uhbr(intel_dp)) {
> >  			if (!intel_dp_lane_max_tx_ffe_reached(train_set_lane))
> >  				return false;
> >  		} else {
> > @@ -640,7 +640,7 @@ intel_dp_update_downspread_ctrl(struct intel_dp
> *intel_dp,
> >  	u8 link_config[2];
> >
> >  	link_config[0] = crtc_state->vrr.flipline ?
> DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> > -	link_config[1] = intel_dp_is_uhbr(crtc_state) ?
> > +	link_config[1] = intel_dp_is_uhbr(intel_dp) ?
> >  			 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> >  	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
> link_config,
> > 2);  } @@ -650,7 +650,7 @@ intel_dp_update_link_bw_set(struct intel_dp
> > *intel_dp,
> >  			    const struct intel_crtc_state *crtc_state,
> >  			    u8 link_bw, u8 rate_select)
> >  {
> > -	u8 lane_count = crtc_state->lane_count;
> > +	u8 lane_count = intel_dp->lane_count;
> >
> >  	if (crtc_state->enhanced_framing)
> >  		lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN; @@
> -689,7 +689,7 @@
> > intel_dp_prepare_link_train(struct intel_dp *intel_dp,
> >  	if (intel_dp->prepare_link_retrain)
> >  		intel_dp->prepare_link_retrain(intel_dp, crtc_state);
> >
> > -	intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
> > +	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
> >  			      &link_bw, &rate_select);
> >
> >  	/*
> > @@ -730,16 +730,16 @@ intel_dp_prepare_link_train(struct intel_dp
> *intel_dp,
> >  	return true;
> >  }
> >
> > -static bool intel_dp_adjust_request_changed(const struct
> > intel_crtc_state *crtc_state,
> > +static bool intel_dp_adjust_request_changed(struct intel_dp
> > +*intel_dp,
> >  					    const u8
> old_link_status[DP_LINK_STATUS_SIZE],
> >  					    const u8
> new_link_status[DP_LINK_STATUS_SIZE])
> >  {
> >  	int lane;
> >
> > -	for (lane = 0; lane < crtc_state->lane_count; lane++) {
> > +	for (lane = 0; lane < intel_dp->lane_count; lane++) {
> >  		u8 old, new;
> >
> > -		if (intel_dp_is_uhbr(crtc_state)) {
> > +		if (intel_dp_is_uhbr(intel_dp)) {
> >  			old =
> drm_dp_get_adjust_tx_ffe_preset(old_link_status, lane);
> >  			new =
> drm_dp_get_adjust_tx_ffe_preset(new_link_status, lane);
> >  		} else {
> > @@ -783,7 +783,7 @@ intel_dp_link_training_clock_recovery(struct
> > intel_dp *intel_dp,
> >
> >  	delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux,
> >  						    intel_dp->dpcd, dp_phy,
> > -
> intel_dp_is_uhbr(crtc_state));
> > +						    intel_dp_is_uhbr(intel_dp));
> >
> >  	/* clock recovery */
> >  	if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy, @@
> > -816,7 +816,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp
> *intel_dp,
> >  			return false;
> >  		}
> >
> > -		if (drm_dp_clock_recovery_ok(link_status, crtc_state-
> >lane_count)) {
> > +		if (drm_dp_clock_recovery_ok(link_status, intel_dp-
> >lane_count)) {
> >  			lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n");
> >  			return true;
> >  		}
> > @@ -841,7 +841,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp
> *intel_dp,
> >  			return false;
> >  		}
> >
> > -		if (!intel_dp_adjust_request_changed(crtc_state,
> old_link_status, link_status))
> > +		if (!intel_dp_adjust_request_changed(intel_dp, old_link_status,
> > +link_status))
> >  			++voltage_tries;
> >  		else
> >  			voltage_tries = 1;
> > @@ -872,7 +872,7 @@ static u32 intel_dp_training_pattern(struct intel_dp
> *intel_dp,
> >  	bool source_tps3, sink_tps3, source_tps4, sink_tps4;
> >
> >  	/* UHBR+ use separate 128b/132b TPS2 */
> > -	if (intel_dp_is_uhbr(crtc_state))
> > +	if (intel_dp_is_uhbr(intel_dp))
> >  		return DP_TRAINING_PATTERN_2;
> >
> >  	/*
> > @@ -886,7 +886,7 @@ static u32 intel_dp_training_pattern(struct intel_dp
> *intel_dp,
> >  		    drm_dp_tps4_supported(intel_dp->dpcd);
> >  	if (source_tps4 && sink_tps4) {
> >  		return DP_TRAINING_PATTERN_4;
> > -	} else if (crtc_state->port_clock == 810000) {
> > +	} else if (intel_dp->link_rate == 810000) {
> >  		if (!source_tps4)
> >  			lt_dbg(intel_dp, dp_phy,
> >  			       "8.1 Gbps link rate without source TPS4
> support\n"); @@
> > -904,7 +904,7 @@ static u32 intel_dp_training_pattern(struct intel_dp
> *intel_dp,
> >  		    drm_dp_tps3_supported(intel_dp->dpcd);
> >  	if (source_tps3 && sink_tps3) {
> >  		return  DP_TRAINING_PATTERN_3;
> > -	} else if (crtc_state->port_clock >= 540000) {
> > +	} else if (intel_dp->link_rate >= 540000) {
> >  		if (!source_tps3)
> >  			lt_dbg(intel_dp, dp_phy,
> >  			       ">=5.4/6.48 Gbps link rate without source TPS3
> support\n");
> > @@ -934,7 +934,7 @@ intel_dp_link_training_channel_equalization(struct
> > intel_dp *intel_dp,
> >
> >  	delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux,
> >  						intel_dp->dpcd, dp_phy,
> > -						intel_dp_is_uhbr(crtc_state));
> > +						intel_dp_is_uhbr(intel_dp));
> >
> >  	training_pattern = intel_dp_training_pattern(intel_dp, crtc_state,
> dp_phy);
> >  	/* Scrambling is disabled for TPS2/3 and enabled for TPS4 */ @@
> > -959,7 +959,7 @@ intel_dp_link_training_channel_equalization(struct
> > intel_dp *intel_dp,
> >
> >  		/* Make sure clock is still ok */
> >  		if (!drm_dp_clock_recovery_ok(link_status,
> > -					      crtc_state->lane_count)) {
> > +					      intel_dp->lane_count)) {
> >  			intel_dp_dump_link_status(intel_dp, dp_phy,
> link_status);
> >  			lt_dbg(intel_dp, dp_phy,
> >  			       "Clock recovery check failed, cannot continue
> channel
> > equalization\n"); @@ -967,7 +967,7 @@
> intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
> >  		}
> >
> >  		if (drm_dp_channel_eq_ok(link_status,
> > -					 crtc_state->lane_count)) {
> > +					 intel_dp->lane_count)) {
> >  			channel_eq = true;
> >  			lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP
> Training successful\n");
> >  			break;
> > @@ -1041,7 +1041,7 @@ void intel_dp_stop_link_train(struct intel_dp
> *intel_dp,
> >  	intel_dp_program_link_training_pattern(intel_dp, crtc_state,
> DP_PHY_DPRX,
> >
> DP_TRAINING_PATTERN_DISABLE);
> >
> > -	if (intel_dp_is_uhbr(crtc_state) &&
> > +	if (intel_dp_is_uhbr(intel_dp) &&
> >  	    wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0,
> 500)) {
> >  		lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not
> clearing\n");
> >  	}
> > @@ -1066,7 +1066,7 @@ intel_dp_link_train_phy(struct intel_dp *intel_dp,
> >  	lt_dbg(intel_dp, dp_phy,
> >  	       "Link Training %s at link rate = %d, lane count = %d\n",
> >  	       ret ? "passed" : "failed",
> > -	       crtc_state->port_clock, crtc_state->lane_count);
> > +	       intel_dp->link_rate, intel_dp->lane_count);
> >
> >  	return ret;
> >  }
> > @@ -1085,8 +1085,8 @@ static void
> intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
> >  		       "Link Training failed with HOBL active, not enabling it from
> now on\n");
> >  		intel_dp->hobl_failed = true;
> >  	} else if (intel_dp_get_link_train_fallback_values(intel_dp,
> > -							   crtc_state-
> >port_clock,
> > -							   crtc_state-
> >lane_count)) {
> > +							   intel_dp->link_rate,
> > +							   intel_dp-
> >lane_count)) {
> >  		return;
> >  	}
> >
> > @@ -1192,7 +1192,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp
> *intel_dp,
> >  			return false;
> >  		}
> >
> > -		if (drm_dp_128b132b_lane_channel_eq_done(link_status,
> crtc_state->lane_count)) {
> > +		if (drm_dp_128b132b_lane_channel_eq_done(link_status,
> > +intel_dp->lane_count)) {
> >  			lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq
> done\n");
> >  			break;
> >  		}
> > @@ -1287,7 +1287,7 @@ intel_dp_128b132b_lane_cds(struct intel_dp
> > *intel_dp,
> >
> >  		if (drm_dp_128b132b_eq_interlane_align_done(link_status)
> &&
> >  		    drm_dp_128b132b_cds_interlane_align_done(link_status)
> &&
> > -		    drm_dp_128b132b_lane_symbol_locked(link_status,
> crtc_state->lane_count)) {
> > +		    drm_dp_128b132b_lane_symbol_locked(link_status,
> > +intel_dp->lane_count)) {
> >  			lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align
> done\n");
> >  			break;
> >  		}
> > @@ -1330,7 +1330,7 @@ intel_dp_128b132b_link_train(struct intel_dp
> *intel_dp,
> >  	lt_dbg(intel_dp, DP_PHY_DPRX,
> >  	       "128b/132b Link Training %s at link rate = %d, lane count = %d\n",
> >  	       passed ? "passed" : "failed",
> > -	       crtc_state->port_clock, crtc_state->lane_count);
> > +	       intel_dp->link_rate, intel_dp->lane_count);
> >
> >  	return passed;
> >  }
> > @@ -1344,8 +1344,9 @@ intel_dp_128b132b_link_train(struct intel_dp
> *intel_dp,
> >   * retraining with reduced link rate/lane parameters if the link training
> >   * fails.
> >   * After calling this function intel_dp_stop_link_train() must be called.
> > + * Return: Link trained status success/failure.
> >   */
> > -void intel_dp_start_link_train(struct intel_dp *intel_dp,
> > +bool intel_dp_start_link_train(struct intel_dp *intel_dp,
> >  			       const struct intel_crtc_state *crtc_state)  {
> >  	struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -1363,7
> > +1364,7 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
> >
> >  	intel_dp_prepare_link_train(intel_dp, crtc_state);
> >
> > -	if (intel_dp_is_uhbr(crtc_state))
> > +	if (intel_dp_is_uhbr(intel_dp))
> >  		passed = intel_dp_128b132b_link_train(intel_dp, crtc_state,
> lttpr_count);
> >  	else
> >  		passed = intel_dp_link_train_all_phys(intel_dp, crtc_state,
> > lttpr_count); @@ -1382,11 +1383,13 @@ void
> intel_dp_start_link_train(struct intel_dp *intel_dp,
> >  	 */
> >  	if (!passed && i915->display.hotplug.ignore_long_hpd) {
> >  		lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n");
> > -		return;
> > +		return true;
> >  	}
> >
> >  	if (!passed)
> >  		intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
> > +
> > +	return passed;
> >  }
> >
> >  void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, @@
> > -1398,7 +1401,7 @@ void intel_dp_128b132b_sdp_crc16(struct intel_dp
> *intel_dp,
> >  	 * Default value of bit 31 is '0' hence discarding the write
> >  	 * TODO: Corrective actions on SDP corruption yet to be defined
> >  	 */
> > -	if (!intel_dp_is_uhbr(crtc_state))
> > +	if (!intel_dp_is_uhbr(intel_dp))
> >  		return;
> >
> >  	/* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ diff --git
> > a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> > index 2c8f2775891b..601f7e80476e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> > @@ -24,7 +24,7 @@ void intel_dp_program_link_training_pattern(struct
> > intel_dp *intel_dp,  void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
> >  				const struct intel_crtc_state *crtc_state,
> >  				enum drm_dp_phy dp_phy);
> > -void intel_dp_start_link_train(struct intel_dp *intel_dp,
> > +bool intel_dp_start_link_train(struct intel_dp *intel_dp,
> >  			       const struct intel_crtc_state *crtc_state);  void
> > intel_dp_stop_link_train(struct intel_dp *intel_dp,
> >  			      const struct intel_crtc_state *crtc_state); diff --git
> > a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 5fa25a5a36b5..27994a3b568c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -52,13 +52,13 @@
> >
> >  static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int
> bpp,
> >  					  const struct drm_display_mode
> *adjusted_mode,
> > -					  struct intel_crtc_state *crtc_state,
> > +					  struct intel_dp *intel_dp,
> >  					  bool dsc)
> >  {
> > -	if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) {
> > +	if (intel_dp_is_uhbr(intel_dp) && DISPLAY_VER(i915) < 14 && dsc) {
> >  		int output_bpp = bpp;
> >  		/* DisplayPort 2 128b/132b, bits per lane is always 32 */
> > -		int symbol_clock = crtc_state->port_clock / 32;
> > +		int symbol_clock = intel_dp->link_rate / 32;
> >
> >  		if (output_bpp * adjusted_mode->crtc_clock >=
> >  		    symbol_clock * 72) {
> > @@ -71,7 +71,8 @@ static int intel_dp_mst_check_constraints(struct
> drm_i915_private *i915, int bpp
> >  	return 0;
> >  }
> >
> > -static int intel_dp_mst_bw_overhead(const struct intel_crtc_state
> > *crtc_state,
> > +static int intel_dp_mst_bw_overhead(struct intel_dp *intel_dp,
> > +				    const struct intel_crtc_state *crtc_state,
> >  				    const struct intel_connector *connector,
> >  				    bool ssc, bool dsc, int bpp_x16)  { @@ -81,7
> +82,7 @@ static
> > int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
> >  	int dsc_slice_count = 0;
> >  	int overhead;
> >
> > -	flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR
> : 0;
> > +	flags |= intel_dp_is_uhbr(intel_dp) ? DRM_DP_BW_OVERHEAD_UHBR :
> 0;
> >  	flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
> >  	flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
> >
> > @@ -170,12 +171,12 @@ static int
> intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> >  		if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))
> >  			return -EINVAL;
> >
> > -		crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
> > +		crtc_state->fec_enable = !intel_dp_is_uhbr(intel_dp);
> >  	}
> >
> >  	mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp-
> >mst_mgr,
> > -						      crtc_state->port_clock,
> > -						      crtc_state->lane_count);
> > +						      intel_dp->link_rate,
> > +						      intel_dp->lane_count);
> >
> >  	drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max
> bpp %d\n",
> >  		    min_bpp, max_bpp);
> > @@ -188,16 +189,18 @@ static int
> > intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> >
> >  		drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
> >
> > -		ret = intel_dp_mst_check_constraints(i915, bpp,
> adjusted_mode, crtc_state, dsc);
> > +		ret = intel_dp_mst_check_constraints(i915, bpp,
> adjusted_mode,
> > +intel_dp, dsc);
> >  		if (ret)
> >  			continue;
> >
> >  		link_bpp_x16 = to_bpp_x16(dsc ? bpp :
> >  					  intel_dp_output_bpp(crtc_state-
> >output_format, bpp));
> >
> > -		local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
> connector,
> > +		local_bw_overhead = intel_dp_mst_bw_overhead(intel_dp,
> > +							     crtc_state,
> connector,
> >  							     false, dsc,
> link_bpp_x16);
> > -		remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
> connector,
> > +		remote_bw_overhead = intel_dp_mst_bw_overhead(intel_dp,
> > +							      crtc_state,
> connector,
> >  							      true, dsc,
> link_bpp_x16);
> >
> >  		intel_dp_mst_compute_m_n(crtc_state, connector, @@ -368,7
> +371,7 @@
> > static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
> >  	struct intel_dp *intel_dp = &intel_mst->primary->dp;
> >  	struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
> >  	struct drm_dp_mst_topology_state *topology_state;
> > -	u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?
> > +	u8 link_coding_cap = intel_dp_is_uhbr(intel_dp) ?
> >  		DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;
> >
> >  	topology_state =
> > drm_atomic_get_mst_topology_state(conn_state->state, mgr); @@ -1123,7
> > +1126,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state
> > *state,
> >
> >  	drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
> >
> > -	if (intel_dp_is_uhbr(pipe_config)) {
> > +	if (intel_dp_is_uhbr(intel_dp)) {
> >  		const struct drm_display_mode *adjusted_mode =
> >  			&pipe_config->hw.adjusted_mode;
> >  		u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
> 
> --
> Jani Nikula, Intel

RE: [RFC 3/4] drm/i915/dp: use link rate and lane count in intel_dp struct

[Jani Nikula]

On Wed, 14 Feb 2024, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani <jani.nikula@intel.com>
>> Sent: Tuesday, February 13, 2024 11:43 PM
>> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-gfx@lists.freedesktop.org
>> Cc: Deak, Imre <imre.deak@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
>> Shankar, Uma <uma.shankar@intel.com>; Murthy, Arun R
>> <arun.r.murthy@intel.com>
>> Subject: Re: [RFC 3/4] drm/i915/dp: use link rate and lane count in intel_dp
>> struct
>>
>> On Tue, 06 Feb 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
>> > The link rate and lane count are now part of the intel_crtc_state
>> > structure. These two parameters are nothing to do with the crtc and
>> > are more confined to DP.
>>
>> As said offline, the parameters were specifically added to crtc state for both
>> atomic and the state checker.
>>
> I am a bit lost as to from where we need this in atomic and state checker for link rate and lane count as none of these parameters are coming from user nor does it change in modeset. On driver init the link rate and lane count value is fetched from the table and thereafter its constant, but used in many places for configuration/calculation purpose for which the same in intel_dp struct would do.

Compute config chooses the link rate and lane count to use.

Compute config may only modify crtc state, nothing else.

State checker reads out the state from the hardware, and it must only
read it to the crtc state, nowhere else.

State checker must only compare two crtc states, one from software and
one read from the hardware.

Having the link rate and lane count in struct intel_dp does not satisfy
these conditions.

See also 90a6b7b052b1 ("drm/i915: Move intel_dp->lane_count into
pipe_config").


BR,
Jani.


>
> On link training failure, the link rate and lane count tends to change and new value is initialized in intel_dp struct.
>
> Thanks and Regards,
> Arun R Murthy
> --------------------
>
>> No go.
>>
>>
>> BR,
>> Jani.
>>
>> >
>> > TODO: Need to still seperate out the use of link rate and port clock
>> > which is in intel_dp and intel_crtc_state structure.
>> >
>> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 16 ++--
>> >  drivers/gpu/drm/i915/display/intel_ddi.c      | 21 ++---
>> >  .../drm/i915/display/intel_ddi_buf_trans.c    |  7 +-
>> >  drivers/gpu/drm/i915/display/intel_dp.c       |  8 +-
>> >  drivers/gpu/drm/i915/display/intel_dp.h       |  2 +-
>> >  .../drm/i915/display/intel_dp_link_training.c | 81
>> > ++++++++++---------  .../drm/i915/display/intel_dp_link_training.h |  2 +-
>> >  drivers/gpu/drm/i915/display/intel_dp_mst.c   | 29 ++++---
>> >  8 files changed, 92 insertions(+), 74 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > index 288a00e083c8..cde8f26ba26b 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > @@ -414,6 +414,7 @@ void intel_cx0_phy_set_signal_levels(struct
>> > intel_encoder *encoder,  {
>> >     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>> >     const struct intel_ddi_buf_trans *trans;
>> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> >     enum phy phy = intel_port_to_phy(i915, encoder->port);
>> >     u8 owned_lane_mask;
>> >     intel_wakeref_t wakeref;
>> > @@ -446,7 +447,7 @@ void intel_cx0_phy_set_signal_levels(struct
>> intel_encoder *encoder,
>> >                           MB_WRITE_COMMITTED);
>> >     }
>> >
>> > -   for (ln = 0; ln < crtc_state->lane_count; ln++) {
>> > +   for (ln = 0; ln < intel_dp->lane_count; ln++) {
>> >             int level = intel_ddi_level(encoder, crtc_state, ln);
>> >             int lane = ln / 2;
>> >             int tx = ln % 2;
>> > @@ -2327,10 +2328,11 @@ static void intel_c20_pll_program(struct
>> drm_i915_private *i915,
>> >                               const struct intel_crtc_state *crtc_state,
>> >                               struct intel_encoder *encoder)
>> >  {
>> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> >     const struct intel_c20pll_state *pll_state = &crtc_state-
>> >cx0pll_state.c20;
>> >     bool dp = false;
>> > -   int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES :
>> INTEL_CX0_LANE0;
>> > -   u32 clock = crtc_state->port_clock;
>> > +   int lane = intel_dp->lane_count > 2 ? INTEL_CX0_BOTH_LANES :
>> INTEL_CX0_LANE0;
>> > +   u32 clock = intel_dp->link_rate;
>> >     bool cntx;
>> >     int i;
>> >
>> > @@ -2455,6 +2457,7 @@ static void intel_program_port_clock_ctl(struct
>> intel_encoder *encoder,
>> >                                      const struct intel_crtc_state
>> *crtc_state,
>> >                                      bool lane_reversal)
>> >  {
>> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> >     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>> >     u32 val = 0;
>> >
>> > @@ -2475,7 +2478,7 @@ static void intel_program_port_clock_ctl(struct
>> > intel_encoder *encoder,
>> >
>> >     /* TODO: HDMI FRL */
>> >     /* DP2.0 10G and 20G rates enable MPLLA*/
>> > -   if (crtc_state->port_clock == 1000000 || crtc_state->port_clock ==
>> 2000000)
>> > +   if (intel_dp->link_rate == 1000000 || intel_dp->link_rate ==
>> > +2000000)
>> >             val |= crtc_state->cx0pll_state.ssc_enabled ?
>> XELPDP_SSC_ENABLE_PLLA : 0;
>> >     else
>> >             val |= crtc_state->cx0pll_state.ssc_enabled ?
>> > XELPDP_SSC_ENABLE_PLLB : 0; @@ -2705,6 +2708,7 @@ static void
>> intel_cx0pll_enable(struct intel_encoder *encoder,
>> >                             const struct intel_crtc_state *crtc_state)  {
>> >     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> >     enum phy phy = intel_port_to_phy(i915, encoder->port);
>> >     struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>> >     bool lane_reversal = dig_port->saved_port_bits &
>> > DDI_BUF_PORT_REVERSAL; @@ -2744,7 +2748,7 @@ static void
>> intel_cx0pll_enable(struct intel_encoder *encoder,
>> >      * 6. Program the enabled and disabled owned PHY lane
>> >      * transmitters over message bus
>> >      */
>> > -   intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count,
>> lane_reversal);
>> > +   intel_cx0_program_phy_lane(i915, encoder, intel_dp->lane_count,
>> > +lane_reversal);
>> >
>> >     /*
>> >      * 7. Follow the Display Voltage Frequency Switching - Sequence @@
>> > -2756,7 +2760,7 @@ static void intel_cx0pll_enable(struct intel_encoder
>> *encoder,
>> >      * clock frequency.
>> >      */
>> >     intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
>> > -                  crtc_state->port_clock);
>> > +                  intel_dp->link_rate);
>> >
>> >     /*
>> >      * 9. Set PORT_CLOCK_CTL register PCLK PLL Request diff --git
>> > a/drivers/gpu/drm/i915/display/intel_ddi.c
>> > b/drivers/gpu/drm/i915/display/intel_ddi.c
>> > index bea441590204..ed7620e7f763 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> > @@ -334,18 +334,18 @@ static void intel_ddi_init_dp_buf_reg(struct
>> > intel_encoder *encoder,
>> >
>> >     /* DDI_BUF_CTL_ENABLE will be set by
>> intel_ddi_prepare_link_retrain() later */
>> >     intel_dp->DP = dig_port->saved_port_bits |
>> > -           DDI_PORT_WIDTH(crtc_state->lane_count) |
>> > +           DDI_PORT_WIDTH(intel_dp->lane_count) |
>> >             DDI_BUF_TRANS_SELECT(0);
>> >
>> >     if (DISPLAY_VER(i915) >= 14) {
>> > -           if (intel_dp_is_uhbr(crtc_state))
>> > +           if (intel_dp_is_uhbr(intel_dp))
>> >                     intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
>> >             else
>> >                     intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
>> >     }
>> >
>> >     if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
>> > -           intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
>> > +           intel_dp->DP |= ddi_buf_phy_link_rate(intel_dp->link_rate);
>> >             if (!intel_tc_port_in_tbt_alt_mode(dig_port))
>> >                     intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
>> >     }
>> > @@ -456,10 +456,11 @@ intel_ddi_config_transcoder_dp2(struct
>> intel_encoder *encoder,
>> >                             const struct intel_crtc_state *crtc_state)  {
>> >     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> >     enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> >     u32 val = 0;
>> >
>> > -   if (intel_dp_is_uhbr(crtc_state))
>> > +   if (intel_dp_is_uhbr(intel_dp))
>> >             val = TRANS_DP2_128B132B_CHANNEL_CODING;
>> >
>> >     intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); @@ -
>> 477,6
>> > +478,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder
>> > *encoder,  {
>> >     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> >     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> >     enum pipe pipe = crtc->pipe;
>> >     enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> >     enum port port = encoder->port;
>> > @@ -552,11 +554,11 @@ intel_ddi_transcoder_func_reg_val_get(struct
>> intel_encoder *encoder,
>> >             temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
>> >             temp |= (crtc_state->fdi_lanes - 1) << 1;
>> >     } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
>> > -           if (intel_dp_is_uhbr(crtc_state))
>> > +           if (intel_dp_is_uhbr(intel_dp))
>> >                     temp |=
>> TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
>> >             else
>> >                     temp |= TRANS_DDI_MODE_SELECT_DP_MST;
>> > -           temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
>> > +           temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
>> >
>> >             if (DISPLAY_VER(dev_priv) >= 12) {
>> >                     enum transcoder master;
>> > @@ -1414,7 +1416,7 @@ static int intel_ddi_dp_level(struct intel_dp
>> > *intel_dp,  {
>> >     u8 train_set = intel_dp->train_set[lane];
>> >
>> > -   if (intel_dp_is_uhbr(crtc_state)) {
>> > +   if (intel_dp_is_uhbr(intel_dp)) {
>> >             return train_set & DP_TX_FFE_PRESET_VALUE_MASK;
>> >     } else {
>> >             u8 signal_levels = train_set &
>> (DP_TRAIN_VOLTAGE_SWING_MASK | @@
>> > -2456,15 +2458,16 @@ static void mtl_port_buf_ctl_program(struct
>> > intel_encoder *encoder,  {
>> >     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>> >     struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> >     enum port port = encoder->port;
>> >     u32 val;
>> >
>> >     val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port));
>> >     val &= ~XELPDP_PORT_WIDTH_MASK;
>> > -   val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state-
>> >lane_count));
>> > +   val |= XELPDP_PORT_WIDTH(mtl_get_port_width(intel_dp-
>> >lane_count));
>> >
>> >     val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK;
>> > -   if (intel_dp_is_uhbr(crtc_state))
>> > +   if (intel_dp_is_uhbr(intel_dp))
>> >             val |= XELPDP_PORT_BUF_PORT_DATA_40BIT;
>> >     else
>> >             val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; diff --git
>> > a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
>> > b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
>> > index de809e2d9cac..e490bffd3e49 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
>> > @@ -1679,8 +1679,10 @@ dg2_get_snps_buf_trans(struct intel_encoder
>> *encoder,
>> >                    const struct intel_crtc_state *crtc_state,
>> >                    int *n_entries)
>> >  {
>> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> > +
>> >     if (intel_crtc_has_dp_encoder(crtc_state) &&
>> > -       intel_dp_is_uhbr(crtc_state))
>> > +       intel_dp_is_uhbr(intel_dp))
>> >             return intel_get_buf_trans(&dg2_snps_trans_uhbr, n_entries);
>> >     else
>> >             return intel_get_buf_trans(&dg2_snps_trans, n_entries); @@ -
>> 1692,9
>> > +1694,10 @@ mtl_get_cx0_buf_trans(struct intel_encoder *encoder,
>> >                   int *n_entries)
>> >  {
>> >     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> >     enum phy phy = intel_port_to_phy(i915, encoder->port);
>> >
>> > -   if (intel_crtc_has_dp_encoder(crtc_state) && crtc_state->port_clock >=
>> 1000000)
>> > +   if (intel_crtc_has_dp_encoder(crtc_state) &&
>> > +intel_dp_is_uhbr(intel_dp))
>> >             return intel_get_buf_trans(&mtl_c20_trans_uhbr, n_entries);
>> >     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
>> !(intel_is_c10phy(i915, phy)))
>> >             return intel_get_buf_trans(&mtl_c20_trans_hdmi, n_entries);
>> diff
>> > --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> > b/drivers/gpu/drm/i915/display/intel_dp.c
>> > index 82d354a6b0cd..ba3c8201c0ef 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> > @@ -167,9 +167,9 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
>> > static void intel_dp_unset_edid(struct intel_dp *intel_dp);
>> >
>> >  /* Is link rate UHBR and thus 128b/132b? */ -bool
>> > intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
>> > +bool intel_dp_is_uhbr(struct intel_dp *intel_dp)
>> >  {
>> > -   return drm_dp_is_uhbr_rate(crtc_state->port_clock);
>> > +   return drm_dp_is_uhbr_rate(intel_dp->link_rate);
>> >  }
>> >
>> >  /**
>> > @@ -2901,12 +2901,14 @@ intel_dp_audio_compute_config(struct
>> intel_encoder *encoder,
>> >                           struct intel_crtc_state *pipe_config,
>> >                           struct drm_connector_state *conn_state)  {
>> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> > +
>> >     pipe_config->has_audio =
>> >             intel_dp_has_audio(encoder, pipe_config, conn_state) &&
>> >             intel_audio_compute_config(encoder, pipe_config, conn_state);
>> >
>> >     pipe_config->sdp_split_enable = pipe_config->has_audio &&
>> > -                                   intel_dp_is_uhbr(pipe_config);
>> > +                                   intel_dp_is_uhbr(intel_dp);
>> >  }
>> >
>> >  int
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
>> > b/drivers/gpu/drm/i915/display/intel_dp.h
>> > index 530cc97bc42f..cc93c244a2f9 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> > @@ -80,7 +80,7 @@ void intel_dp_audio_compute_config(struct
>> intel_encoder *encoder,
>> >                                struct drm_connector_state *conn_state);
>> bool
>> > intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);  bool
>> > intel_dp_is_edp(struct intel_dp *intel_dp); -bool
>> > intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
>> > +bool intel_dp_is_uhbr(struct intel_dp *intel_dp);
>> >  int intel_dp_link_symbol_size(int rate);  int
>> > intel_dp_link_symbol_clock(int rate);  bool
>> > intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port
>> > port); diff --git
>> > a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> > index 242cb08e9fc4..eb25b59a4eb3 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> > @@ -355,7 +355,7 @@ static u8
>> intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp,
>> >             v = drm_dp_get_adjust_request_voltage(link_status, lane);
>> >             p = drm_dp_get_adjust_request_pre_emphasis(link_status,
>> lane);
>> >     } else {
>> > -           for (lane = 0; lane < crtc_state->lane_count; lane++) {
>> > +           for (lane = 0; lane < intel_dp->lane_count; lane++) {
>> >                     v = max(v,
>> drm_dp_get_adjust_request_voltage(link_status, lane));
>> >                     p = max(p,
>> drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
>> >             }
>> > @@ -380,7 +380,7 @@ static u8 intel_dp_get_lane_adjust_train(struct
>> intel_dp *intel_dp,
>> >                                      const u8
>> link_status[DP_LINK_STATUS_SIZE],
>> >                                      int lane)
>> >  {
>> > -   if (intel_dp_is_uhbr(crtc_state))
>> > +   if (intel_dp_is_uhbr(intel_dp))
>> >             return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp,
>> crtc_state,
>> >                                                           dp_phy,
>> link_status, lane);
>> >     else
>> > @@ -419,18 +419,18 @@ intel_dp_get_adjust_train(struct intel_dp
>> > *intel_dp,  {
>> >     int lane;
>> >
>> > -   if (intel_dp_is_uhbr(crtc_state)) {
>> > +   if (intel_dp_is_uhbr(intel_dp)) {
>> >             lt_dbg(intel_dp, dp_phy,
>> >                    "128b/132b, lanes: %d, "
>> >                    "TX FFE request: " TRAIN_REQ_FMT "\n",
>> > -                  crtc_state->lane_count,
>> > +                  intel_dp->lane_count,
>> >                    TRAIN_REQ_TX_FFE_ARGS(link_status));
>> >     } else {
>> >             lt_dbg(intel_dp, dp_phy,
>> >                    "8b/10b, lanes: %d, "
>> >                    "vswing request: " TRAIN_REQ_FMT ", "
>> >                    "pre-emphasis request: " TRAIN_REQ_FMT "\n",
>> > -                  crtc_state->lane_count,
>> > +                  intel_dp->lane_count,
>> >                    TRAIN_REQ_VSWING_ARGS(link_status),
>> >                    TRAIN_REQ_PREEMPH_ARGS(link_status));
>> >     }
>> > @@ -464,7 +464,7 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
>> >
>> >     buf[0] = dp_train_pat;
>> >     /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
>> > -   memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
>> > +   memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
>> >     len = crtc_state->lane_count + 1;
>> >
>> >     return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len; @@
>> > -531,18 +531,18 @@ void intel_dp_set_signal_levels(struct intel_dp
>> > *intel_dp,  {
>> >     struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>> >
>> > -   if (intel_dp_is_uhbr(crtc_state)) {
>> > +   if (intel_dp_is_uhbr(intel_dp)){
>> >             lt_dbg(intel_dp, dp_phy,
>> >                    "128b/132b, lanes: %d, "
>> >                    "TX FFE presets: " TRAIN_SET_FMT "\n",
>> > -                  crtc_state->lane_count,
>> > +                  intel_dp->lane_count,
>> >                    TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set));
>> >     } else {
>> >             lt_dbg(intel_dp, dp_phy,
>> >                    "8b/10b, lanes: %d, "
>> >                    "vswing levels: " TRAIN_SET_FMT ", "
>> >                    "pre-emphasis levels: " TRAIN_SET_FMT "\n",
>> > -                  crtc_state->lane_count,
>> > +                  intel_dp->lane_count,
>> >                    TRAIN_SET_VSWING_ARGS(intel_dp->train_set),
>> >                    TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set));
>> >     }
>> > @@ -575,9 +575,9 @@ intel_dp_update_link_train(struct intel_dp *intel_dp,
>> >     intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
>> >
>> >     ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
>> > -                           intel_dp->train_set, crtc_state->lane_count);
>> > +                           intel_dp->train_set, intel_dp->lane_count);
>> >
>> > -   return ret == crtc_state->lane_count;
>> > +   return ret == intel_dp->lane_count;
>> >  }
>> >
>> >  /* 128b/132b */
>> > @@ -618,10 +618,10 @@ static bool
>> > intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,  {
>> >     int lane;
>> >
>> > -   for (lane = 0; lane < crtc_state->lane_count; lane++) {
>> > +   for (lane = 0; lane < intel_dp->lane_count; lane++) {
>> >             u8 train_set_lane = intel_dp->train_set[lane];
>> >
>> > -           if (intel_dp_is_uhbr(crtc_state)) {
>> > +           if (intel_dp_is_uhbr(intel_dp)) {
>> >                     if (!intel_dp_lane_max_tx_ffe_reached(train_set_lane))
>> >                             return false;
>> >             } else {
>> > @@ -640,7 +640,7 @@ intel_dp_update_downspread_ctrl(struct intel_dp
>> *intel_dp,
>> >     u8 link_config[2];
>> >
>> >     link_config[0] = crtc_state->vrr.flipline ?
>> DP_MSA_TIMING_PAR_IGNORE_EN : 0;
>> > -   link_config[1] = intel_dp_is_uhbr(crtc_state) ?
>> > +   link_config[1] = intel_dp_is_uhbr(intel_dp) ?
>> >                      DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
>> >     drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
>> link_config,
>> > 2);  } @@ -650,7 +650,7 @@ intel_dp_update_link_bw_set(struct intel_dp
>> > *intel_dp,
>> >                         const struct intel_crtc_state *crtc_state,
>> >                         u8 link_bw, u8 rate_select)
>> >  {
>> > -   u8 lane_count = crtc_state->lane_count;
>> > +   u8 lane_count = intel_dp->lane_count;
>> >
>> >     if (crtc_state->enhanced_framing)
>> >             lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN; @@
>> -689,7 +689,7 @@
>> > intel_dp_prepare_link_train(struct intel_dp *intel_dp,
>> >     if (intel_dp->prepare_link_retrain)
>> >             intel_dp->prepare_link_retrain(intel_dp, crtc_state);
>> >
>> > -   intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
>> > +   intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
>> >                           &link_bw, &rate_select);
>> >
>> >     /*
>> > @@ -730,16 +730,16 @@ intel_dp_prepare_link_train(struct intel_dp
>> *intel_dp,
>> >     return true;
>> >  }
>> >
>> > -static bool intel_dp_adjust_request_changed(const struct
>> > intel_crtc_state *crtc_state,
>> > +static bool intel_dp_adjust_request_changed(struct intel_dp
>> > +*intel_dp,
>> >                                         const u8
>> old_link_status[DP_LINK_STATUS_SIZE],
>> >                                         const u8
>> new_link_status[DP_LINK_STATUS_SIZE])
>> >  {
>> >     int lane;
>> >
>> > -   for (lane = 0; lane < crtc_state->lane_count; lane++) {
>> > +   for (lane = 0; lane < intel_dp->lane_count; lane++) {
>> >             u8 old, new;
>> >
>> > -           if (intel_dp_is_uhbr(crtc_state)) {
>> > +           if (intel_dp_is_uhbr(intel_dp)) {
>> >                     old =
>> drm_dp_get_adjust_tx_ffe_preset(old_link_status, lane);
>> >                     new =
>> drm_dp_get_adjust_tx_ffe_preset(new_link_status, lane);
>> >             } else {
>> > @@ -783,7 +783,7 @@ intel_dp_link_training_clock_recovery(struct
>> > intel_dp *intel_dp,
>> >
>> >     delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux,
>> >                                                 intel_dp->dpcd, dp_phy,
>> > -
>> intel_dp_is_uhbr(crtc_state));
>> > +                                               intel_dp_is_uhbr(intel_dp));
>> >
>> >     /* clock recovery */
>> >     if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy, @@
>> > -816,7 +816,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp
>> *intel_dp,
>> >                     return false;
>> >             }
>> >
>> > -           if (drm_dp_clock_recovery_ok(link_status, crtc_state-
>> >lane_count)) {
>> > +           if (drm_dp_clock_recovery_ok(link_status, intel_dp-
>> >lane_count)) {
>> >                     lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n");
>> >                     return true;
>> >             }
>> > @@ -841,7 +841,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp
>> *intel_dp,
>> >                     return false;
>> >             }
>> >
>> > -           if (!intel_dp_adjust_request_changed(crtc_state,
>> old_link_status, link_status))
>> > +           if (!intel_dp_adjust_request_changed(intel_dp, old_link_status,
>> > +link_status))
>> >                     ++voltage_tries;
>> >             else
>> >                     voltage_tries = 1;
>> > @@ -872,7 +872,7 @@ static u32 intel_dp_training_pattern(struct intel_dp
>> *intel_dp,
>> >     bool source_tps3, sink_tps3, source_tps4, sink_tps4;
>> >
>> >     /* UHBR+ use separate 128b/132b TPS2 */
>> > -   if (intel_dp_is_uhbr(crtc_state))
>> > +   if (intel_dp_is_uhbr(intel_dp))
>> >             return DP_TRAINING_PATTERN_2;
>> >
>> >     /*
>> > @@ -886,7 +886,7 @@ static u32 intel_dp_training_pattern(struct intel_dp
>> *intel_dp,
>> >                 drm_dp_tps4_supported(intel_dp->dpcd);
>> >     if (source_tps4 && sink_tps4) {
>> >             return DP_TRAINING_PATTERN_4;
>> > -   } else if (crtc_state->port_clock == 810000) {
>> > +   } else if (intel_dp->link_rate == 810000) {
>> >             if (!source_tps4)
>> >                     lt_dbg(intel_dp, dp_phy,
>> >                            "8.1 Gbps link rate without source TPS4
>> support\n"); @@
>> > -904,7 +904,7 @@ static u32 intel_dp_training_pattern(struct intel_dp
>> *intel_dp,
>> >                 drm_dp_tps3_supported(intel_dp->dpcd);
>> >     if (source_tps3 && sink_tps3) {
>> >             return  DP_TRAINING_PATTERN_3;
>> > -   } else if (crtc_state->port_clock >= 540000) {
>> > +   } else if (intel_dp->link_rate >= 540000) {
>> >             if (!source_tps3)
>> >                     lt_dbg(intel_dp, dp_phy,
>> >                            ">=5.4/6.48 Gbps link rate without source TPS3
>> support\n");
>> > @@ -934,7 +934,7 @@ intel_dp_link_training_channel_equalization(struct
>> > intel_dp *intel_dp,
>> >
>> >     delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux,
>> >                                             intel_dp->dpcd, dp_phy,
>> > -                                           intel_dp_is_uhbr(crtc_state));
>> > +                                           intel_dp_is_uhbr(intel_dp));
>> >
>> >     training_pattern = intel_dp_training_pattern(intel_dp, crtc_state,
>> dp_phy);
>> >     /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */ @@
>> > -959,7 +959,7 @@ intel_dp_link_training_channel_equalization(struct
>> > intel_dp *intel_dp,
>> >
>> >             /* Make sure clock is still ok */
>> >             if (!drm_dp_clock_recovery_ok(link_status,
>> > -                                         crtc_state->lane_count)) {
>> > +                                         intel_dp->lane_count)) {
>> >                     intel_dp_dump_link_status(intel_dp, dp_phy,
>> link_status);
>> >                     lt_dbg(intel_dp, dp_phy,
>> >                            "Clock recovery check failed, cannot continue
>> channel
>> > equalization\n"); @@ -967,7 +967,7 @@
>> intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
>> >             }
>> >
>> >             if (drm_dp_channel_eq_ok(link_status,
>> > -                                    crtc_state->lane_count)) {
>> > +                                    intel_dp->lane_count)) {
>> >                     channel_eq = true;
>> >                     lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP
>> Training successful\n");
>> >                     break;
>> > @@ -1041,7 +1041,7 @@ void intel_dp_stop_link_train(struct intel_dp
>> *intel_dp,
>> >     intel_dp_program_link_training_pattern(intel_dp, crtc_state,
>> DP_PHY_DPRX,
>> >
>> DP_TRAINING_PATTERN_DISABLE);
>> >
>> > -   if (intel_dp_is_uhbr(crtc_state) &&
>> > +   if (intel_dp_is_uhbr(intel_dp) &&
>> >         wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0,
>> 500)) {
>> >             lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not
>> clearing\n");
>> >     }
>> > @@ -1066,7 +1066,7 @@ intel_dp_link_train_phy(struct intel_dp *intel_dp,
>> >     lt_dbg(intel_dp, dp_phy,
>> >            "Link Training %s at link rate = %d, lane count = %d\n",
>> >            ret ? "passed" : "failed",
>> > -          crtc_state->port_clock, crtc_state->lane_count);
>> > +          intel_dp->link_rate, intel_dp->lane_count);
>> >
>> >     return ret;
>> >  }
>> > @@ -1085,8 +1085,8 @@ static void
>> intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
>> >                    "Link Training failed with HOBL active, not enabling it from
>> now on\n");
>> >             intel_dp->hobl_failed = true;
>> >     } else if (intel_dp_get_link_train_fallback_values(intel_dp,
>> > -                                                      crtc_state-
>> >port_clock,
>> > -                                                      crtc_state-
>> >lane_count)) {
>> > +                                                      intel_dp->link_rate,
>> > +                                                      intel_dp-
>> >lane_count)) {
>> >             return;
>> >     }
>> >
>> > @@ -1192,7 +1192,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp
>> *intel_dp,
>> >                     return false;
>> >             }
>> >
>> > -           if (drm_dp_128b132b_lane_channel_eq_done(link_status,
>> crtc_state->lane_count)) {
>> > +           if (drm_dp_128b132b_lane_channel_eq_done(link_status,
>> > +intel_dp->lane_count)) {
>> >                     lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq
>> done\n");
>> >                     break;
>> >             }
>> > @@ -1287,7 +1287,7 @@ intel_dp_128b132b_lane_cds(struct intel_dp
>> > *intel_dp,
>> >
>> >             if (drm_dp_128b132b_eq_interlane_align_done(link_status)
>> &&
>> >                 drm_dp_128b132b_cds_interlane_align_done(link_status)
>> &&
>> > -               drm_dp_128b132b_lane_symbol_locked(link_status,
>> crtc_state->lane_count)) {
>> > +               drm_dp_128b132b_lane_symbol_locked(link_status,
>> > +intel_dp->lane_count)) {
>> >                     lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align
>> done\n");
>> >                     break;
>> >             }
>> > @@ -1330,7 +1330,7 @@ intel_dp_128b132b_link_train(struct intel_dp
>> *intel_dp,
>> >     lt_dbg(intel_dp, DP_PHY_DPRX,
>> >            "128b/132b Link Training %s at link rate = %d, lane count = %d\n",
>> >            passed ? "passed" : "failed",
>> > -          crtc_state->port_clock, crtc_state->lane_count);
>> > +          intel_dp->link_rate, intel_dp->lane_count);
>> >
>> >     return passed;
>> >  }
>> > @@ -1344,8 +1344,9 @@ intel_dp_128b132b_link_train(struct intel_dp
>> *intel_dp,
>> >   * retraining with reduced link rate/lane parameters if the link training
>> >   * fails.
>> >   * After calling this function intel_dp_stop_link_train() must be called.
>> > + * Return: Link trained status success/failure.
>> >   */
>> > -void intel_dp_start_link_train(struct intel_dp *intel_dp,
>> > +bool intel_dp_start_link_train(struct intel_dp *intel_dp,
>> >                            const struct intel_crtc_state *crtc_state)  {
>> >     struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -1363,7
>> > +1364,7 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
>> >
>> >     intel_dp_prepare_link_train(intel_dp, crtc_state);
>> >
>> > -   if (intel_dp_is_uhbr(crtc_state))
>> > +   if (intel_dp_is_uhbr(intel_dp))
>> >             passed = intel_dp_128b132b_link_train(intel_dp, crtc_state,
>> lttpr_count);
>> >     else
>> >             passed = intel_dp_link_train_all_phys(intel_dp, crtc_state,
>> > lttpr_count); @@ -1382,11 +1383,13 @@ void
>> intel_dp_start_link_train(struct intel_dp *intel_dp,
>> >      */
>> >     if (!passed && i915->display.hotplug.ignore_long_hpd) {
>> >             lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n");
>> > -           return;
>> > +           return true;
>> >     }
>> >
>> >     if (!passed)
>> >             intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
>> > +
>> > +   return passed;
>> >  }
>> >
>> >  void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, @@
>> > -1398,7 +1401,7 @@ void intel_dp_128b132b_sdp_crc16(struct intel_dp
>> *intel_dp,
>> >      * Default value of bit 31 is '0' hence discarding the write
>> >      * TODO: Corrective actions on SDP corruption yet to be defined
>> >      */
>> > -   if (!intel_dp_is_uhbr(crtc_state))
>> > +   if (!intel_dp_is_uhbr(intel_dp))
>> >             return;
>> >
>> >     /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ diff --git
>> > a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> > index 2c8f2775891b..601f7e80476e 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> > @@ -24,7 +24,7 @@ void intel_dp_program_link_training_pattern(struct
>> > intel_dp *intel_dp,  void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
>> >                             const struct intel_crtc_state *crtc_state,
>> >                             enum drm_dp_phy dp_phy);
>> > -void intel_dp_start_link_train(struct intel_dp *intel_dp,
>> > +bool intel_dp_start_link_train(struct intel_dp *intel_dp,
>> >                            const struct intel_crtc_state *crtc_state);  void
>> > intel_dp_stop_link_train(struct intel_dp *intel_dp,
>> >                           const struct intel_crtc_state *crtc_state); diff --git
>> > a/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> > index 5fa25a5a36b5..27994a3b568c 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> > @@ -52,13 +52,13 @@
>> >
>> >  static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int
>> bpp,
>> >                                       const struct drm_display_mode
>> *adjusted_mode,
>> > -                                     struct intel_crtc_state *crtc_state,
>> > +                                     struct intel_dp *intel_dp,
>> >                                       bool dsc)
>> >  {
>> > -   if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) {
>> > +   if (intel_dp_is_uhbr(intel_dp) && DISPLAY_VER(i915) < 14 && dsc) {
>> >             int output_bpp = bpp;
>> >             /* DisplayPort 2 128b/132b, bits per lane is always 32 */
>> > -           int symbol_clock = crtc_state->port_clock / 32;
>> > +           int symbol_clock = intel_dp->link_rate / 32;
>> >
>> >             if (output_bpp * adjusted_mode->crtc_clock >=
>> >                 symbol_clock * 72) {
>> > @@ -71,7 +71,8 @@ static int intel_dp_mst_check_constraints(struct
>> drm_i915_private *i915, int bpp
>> >     return 0;
>> >  }
>> >
>> > -static int intel_dp_mst_bw_overhead(const struct intel_crtc_state
>> > *crtc_state,
>> > +static int intel_dp_mst_bw_overhead(struct intel_dp *intel_dp,
>> > +                               const struct intel_crtc_state *crtc_state,
>> >                                 const struct intel_connector *connector,
>> >                                 bool ssc, bool dsc, int bpp_x16)  { @@ -81,7
>> +82,7 @@ static
>> > int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
>> >     int dsc_slice_count = 0;
>> >     int overhead;
>> >
>> > -   flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR
>> : 0;
>> > +   flags |= intel_dp_is_uhbr(intel_dp) ? DRM_DP_BW_OVERHEAD_UHBR :
>> 0;
>> >     flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
>> >     flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
>> >
>> > @@ -170,12 +171,12 @@ static int
>> intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
>> >             if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))
>> >                     return -EINVAL;
>> >
>> > -           crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
>> > +           crtc_state->fec_enable = !intel_dp_is_uhbr(intel_dp);
>> >     }
>> >
>> >     mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp-
>> >mst_mgr,
>> > -                                                 crtc_state->port_clock,
>> > -                                                 crtc_state->lane_count);
>> > +                                                 intel_dp->link_rate,
>> > +                                                 intel_dp->lane_count);
>> >
>> >     drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max
>> bpp %d\n",
>> >                 min_bpp, max_bpp);
>> > @@ -188,16 +189,18 @@ static int
>> > intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
>> >
>> >             drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
>> >
>> > -           ret = intel_dp_mst_check_constraints(i915, bpp,
>> adjusted_mode, crtc_state, dsc);
>> > +           ret = intel_dp_mst_check_constraints(i915, bpp,
>> adjusted_mode,
>> > +intel_dp, dsc);
>> >             if (ret)
>> >                     continue;
>> >
>> >             link_bpp_x16 = to_bpp_x16(dsc ? bpp :
>> >                                       intel_dp_output_bpp(crtc_state-
>> >output_format, bpp));
>> >
>> > -           local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
>> connector,
>> > +           local_bw_overhead = intel_dp_mst_bw_overhead(intel_dp,
>> > +                                                        crtc_state,
>> connector,
>> >                                                          false, dsc,
>> link_bpp_x16);
>> > -           remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
>> connector,
>> > +           remote_bw_overhead = intel_dp_mst_bw_overhead(intel_dp,
>> > +                                                         crtc_state,
>> connector,
>> >                                                           true, dsc,
>> link_bpp_x16);
>> >
>> >             intel_dp_mst_compute_m_n(crtc_state, connector, @@ -368,7
>> +371,7 @@
>> > static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
>> >     struct intel_dp *intel_dp = &intel_mst->primary->dp;
>> >     struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
>> >     struct drm_dp_mst_topology_state *topology_state;
>> > -   u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?
>> > +   u8 link_coding_cap = intel_dp_is_uhbr(intel_dp) ?
>> >             DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;
>> >
>> >     topology_state =
>> > drm_atomic_get_mst_topology_state(conn_state->state, mgr); @@ -1123,7
>> > +1126,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state
>> > *state,
>> >
>> >     drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
>> >
>> > -   if (intel_dp_is_uhbr(pipe_config)) {
>> > +   if (intel_dp_is_uhbr(intel_dp)) {
>> >             const struct drm_display_mode *adjusted_mode =
>> >                     &pipe_config->hw.adjusted_mode;
>> >             u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
>>
>> --
>> Jani Nikula, Intel

-- 
Jani Nikula, Intel

RE: [RFC 3/4] drm/i915/dp: use link rate and lane count in intel_dp struct

[Murthy, Arun R]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Wednesday, February 14, 2024 5:07 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Deak, Imre <imre.deak@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>
> Subject: RE: [RFC 3/4] drm/i915/dp: use link rate and lane count in intel_dp
> struct
> 
> On Wed, 14 Feb 2024, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> >> -----Original Message-----
> >> From: Nikula, Jani <jani.nikula@intel.com>
> >> Sent: Tuesday, February 13, 2024 11:43 PM
> >> To: Murthy, Arun R <arun.r.murthy@intel.com>;
> >> intel-gfx@lists.freedesktop.org
> >> Cc: Deak, Imre <imre.deak@intel.com>; Syrjala, Ville
> >> <ville.syrjala@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> >> Murthy, Arun R <arun.r.murthy@intel.com>
> >> Subject: Re: [RFC 3/4] drm/i915/dp: use link rate and lane count in
> >> intel_dp struct
> >>
> >> On Tue, 06 Feb 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> >> > The link rate and lane count are now part of the intel_crtc_state
> >> > structure. These two parameters are nothing to do with the crtc and
> >> > are more confined to DP.
> >>
> >> As said offline, the parameters were specifically added to crtc state
> >> for both atomic and the state checker.
> >>
> > I am a bit lost as to from where we need this in atomic and state checker for
> link rate and lane count as none of these parameters are coming from user nor
> does it change in modeset. On driver init the link rate and lane count value is
> fetched from the table and thereafter its constant, but used in many places for
> configuration/calculation purpose for which the same in intel_dp struct would
> do.
> 
> Compute config chooses the link rate and lane count to use.
> 
> Compute config may only modify crtc state, nothing else.
> 
> State checker reads out the state from the hardware, and it must only read it to
> the crtc state, nowhere else.
> 
> State checker must only compare two crtc states, one from software and one
> read from the hardware.
> 
> Having the link rate and lane count in struct intel_dp does not satisfy these
> conditions.
> 
> See also 90a6b7b052b1 ("drm/i915: Move intel_dp->lane_count into
> pipe_config").
> 
This link rate and lane count computation is done in dp_detect and nothing to be done in compute.
Also for this reason having every variable in intel_crtc would eventually make intel_crtc_state the way i915 device private moved. I felt link_rate and lane_count can be confined to intel_dp without modifying the existing code flow.

As commented in the other patch if for each and every fallback we need to send uevent to the user is recommended, then this discussion doesn't arise. If this is really required I am *open* to take this change and float the patch.

Thanks and Regards,
Arun R Murthy
-------------------

> 
> BR,
> Jani.
> 
> 
> >
> > On link training failure, the link rate and lane count tends to change and new
> value is initialized in intel_dp struct.
> >
> > Thanks and Regards,
> > Arun R Murthy
> > --------------------
> >
> >> No go.
> >>
> >>
> >> BR,
> >> Jani.
> >>
> >> >
> >> > TODO: Need to still seperate out the use of link rate and port
> >> > clock which is in intel_dp and intel_crtc_state structure.
> >> >
> >> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 16 ++--
> >> >  drivers/gpu/drm/i915/display/intel_ddi.c      | 21 ++---
> >> >  .../drm/i915/display/intel_ddi_buf_trans.c    |  7 +-
> >> >  drivers/gpu/drm/i915/display/intel_dp.c       |  8 +-
> >> >  drivers/gpu/drm/i915/display/intel_dp.h       |  2 +-
> >> >  .../drm/i915/display/intel_dp_link_training.c | 81
> >> > ++++++++++---------  .../drm/i915/display/intel_dp_link_training.h
> >> > ++++++++++|  2 +-
> >> >  drivers/gpu/drm/i915/display/intel_dp_mst.c   | 29 ++++---
> >> >  8 files changed, 92 insertions(+), 74 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >> > index 288a00e083c8..cde8f26ba26b 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >> > @@ -414,6 +414,7 @@ void intel_cx0_phy_set_signal_levels(struct
> >> > intel_encoder *encoder,  {
> >> >     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> >> >     const struct intel_ddi_buf_trans *trans;
> >> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >> >     enum phy phy = intel_port_to_phy(i915, encoder->port);
> >> >     u8 owned_lane_mask;
> >> >     intel_wakeref_t wakeref;
> >> > @@ -446,7 +447,7 @@ void intel_cx0_phy_set_signal_levels(struct
> >> intel_encoder *encoder,
> >> >                           MB_WRITE_COMMITTED);
> >> >     }
> >> >
> >> > -   for (ln = 0; ln < crtc_state->lane_count; ln++) {
> >> > +   for (ln = 0; ln < intel_dp->lane_count; ln++) {
> >> >             int level = intel_ddi_level(encoder, crtc_state, ln);
> >> >             int lane = ln / 2;
> >> >             int tx = ln % 2;
> >> > @@ -2327,10 +2328,11 @@ static void intel_c20_pll_program(struct
> >> drm_i915_private *i915,
> >> >                               const struct intel_crtc_state *crtc_state,
> >> >                               struct intel_encoder *encoder)  {
> >> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >> >     const struct intel_c20pll_state *pll_state = &crtc_state-
> >> >cx0pll_state.c20;
> >> >     bool dp = false;
> >> > -   int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES :
> >> INTEL_CX0_LANE0;
> >> > -   u32 clock = crtc_state->port_clock;
> >> > +   int lane = intel_dp->lane_count > 2 ? INTEL_CX0_BOTH_LANES :
> >> INTEL_CX0_LANE0;
> >> > +   u32 clock = intel_dp->link_rate;
> >> >     bool cntx;
> >> >     int i;
> >> >
> >> > @@ -2455,6 +2457,7 @@ static void
> >> > intel_program_port_clock_ctl(struct
> >> intel_encoder *encoder,
> >> >                                      const struct intel_crtc_state
> >> *crtc_state,
> >> >                                      bool lane_reversal)  {
> >> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >> >     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> >> >     u32 val = 0;
> >> >
> >> > @@ -2475,7 +2478,7 @@ static void
> >> > intel_program_port_clock_ctl(struct
> >> > intel_encoder *encoder,
> >> >
> >> >     /* TODO: HDMI FRL */
> >> >     /* DP2.0 10G and 20G rates enable MPLLA*/
> >> > -   if (crtc_state->port_clock == 1000000 || crtc_state->port_clock ==
> >> 2000000)
> >> > +   if (intel_dp->link_rate == 1000000 || intel_dp->link_rate ==
> >> > +2000000)
> >> >             val |= crtc_state->cx0pll_state.ssc_enabled ?
> >> XELPDP_SSC_ENABLE_PLLA : 0;
> >> >     else
> >> >             val |= crtc_state->cx0pll_state.ssc_enabled ?
> >> > XELPDP_SSC_ENABLE_PLLB : 0; @@ -2705,6 +2708,7 @@ static void
> >> intel_cx0pll_enable(struct intel_encoder *encoder,
> >> >                             const struct intel_crtc_state *crtc_state)  {
> >> >     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> >> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >> >     enum phy phy = intel_port_to_phy(i915, encoder->port);
> >> >     struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> >> >     bool lane_reversal = dig_port->saved_port_bits &
> >> > DDI_BUF_PORT_REVERSAL; @@ -2744,7 +2748,7 @@ static void
> >> intel_cx0pll_enable(struct intel_encoder *encoder,
> >> >      * 6. Program the enabled and disabled owned PHY lane
> >> >      * transmitters over message bus
> >> >      */
> >> > -   intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count,
> >> lane_reversal);
> >> > +   intel_cx0_program_phy_lane(i915, encoder, intel_dp->lane_count,
> >> > +lane_reversal);
> >> >
> >> >     /*
> >> >      * 7. Follow the Display Voltage Frequency Switching - Sequence
> >> > @@
> >> > -2756,7 +2760,7 @@ static void intel_cx0pll_enable(struct
> >> > intel_encoder
> >> *encoder,
> >> >      * clock frequency.
> >> >      */
> >> >     intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
> >> > -                  crtc_state->port_clock);
> >> > +                  intel_dp->link_rate);
> >> >
> >> >     /*
> >> >      * 9. Set PORT_CLOCK_CTL register PCLK PLL Request diff --git
> >> > a/drivers/gpu/drm/i915/display/intel_ddi.c
> >> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> > index bea441590204..ed7620e7f763 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> > @@ -334,18 +334,18 @@ static void intel_ddi_init_dp_buf_reg(struct
> >> > intel_encoder *encoder,
> >> >
> >> >     /* DDI_BUF_CTL_ENABLE will be set by
> >> intel_ddi_prepare_link_retrain() later */
> >> >     intel_dp->DP = dig_port->saved_port_bits |
> >> > -           DDI_PORT_WIDTH(crtc_state->lane_count) |
> >> > +           DDI_PORT_WIDTH(intel_dp->lane_count) |
> >> >             DDI_BUF_TRANS_SELECT(0);
> >> >
> >> >     if (DISPLAY_VER(i915) >= 14) {
> >> > -           if (intel_dp_is_uhbr(crtc_state))
> >> > +           if (intel_dp_is_uhbr(intel_dp))
> >> >                     intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
> >> >             else
> >> >                     intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
> >> >     }
> >> >
> >> >     if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
> >> > -           intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
> >> > +           intel_dp->DP |=
> >> > + ddi_buf_phy_link_rate(intel_dp->link_rate);
> >> >             if (!intel_tc_port_in_tbt_alt_mode(dig_port))
> >> >                     intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> >> >     }
> >> > @@ -456,10 +456,11 @@ intel_ddi_config_transcoder_dp2(struct
> >> intel_encoder *encoder,
> >> >                             const struct intel_crtc_state *crtc_state)  {
> >> >     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> >> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >> >     enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >> >     u32 val = 0;
> >> >
> >> > -   if (intel_dp_is_uhbr(crtc_state))
> >> > +   if (intel_dp_is_uhbr(intel_dp))
> >> >             val = TRANS_DP2_128B132B_CHANNEL_CODING;
> >> >
> >> >     intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); @@ -
> >> 477,6
> >> > +478,7 @@ intel_ddi_transcoder_func_reg_val_get(struct
> >> > +intel_encoder
> >> > *encoder,  {
> >> >     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> >     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >> >     enum pipe pipe = crtc->pipe;
> >> >     enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >> >     enum port port = encoder->port; @@ -552,11 +554,11 @@
> >> > intel_ddi_transcoder_func_reg_val_get(struct
> >> intel_encoder *encoder,
> >> >             temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
> >> >             temp |= (crtc_state->fdi_lanes - 1) << 1;
> >> >     } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
> >> > -           if (intel_dp_is_uhbr(crtc_state))
> >> > +           if (intel_dp_is_uhbr(intel_dp))
> >> >                     temp |=
> >> TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
> >> >             else
> >> >                     temp |= TRANS_DDI_MODE_SELECT_DP_MST;
> >> > -           temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
> >> > +           temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
> >> >
> >> >             if (DISPLAY_VER(dev_priv) >= 12) {
> >> >                     enum transcoder master; @@ -1414,7 +1416,7 @@
> >> > static int intel_ddi_dp_level(struct intel_dp *intel_dp,  {
> >> >     u8 train_set = intel_dp->train_set[lane];
> >> >
> >> > -   if (intel_dp_is_uhbr(crtc_state)) {
> >> > +   if (intel_dp_is_uhbr(intel_dp)) {
> >> >             return train_set & DP_TX_FFE_PRESET_VALUE_MASK;
> >> >     } else {
> >> >             u8 signal_levels = train_set &
> >> (DP_TRAIN_VOLTAGE_SWING_MASK | @@
> >> > -2456,15 +2458,16 @@ static void mtl_port_buf_ctl_program(struct
> >> > intel_encoder *encoder,  {
> >> >     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> >> >     struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> >> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >> >     enum port port = encoder->port;
> >> >     u32 val;
> >> >
> >> >     val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port));
> >> >     val &= ~XELPDP_PORT_WIDTH_MASK;
> >> > -   val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state-
> >> >lane_count));
> >> > +   val |= XELPDP_PORT_WIDTH(mtl_get_port_width(intel_dp-
> >> >lane_count));
> >> >
> >> >     val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK;
> >> > -   if (intel_dp_is_uhbr(crtc_state))
> >> > +   if (intel_dp_is_uhbr(intel_dp))
> >> >             val |= XELPDP_PORT_BUF_PORT_DATA_40BIT;
> >> >     else
> >> >             val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; diff --git
> >> > a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> >> > b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> >> > index de809e2d9cac..e490bffd3e49 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> >> > @@ -1679,8 +1679,10 @@ dg2_get_snps_buf_trans(struct intel_encoder
> >> *encoder,
> >> >                    const struct intel_crtc_state *crtc_state,
> >> >                    int *n_entries)
> >> >  {
> >> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >> > +
> >> >     if (intel_crtc_has_dp_encoder(crtc_state) &&
> >> > -       intel_dp_is_uhbr(crtc_state))
> >> > +       intel_dp_is_uhbr(intel_dp))
> >> >             return intel_get_buf_trans(&dg2_snps_trans_uhbr, n_entries);
> >> >     else
> >> >             return intel_get_buf_trans(&dg2_snps_trans, n_entries);
> >> > @@ -
> >> 1692,9
> >> > +1694,10 @@ mtl_get_cx0_buf_trans(struct intel_encoder *encoder,
> >> >                   int *n_entries)
> >> >  {
> >> >     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> >> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >> >     enum phy phy = intel_port_to_phy(i915, encoder->port);
> >> >
> >> > -   if (intel_crtc_has_dp_encoder(crtc_state) && crtc_state->port_clock >=
> >> 1000000)
> >> > +   if (intel_crtc_has_dp_encoder(crtc_state) &&
> >> > +intel_dp_is_uhbr(intel_dp))
> >> >             return intel_get_buf_trans(&mtl_c20_trans_uhbr, n_entries);
> >> >     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> >> !(intel_is_c10phy(i915, phy)))
> >> >             return intel_get_buf_trans(&mtl_c20_trans_hdmi,
> >> > n_entries);
> >> diff
> >> > --git a/drivers/gpu/drm/i915/display/intel_dp.c
> >> > b/drivers/gpu/drm/i915/display/intel_dp.c
> >> > index 82d354a6b0cd..ba3c8201c0ef 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> > @@ -167,9 +167,9 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
> >> > static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> >> >
> >> >  /* Is link rate UHBR and thus 128b/132b? */ -bool
> >> > intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
> >> > +bool intel_dp_is_uhbr(struct intel_dp *intel_dp)
> >> >  {
> >> > -   return drm_dp_is_uhbr_rate(crtc_state->port_clock);
> >> > +   return drm_dp_is_uhbr_rate(intel_dp->link_rate);
> >> >  }
> >> >
> >> >  /**
> >> > @@ -2901,12 +2901,14 @@ intel_dp_audio_compute_config(struct
> >> intel_encoder *encoder,
> >> >                           struct intel_crtc_state *pipe_config,
> >> >                           struct drm_connector_state *conn_state)
> >> > {
> >> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >> > +
> >> >     pipe_config->has_audio =
> >> >             intel_dp_has_audio(encoder, pipe_config, conn_state) &&
> >> >             intel_audio_compute_config(encoder, pipe_config,
> >> > conn_state);
> >> >
> >> >     pipe_config->sdp_split_enable = pipe_config->has_audio &&
> >> > -                                   intel_dp_is_uhbr(pipe_config);
> >> > +                                   intel_dp_is_uhbr(intel_dp);
> >> >  }
> >> >
> >> >  int
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> >> > b/drivers/gpu/drm/i915/display/intel_dp.h
> >> > index 530cc97bc42f..cc93c244a2f9 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> >> > @@ -80,7 +80,7 @@ void intel_dp_audio_compute_config(struct
> >> intel_encoder *encoder,
> >> >                                struct drm_connector_state
> >> > *conn_state);
> >> bool
> >> > intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);  bool
> >> > intel_dp_is_edp(struct intel_dp *intel_dp); -bool
> >> > intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
> >> > +bool intel_dp_is_uhbr(struct intel_dp *intel_dp);
> >> >  int intel_dp_link_symbol_size(int rate);  int
> >> > intel_dp_link_symbol_clock(int rate);  bool
> >> > intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port
> >> > port); diff --git
> >> > a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> > index 242cb08e9fc4..eb25b59a4eb3 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> > @@ -355,7 +355,7 @@ static u8
> >> intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp,
> >> >             v = drm_dp_get_adjust_request_voltage(link_status, lane);
> >> >             p = drm_dp_get_adjust_request_pre_emphasis(link_status,
> >> lane);
> >> >     } else {
> >> > -           for (lane = 0; lane < crtc_state->lane_count; lane++) {
> >> > +           for (lane = 0; lane < intel_dp->lane_count; lane++) {
> >> >                     v = max(v,
> >> drm_dp_get_adjust_request_voltage(link_status, lane));
> >> >                     p = max(p,
> >> drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
> >> >             }
> >> > @@ -380,7 +380,7 @@ static u8 intel_dp_get_lane_adjust_train(struct
> >> intel_dp *intel_dp,
> >> >                                      const u8
> >> link_status[DP_LINK_STATUS_SIZE],
> >> >                                      int lane)  {
> >> > -   if (intel_dp_is_uhbr(crtc_state))
> >> > +   if (intel_dp_is_uhbr(intel_dp))
> >> >             return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp,
> >> crtc_state,
> >> >                                                           dp_phy,
> >> link_status, lane);
> >> >     else
> >> > @@ -419,18 +419,18 @@ intel_dp_get_adjust_train(struct intel_dp
> >> > *intel_dp,  {
> >> >     int lane;
> >> >
> >> > -   if (intel_dp_is_uhbr(crtc_state)) {
> >> > +   if (intel_dp_is_uhbr(intel_dp)) {
> >> >             lt_dbg(intel_dp, dp_phy,
> >> >                    "128b/132b, lanes: %d, "
> >> >                    "TX FFE request: " TRAIN_REQ_FMT "\n",
> >> > -                  crtc_state->lane_count,
> >> > +                  intel_dp->lane_count,
> >> >                    TRAIN_REQ_TX_FFE_ARGS(link_status));
> >> >     } else {
> >> >             lt_dbg(intel_dp, dp_phy,
> >> >                    "8b/10b, lanes: %d, "
> >> >                    "vswing request: " TRAIN_REQ_FMT ", "
> >> >                    "pre-emphasis request: " TRAIN_REQ_FMT "\n",
> >> > -                  crtc_state->lane_count,
> >> > +                  intel_dp->lane_count,
> >> >                    TRAIN_REQ_VSWING_ARGS(link_status),
> >> >                    TRAIN_REQ_PREEMPH_ARGS(link_status));
> >> >     }
> >> > @@ -464,7 +464,7 @@ intel_dp_set_link_train(struct intel_dp
> >> > *intel_dp,
> >> >
> >> >     buf[0] = dp_train_pat;
> >> >     /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
> >> > -   memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
> >> > +   memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
> >> >     len = crtc_state->lane_count + 1;
> >> >
> >> >     return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
> >> > @@
> >> > -531,18 +531,18 @@ void intel_dp_set_signal_levels(struct intel_dp
> >> > *intel_dp,  {
> >> >     struct intel_encoder *encoder =
> >> > &dp_to_dig_port(intel_dp)->base;
> >> >
> >> > -   if (intel_dp_is_uhbr(crtc_state)) {
> >> > +   if (intel_dp_is_uhbr(intel_dp)){
> >> >             lt_dbg(intel_dp, dp_phy,
> >> >                    "128b/132b, lanes: %d, "
> >> >                    "TX FFE presets: " TRAIN_SET_FMT "\n",
> >> > -                  crtc_state->lane_count,
> >> > +                  intel_dp->lane_count,
> >> >                    TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set));
> >> >     } else {
> >> >             lt_dbg(intel_dp, dp_phy,
> >> >                    "8b/10b, lanes: %d, "
> >> >                    "vswing levels: " TRAIN_SET_FMT ", "
> >> >                    "pre-emphasis levels: " TRAIN_SET_FMT "\n",
> >> > -                  crtc_state->lane_count,
> >> > +                  intel_dp->lane_count,
> >> >                    TRAIN_SET_VSWING_ARGS(intel_dp->train_set),
> >> >                    TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set));
> >> >     }
> >> > @@ -575,9 +575,9 @@ intel_dp_update_link_train(struct intel_dp
> *intel_dp,
> >> >     intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
> >> >
> >> >     ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
> >> > -                           intel_dp->train_set, crtc_state->lane_count);
> >> > +                           intel_dp->train_set,
> >> > + intel_dp->lane_count);
> >> >
> >> > -   return ret == crtc_state->lane_count;
> >> > +   return ret == intel_dp->lane_count;
> >> >  }
> >> >
> >> >  /* 128b/132b */
> >> > @@ -618,10 +618,10 @@ static bool
> >> > intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,  {
> >> >     int lane;
> >> >
> >> > -   for (lane = 0; lane < crtc_state->lane_count; lane++) {
> >> > +   for (lane = 0; lane < intel_dp->lane_count; lane++) {
> >> >             u8 train_set_lane = intel_dp->train_set[lane];
> >> >
> >> > -           if (intel_dp_is_uhbr(crtc_state)) {
> >> > +           if (intel_dp_is_uhbr(intel_dp)) {
> >> >                     if (!intel_dp_lane_max_tx_ffe_reached(train_set_lane))
> >> >                             return false;
> >> >             } else {
> >> > @@ -640,7 +640,7 @@ intel_dp_update_downspread_ctrl(struct intel_dp
> >> *intel_dp,
> >> >     u8 link_config[2];
> >> >
> >> >     link_config[0] = crtc_state->vrr.flipline ?
> >> DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> >> > -   link_config[1] = intel_dp_is_uhbr(crtc_state) ?
> >> > +   link_config[1] = intel_dp_is_uhbr(intel_dp) ?
> >> >                      DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> >> >     drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
> >> link_config,
> >> > 2);  } @@ -650,7 +650,7 @@ intel_dp_update_link_bw_set(struct
> >> > intel_dp *intel_dp,
> >> >                         const struct intel_crtc_state *crtc_state,
> >> >                         u8 link_bw, u8 rate_select)  {
> >> > -   u8 lane_count = crtc_state->lane_count;
> >> > +   u8 lane_count = intel_dp->lane_count;
> >> >
> >> >     if (crtc_state->enhanced_framing)
> >> >             lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN; @@
> >> -689,7 +689,7 @@
> >> > intel_dp_prepare_link_train(struct intel_dp *intel_dp,
> >> >     if (intel_dp->prepare_link_retrain)
> >> >             intel_dp->prepare_link_retrain(intel_dp, crtc_state);
> >> >
> >> > -   intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
> >> > +   intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
> >> >                           &link_bw, &rate_select);
> >> >
> >> >     /*
> >> > @@ -730,16 +730,16 @@ intel_dp_prepare_link_train(struct intel_dp
> >> *intel_dp,
> >> >     return true;
> >> >  }
> >> >
> >> > -static bool intel_dp_adjust_request_changed(const struct
> >> > intel_crtc_state *crtc_state,
> >> > +static bool intel_dp_adjust_request_changed(struct intel_dp
> >> > +*intel_dp,
> >> >                                         const u8
> >> old_link_status[DP_LINK_STATUS_SIZE],
> >> >                                         const u8
> >> new_link_status[DP_LINK_STATUS_SIZE])
> >> >  {
> >> >     int lane;
> >> >
> >> > -   for (lane = 0; lane < crtc_state->lane_count; lane++) {
> >> > +   for (lane = 0; lane < intel_dp->lane_count; lane++) {
> >> >             u8 old, new;
> >> >
> >> > -           if (intel_dp_is_uhbr(crtc_state)) {
> >> > +           if (intel_dp_is_uhbr(intel_dp)) {
> >> >                     old =
> >> drm_dp_get_adjust_tx_ffe_preset(old_link_status, lane);
> >> >                     new =
> >> drm_dp_get_adjust_tx_ffe_preset(new_link_status, lane);
> >> >             } else {
> >> > @@ -783,7 +783,7 @@ intel_dp_link_training_clock_recovery(struct
> >> > intel_dp *intel_dp,
> >> >
> >> >     delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux,
> >> >                                                 intel_dp->dpcd,
> >> > dp_phy,
> >> > -
> >> intel_dp_is_uhbr(crtc_state));
> >> > +
> >> > + intel_dp_is_uhbr(intel_dp));
> >> >
> >> >     /* clock recovery */
> >> >     if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy, @@
> >> > -816,7 +816,7 @@ intel_dp_link_training_clock_recovery(struct
> >> > intel_dp
> >> *intel_dp,
> >> >                     return false;
> >> >             }
> >> >
> >> > -           if (drm_dp_clock_recovery_ok(link_status, crtc_state-
> >> >lane_count)) {
> >> > +           if (drm_dp_clock_recovery_ok(link_status, intel_dp-
> >> >lane_count)) {
> >> >                     lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n");
> >> >                     return true;
> >> >             }
> >> > @@ -841,7 +841,7 @@ intel_dp_link_training_clock_recovery(struct
> >> >intel_dp
> >> *intel_dp,
> >> >                     return false;
> >> >             }
> >> >
> >> > -           if (!intel_dp_adjust_request_changed(crtc_state,
> >> old_link_status, link_status))
> >> > +           if (!intel_dp_adjust_request_changed(intel_dp,
> >> > +old_link_status,
> >> > +link_status))
> >> >                     ++voltage_tries;
> >> >             else
> >> >                     voltage_tries = 1; @@ -872,7 +872,7 @@ static
> >> > u32 intel_dp_training_pattern(struct intel_dp
> >> *intel_dp,
> >> >     bool source_tps3, sink_tps3, source_tps4, sink_tps4;
> >> >
> >> >     /* UHBR+ use separate 128b/132b TPS2 */
> >> > -   if (intel_dp_is_uhbr(crtc_state))
> >> > +   if (intel_dp_is_uhbr(intel_dp))
> >> >             return DP_TRAINING_PATTERN_2;
> >> >
> >> >     /*
> >> > @@ -886,7 +886,7 @@ static u32 intel_dp_training_pattern(struct
> >> > intel_dp
> >> *intel_dp,
> >> >                 drm_dp_tps4_supported(intel_dp->dpcd);
> >> >     if (source_tps4 && sink_tps4) {
> >> >             return DP_TRAINING_PATTERN_4;
> >> > -   } else if (crtc_state->port_clock == 810000) {
> >> > +   } else if (intel_dp->link_rate == 810000) {
> >> >             if (!source_tps4)
> >> >                     lt_dbg(intel_dp, dp_phy,
> >> >                            "8.1 Gbps link rate without source TPS4
> >> support\n"); @@
> >> > -904,7 +904,7 @@ static u32 intel_dp_training_pattern(struct
> >> > intel_dp
> >> *intel_dp,
> >> >                 drm_dp_tps3_supported(intel_dp->dpcd);
> >> >     if (source_tps3 && sink_tps3) {
> >> >             return  DP_TRAINING_PATTERN_3;
> >> > -   } else if (crtc_state->port_clock >= 540000) {
> >> > +   } else if (intel_dp->link_rate >= 540000) {
> >> >             if (!source_tps3)
> >> >                     lt_dbg(intel_dp, dp_phy,
> >> >                            ">=5.4/6.48 Gbps link rate without
> >> > source TPS3
> >> support\n");
> >> > @@ -934,7 +934,7 @@
> >> > intel_dp_link_training_channel_equalization(struct
> >> > intel_dp *intel_dp,
> >> >
> >> >     delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux,
> >> >                                             intel_dp->dpcd, dp_phy,
> >> > -                                           intel_dp_is_uhbr(crtc_state));
> >> > +
> >> > + intel_dp_is_uhbr(intel_dp));
> >> >
> >> >     training_pattern = intel_dp_training_pattern(intel_dp,
> >> > crtc_state,
> >> dp_phy);
> >> >     /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */ @@
> >> > -959,7 +959,7 @@ intel_dp_link_training_channel_equalization(struct
> >> > intel_dp *intel_dp,
> >> >
> >> >             /* Make sure clock is still ok */
> >> >             if (!drm_dp_clock_recovery_ok(link_status,
> >> > -                                         crtc_state->lane_count)) {
> >> > +                                         intel_dp->lane_count)) {
> >> >                     intel_dp_dump_link_status(intel_dp, dp_phy,
> >> link_status);
> >> >                     lt_dbg(intel_dp, dp_phy,
> >> >                            "Clock recovery check failed, cannot
> >> > continue
> >> channel
> >> > equalization\n"); @@ -967,7 +967,7 @@
> >> intel_dp_link_training_channel_equalization(struct intel_dp
> >> *intel_dp,
> >> >             }
> >> >
> >> >             if (drm_dp_channel_eq_ok(link_status,
> >> > -                                    crtc_state->lane_count)) {
> >> > +                                    intel_dp->lane_count)) {
> >> >                     channel_eq = true;
> >> >                     lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP
> >> Training successful\n");
> >> >                     break;
> >> > @@ -1041,7 +1041,7 @@ void intel_dp_stop_link_train(struct intel_dp
> >> *intel_dp,
> >> >     intel_dp_program_link_training_pattern(intel_dp, crtc_state,
> >> DP_PHY_DPRX,
> >> >
> >> DP_TRAINING_PATTERN_DISABLE);
> >> >
> >> > -   if (intel_dp_is_uhbr(crtc_state) &&
> >> > +   if (intel_dp_is_uhbr(intel_dp) &&
> >> >         wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state)
> >> > == 0,
> >> 500)) {
> >> >             lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not
> >> clearing\n");
> >> >     }
> >> > @@ -1066,7 +1066,7 @@ intel_dp_link_train_phy(struct intel_dp
> *intel_dp,
> >> >     lt_dbg(intel_dp, dp_phy,
> >> >            "Link Training %s at link rate = %d, lane count = %d\n",
> >> >            ret ? "passed" : "failed",
> >> > -          crtc_state->port_clock, crtc_state->lane_count);
> >> > +          intel_dp->link_rate, intel_dp->lane_count);
> >> >
> >> >     return ret;
> >> >  }
> >> > @@ -1085,8 +1085,8 @@ static void
> >> intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
> >> >                    "Link Training failed with HOBL active, not
> >> > enabling it from
> >> now on\n");
> >> >             intel_dp->hobl_failed = true;
> >> >     } else if (intel_dp_get_link_train_fallback_values(intel_dp,
> >> > -                                                      crtc_state-
> >> >port_clock,
> >> > -                                                      crtc_state-
> >> >lane_count)) {
> >> > +                                                      intel_dp->link_rate,
> >> > +                                                      intel_dp-
> >> >lane_count)) {
> >> >             return;
> >> >     }
> >> >
> >> > @@ -1192,7 +1192,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp
> >> *intel_dp,
> >> >                     return false;
> >> >             }
> >> >
> >> > -           if (drm_dp_128b132b_lane_channel_eq_done(link_status,
> >> crtc_state->lane_count)) {
> >> > +           if (drm_dp_128b132b_lane_channel_eq_done(link_status,
> >> > +intel_dp->lane_count)) {
> >> >                     lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq
> >> done\n");
> >> >                     break;
> >> >             }
> >> > @@ -1287,7 +1287,7 @@ intel_dp_128b132b_lane_cds(struct intel_dp
> >> > *intel_dp,
> >> >
> >> >             if
> >> > (drm_dp_128b132b_eq_interlane_align_done(link_status)
> >> &&
> >> >
> >> > drm_dp_128b132b_cds_interlane_align_done(link_status)
> >> &&
> >> > -               drm_dp_128b132b_lane_symbol_locked(link_status,
> >> crtc_state->lane_count)) {
> >> > +               drm_dp_128b132b_lane_symbol_locked(link_status,
> >> > +intel_dp->lane_count)) {
> >> >                     lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane
> >> > align
> >> done\n");
> >> >                     break;
> >> >             }
> >> > @@ -1330,7 +1330,7 @@ intel_dp_128b132b_link_train(struct intel_dp
> >> *intel_dp,
> >> >     lt_dbg(intel_dp, DP_PHY_DPRX,
> >> >            "128b/132b Link Training %s at link rate = %d, lane count = %d\n",
> >> >            passed ? "passed" : "failed",
> >> > -          crtc_state->port_clock, crtc_state->lane_count);
> >> > +          intel_dp->link_rate, intel_dp->lane_count);
> >> >
> >> >     return passed;
> >> >  }
> >> > @@ -1344,8 +1344,9 @@ intel_dp_128b132b_link_train(struct intel_dp
> >> *intel_dp,
> >> >   * retraining with reduced link rate/lane parameters if the link training
> >> >   * fails.
> >> >   * After calling this function intel_dp_stop_link_train() must be called.
> >> > + * Return: Link trained status success/failure.
> >> >   */
> >> > -void intel_dp_start_link_train(struct intel_dp *intel_dp,
> >> > +bool intel_dp_start_link_train(struct intel_dp *intel_dp,
> >> >                            const struct intel_crtc_state *crtc_state)  {
> >> >     struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@
> >> > -1363,7
> >> > +1364,7 @@ void intel_dp_start_link_train(struct intel_dp
> >> > +*intel_dp,
> >> >
> >> >     intel_dp_prepare_link_train(intel_dp, crtc_state);
> >> >
> >> > -   if (intel_dp_is_uhbr(crtc_state))
> >> > +   if (intel_dp_is_uhbr(intel_dp))
> >> >             passed = intel_dp_128b132b_link_train(intel_dp,
> >> > crtc_state,
> >> lttpr_count);
> >> >     else
> >> >             passed = intel_dp_link_train_all_phys(intel_dp,
> >> > crtc_state, lttpr_count); @@ -1382,11 +1383,13 @@ void
> >> intel_dp_start_link_train(struct intel_dp *intel_dp,
> >> >      */
> >> >     if (!passed && i915->display.hotplug.ignore_long_hpd) {
> >> >             lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n");
> >> > -           return;
> >> > +           return true;
> >> >     }
> >> >
> >> >     if (!passed)
> >> >             intel_dp_schedule_fallback_link_training(intel_dp,
> >> > crtc_state);
> >> > +
> >> > +   return passed;
> >> >  }
> >> >
> >> >  void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, @@
> >> > -1398,7 +1401,7 @@ void intel_dp_128b132b_sdp_crc16(struct intel_dp
> >> *intel_dp,
> >> >      * Default value of bit 31 is '0' hence discarding the write
> >> >      * TODO: Corrective actions on SDP corruption yet to be defined
> >> >      */
> >> > -   if (!intel_dp_is_uhbr(crtc_state))
> >> > +   if (!intel_dp_is_uhbr(intel_dp))
> >> >             return;
> >> >
> >> >     /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ diff
> >> > --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> >> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> >> > index 2c8f2775891b..601f7e80476e 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> >> > @@ -24,7 +24,7 @@ void
> >> > intel_dp_program_link_training_pattern(struct
> >> > intel_dp *intel_dp,  void intel_dp_set_signal_levels(struct intel_dp
> *intel_dp,
> >> >                             const struct intel_crtc_state *crtc_state,
> >> >                             enum drm_dp_phy dp_phy); -void
> >> > intel_dp_start_link_train(struct intel_dp *intel_dp,
> >> > +bool intel_dp_start_link_train(struct intel_dp *intel_dp,
> >> >                            const struct intel_crtc_state
> >> > *crtc_state);  void intel_dp_stop_link_train(struct intel_dp *intel_dp,
> >> >                           const struct intel_crtc_state
> >> > *crtc_state); diff --git
> >> > a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> >> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> >> > index 5fa25a5a36b5..27994a3b568c 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> >> > @@ -52,13 +52,13 @@
> >> >
> >> >  static int intel_dp_mst_check_constraints(struct drm_i915_private
> >> > *i915, int
> >> bpp,
> >> >                                       const struct drm_display_mode
> >> *adjusted_mode,
> >> > -                                     struct intel_crtc_state *crtc_state,
> >> > +                                     struct intel_dp *intel_dp,
> >> >                                       bool dsc)  {
> >> > -   if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) {
> >> > +   if (intel_dp_is_uhbr(intel_dp) && DISPLAY_VER(i915) < 14 &&
> >> > + dsc) {
> >> >             int output_bpp = bpp;
> >> >             /* DisplayPort 2 128b/132b, bits per lane is always 32 */
> >> > -           int symbol_clock = crtc_state->port_clock / 32;
> >> > +           int symbol_clock = intel_dp->link_rate / 32;
> >> >
> >> >             if (output_bpp * adjusted_mode->crtc_clock >=
> >> >                 symbol_clock * 72) { @@ -71,7 +71,8 @@ static int
> >> > intel_dp_mst_check_constraints(struct
> >> drm_i915_private *i915, int bpp
> >> >     return 0;
> >> >  }
> >> >
> >> > -static int intel_dp_mst_bw_overhead(const struct intel_crtc_state
> >> > *crtc_state,
> >> > +static int intel_dp_mst_bw_overhead(struct intel_dp *intel_dp,
> >> > +                               const struct intel_crtc_state
> >> > +*crtc_state,
> >> >                                 const struct intel_connector *connector,
> >> >                                 bool ssc, bool dsc, int bpp_x16)  {
> >> > @@ -81,7
> >> +82,7 @@ static
> >> > int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
> >> >     int dsc_slice_count = 0;
> >> >     int overhead;
> >> >
> >> > -   flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR
> >> : 0;
> >> > +   flags |= intel_dp_is_uhbr(intel_dp) ? DRM_DP_BW_OVERHEAD_UHBR :
> >> 0;
> >> >     flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
> >> >     flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
> >> >
> >> > @@ -170,12 +171,12 @@ static int
> >> intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> >> >             if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))
> >> >                     return -EINVAL;
> >> >
> >> > -           crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
> >> > +           crtc_state->fec_enable = !intel_dp_is_uhbr(intel_dp);
> >> >     }
> >> >
> >> >     mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp-
> >> >mst_mgr,
> >> > -                                                 crtc_state->port_clock,
> >> > -                                                 crtc_state->lane_count);
> >> > +                                                 intel_dp->link_rate,
> >> > +
> >> > + intel_dp->lane_count);
> >> >
> >> >     drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d
> >> > max
> >> bpp %d\n",
> >> >                 min_bpp, max_bpp);
> >> > @@ -188,16 +189,18 @@ static int
> >> > intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> >> >
> >> >             drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
> >> >
> >> > -           ret = intel_dp_mst_check_constraints(i915, bpp,
> >> adjusted_mode, crtc_state, dsc);
> >> > +           ret = intel_dp_mst_check_constraints(i915, bpp,
> >> adjusted_mode,
> >> > +intel_dp, dsc);
> >> >             if (ret)
> >> >                     continue;
> >> >
> >> >             link_bpp_x16 = to_bpp_x16(dsc ? bpp :
> >> >
> >> >intel_dp_output_bpp(crtc_state- output_format, bpp));
> >> >
> >> > -           local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
> >> connector,
> >> > +           local_bw_overhead = intel_dp_mst_bw_overhead(intel_dp,
> >> > +
> >> > + crtc_state,
> >> connector,
> >> >                                                          false,
> >> > dsc,
> >> link_bpp_x16);
> >> > -           remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
> >> connector,
> >> > +           remote_bw_overhead = intel_dp_mst_bw_overhead(intel_dp,
> >> > +
> >> > + crtc_state,
> >> connector,
> >> >                                                           true,
> >> > dsc,
> >> link_bpp_x16);
> >> >
> >> >             intel_dp_mst_compute_m_n(crtc_state, connector, @@
> >> > -368,7
> >> +371,7 @@
> >> > static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
> >> >     struct intel_dp *intel_dp = &intel_mst->primary->dp;
> >> >     struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
> >> >     struct drm_dp_mst_topology_state *topology_state;
> >> > -   u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?
> >> > +   u8 link_coding_cap = intel_dp_is_uhbr(intel_dp) ?
> >> >             DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;
> >> >
> >> >     topology_state =
> >> > drm_atomic_get_mst_topology_state(conn_state->state, mgr); @@
> >> > -1123,7
> >> > +1126,7 @@ static void intel_mst_enable_dp(struct
> >> > +intel_atomic_state
> >> > *state,
> >> >
> >> >     drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
> >> >
> >> > -   if (intel_dp_is_uhbr(pipe_config)) {
> >> > +   if (intel_dp_is_uhbr(intel_dp)) {
> >> >             const struct drm_display_mode *adjusted_mode =
> >> >                     &pipe_config->hw.adjusted_mode;
> >> >             u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
> >>
> >> --
> >> Jani Nikula, Intel
> 
> --
> Jani Nikula, Intel

Re: [RFC 3/4] drm/i915/dp: use link rate and lane count in intel_dp struct

[Ville Syrjälä]

On Wed, Feb 14, 2024 at 02:30:35PM +0000, Murthy, Arun R wrote:
> 
> > -----Original Message-----
> > From: Nikula, Jani <jani.nikula@intel.com>
> > Sent: Wednesday, February 14, 2024 5:07 PM
> > To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-gfx@lists.freedesktop.org
> > Cc: Deak, Imre <imre.deak@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
> > Shankar, Uma <uma.shankar@intel.com>
> > Subject: RE: [RFC 3/4] drm/i915/dp: use link rate and lane count in intel_dp
> > struct
> > 
> > On Wed, 14 Feb 2024, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> > >> -----Original Message-----
> > >> From: Nikula, Jani <jani.nikula@intel.com>
> > >> Sent: Tuesday, February 13, 2024 11:43 PM
> > >> To: Murthy, Arun R <arun.r.murthy@intel.com>;
> > >> intel-gfx@lists.freedesktop.org
> > >> Cc: Deak, Imre <imre.deak@intel.com>; Syrjala, Ville
> > >> <ville.syrjala@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> > >> Murthy, Arun R <arun.r.murthy@intel.com>
> > >> Subject: Re: [RFC 3/4] drm/i915/dp: use link rate and lane count in
> > >> intel_dp struct
> > >>
> > >> On Tue, 06 Feb 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> > >> > The link rate and lane count are now part of the intel_crtc_state
> > >> > structure. These two parameters are nothing to do with the crtc and
> > >> > are more confined to DP.
> > >>
> > >> As said offline, the parameters were specifically added to crtc state
> > >> for both atomic and the state checker.
> > >>
> > > I am a bit lost as to from where we need this in atomic and state checker for
> > link rate and lane count as none of these parameters are coming from user nor
> > does it change in modeset. On driver init the link rate and lane count value is
> > fetched from the table and thereafter its constant, but used in many places for
> > configuration/calculation purpose for which the same in intel_dp struct would
> > do.
> > 
> > Compute config chooses the link rate and lane count to use.
> > 
> > Compute config may only modify crtc state, nothing else.
> > 
> > State checker reads out the state from the hardware, and it must only read it to
> > the crtc state, nowhere else.
> > 
> > State checker must only compare two crtc states, one from software and one
> > read from the hardware.
> > 
> > Having the link rate and lane count in struct intel_dp does not satisfy these
> > conditions.
> > 
> > See also 90a6b7b052b1 ("drm/i915: Move intel_dp->lane_count into
> > pipe_config").
> > 
> This link rate and lane count computation is done in dp_detect and nothing to be done in compute.

No. Detect only fills the limits. The actual parameters are
selected during compute_config().

> Also for this reason having every variable in intel_crtc would eventually make intel_crtc_state the way i915 device private moved. I felt link_rate and lane_count can be confined to intel_dp without modifying the existing code flow.
> 
> As commented in the other patch if for each and every fallback we need to send uevent to the user is recommended, then this discussion doesn't arise. If this is really required I am *open* to take this change and float the patch.
> 
> Thanks and Regards,
> Arun R Murthy
> -------------------
> 
> > 
> > BR,
> > Jani.
> > 
> > 
> > >
> > > On link training failure, the link rate and lane count tends to change and new
> > value is initialized in intel_dp struct.
> > >
> > > Thanks and Regards,
> > > Arun R Murthy
> > > --------------------
> > >
> > >> No go.
> > >>
> > >>
> > >> BR,
> > >> Jani.
> > >>
> > >> >
> > >> > TODO: Need to still seperate out the use of link rate and port
> > >> > clock which is in intel_dp and intel_crtc_state structure.
> > >> >
> > >> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > >> > ---
> > >> >  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 16 ++--
> > >> >  drivers/gpu/drm/i915/display/intel_ddi.c      | 21 ++---
> > >> >  .../drm/i915/display/intel_ddi_buf_trans.c    |  7 +-
> > >> >  drivers/gpu/drm/i915/display/intel_dp.c       |  8 +-
> > >> >  drivers/gpu/drm/i915/display/intel_dp.h       |  2 +-
> > >> >  .../drm/i915/display/intel_dp_link_training.c | 81
> > >> > ++++++++++---------  .../drm/i915/display/intel_dp_link_training.h
> > >> > ++++++++++|  2 +-
> > >> >  drivers/gpu/drm/i915/display/intel_dp_mst.c   | 29 ++++---
> > >> >  8 files changed, 92 insertions(+), 74 deletions(-)
> > >> >
> > >> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > >> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > >> > index 288a00e083c8..cde8f26ba26b 100644
> > >> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > >> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > >> > @@ -414,6 +414,7 @@ void intel_cx0_phy_set_signal_levels(struct
> > >> > intel_encoder *encoder,  {
> > >> >     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > >> >     const struct intel_ddi_buf_trans *trans;
> > >> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > >> >     enum phy phy = intel_port_to_phy(i915, encoder->port);
> > >> >     u8 owned_lane_mask;
> > >> >     intel_wakeref_t wakeref;
> > >> > @@ -446,7 +447,7 @@ void intel_cx0_phy_set_signal_levels(struct
> > >> intel_encoder *encoder,
> > >> >                           MB_WRITE_COMMITTED);
> > >> >     }
> > >> >
> > >> > -   for (ln = 0; ln < crtc_state->lane_count; ln++) {
> > >> > +   for (ln = 0; ln < intel_dp->lane_count; ln++) {
> > >> >             int level = intel_ddi_level(encoder, crtc_state, ln);
> > >> >             int lane = ln / 2;
> > >> >             int tx = ln % 2;
> > >> > @@ -2327,10 +2328,11 @@ static void intel_c20_pll_program(struct
> > >> drm_i915_private *i915,
> > >> >                               const struct intel_crtc_state *crtc_state,
> > >> >                               struct intel_encoder *encoder)  {
> > >> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > >> >     const struct intel_c20pll_state *pll_state = &crtc_state-
> > >> >cx0pll_state.c20;
> > >> >     bool dp = false;
> > >> > -   int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES :
> > >> INTEL_CX0_LANE0;
> > >> > -   u32 clock = crtc_state->port_clock;
> > >> > +   int lane = intel_dp->lane_count > 2 ? INTEL_CX0_BOTH_LANES :
> > >> INTEL_CX0_LANE0;
> > >> > +   u32 clock = intel_dp->link_rate;
> > >> >     bool cntx;
> > >> >     int i;
> > >> >
> > >> > @@ -2455,6 +2457,7 @@ static void
> > >> > intel_program_port_clock_ctl(struct
> > >> intel_encoder *encoder,
> > >> >                                      const struct intel_crtc_state
> > >> *crtc_state,
> > >> >                                      bool lane_reversal)  {
> > >> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > >> >     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > >> >     u32 val = 0;
> > >> >
> > >> > @@ -2475,7 +2478,7 @@ static void
> > >> > intel_program_port_clock_ctl(struct
> > >> > intel_encoder *encoder,
> > >> >
> > >> >     /* TODO: HDMI FRL */
> > >> >     /* DP2.0 10G and 20G rates enable MPLLA*/
> > >> > -   if (crtc_state->port_clock == 1000000 || crtc_state->port_clock ==
> > >> 2000000)
> > >> > +   if (intel_dp->link_rate == 1000000 || intel_dp->link_rate ==
> > >> > +2000000)
> > >> >             val |= crtc_state->cx0pll_state.ssc_enabled ?
> > >> XELPDP_SSC_ENABLE_PLLA : 0;
> > >> >     else
> > >> >             val |= crtc_state->cx0pll_state.ssc_enabled ?
> > >> > XELPDP_SSC_ENABLE_PLLB : 0; @@ -2705,6 +2708,7 @@ static void
> > >> intel_cx0pll_enable(struct intel_encoder *encoder,
> > >> >                             const struct intel_crtc_state *crtc_state)  {
> > >> >     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > >> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > >> >     enum phy phy = intel_port_to_phy(i915, encoder->port);
> > >> >     struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > >> >     bool lane_reversal = dig_port->saved_port_bits &
> > >> > DDI_BUF_PORT_REVERSAL; @@ -2744,7 +2748,7 @@ static void
> > >> intel_cx0pll_enable(struct intel_encoder *encoder,
> > >> >      * 6. Program the enabled and disabled owned PHY lane
> > >> >      * transmitters over message bus
> > >> >      */
> > >> > -   intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count,
> > >> lane_reversal);
> > >> > +   intel_cx0_program_phy_lane(i915, encoder, intel_dp->lane_count,
> > >> > +lane_reversal);
> > >> >
> > >> >     /*
> > >> >      * 7. Follow the Display Voltage Frequency Switching - Sequence
> > >> > @@
> > >> > -2756,7 +2760,7 @@ static void intel_cx0pll_enable(struct
> > >> > intel_encoder
> > >> *encoder,
> > >> >      * clock frequency.
> > >> >      */
> > >> >     intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
> > >> > -                  crtc_state->port_clock);
> > >> > +                  intel_dp->link_rate);
> > >> >
> > >> >     /*
> > >> >      * 9. Set PORT_CLOCK_CTL register PCLK PLL Request diff --git
> > >> > a/drivers/gpu/drm/i915/display/intel_ddi.c
> > >> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > >> > index bea441590204..ed7620e7f763 100644
> > >> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > >> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > >> > @@ -334,18 +334,18 @@ static void intel_ddi_init_dp_buf_reg(struct
> > >> > intel_encoder *encoder,
> > >> >
> > >> >     /* DDI_BUF_CTL_ENABLE will be set by
> > >> intel_ddi_prepare_link_retrain() later */
> > >> >     intel_dp->DP = dig_port->saved_port_bits |
> > >> > -           DDI_PORT_WIDTH(crtc_state->lane_count) |
> > >> > +           DDI_PORT_WIDTH(intel_dp->lane_count) |
> > >> >             DDI_BUF_TRANS_SELECT(0);
> > >> >
> > >> >     if (DISPLAY_VER(i915) >= 14) {
> > >> > -           if (intel_dp_is_uhbr(crtc_state))
> > >> > +           if (intel_dp_is_uhbr(intel_dp))
> > >> >                     intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
> > >> >             else
> > >> >                     intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
> > >> >     }
> > >> >
> > >> >     if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
> > >> > -           intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
> > >> > +           intel_dp->DP |=
> > >> > + ddi_buf_phy_link_rate(intel_dp->link_rate);
> > >> >             if (!intel_tc_port_in_tbt_alt_mode(dig_port))
> > >> >                     intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> > >> >     }
> > >> > @@ -456,10 +456,11 @@ intel_ddi_config_transcoder_dp2(struct
> > >> intel_encoder *encoder,
> > >> >                             const struct intel_crtc_state *crtc_state)  {
> > >> >     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > >> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > >> >     enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > >> >     u32 val = 0;
> > >> >
> > >> > -   if (intel_dp_is_uhbr(crtc_state))
> > >> > +   if (intel_dp_is_uhbr(intel_dp))
> > >> >             val = TRANS_DP2_128B132B_CHANNEL_CODING;
> > >> >
> > >> >     intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); @@ -
> > >> 477,6
> > >> > +478,7 @@ intel_ddi_transcoder_func_reg_val_get(struct
> > >> > +intel_encoder
> > >> > *encoder,  {
> > >> >     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > >> >     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > >> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > >> >     enum pipe pipe = crtc->pipe;
> > >> >     enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > >> >     enum port port = encoder->port; @@ -552,11 +554,11 @@
> > >> > intel_ddi_transcoder_func_reg_val_get(struct
> > >> intel_encoder *encoder,
> > >> >             temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
> > >> >             temp |= (crtc_state->fdi_lanes - 1) << 1;
> > >> >     } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
> > >> > -           if (intel_dp_is_uhbr(crtc_state))
> > >> > +           if (intel_dp_is_uhbr(intel_dp))
> > >> >                     temp |=
> > >> TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
> > >> >             else
> > >> >                     temp |= TRANS_DDI_MODE_SELECT_DP_MST;
> > >> > -           temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
> > >> > +           temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
> > >> >
> > >> >             if (DISPLAY_VER(dev_priv) >= 12) {
> > >> >                     enum transcoder master; @@ -1414,7 +1416,7 @@
> > >> > static int intel_ddi_dp_level(struct intel_dp *intel_dp,  {
> > >> >     u8 train_set = intel_dp->train_set[lane];
> > >> >
> > >> > -   if (intel_dp_is_uhbr(crtc_state)) {
> > >> > +   if (intel_dp_is_uhbr(intel_dp)) {
> > >> >             return train_set & DP_TX_FFE_PRESET_VALUE_MASK;
> > >> >     } else {
> > >> >             u8 signal_levels = train_set &
> > >> (DP_TRAIN_VOLTAGE_SWING_MASK | @@
> > >> > -2456,15 +2458,16 @@ static void mtl_port_buf_ctl_program(struct
> > >> > intel_encoder *encoder,  {
> > >> >     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > >> >     struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > >> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > >> >     enum port port = encoder->port;
> > >> >     u32 val;
> > >> >
> > >> >     val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port));
> > >> >     val &= ~XELPDP_PORT_WIDTH_MASK;
> > >> > -   val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state-
> > >> >lane_count));
> > >> > +   val |= XELPDP_PORT_WIDTH(mtl_get_port_width(intel_dp-
> > >> >lane_count));
> > >> >
> > >> >     val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK;
> > >> > -   if (intel_dp_is_uhbr(crtc_state))
> > >> > +   if (intel_dp_is_uhbr(intel_dp))
> > >> >             val |= XELPDP_PORT_BUF_PORT_DATA_40BIT;
> > >> >     else
> > >> >             val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; diff --git
> > >> > a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> > >> > b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> > >> > index de809e2d9cac..e490bffd3e49 100644
> > >> > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> > >> > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> > >> > @@ -1679,8 +1679,10 @@ dg2_get_snps_buf_trans(struct intel_encoder
> > >> *encoder,
> > >> >                    const struct intel_crtc_state *crtc_state,
> > >> >                    int *n_entries)
> > >> >  {
> > >> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > >> > +
> > >> >     if (intel_crtc_has_dp_encoder(crtc_state) &&
> > >> > -       intel_dp_is_uhbr(crtc_state))
> > >> > +       intel_dp_is_uhbr(intel_dp))
> > >> >             return intel_get_buf_trans(&dg2_snps_trans_uhbr, n_entries);
> > >> >     else
> > >> >             return intel_get_buf_trans(&dg2_snps_trans, n_entries);
> > >> > @@ -
> > >> 1692,9
> > >> > +1694,10 @@ mtl_get_cx0_buf_trans(struct intel_encoder *encoder,
> > >> >                   int *n_entries)
> > >> >  {
> > >> >     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > >> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > >> >     enum phy phy = intel_port_to_phy(i915, encoder->port);
> > >> >
> > >> > -   if (intel_crtc_has_dp_encoder(crtc_state) && crtc_state->port_clock >=
> > >> 1000000)
> > >> > +   if (intel_crtc_has_dp_encoder(crtc_state) &&
> > >> > +intel_dp_is_uhbr(intel_dp))
> > >> >             return intel_get_buf_trans(&mtl_c20_trans_uhbr, n_entries);
> > >> >     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> > >> !(intel_is_c10phy(i915, phy)))
> > >> >             return intel_get_buf_trans(&mtl_c20_trans_hdmi,
> > >> > n_entries);
> > >> diff
> > >> > --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > >> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > >> > index 82d354a6b0cd..ba3c8201c0ef 100644
> > >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > >> > @@ -167,9 +167,9 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
> > >> > static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> > >> >
> > >> >  /* Is link rate UHBR and thus 128b/132b? */ -bool
> > >> > intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
> > >> > +bool intel_dp_is_uhbr(struct intel_dp *intel_dp)
> > >> >  {
> > >> > -   return drm_dp_is_uhbr_rate(crtc_state->port_clock);
> > >> > +   return drm_dp_is_uhbr_rate(intel_dp->link_rate);
> > >> >  }
> > >> >
> > >> >  /**
> > >> > @@ -2901,12 +2901,14 @@ intel_dp_audio_compute_config(struct
> > >> intel_encoder *encoder,
> > >> >                           struct intel_crtc_state *pipe_config,
> > >> >                           struct drm_connector_state *conn_state)
> > >> > {
> > >> > +   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > >> > +
> > >> >     pipe_config->has_audio =
> > >> >             intel_dp_has_audio(encoder, pipe_config, conn_state) &&
> > >> >             intel_audio_compute_config(encoder, pipe_config,
> > >> > conn_state);
> > >> >
> > >> >     pipe_config->sdp_split_enable = pipe_config->has_audio &&
> > >> > -                                   intel_dp_is_uhbr(pipe_config);
> > >> > +                                   intel_dp_is_uhbr(intel_dp);
> > >> >  }
> > >> >
> > >> >  int
> > >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> > >> > b/drivers/gpu/drm/i915/display/intel_dp.h
> > >> > index 530cc97bc42f..cc93c244a2f9 100644
> > >> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > >> > @@ -80,7 +80,7 @@ void intel_dp_audio_compute_config(struct
> > >> intel_encoder *encoder,
> > >> >                                struct drm_connector_state
> > >> > *conn_state);
> > >> bool
> > >> > intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);  bool
> > >> > intel_dp_is_edp(struct intel_dp *intel_dp); -bool
> > >> > intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
> > >> > +bool intel_dp_is_uhbr(struct intel_dp *intel_dp);
> > >> >  int intel_dp_link_symbol_size(int rate);  int
> > >> > intel_dp_link_symbol_clock(int rate);  bool
> > >> > intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port
> > >> > port); diff --git
> > >> > a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > >> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > >> > index 242cb08e9fc4..eb25b59a4eb3 100644
> > >> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > >> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > >> > @@ -355,7 +355,7 @@ static u8
> > >> intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp,
> > >> >             v = drm_dp_get_adjust_request_voltage(link_status, lane);
> > >> >             p = drm_dp_get_adjust_request_pre_emphasis(link_status,
> > >> lane);
> > >> >     } else {
> > >> > -           for (lane = 0; lane < crtc_state->lane_count; lane++) {
> > >> > +           for (lane = 0; lane < intel_dp->lane_count; lane++) {
> > >> >                     v = max(v,
> > >> drm_dp_get_adjust_request_voltage(link_status, lane));
> > >> >                     p = max(p,
> > >> drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
> > >> >             }
> > >> > @@ -380,7 +380,7 @@ static u8 intel_dp_get_lane_adjust_train(struct
> > >> intel_dp *intel_dp,
> > >> >                                      const u8
> > >> link_status[DP_LINK_STATUS_SIZE],
> > >> >                                      int lane)  {
> > >> > -   if (intel_dp_is_uhbr(crtc_state))
> > >> > +   if (intel_dp_is_uhbr(intel_dp))
> > >> >             return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp,
> > >> crtc_state,
> > >> >                                                           dp_phy,
> > >> link_status, lane);
> > >> >     else
> > >> > @@ -419,18 +419,18 @@ intel_dp_get_adjust_train(struct intel_dp
> > >> > *intel_dp,  {
> > >> >     int lane;
> > >> >
> > >> > -   if (intel_dp_is_uhbr(crtc_state)) {
> > >> > +   if (intel_dp_is_uhbr(intel_dp)) {
> > >> >             lt_dbg(intel_dp, dp_phy,
> > >> >                    "128b/132b, lanes: %d, "
> > >> >                    "TX FFE request: " TRAIN_REQ_FMT "\n",
> > >> > -                  crtc_state->lane_count,
> > >> > +                  intel_dp->lane_count,
> > >> >                    TRAIN_REQ_TX_FFE_ARGS(link_status));
> > >> >     } else {
> > >> >             lt_dbg(intel_dp, dp_phy,
> > >> >                    "8b/10b, lanes: %d, "
> > >> >                    "vswing request: " TRAIN_REQ_FMT ", "
> > >> >                    "pre-emphasis request: " TRAIN_REQ_FMT "\n",
> > >> > -                  crtc_state->lane_count,
> > >> > +                  intel_dp->lane_count,
> > >> >                    TRAIN_REQ_VSWING_ARGS(link_status),
> > >> >                    TRAIN_REQ_PREEMPH_ARGS(link_status));
> > >> >     }
> > >> > @@ -464,7 +464,7 @@ intel_dp_set_link_train(struct intel_dp
> > >> > *intel_dp,
> > >> >
> > >> >     buf[0] = dp_train_pat;
> > >> >     /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
> > >> > -   memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
> > >> > +   memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
> > >> >     len = crtc_state->lane_count + 1;
> > >> >
> > >> >     return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
> > >> > @@
> > >> > -531,18 +531,18 @@ void intel_dp_set_signal_levels(struct intel_dp
> > >> > *intel_dp,  {
> > >> >     struct intel_encoder *encoder =
> > >> > &dp_to_dig_port(intel_dp)->base;
> > >> >
> > >> > -   if (intel_dp_is_uhbr(crtc_state)) {
> > >> > +   if (intel_dp_is_uhbr(intel_dp)){
> > >> >             lt_dbg(intel_dp, dp_phy,
> > >> >                    "128b/132b, lanes: %d, "
> > >> >                    "TX FFE presets: " TRAIN_SET_FMT "\n",
> > >> > -                  crtc_state->lane_count,
> > >> > +                  intel_dp->lane_count,
> > >> >                    TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set));
> > >> >     } else {
> > >> >             lt_dbg(intel_dp, dp_phy,
> > >> >                    "8b/10b, lanes: %d, "
> > >> >                    "vswing levels: " TRAIN_SET_FMT ", "
> > >> >                    "pre-emphasis levels: " TRAIN_SET_FMT "\n",
> > >> > -                  crtc_state->lane_count,
> > >> > +                  intel_dp->lane_count,
> > >> >                    TRAIN_SET_VSWING_ARGS(intel_dp->train_set),
> > >> >                    TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set));
> > >> >     }
> > >> > @@ -575,9 +575,9 @@ intel_dp_update_link_train(struct intel_dp
> > *intel_dp,
> > >> >     intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
> > >> >
> > >> >     ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
> > >> > -                           intel_dp->train_set, crtc_state->lane_count);
> > >> > +                           intel_dp->train_set,
> > >> > + intel_dp->lane_count);
> > >> >
> > >> > -   return ret == crtc_state->lane_count;
> > >> > +   return ret == intel_dp->lane_count;
> > >> >  }
> > >> >
> > >> >  /* 128b/132b */
> > >> > @@ -618,10 +618,10 @@ static bool
> > >> > intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,  {
> > >> >     int lane;
> > >> >
> > >> > -   for (lane = 0; lane < crtc_state->lane_count; lane++) {
> > >> > +   for (lane = 0; lane < intel_dp->lane_count; lane++) {
> > >> >             u8 train_set_lane = intel_dp->train_set[lane];
> > >> >
> > >> > -           if (intel_dp_is_uhbr(crtc_state)) {
> > >> > +           if (intel_dp_is_uhbr(intel_dp)) {
> > >> >                     if (!intel_dp_lane_max_tx_ffe_reached(train_set_lane))
> > >> >                             return false;
> > >> >             } else {
> > >> > @@ -640,7 +640,7 @@ intel_dp_update_downspread_ctrl(struct intel_dp
> > >> *intel_dp,
> > >> >     u8 link_config[2];
> > >> >
> > >> >     link_config[0] = crtc_state->vrr.flipline ?
> > >> DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> > >> > -   link_config[1] = intel_dp_is_uhbr(crtc_state) ?
> > >> > +   link_config[1] = intel_dp_is_uhbr(intel_dp) ?
> > >> >                      DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> > >> >     drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
> > >> link_config,
> > >> > 2);  } @@ -650,7 +650,7 @@ intel_dp_update_link_bw_set(struct
> > >> > intel_dp *intel_dp,
> > >> >                         const struct intel_crtc_state *crtc_state,
> > >> >                         u8 link_bw, u8 rate_select)  {
> > >> > -   u8 lane_count = crtc_state->lane_count;
> > >> > +   u8 lane_count = intel_dp->lane_count;
> > >> >
> > >> >     if (crtc_state->enhanced_framing)
> > >> >             lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN; @@
> > >> -689,7 +689,7 @@
> > >> > intel_dp_prepare_link_train(struct intel_dp *intel_dp,
> > >> >     if (intel_dp->prepare_link_retrain)
> > >> >             intel_dp->prepare_link_retrain(intel_dp, crtc_state);
> > >> >
> > >> > -   intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
> > >> > +   intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
> > >> >                           &link_bw, &rate_select);
> > >> >
> > >> >     /*
> > >> > @@ -730,16 +730,16 @@ intel_dp_prepare_link_train(struct intel_dp
> > >> *intel_dp,
> > >> >     return true;
> > >> >  }
> > >> >
> > >> > -static bool intel_dp_adjust_request_changed(const struct
> > >> > intel_crtc_state *crtc_state,
> > >> > +static bool intel_dp_adjust_request_changed(struct intel_dp
> > >> > +*intel_dp,
> > >> >                                         const u8
> > >> old_link_status[DP_LINK_STATUS_SIZE],
> > >> >                                         const u8
> > >> new_link_status[DP_LINK_STATUS_SIZE])
> > >> >  {
> > >> >     int lane;
> > >> >
> > >> > -   for (lane = 0; lane < crtc_state->lane_count; lane++) {
> > >> > +   for (lane = 0; lane < intel_dp->lane_count; lane++) {
> > >> >             u8 old, new;
> > >> >
> > >> > -           if (intel_dp_is_uhbr(crtc_state)) {
> > >> > +           if (intel_dp_is_uhbr(intel_dp)) {
> > >> >                     old =
> > >> drm_dp_get_adjust_tx_ffe_preset(old_link_status, lane);
> > >> >                     new =
> > >> drm_dp_get_adjust_tx_ffe_preset(new_link_status, lane);
> > >> >             } else {
> > >> > @@ -783,7 +783,7 @@ intel_dp_link_training_clock_recovery(struct
> > >> > intel_dp *intel_dp,
> > >> >
> > >> >     delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux,
> > >> >                                                 intel_dp->dpcd,
> > >> > dp_phy,
> > >> > -
> > >> intel_dp_is_uhbr(crtc_state));
> > >> > +
> > >> > + intel_dp_is_uhbr(intel_dp));
> > >> >
> > >> >     /* clock recovery */
> > >> >     if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy, @@
> > >> > -816,7 +816,7 @@ intel_dp_link_training_clock_recovery(struct
> > >> > intel_dp
> > >> *intel_dp,
> > >> >                     return false;
> > >> >             }
> > >> >
> > >> > -           if (drm_dp_clock_recovery_ok(link_status, crtc_state-
> > >> >lane_count)) {
> > >> > +           if (drm_dp_clock_recovery_ok(link_status, intel_dp-
> > >> >lane_count)) {
> > >> >                     lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n");
> > >> >                     return true;
> > >> >             }
> > >> > @@ -841,7 +841,7 @@ intel_dp_link_training_clock_recovery(struct
> > >> >intel_dp
> > >> *intel_dp,
> > >> >                     return false;
> > >> >             }
> > >> >
> > >> > -           if (!intel_dp_adjust_request_changed(crtc_state,
> > >> old_link_status, link_status))
> > >> > +           if (!intel_dp_adjust_request_changed(intel_dp,
> > >> > +old_link_status,
> > >> > +link_status))
> > >> >                     ++voltage_tries;
> > >> >             else
> > >> >                     voltage_tries = 1; @@ -872,7 +872,7 @@ static
> > >> > u32 intel_dp_training_pattern(struct intel_dp
> > >> *intel_dp,
> > >> >     bool source_tps3, sink_tps3, source_tps4, sink_tps4;
> > >> >
> > >> >     /* UHBR+ use separate 128b/132b TPS2 */
> > >> > -   if (intel_dp_is_uhbr(crtc_state))
> > >> > +   if (intel_dp_is_uhbr(intel_dp))
> > >> >             return DP_TRAINING_PATTERN_2;
> > >> >
> > >> >     /*
> > >> > @@ -886,7 +886,7 @@ static u32 intel_dp_training_pattern(struct
> > >> > intel_dp
> > >> *intel_dp,
> > >> >                 drm_dp_tps4_supported(intel_dp->dpcd);
> > >> >     if (source_tps4 && sink_tps4) {
> > >> >             return DP_TRAINING_PATTERN_4;
> > >> > -   } else if (crtc_state->port_clock == 810000) {
> > >> > +   } else if (intel_dp->link_rate == 810000) {
> > >> >             if (!source_tps4)
> > >> >                     lt_dbg(intel_dp, dp_phy,
> > >> >                            "8.1 Gbps link rate without source TPS4
> > >> support\n"); @@
> > >> > -904,7 +904,7 @@ static u32 intel_dp_training_pattern(struct
> > >> > intel_dp
> > >> *intel_dp,
> > >> >                 drm_dp_tps3_supported(intel_dp->dpcd);
> > >> >     if (source_tps3 && sink_tps3) {
> > >> >             return  DP_TRAINING_PATTERN_3;
> > >> > -   } else if (crtc_state->port_clock >= 540000) {
> > >> > +   } else if (intel_dp->link_rate >= 540000) {
> > >> >             if (!source_tps3)
> > >> >                     lt_dbg(intel_dp, dp_phy,
> > >> >                            ">=5.4/6.48 Gbps link rate without
> > >> > source TPS3
> > >> support\n");
> > >> > @@ -934,7 +934,7 @@
> > >> > intel_dp_link_training_channel_equalization(struct
> > >> > intel_dp *intel_dp,
> > >> >
> > >> >     delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux,
> > >> >                                             intel_dp->dpcd, dp_phy,
> > >> > -                                           intel_dp_is_uhbr(crtc_state));
> > >> > +
> > >> > + intel_dp_is_uhbr(intel_dp));
> > >> >
> > >> >     training_pattern = intel_dp_training_pattern(intel_dp,
> > >> > crtc_state,
> > >> dp_phy);
> > >> >     /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */ @@
> > >> > -959,7 +959,7 @@ intel_dp_link_training_channel_equalization(struct
> > >> > intel_dp *intel_dp,
> > >> >
> > >> >             /* Make sure clock is still ok */
> > >> >             if (!drm_dp_clock_recovery_ok(link_status,
> > >> > -                                         crtc_state->lane_count)) {
> > >> > +                                         intel_dp->lane_count)) {
> > >> >                     intel_dp_dump_link_status(intel_dp, dp_phy,
> > >> link_status);
> > >> >                     lt_dbg(intel_dp, dp_phy,
> > >> >                            "Clock recovery check failed, cannot
> > >> > continue
> > >> channel
> > >> > equalization\n"); @@ -967,7 +967,7 @@
> > >> intel_dp_link_training_channel_equalization(struct intel_dp
> > >> *intel_dp,
> > >> >             }
> > >> >
> > >> >             if (drm_dp_channel_eq_ok(link_status,
> > >> > -                                    crtc_state->lane_count)) {
> > >> > +                                    intel_dp->lane_count)) {
> > >> >                     channel_eq = true;
> > >> >                     lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP
> > >> Training successful\n");
> > >> >                     break;
> > >> > @@ -1041,7 +1041,7 @@ void intel_dp_stop_link_train(struct intel_dp
> > >> *intel_dp,
> > >> >     intel_dp_program_link_training_pattern(intel_dp, crtc_state,
> > >> DP_PHY_DPRX,
> > >> >
> > >> DP_TRAINING_PATTERN_DISABLE);
> > >> >
> > >> > -   if (intel_dp_is_uhbr(crtc_state) &&
> > >> > +   if (intel_dp_is_uhbr(intel_dp) &&
> > >> >         wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state)
> > >> > == 0,
> > >> 500)) {
> > >> >             lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not
> > >> clearing\n");
> > >> >     }
> > >> > @@ -1066,7 +1066,7 @@ intel_dp_link_train_phy(struct intel_dp
> > *intel_dp,
> > >> >     lt_dbg(intel_dp, dp_phy,
> > >> >            "Link Training %s at link rate = %d, lane count = %d\n",
> > >> >            ret ? "passed" : "failed",
> > >> > -          crtc_state->port_clock, crtc_state->lane_count);
> > >> > +          intel_dp->link_rate, intel_dp->lane_count);
> > >> >
> > >> >     return ret;
> > >> >  }
> > >> > @@ -1085,8 +1085,8 @@ static void
> > >> intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
> > >> >                    "Link Training failed with HOBL active, not
> > >> > enabling it from
> > >> now on\n");
> > >> >             intel_dp->hobl_failed = true;
> > >> >     } else if (intel_dp_get_link_train_fallback_values(intel_dp,
> > >> > -                                                      crtc_state-
> > >> >port_clock,
> > >> > -                                                      crtc_state-
> > >> >lane_count)) {
> > >> > +                                                      intel_dp->link_rate,
> > >> > +                                                      intel_dp-
> > >> >lane_count)) {
> > >> >             return;
> > >> >     }
> > >> >
> > >> > @@ -1192,7 +1192,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp
> > >> *intel_dp,
> > >> >                     return false;
> > >> >             }
> > >> >
> > >> > -           if (drm_dp_128b132b_lane_channel_eq_done(link_status,
> > >> crtc_state->lane_count)) {
> > >> > +           if (drm_dp_128b132b_lane_channel_eq_done(link_status,
> > >> > +intel_dp->lane_count)) {
> > >> >                     lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq
> > >> done\n");
> > >> >                     break;
> > >> >             }
> > >> > @@ -1287,7 +1287,7 @@ intel_dp_128b132b_lane_cds(struct intel_dp
> > >> > *intel_dp,
> > >> >
> > >> >             if
> > >> > (drm_dp_128b132b_eq_interlane_align_done(link_status)
> > >> &&
> > >> >
> > >> > drm_dp_128b132b_cds_interlane_align_done(link_status)
> > >> &&
> > >> > -               drm_dp_128b132b_lane_symbol_locked(link_status,
> > >> crtc_state->lane_count)) {
> > >> > +               drm_dp_128b132b_lane_symbol_locked(link_status,
> > >> > +intel_dp->lane_count)) {
> > >> >                     lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane
> > >> > align
> > >> done\n");
> > >> >                     break;
> > >> >             }
> > >> > @@ -1330,7 +1330,7 @@ intel_dp_128b132b_link_train(struct intel_dp
> > >> *intel_dp,
> > >> >     lt_dbg(intel_dp, DP_PHY_DPRX,
> > >> >            "128b/132b Link Training %s at link rate = %d, lane count = %d\n",
> > >> >            passed ? "passed" : "failed",
> > >> > -          crtc_state->port_clock, crtc_state->lane_count);
> > >> > +          intel_dp->link_rate, intel_dp->lane_count);
> > >> >
> > >> >     return passed;
> > >> >  }
> > >> > @@ -1344,8 +1344,9 @@ intel_dp_128b132b_link_train(struct intel_dp
> > >> *intel_dp,
> > >> >   * retraining with reduced link rate/lane parameters if the link training
> > >> >   * fails.
> > >> >   * After calling this function intel_dp_stop_link_train() must be called.
> > >> > + * Return: Link trained status success/failure.
> > >> >   */
> > >> > -void intel_dp_start_link_train(struct intel_dp *intel_dp,
> > >> > +bool intel_dp_start_link_train(struct intel_dp *intel_dp,
> > >> >                            const struct intel_crtc_state *crtc_state)  {
> > >> >     struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@
> > >> > -1363,7
> > >> > +1364,7 @@ void intel_dp_start_link_train(struct intel_dp
> > >> > +*intel_dp,
> > >> >
> > >> >     intel_dp_prepare_link_train(intel_dp, crtc_state);
> > >> >
> > >> > -   if (intel_dp_is_uhbr(crtc_state))
> > >> > +   if (intel_dp_is_uhbr(intel_dp))
> > >> >             passed = intel_dp_128b132b_link_train(intel_dp,
> > >> > crtc_state,
> > >> lttpr_count);
> > >> >     else
> > >> >             passed = intel_dp_link_train_all_phys(intel_dp,
> > >> > crtc_state, lttpr_count); @@ -1382,11 +1383,13 @@ void
> > >> intel_dp_start_link_train(struct intel_dp *intel_dp,
> > >> >      */
> > >> >     if (!passed && i915->display.hotplug.ignore_long_hpd) {
> > >> >             lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n");
> > >> > -           return;
> > >> > +           return true;
> > >> >     }
> > >> >
> > >> >     if (!passed)
> > >> >             intel_dp_schedule_fallback_link_training(intel_dp,
> > >> > crtc_state);
> > >> > +
> > >> > +   return passed;
> > >> >  }
> > >> >
> > >> >  void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, @@
> > >> > -1398,7 +1401,7 @@ void intel_dp_128b132b_sdp_crc16(struct intel_dp
> > >> *intel_dp,
> > >> >      * Default value of bit 31 is '0' hence discarding the write
> > >> >      * TODO: Corrective actions on SDP corruption yet to be defined
> > >> >      */
> > >> > -   if (!intel_dp_is_uhbr(crtc_state))
> > >> > +   if (!intel_dp_is_uhbr(intel_dp))
> > >> >             return;
> > >> >
> > >> >     /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ diff
> > >> > --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> > >> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> > >> > index 2c8f2775891b..601f7e80476e 100644
> > >> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> > >> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> > >> > @@ -24,7 +24,7 @@ void
> > >> > intel_dp_program_link_training_pattern(struct
> > >> > intel_dp *intel_dp,  void intel_dp_set_signal_levels(struct intel_dp
> > *intel_dp,
> > >> >                             const struct intel_crtc_state *crtc_state,
> > >> >                             enum drm_dp_phy dp_phy); -void
> > >> > intel_dp_start_link_train(struct intel_dp *intel_dp,
> > >> > +bool intel_dp_start_link_train(struct intel_dp *intel_dp,
> > >> >                            const struct intel_crtc_state
> > >> > *crtc_state);  void intel_dp_stop_link_train(struct intel_dp *intel_dp,
> > >> >                           const struct intel_crtc_state
> > >> > *crtc_state); diff --git
> > >> > a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > >> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > >> > index 5fa25a5a36b5..27994a3b568c 100644
> > >> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > >> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > >> > @@ -52,13 +52,13 @@
> > >> >
> > >> >  static int intel_dp_mst_check_constraints(struct drm_i915_private
> > >> > *i915, int
> > >> bpp,
> > >> >                                       const struct drm_display_mode
> > >> *adjusted_mode,
> > >> > -                                     struct intel_crtc_state *crtc_state,
> > >> > +                                     struct intel_dp *intel_dp,
> > >> >                                       bool dsc)  {
> > >> > -   if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) {
> > >> > +   if (intel_dp_is_uhbr(intel_dp) && DISPLAY_VER(i915) < 14 &&
> > >> > + dsc) {
> > >> >             int output_bpp = bpp;
> > >> >             /* DisplayPort 2 128b/132b, bits per lane is always 32 */
> > >> > -           int symbol_clock = crtc_state->port_clock / 32;
> > >> > +           int symbol_clock = intel_dp->link_rate / 32;
> > >> >
> > >> >             if (output_bpp * adjusted_mode->crtc_clock >=
> > >> >                 symbol_clock * 72) { @@ -71,7 +71,8 @@ static int
> > >> > intel_dp_mst_check_constraints(struct
> > >> drm_i915_private *i915, int bpp
> > >> >     return 0;
> > >> >  }
> > >> >
> > >> > -static int intel_dp_mst_bw_overhead(const struct intel_crtc_state
> > >> > *crtc_state,
> > >> > +static int intel_dp_mst_bw_overhead(struct intel_dp *intel_dp,
> > >> > +                               const struct intel_crtc_state
> > >> > +*crtc_state,
> > >> >                                 const struct intel_connector *connector,
> > >> >                                 bool ssc, bool dsc, int bpp_x16)  {
> > >> > @@ -81,7
> > >> +82,7 @@ static
> > >> > int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
> > >> >     int dsc_slice_count = 0;
> > >> >     int overhead;
> > >> >
> > >> > -   flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR
> > >> : 0;
> > >> > +   flags |= intel_dp_is_uhbr(intel_dp) ? DRM_DP_BW_OVERHEAD_UHBR :
> > >> 0;
> > >> >     flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
> > >> >     flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
> > >> >
> > >> > @@ -170,12 +171,12 @@ static int
> > >> intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> > >> >             if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))
> > >> >                     return -EINVAL;
> > >> >
> > >> > -           crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
> > >> > +           crtc_state->fec_enable = !intel_dp_is_uhbr(intel_dp);
> > >> >     }
> > >> >
> > >> >     mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp-
> > >> >mst_mgr,
> > >> > -                                                 crtc_state->port_clock,
> > >> > -                                                 crtc_state->lane_count);
> > >> > +                                                 intel_dp->link_rate,
> > >> > +
> > >> > + intel_dp->lane_count);
> > >> >
> > >> >     drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d
> > >> > max
> > >> bpp %d\n",
> > >> >                 min_bpp, max_bpp);
> > >> > @@ -188,16 +189,18 @@ static int
> > >> > intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> > >> >
> > >> >             drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
> > >> >
> > >> > -           ret = intel_dp_mst_check_constraints(i915, bpp,
> > >> adjusted_mode, crtc_state, dsc);
> > >> > +           ret = intel_dp_mst_check_constraints(i915, bpp,
> > >> adjusted_mode,
> > >> > +intel_dp, dsc);
> > >> >             if (ret)
> > >> >                     continue;
> > >> >
> > >> >             link_bpp_x16 = to_bpp_x16(dsc ? bpp :
> > >> >
> > >> >intel_dp_output_bpp(crtc_state- output_format, bpp));
> > >> >
> > >> > -           local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
> > >> connector,
> > >> > +           local_bw_overhead = intel_dp_mst_bw_overhead(intel_dp,
> > >> > +
> > >> > + crtc_state,
> > >> connector,
> > >> >                                                          false,
> > >> > dsc,
> > >> link_bpp_x16);
> > >> > -           remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
> > >> connector,
> > >> > +           remote_bw_overhead = intel_dp_mst_bw_overhead(intel_dp,
> > >> > +
> > >> > + crtc_state,
> > >> connector,
> > >> >                                                           true,
> > >> > dsc,
> > >> link_bpp_x16);
> > >> >
> > >> >             intel_dp_mst_compute_m_n(crtc_state, connector, @@
> > >> > -368,7
> > >> +371,7 @@
> > >> > static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
> > >> >     struct intel_dp *intel_dp = &intel_mst->primary->dp;
> > >> >     struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
> > >> >     struct drm_dp_mst_topology_state *topology_state;
> > >> > -   u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?
> > >> > +   u8 link_coding_cap = intel_dp_is_uhbr(intel_dp) ?
> > >> >             DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;
> > >> >
> > >> >     topology_state =
> > >> > drm_atomic_get_mst_topology_state(conn_state->state, mgr); @@
> > >> > -1123,7
> > >> > +1126,7 @@ static void intel_mst_enable_dp(struct
> > >> > +intel_atomic_state
> > >> > *state,
> > >> >
> > >> >     drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
> > >> >
> > >> > -   if (intel_dp_is_uhbr(pipe_config)) {
> > >> > +   if (intel_dp_is_uhbr(intel_dp)) {
> > >> >             const struct drm_display_mode *adjusted_mode =
> > >> >                     &pipe_config->hw.adjusted_mode;
> > >> >             u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
> > >>
> > >> --
> > >> Jani Nikula, Intel
> > 
> > --
> > Jani Nikula, Intel

-- 
Ville Syrjälä
Intel

[RFC 4/4] drm/i915/display/dp: On LT failure retry LT

[Arun R Murthy]

On link training failure retry link training with a lesser link
rate/lane count as specified in the DP spec.

Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ed7620e7f763..29d785a4b904 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2502,6 +2502,7 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 				 crtc_state->port_clock,
 				 crtc_state->lane_count);
 
+retry:
 	/*
 	 * We only configure what the register value will be here.  Actual
 	 * enabling happens during link training farther down.
@@ -2586,7 +2587,14 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	 *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
 	 *     (timeout after 800 us)
 	 */
-	intel_dp_start_link_train(intel_dp, crtc_state);
+	if (!intel_dp_start_link_train(intel_dp, crtc_state)) {
+		/* Link Training failed, retain */
+		intel_dp->link_trained = false;
+		intel_dp_stop_link_train(intel_dp, crtc_state);
+		encoder->post_disable(state, encoder,
+				   crtc_state, conn_state);
+		goto retry;
+	}
 
 	/* 6.n Set DP_TP_CTL link training to Normal */
 	if (!is_trans_port_sync_mode(crtc_state))
-- 
2.25.1

Re: [RFC 4/4] drm/i915/display/dp: On LT failure retry LT

[Jani Nikula]

On Tue, 06 Feb 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> On link training failure retry link training with a lesser link
> rate/lane count as specified in the DP spec.
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index ed7620e7f763..29d785a4b904 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2502,6 +2502,7 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>  				 crtc_state->port_clock,
>  				 crtc_state->lane_count);
>  
> +retry:
>  	/*
>  	 * We only configure what the register value will be here.  Actual
>  	 * enabling happens during link training farther down.
> @@ -2586,7 +2587,14 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>  	 *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
>  	 *     (timeout after 800 us)
>  	 */
> -	intel_dp_start_link_train(intel_dp, crtc_state);
> +	if (!intel_dp_start_link_train(intel_dp, crtc_state)) {
> +		/* Link Training failed, retain */
> +		intel_dp->link_trained = false;
> +		intel_dp_stop_link_train(intel_dp, crtc_state);
> +		encoder->post_disable(state, encoder,
> +				   crtc_state, conn_state);
> +		goto retry;
> +	}

As said, the retry needs to go via userspace.

BR,
Jani.


>  
>  	/* 6.n Set DP_TP_CTL link training to Normal */
>  	if (!is_trans_port_sync_mode(crtc_state))

-- 
Jani Nikula, Intel

RE: [RFC 4/4] drm/i915/display/dp: On LT failure retry LT

[Murthy, Arun R]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, February 13, 2024 11:45 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Deak, Imre <imre.deak@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>
> Subject: Re: [RFC 4/4] drm/i915/display/dp: On LT failure retry LT
> 
> On Tue, 06 Feb 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> > On link training failure retry link training with a lesser link
> > rate/lane count as specified in the DP spec.
> >
> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++++++++-
> >  1 file changed, 9 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index ed7620e7f763..29d785a4b904 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -2502,6 +2502,7 @@ static void mtl_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
> >  				 crtc_state->port_clock,
> >  				 crtc_state->lane_count);
> >
> > +retry:
> >  	/*
> >  	 * We only configure what the register value will be here.  Actual
> >  	 * enabling happens during link training farther down.
> > @@ -2586,7 +2587,14 @@ static void mtl_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
> >  	 *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
> >  	 *     (timeout after 800 us)
> >  	 */
> > -	intel_dp_start_link_train(intel_dp, crtc_state);
> > +	if (!intel_dp_start_link_train(intel_dp, crtc_state)) {
> > +		/* Link Training failed, retain */
> > +		intel_dp->link_trained = false;
> > +		intel_dp_stop_link_train(intel_dp, crtc_state);
> > +		encoder->post_disable(state, encoder,
> > +				   crtc_state, conn_state);
> > +		goto retry;
> > +	}
> 
> As said, the retry needs to go via userspace.

If within the supported mode range then also do we need to send uevent to user and should it come via userspace?
The fallback mandates in DP2.1 spec does this fallback in a loop.

The present fallback structure
Struct dp_fallback {
	U32 link rate;
	U8 lane_count;
	U32 resolution;
}

In the same fallback code, the present mode will be verified to see if its less than or equal to the resolution in dp_fallback. If so proceed within the fallback loop else set the max link_rate/lane count values and sent uevent.

Thanks and Regards,
Arun R Murthy
--------------------
> 
> BR,
> Jani.
> 
> 
> >
> >  	/* 6.n Set DP_TP_CTL link training to Normal */
> >  	if (!is_trans_port_sync_mode(crtc_state))
> 
> --
> Jani Nikula, Intel

RE: [RFC 4/4] drm/i915/display/dp: On LT failure retry LT

[Jani Nikula]

On Wed, 14 Feb 2024, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani <jani.nikula@intel.com>
>> Sent: Tuesday, February 13, 2024 11:45 PM
>> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-gfx@lists.freedesktop.org
>> Cc: Deak, Imre <imre.deak@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
>> Shankar, Uma <uma.shankar@intel.com>; Murthy, Arun R
>> <arun.r.murthy@intel.com>
>> Subject: Re: [RFC 4/4] drm/i915/display/dp: On LT failure retry LT
>>
>> On Tue, 06 Feb 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
>> > On link training failure retry link training with a lesser link
>> > rate/lane count as specified in the DP spec.
>> >
>> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++++++++-
>> >  1 file changed, 9 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
>> > b/drivers/gpu/drm/i915/display/intel_ddi.c
>> > index ed7620e7f763..29d785a4b904 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> > @@ -2502,6 +2502,7 @@ static void mtl_ddi_pre_enable_dp(struct
>> intel_atomic_state *state,
>> >                              crtc_state->port_clock,
>> >                              crtc_state->lane_count);
>> >
>> > +retry:
>> >     /*
>> >      * We only configure what the register value will be here.  Actual
>> >      * enabling happens during link training farther down.
>> > @@ -2586,7 +2587,14 @@ static void mtl_ddi_pre_enable_dp(struct
>> intel_atomic_state *state,
>> >      *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
>> >      *     (timeout after 800 us)
>> >      */
>> > -   intel_dp_start_link_train(intel_dp, crtc_state);
>> > +   if (!intel_dp_start_link_train(intel_dp, crtc_state)) {
>> > +           /* Link Training failed, retain */
>> > +           intel_dp->link_trained = false;
>> > +           intel_dp_stop_link_train(intel_dp, crtc_state);
>> > +           encoder->post_disable(state, encoder,
>> > +                              crtc_state, conn_state);
>> > +           goto retry;
>> > +   }
>>
>> As said, the retry needs to go via userspace.
>
> If within the supported mode range then also do we need to send uevent to user and should it come via userspace?
> The fallback mandates in DP2.1 spec does this fallback in a loop.
>
> The present fallback structure
> Struct dp_fallback {
>         U32 link rate;
>         U8 lane_count;
>         U32 resolution;
> }
>
> In the same fallback code, the present mode will be verified to see if its less than or equal to the resolution in dp_fallback. If so proceed within the fallback loop else set the max link_rate/lane count values and sent uevent.

I think I'll want *all* the link training fallbacks to go via userspace.

Trying to sometimes do it in kernel is a premature optimization for a
rare case, and it just complicates matters. We'll need the path via
uevent and userspace retry anyway, for when the mode doesn't fit, so use
it always. Let's not add multiple ways to do things, everything around
this is already quite complicated.

And as said, the uevent does give userspace some inkling that something
fishy is going on, and could use that info to inform the user that a
degraded experience may be expected. Again, adding a new stream to MST
at a later time might not fit because of the reduced parameters, and
it'll be surprising to the user if it used to work in the past (when
full param link training succeeded).

BR,
Jani.

>
> Thanks and Regards,
> Arun R Murthy
> --------------------
>>
>> BR,
>> Jani.
>>
>>
>> >
>> >     /* 6.n Set DP_TP_CTL link training to Normal */
>> >     if (!is_trans_port_sync_mode(crtc_state))
>>
>> --
>> Jani Nikula, Intel

-- 
Jani Nikula, Intel

RE: [RFC 4/4] drm/i915/display/dp: On LT failure retry LT

[Murthy, Arun R]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Wednesday, February 14, 2024 5:01 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Deak, Imre <imre.deak@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>
> Subject: RE: [RFC 4/4] drm/i915/display/dp: On LT failure retry LT
> 
> On Wed, 14 Feb 2024, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> >> -----Original Message-----
> >> From: Nikula, Jani <jani.nikula@intel.com>
> >> Sent: Tuesday, February 13, 2024 11:45 PM
> >> To: Murthy, Arun R <arun.r.murthy@intel.com>;
> >> intel-gfx@lists.freedesktop.org
> >> Cc: Deak, Imre <imre.deak@intel.com>; Syrjala, Ville
> >> <ville.syrjala@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> >> Murthy, Arun R <arun.r.murthy@intel.com>
> >> Subject: Re: [RFC 4/4] drm/i915/display/dp: On LT failure retry LT
> >>
> >> On Tue, 06 Feb 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> >> > On link training failure retry link training with a lesser link
> >> > rate/lane count as specified in the DP spec.
> >> >
> >> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++++++++-
> >> >  1 file changed, 9 insertions(+), 1 deletion(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> >> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> > index ed7620e7f763..29d785a4b904 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> > @@ -2502,6 +2502,7 @@ static void mtl_ddi_pre_enable_dp(struct
> >> intel_atomic_state *state,
> >> >                              crtc_state->port_clock,
> >> >                              crtc_state->lane_count);
> >> >
> >> > +retry:
> >> >     /*
> >> >      * We only configure what the register value will be here.  Actual
> >> >      * enabling happens during link training farther down.
> >> > @@ -2586,7 +2587,14 @@ static void mtl_ddi_pre_enable_dp(struct
> >> intel_atomic_state *state,
> >> >      *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
> >> >      *     (timeout after 800 us)
> >> >      */
> >> > -   intel_dp_start_link_train(intel_dp, crtc_state);
> >> > +   if (!intel_dp_start_link_train(intel_dp, crtc_state)) {
> >> > +           /* Link Training failed, retain */
> >> > +           intel_dp->link_trained = false;
> >> > +           intel_dp_stop_link_train(intel_dp, crtc_state);
> >> > +           encoder->post_disable(state, encoder,
> >> > +                              crtc_state, conn_state);
> >> > +           goto retry;
> >> > +   }
> >>
> >> As said, the retry needs to go via userspace.
> >
> > If within the supported mode range then also do we need to send uevent to
> user and should it come via userspace?
> > The fallback mandates in DP2.1 spec does this fallback in a loop.
> >
> > The present fallback structure
> > Struct dp_fallback {
> >         U32 link rate;
> >         U8 lane_count;
> >         U32 resolution;
> > }
> >
> > In the same fallback code, the present mode will be verified to see if its less
> than or equal to the resolution in dp_fallback. If so proceed within the fallback
> loop else set the max link_rate/lane count values and sent uevent.
> 
> I think I'll want *all* the link training fallbacks to go via userspace.
> 
Wouldn't this be an optimized way of handling the fallback values.
Figure 3-52 of the DP2.1 spec also says to restart from the beginning of link training.

> Trying to sometimes do it in kernel is a premature optimization for a rare case,
> and it just complicates matters. We'll need the path via uevent and userspace
> retry anyway, for when the mode doesn't fit, so use it always. Let's not add
> multiple ways to do things, everything around this is already quite complicated.
> 
When a mode change required due to limitation of the new fallback link rate, will use the existing path of sending uevent.
I felt taking would approach would an optimal way of handling fallback.
I am open to remove this optimization and take the uevent path always if *required*.

> And as said, the uevent does give userspace some inkling that something fishy
> is going on, and could use that info to inform the user that a degraded
> experience may be expected. Again, adding a new stream to MST at a later time
> might not fit because of the reduced parameters, and it'll be surprising to the
> user if it used to work in the past (when full param link training succeeded).
This FRC is not targeting to have fallback of MST streams. Its targeting only the link training for a particular stream only.
As said above if no *optimization* is required and uevent path to be taken always for any fallback  value I am open to remove this optimization and implement the way you suggest.

Thanks and Regards,
Arun R Murthy
-------------------

> 
> BR,
> Jani.
> 
> >
> > Thanks and Regards,
> > Arun R Murthy
> > --------------------
> >>
> >> BR,
> >> Jani.
> >>
> >>
> >> >
> >> >     /* 6.n Set DP_TP_CTL link training to Normal */
> >> >     if (!is_trans_port_sync_mode(crtc_state))
> >>
> >> --
> >> Jani Nikula, Intel
> 
> --
> Jani Nikula, Intel

✗ Fi.CI.CHECKPATCH: warning for DP link training failure fallback

[Patchwork]

== Series Details ==

Series: DP link training failure fallback
URL   : https://patchwork.freedesktop.org/series/129572/
State : warning

== Summary ==

Error: dim checkpatch failed
7517157fd57d drm/i915/display/dp: Add DP fallback on LT
-:79: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#79: FILE: drivers/gpu/drm/i915/display/intel_dp.c:353:
+			return true;
+		else

-:110: ERROR:SPACING: space required before the open parenthesis '('
#110: FILE: drivers/gpu/drm/i915/display/intel_dp.c:740:
+		for(index = 0; index < ARRAY_SIZE(dp2dot0_fallback); index++) {

-:112: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#112: FILE: drivers/gpu/drm/i915/display/intel_dp.c:742:
+			if (link_rate == dp2dot0_fallback[index].link_rate &&
+				lane_count == dp2dot0_fallback[index].lane_count) {

-:113: ERROR:SPACING: space required before the open parenthesis '('
#113: FILE: drivers/gpu/drm/i915/display/intel_dp.c:743:
+				for(index += 1; index < ARRAY_SIZE(dp2dot0_fallback); index++) {

-:115: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#115: FILE: drivers/gpu/drm/i915/display/intel_dp.c:745:
+					if (intel_dp_link_rate_supported(intel_dp,
+							dp2dot0_fallback[index].link_rate)) {

-:117: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#117: FILE: drivers/gpu/drm/i915/display/intel_dp.c:747:
+								      dp2dot0_fallback[index].link_rate,

-:117: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#117: FILE: drivers/gpu/drm/i915/display/intel_dp.c:747:
+						intel_dp_set_link_params(intel_dp,
+								      dp2dot0_fallback[index].link_rate,

-:118: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#118: FILE: drivers/gpu/drm/i915/display/intel_dp.c:748:
+								      dp2dot0_fallback[index].lane_count);

total: 2 errors, 3 warnings, 3 checks, 122 lines checked
0037936f87cd drm/i915/display/dp: Dont send hotplug event on LT failure
-:7: WARNING:TYPO_SPELLING: 'requried' may be misspelled - perhaps 'required'?
#7: 
the user, but this is not requried as we are not changing the mode and
                          ^^^^^^^^

-:32: WARNING:LONG_LINE_COMMENT: line length of 117 exceeds 100 columns
#32: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:1093:
+	/* TODO: Re-visit, sending hotplug is not required. No need to notify user as we are not changing the mode */

total: 0 errors, 2 warnings, 0 checks, 17 lines checked
59b2a6a6079a drm/i915/dp: use link rate and lane count in intel_dp struct
-:10: WARNING:TYPO_SPELLING: 'seperate' may be misspelled - perhaps 'separate'?
#10: 
TODO: Need to still seperate out the use of link rate and port clock
                    ^^^^^^^^

-:313: ERROR:SPACING: space required before the open brace '{'
#313: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:534:
+	if (intel_dp_is_uhbr(intel_dp)){

total: 1 errors, 1 warnings, 0 checks, 588 lines checked
19a8d10154b4 drm/i915/display/dp: On LT failure retry LT

✗ Fi.CI.SPARSE: warning for DP link training failure fallback

[Patchwork]

== Series Details ==

Series: DP link training failure fallback
URL   : https://patchwork.freedesktop.org/series/129572/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+drivers/gpu/drm/i915/display/intel_display_types.h:1917:17: warning: unreplaced symbol 'encoder'
+drivers/gpu/drm/i915/display/intel_display_types.h:1917:17: warning: unreplaced symbol 'encoder'
+drivers/gpu/drm/i915/display/intel_display_types.h:1917:9: warning: unreplaced symbol 'break'
+drivers/gpu/drm/i915/display/intel_display_types.h:1917:9: warning: unreplaced symbol 'break'
+drivers/gpu/drm/i915/display/intel_display_types.h:1917:9: warning: unreplaced symbol 'case'
+drivers/gpu/drm/i915/display/intel_display_types.h:1917:9: warning: unreplaced symbol 'case'
+drivers/gpu/drm/i915/display/intel_display_types.h:1918:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1918:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1918:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1918:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1919:9: warning: too many warnings
+drivers/gpu/drm/i915/display/intel_display_types.h:1919:9: warning: too many warnings
+drivers/gpu/drm/i915/display/intel_display_types.h:1919:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1919:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1920:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1920:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1921:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1921:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1922:17: warning: unreplaced symbol 'return'
+drivers/gpu/drm/i915/display/intel_display_types.h:1922:17: warning: unreplaced symbol 'return'
+drivers/gpu/drm/i915/display/intel_display_types.h:1923:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1923:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1924:17: warning: unreplaced symbol 'return'
+drivers/gpu/drm/i915/display/intel_display_types.h:1924:17: warning: unreplaced symbol 'return'
+drivers/gpu/drm/i915/display/intel_display_types.h:1943:9: warning: unreplaced symbol 'intel_encoder'
+drivers/gpu/drm/i915/display/intel_display_types.h:1943:9: warning: unreplaced symbol 'intel_encoder'
+drivers/gpu/drm/i915/display/intel_display_types.h:1990:24: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/display/intel_display_types.h:1990:24: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/display/intel_display_types.h:1990:24: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/display/intel_display_types.h:1990:24: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/display/intel_display_types.h:1990:24: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/display/intel_display_types.h:1990:24: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/display/intel_dp.c:127:20: warning: symbol 'dp2dot0_fallback' was not declared. Should it be static?
+./drivers/gpu/drm/i915/intel_uncore.h:351:1: warning: trying to copy expression type 31
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
+./include/asm-generi

✗ Fi.CI.BAT: failure for DP link training failure fallback

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 24662 bytes --]

== Series Details ==

Series: DP link training failure fallback
URL   : https://patchwork.freedesktop.org/series/129572/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14231 -> Patchwork_129572v1
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_129572v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_129572v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/index.html

Participating hosts (31 -> 40)
------------------------------

  Additional (10): fi-kbl-7567u fi-rkl-11600 fi-bsw-n3050 bat-dg2-8 fi-tgl-1115g4 bat-dg2-9 fi-pnv-d510 bat-jsl-1 fi-skl-6600u bat-mtlp-6 
  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_129572v1:

### IGT changes ###

#### Possible regressions ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-kbl-7567u:       NOTRUN -> [ABORT][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-kbl-7567u/igt@core_hotunplug@unbind-rebind.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_module_load@load:
    - {bat-arls-1}:       [PASS][2] -> [ABORT][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14231/bat-arls-1/igt@i915_module_load@load.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-arls-1/igt@i915_module_load@load.html

  * igt@kms_hdmi_inject@inject-audio:
    - {bat-arls-2}:       [PASS][4] -> [ABORT][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14231/bat-arls-2/igt@kms_hdmi_inject@inject-audio.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-arls-2/igt@kms_hdmi_inject@inject-audio.html

  
Known issues
------------

  Here are the changes found in Patchwork_129572v1 that come from known issues:

### CI changes ###

#### Issues hit ####

  * boot:
    - fi-bsw-n3050:       NOTRUN -> [FAIL][6] ([i915#8293])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-bsw-n3050/boot.html

  

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - fi-rkl-11600:       NOTRUN -> [SKIP][7] ([i915#9318])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-rkl-11600/igt@debugfs_test@basic-hwmon.html
    - bat-jsl-1:          NOTRUN -> [SKIP][8] ([i915#9318])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-jsl-1/igt@debugfs_test@basic-hwmon.html
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][9] ([i915#9318])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-tgl-1115g4/igt@debugfs_test@basic-hwmon.html
    - bat-mtlp-6:         NOTRUN -> [SKIP][10] ([i915#9318])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-mtlp-6/igt@debugfs_test@basic-hwmon.html

  * igt@fbdev@info:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][11] ([i915#1849] / [i915#2582])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-tgl-1115g4/igt@fbdev@info.html
    - bat-mtlp-6:         NOTRUN -> [SKIP][12] ([i915#1849] / [i915#2582])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-mtlp-6/igt@fbdev@info.html

  * igt@fbdev@nullptr:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][13] ([i915#2582]) +3 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-tgl-1115g4/igt@fbdev@nullptr.html

  * igt@fbdev@write:
    - bat-mtlp-6:         NOTRUN -> [SKIP][14] ([i915#2582]) +3 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-mtlp-6/igt@fbdev@write.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-7567u:       NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#2190])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-kbl-7567u/igt@gem_huc_copy@huc-copy.html
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][16] ([i915#2190])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html
    - bat-jsl-1:          NOTRUN -> [SKIP][17] ([i915#2190])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-jsl-1/igt@gem_huc_copy@huc-copy.html
    - fi-rkl-11600:       NOTRUN -> [SKIP][18] ([i915#2190])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html
    - fi-skl-6600u:       NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#2190])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - fi-pnv-d510:        NOTRUN -> [SKIP][20] ([fdo#109271]) +28 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-pnv-d510/igt@gem_lmem_swapping@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-rkl-11600:       NOTRUN -> [SKIP][21] ([i915#4613]) +3 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-rkl-11600/igt@gem_lmem_swapping@parallel-random-engines.html
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][22] ([i915#4613]) +3 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-tgl-1115g4/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
    - fi-skl-6600u:       NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#4613]) +3 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-skl-6600u/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_lmem_swapping@verify-random:
    - bat-mtlp-6:         NOTRUN -> [SKIP][24] ([i915#4613]) +3 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-mtlp-6/igt@gem_lmem_swapping@verify-random.html
    - bat-jsl-1:          NOTRUN -> [SKIP][25] ([i915#4613]) +3 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-jsl-1/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_mmap@basic:
    - bat-dg2-9:          NOTRUN -> [SKIP][26] ([i915#4083])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-9/igt@gem_mmap@basic.html
    - bat-dg2-8:          NOTRUN -> [SKIP][27] ([i915#4083])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-8/igt@gem_mmap@basic.html
    - bat-mtlp-6:         NOTRUN -> [SKIP][28] ([i915#4083])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-mtlp-6/igt@gem_mmap@basic.html

  * igt@gem_mmap_gtt@basic:
    - bat-dg2-9:          NOTRUN -> [SKIP][29] ([i915#4077]) +2 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-9/igt@gem_mmap_gtt@basic.html
    - bat-dg2-8:          NOTRUN -> [SKIP][30] ([i915#4077]) +2 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-8/igt@gem_mmap_gtt@basic.html

  * igt@gem_render_tiled_blits@basic:
    - bat-dg2-9:          NOTRUN -> [SKIP][31] ([i915#4079]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-9/igt@gem_render_tiled_blits@basic.html

  * igt@gem_tiled_blits@basic:
    - bat-mtlp-6:         NOTRUN -> [SKIP][32] ([i915#4077]) +2 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-mtlp-6/igt@gem_tiled_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - fi-rkl-11600:       NOTRUN -> [SKIP][33] ([i915#3282])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html
    - bat-dg2-8:          NOTRUN -> [SKIP][34] ([i915#4079]) +1 other test skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-8/igt@gem_tiled_pread_basic.html
    - bat-mtlp-6:         NOTRUN -> [SKIP][35] ([i915#4079]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-mtlp-6/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-dg2-9:          NOTRUN -> [SKIP][36] ([i915#6621])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-9/igt@i915_pm_rps@basic-api.html
    - bat-dg2-8:          NOTRUN -> [SKIP][37] ([i915#6621])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-8/igt@i915_pm_rps@basic-api.html
    - bat-mtlp-6:         NOTRUN -> [SKIP][38] ([i915#6621])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-mtlp-6/igt@i915_pm_rps@basic-api.html

  * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
    - bat-mtlp-6:         NOTRUN -> [SKIP][39] ([i915#4212] / [i915#9792]) +8 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-mtlp-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-dg2-9:          NOTRUN -> [SKIP][40] ([i915#5190])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-9/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
    - bat-dg2-8:          NOTRUN -> [SKIP][41] ([i915#5190])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
    - bat-mtlp-6:         NOTRUN -> [SKIP][42] ([i915#5190] / [i915#9792])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-mtlp-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-dg2-9:          NOTRUN -> [SKIP][43] ([i915#4215] / [i915#5190])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-9/igt@kms_addfb_basic@basic-y-tiled-legacy.html
    - bat-dg2-8:          NOTRUN -> [SKIP][44] ([i915#4215] / [i915#5190])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
    - bat-dg2-9:          NOTRUN -> [SKIP][45] ([i915#4212]) +7 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-9/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
    - bat-dg2-8:          NOTRUN -> [SKIP][46] ([i915#4212]) +7 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-8/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html

  * igt@kms_busy@basic:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][47] ([i915#10158] / [i915#4303])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-tgl-1115g4/igt@kms_busy@basic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-rkl-11600:       NOTRUN -> [SKIP][48] ([i915#4103]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
    - bat-dg2-9:          NOTRUN -> [SKIP][49] ([i915#4103] / [i915#4213]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-9/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
    - bat-dg2-8:          NOTRUN -> [SKIP][50] ([i915#4103] / [i915#4213]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
    - bat-jsl-1:          NOTRUN -> [SKIP][51] ([i915#4103]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-jsl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
    - bat-mtlp-6:         NOTRUN -> [SKIP][52] ([i915#9792]) +16 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-mtlp-6/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][53] ([i915#10158]) +15 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html

  * igt@kms_dsc@dsc-basic:
    - fi-rkl-11600:       NOTRUN -> [SKIP][54] ([i915#3555] / [i915#3840])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-rkl-11600/igt@kms_dsc@dsc-basic.html
    - bat-jsl-1:          NOTRUN -> [SKIP][55] ([i915#3555] / [i915#9886])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-jsl-1/igt@kms_dsc@dsc-basic.html

  * igt@kms_flip@basic-flip-vs-dpms:
    - bat-mtlp-6:         NOTRUN -> [SKIP][56] ([i915#3637] / [i915#9792]) +3 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-mtlp-6/igt@kms_flip@basic-flip-vs-dpms.html

  * igt@kms_flip@basic-plain-flip:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][57] ([i915#3637]) +3 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-tgl-1115g4/igt@kms_flip@basic-plain-flip.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-kbl-7567u:       NOTRUN -> [SKIP][58] ([fdo#109271]) +7 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-kbl-7567u/igt@kms_force_connector_basic@force-load-detect.html
    - fi-rkl-11600:       NOTRUN -> [SKIP][59] ([fdo#109285])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][60] ([fdo#109285])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html
    - bat-mtlp-6:         NOTRUN -> [SKIP][61] ([fdo#109285] / [i915#9792])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-mtlp-6/igt@kms_force_connector_basic@force-load-detect.html
    - bat-dg2-9:          NOTRUN -> [SKIP][62] ([fdo#109285])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-9/igt@kms_force_connector_basic@force-load-detect.html
    - bat-dg2-8:          NOTRUN -> [SKIP][63] ([fdo#109285])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-8/igt@kms_force_connector_basic@force-load-detect.html
    - bat-jsl-1:          NOTRUN -> [SKIP][64] ([fdo#109285])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-jsl-1/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-dg2-9:          NOTRUN -> [SKIP][65] ([i915#5274])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-9/igt@kms_force_connector_basic@prune-stale-modes.html
    - bat-dg2-8:          NOTRUN -> [SKIP][66] ([i915#5274])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-8/igt@kms_force_connector_basic@prune-stale-modes.html
    - bat-mtlp-6:         NOTRUN -> [SKIP][67] ([i915#5274] / [i915#9792])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-mtlp-6/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][68] ([i915#1849])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-tgl-1115g4/igt@kms_frontbuffer_tracking@basic.html
    - bat-mtlp-6:         NOTRUN -> [SKIP][69] ([i915#4342] / [i915#5354] / [i915#9792])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-mtlp-6/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-edp-1:
    - fi-skl-6600u:       NOTRUN -> [SKIP][70] ([fdo#109271]) +8 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-skl-6600u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-edp-1.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-dg2-11:         NOTRUN -> [SKIP][71] ([i915#9197]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  * igt@kms_pm_backlight@basic-brightness:
    - fi-rkl-11600:       NOTRUN -> [SKIP][72] ([i915#5354])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-rkl-11600/igt@kms_pm_backlight@basic-brightness.html
    - bat-dg2-8:          NOTRUN -> [SKIP][73] ([i915#5354])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-8/igt@kms_pm_backlight@basic-brightness.html
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][74] ([i915#9812])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-tgl-1115g4/igt@kms_pm_backlight@basic-brightness.html
    - bat-mtlp-6:         NOTRUN -> [SKIP][75] ([i915#5354] / [i915#9792])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-mtlp-6/igt@kms_pm_backlight@basic-brightness.html
    - bat-dg2-9:          NOTRUN -> [SKIP][76] ([i915#5354])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-9/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - fi-rkl-11600:       NOTRUN -> [SKIP][77] ([i915#3555])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html
    - bat-dg2-9:          NOTRUN -> [SKIP][78] ([i915#3555])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-9/igt@kms_setmode@basic-clone-single-crtc.html
    - bat-dg2-8:          NOTRUN -> [SKIP][79] ([i915#3555])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-8/igt@kms_setmode@basic-clone-single-crtc.html
    - bat-jsl-1:          NOTRUN -> [SKIP][80] ([i915#3555])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-jsl-1/igt@kms_setmode@basic-clone-single-crtc.html
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][81] ([i915#3555])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-tgl-1115g4/igt@kms_setmode@basic-clone-single-crtc.html
    - bat-mtlp-6:         NOTRUN -> [SKIP][82] ([i915#3555] / [i915#8809] / [i915#9792])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-mtlp-6/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-dg2-9:          NOTRUN -> [SKIP][83] ([i915#3708])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-9/igt@prime_vgem@basic-fence-flip.html
    - bat-dg2-8:          NOTRUN -> [SKIP][84] ([i915#3708])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-8/igt@prime_vgem@basic-fence-flip.html
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][85] ([fdo#109295] / [i915#10158])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-tgl-1115g4/igt@prime_vgem@basic-fence-flip.html
    - bat-mtlp-6:         NOTRUN -> [SKIP][86] ([i915#3708] / [i915#9792])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-mtlp-6/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-dg2-8:          NOTRUN -> [SKIP][87] ([i915#3708] / [i915#4077]) +1 other test skip
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-8/igt@prime_vgem@basic-fence-mmap.html
    - bat-mtlp-6:         NOTRUN -> [SKIP][88] ([i915#3708] / [i915#4077]) +1 other test skip
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-mtlp-6/igt@prime_vgem@basic-fence-mmap.html
    - bat-dg2-9:          NOTRUN -> [SKIP][89] ([i915#3708] / [i915#4077]) +1 other test skip
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-9/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-read:
    - fi-rkl-11600:       NOTRUN -> [SKIP][90] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/fi-rkl-11600/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@basic-write:
    - bat-dg2-9:          NOTRUN -> [SKIP][91] ([i915#3291] / [i915#3708]) +2 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-9/igt@prime_vgem@basic-write.html
    - bat-dg2-8:          NOTRUN -> [SKIP][92] ([i915#3291] / [i915#3708]) +2 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-dg2-8/igt@prime_vgem@basic-write.html
    - bat-mtlp-6:         NOTRUN -> [SKIP][93] ([i915#3708]) +2 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-mtlp-6/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@gem_exec_gttfill@basic:
    - {bat-arls-2}:       [FAIL][94] -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14231/bat-arls-2/igt@gem_exec_gttfill@basic.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/bat-arls-2/igt@gem_exec_gttfill@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [i915#10158]: https://gitlab.freedesktop.org/drm/intel/issues/10158
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#4303]: https://gitlab.freedesktop.org/drm/intel/issues/4303
  [i915#4342]: https://gitlab.freedesktop.org/drm/intel/issues/4342
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
  [i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
  [i915#9197]: https://gitlab.freedesktop.org/drm/intel/issues/9197
  [i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
  [i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
  [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
  [i915#9792]: https://gitlab.freedesktop.org/drm/intel/issues/9792
  [i915#9812]: https://gitlab.freedesktop.org/drm/intel/issues/9812
  [i915#9886]: https://gitlab.freedesktop.org/drm/intel/issues/9886


Build changes
-------------

  * Linux: CI_DRM_14231 -> Patchwork_129572v1

  CI-20190529: 20190529
  CI_DRM_14231: 7c79a8cb401543f9c8aa8a60e497ae1720ec4cf0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7704: 7704
  Patchwork_129572v1: 7c79a8cb401543f9c8aa8a60e497ae1720ec4cf0 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

c50dcde18247 drm/i915/display/dp: On LT failure retry LT
ce5a4a347d94 drm/i915/dp: use link rate and lane count in intel_dp struct
f89e6b5a8d7b drm/i915/display/dp: Dont send hotplug event on LT failure
b863163b9397 drm/i915/display/dp: Add DP fallback on LT

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129572v1/index.html

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