Re: [PATCH v1 5/7] hw/arm/bcm2836: Add the BCM2711 which uses a GICv2

["Alex Bennée" <alex.bennee@linaro.org>]

Alex Bennée <alex.bennee@linaro.org> writes:

> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> The BCM2711 is improvement of the BCM2837:
> - Cortex-A72 instead of the A53
> - peripheral block and local soc controller are mapped differently,
> - GICv2
> - PCIe block
> - exhanced MMU to address over 4GiB of SDRAM
>
<snip>
> ---
> vAJB:
<snip>
>   - move peri_base/ctrl to locations pointed to by DTB (0x7e000000/0x40000000)
<snip>
> +
> +static void bcm2711_class_init(ObjectClass *oc, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(oc);
> +    BCM283XClass *bc = BCM283X_CLASS(oc);
> +
> +    bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a72");
> +    bc->core_count = BCM283X_NCPUS;
> +    bc->peri_base = 0x7e000000;
> +    bc->ctrl_base = 0x40000000;
> +    bc->clusterid = 0x0;
> +    bc->gic_base = 0x40000,
> +    dc->realize = bcm2836_realize;
> +}

It turns out I was misreading the way you calculate addresses from DTS
files. Reverted to:

    bc->peri_base = 0xfe000000;
    bc->ctrl_base = 0xff800000;

-- 
Alex Bennée