Re: [PATCH v2] drm/i915: Add Wa_14019789679

Re: [PATCH v2] drm/i915: Add Wa_14019789679

[Jani Nikula]

On Tue, 30 Jul 2024, Nitin Gote <nitin.r.gote@intel.com> wrote:
> Wa_14019789679 implementation for MTL, ARL and DG2.
>
> v2: Corrected condition
>
> Bspec: 47083
>
> Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gpu_commands.h |  1 +
>  drivers/gpu/drm/i915/gt/intel_workarounds.c  | 14 +++++++++++++-
>  2 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index 2bd8d98d2110..c143d8133a28 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -220,6 +220,7 @@
>  #define GFX_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
>  #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
>  #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
> +#define CMD_3DSTATE_MESH_CONTROL ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x77<<16)|(0x3))
>  
>  #define XY_CTRL_SURF_INSTR_SIZE		5
>  #define MI_FLUSH_DW_SIZE		3
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 09a287c1aedd..cbc2003886d5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -974,7 +974,12 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
>  	if (ret)
>  		return ret;
>  
> -	cs = intel_ring_begin(rq, (wal->count * 2 + 2));
> +	if ((GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70) &&
> +			GRAPHICS_VER_FULL(rq->i915) <= IP_VER(12, 74)) || IS_DG2(rq->i915))

Please use checkpatch and get the indentation right.

BR,
Jani.

> +		cs = intel_ring_begin(rq, (wal->count * 2 + 4));
> +	else
> +		cs = intel_ring_begin(rq, (wal->count * 2 + 2));
> +
>  	if (IS_ERR(cs))
>  		return PTR_ERR(cs);
>  
> @@ -1004,6 +1009,13 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
>  	}
>  	*cs++ = MI_NOOP;
>  
> +	/* Wa_14019789679 */
> +	if ((GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70) &&
> +			GRAPHICS_VER_FULL(rq->i915) <= IP_VER(12, 74)) || IS_DG2(rq->i915)) {
> +		*cs++ = CMD_3DSTATE_MESH_CONTROL;
> +		*cs++ = MI_NOOP;
> +	}
> +
>  	intel_uncore_forcewake_put__locked(uncore, fw);
>  	spin_unlock(&uncore->lock);
>  	intel_gt_mcr_unlock(wal->gt, flags);

-- 
Jani Nikula, Intel

RE: [PATCH v2] drm/i915: Add Wa_14019789679

[Upadhyay, Tejas]

> -----Original Message-----
> From: Gote, Nitin R <nitin.r.gote@intel.com>
> Sent: Tuesday, July 30, 2024 1:22 PM
> To: intel-gfx@lists.freedesktop.org; Upadhyay, Tejas
> <tejas.upadhyay@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Cc: Shyti, Andi <andi.shyti@intel.com>; Wilson, Chris P
> <chris.p.wilson@intel.com>; Gote, Nitin R <nitin.r.gote@intel.com>
> Subject: [PATCH v2] drm/i915: Add Wa_14019789679
> 
> Wa_14019789679 implementation for MTL, ARL and DG2.
> 
> v2: Corrected condition
> 
> Bspec: 47083
> 
> Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gpu_commands.h |  1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c  | 14 +++++++++++++-
>  2 files changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index 2bd8d98d2110..c143d8133a28 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -220,6 +220,7 @@
>  #define GFX_OP_DESTBUFFER_INFO
> ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
>  #define GFX_OP_DRAWRECT_INFO
> ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
>  #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
> +#define CMD_3DSTATE_MESH_CONTROL
> +((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x77<<16)|(0x3))
> 
>  #define XY_CTRL_SURF_INSTR_SIZE		5
>  #define MI_FLUSH_DW_SIZE		3
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 09a287c1aedd..cbc2003886d5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -974,7 +974,12 @@ int intel_engine_emit_ctx_wa(struct i915_request
> *rq)
>  	if (ret)
>  		return ret;
> 
> -	cs = intel_ring_begin(rq, (wal->count * 2 + 2));
> +	if ((GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70) &&
> +			GRAPHICS_VER_FULL(rq->i915) <= IP_VER(12, 74)) ||
> IS_DG2(rq->i915))
> +		cs = intel_ring_begin(rq, (wal->count * 2 + 4));
> +	else
> +		cs = intel_ring_begin(rq, (wal->count * 2 + 2));
> +
>  	if (IS_ERR(cs))
>  		return PTR_ERR(cs);
> 
> @@ -1004,6 +1009,13 @@ int intel_engine_emit_ctx_wa(struct i915_request
> *rq)
>  	}
>  	*cs++ = MI_NOOP;
> 
> +	/* Wa_14019789679 */
> +	if ((GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70) &&
> +			GRAPHICS_VER_FULL(rq->i915) <= IP_VER(12, 74)) ||

Is there any macro to check Graphics range here? If it is, we should use that.

> IS_DG2(rq->i915)) {
> +		*cs++ = CMD_3DSTATE_MESH_CONTROL;
> +		*cs++ = MI_NOOP;

Instead of MI_NOOP, I think you need to write number of dwords to 0 as WA is asking. Please double check.

Tejas
> +	}
> +
>  	intel_uncore_forcewake_put__locked(uncore, fw);
>  	spin_unlock(&uncore->lock);
>  	intel_gt_mcr_unlock(wal->gt, flags);
> --
> 2.25.1

[PATCH v2] drm/i915: Add Wa_14019789679

[Nitin Gote]

Wa_14019789679 implementation for MTL, ARL and DG2.

v2: Corrected condition

Bspec: 47083

Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h |  1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c  | 14 +++++++++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 2bd8d98d2110..c143d8133a28 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -220,6 +220,7 @@
 #define GFX_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
 #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
+#define CMD_3DSTATE_MESH_CONTROL ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x77<<16)|(0x3))
 
 #define XY_CTRL_SURF_INSTR_SIZE		5
 #define MI_FLUSH_DW_SIZE		3
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 09a287c1aedd..cbc2003886d5 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -974,7 +974,12 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
 	if (ret)
 		return ret;
 
-	cs = intel_ring_begin(rq, (wal->count * 2 + 2));
+	if ((GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70) &&
+			GRAPHICS_VER_FULL(rq->i915) <= IP_VER(12, 74)) || IS_DG2(rq->i915))
+		cs = intel_ring_begin(rq, (wal->count * 2 + 4));
+	else
+		cs = intel_ring_begin(rq, (wal->count * 2 + 2));
+
 	if (IS_ERR(cs))
 		return PTR_ERR(cs);
 
@@ -1004,6 +1009,13 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
 	}
 	*cs++ = MI_NOOP;
 
+	/* Wa_14019789679 */
+	if ((GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70) &&
+			GRAPHICS_VER_FULL(rq->i915) <= IP_VER(12, 74)) || IS_DG2(rq->i915)) {
+		*cs++ = CMD_3DSTATE_MESH_CONTROL;
+		*cs++ = MI_NOOP;
+	}
+
 	intel_uncore_forcewake_put__locked(uncore, fw);
 	spin_unlock(&uncore->lock);
 	intel_gt_mcr_unlock(wal->gt, flags);
-- 
2.25.1

✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add Wa_14019789679 (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Add Wa_14019789679 (rev2)
URL   : https://patchwork.freedesktop.org/series/136659/
State : warning

== Summary ==

Error: dim checkpatch failed
32190594967c drm/i915: Add Wa_14019789679
-:22: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#22: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:223:
+#define CMD_3DSTATE_MESH_CONTROL ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x77<<16)|(0x3))
                                       ^

-:22: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV)
#22: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:223:
+#define CMD_3DSTATE_MESH_CONTROL ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x77<<16)|(0x3))
                                            ^

-:22: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#22: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:223:
+#define CMD_3DSTATE_MESH_CONTROL ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x77<<16)|(0x3))
                                                 ^

-:22: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV)
#22: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:223:
+#define CMD_3DSTATE_MESH_CONTROL ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x77<<16)|(0x3))
                                                      ^

-:22: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#22: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:223:
+#define CMD_3DSTATE_MESH_CONTROL ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x77<<16)|(0x3))
                                                           ^

-:22: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV)
#22: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:223:
+#define CMD_3DSTATE_MESH_CONTROL ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x77<<16)|(0x3))
                                                                ^

-:22: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#22: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:223:
+#define CMD_3DSTATE_MESH_CONTROL ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x77<<16)|(0x3))
                                                                      ^

-:22: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV)
#22: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:223:
+#define CMD_3DSTATE_MESH_CONTROL ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x77<<16)|(0x3))
                                                                           ^

-:36: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#36: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:978:
+	if ((GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70) &&
+			GRAPHICS_VER_FULL(rq->i915) <= IP_VER(12, 74)) || IS_DG2(rq->i915))

-:50: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#50: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:1014:
+	if ((GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70) &&
+			GRAPHICS_VER_FULL(rq->i915) <= IP_VER(12, 74)) || IS_DG2(rq->i915)) {

total: 0 errors, 0 warnings, 10 checks, 33 lines checked

✗ Fi.CI.BAT: failure for drm/i915: Add Wa_14019789679 (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5087 bytes --]

== Series Details ==

Series: drm/i915: Add Wa_14019789679 (rev2)
URL   : https://patchwork.freedesktop.org/series/136659/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_15152 -> Patchwork_136659v2
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_136659v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_136659v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_136659v2/index.html

Participating hosts (40 -> 37)
------------------------------

  Additional (1): fi-elk-e7500 
  Missing    (4): bat-dg1-7 bat-arls-1 bat-adlp-6 fi-bsw-n3050 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_136659v2:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@load:
    - bat-arlh-2:         [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15152/bat-arlh-2/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_136659v2/bat-arlh-2/igt@i915_module_load@load.html
    - bat-dg2-13:         [PASS][3] -> [ABORT][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15152/bat-dg2-13/igt@i915_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_136659v2/bat-dg2-13/igt@i915_module_load@load.html
    - bat-dg2-11:         [PASS][5] -> [ABORT][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15152/bat-dg2-11/igt@i915_module_load@load.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_136659v2/bat-dg2-11/igt@i915_module_load@load.html
    - bat-dg2-14:         [PASS][7] -> [ABORT][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15152/bat-dg2-14/igt@i915_module_load@load.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_136659v2/bat-dg2-14/igt@i915_module_load@load.html
    - bat-arls-5:         [PASS][9] -> [ABORT][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15152/bat-arls-5/igt@i915_module_load@load.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_136659v2/bat-arls-5/igt@i915_module_load@load.html
    - bat-mtlp-6:         [PASS][11] -> [ABORT][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15152/bat-mtlp-6/igt@i915_module_load@load.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_136659v2/bat-mtlp-6/igt@i915_module_load@load.html
    - bat-dg2-9:          [PASS][13] -> [ABORT][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15152/bat-dg2-9/igt@i915_module_load@load.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_136659v2/bat-dg2-9/igt@i915_module_load@load.html
    - bat-arls-2:         [PASS][15] -> [ABORT][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15152/bat-arls-2/igt@i915_module_load@load.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_136659v2/bat-arls-2/igt@i915_module_load@load.html
    - bat-mtlp-8:         [PASS][17] -> [ABORT][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15152/bat-mtlp-8/igt@i915_module_load@load.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_136659v2/bat-mtlp-8/igt@i915_module_load@load.html
    - bat-dg2-8:          [PASS][19] -> [ABORT][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15152/bat-dg2-8/igt@i915_module_load@load.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_136659v2/bat-dg2-8/igt@i915_module_load@load.html

  * igt@runner@aborted:
    - fi-elk-e7500:       NOTRUN -> [FAIL][21]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_136659v2/fi-elk-e7500/igt@runner@aborted.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_module_load@load:
    - {bat-arlh-3}:       [PASS][22] -> [ABORT][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15152/bat-arlh-3/igt@i915_module_load@load.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_136659v2/bat-arlh-3/igt@i915_module_load@load.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).



Build changes
-------------

  * Linux: CI_DRM_15152 -> Patchwork_136659v2

  CI-20190529: 20190529
  CI_DRM_15152: 303cbe59515691a5aef01acdfa94ae996cfa3c98 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7942: 0f02dc176959e6296866b1bafd3982e277a5e44b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_136659v2: 303cbe59515691a5aef01acdfa94ae996cfa3c98 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_136659v2/index.html

[-- Attachment #2: Type: text/html, Size: 5828 bytes --]

RE: [PATCH v2] drm/i915: Add Wa_14019789679

[Upadhyay, Tejas]

> -----Original Message-----
> From: Gote, Nitin R <nitin.r.gote@intel.com>
> Sent: Tuesday, July 30, 2024 1:22 PM
> To: intel-gfx@lists.freedesktop.org; Upadhyay, Tejas
> <tejas.upadhyay@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Cc: Shyti, Andi <andi.shyti@intel.com>; Wilson, Chris P
> <chris.p.wilson@intel.com>; Gote, Nitin R <nitin.r.gote@intel.com>
> Subject: [PATCH v2] drm/i915: Add Wa_14019789679
> 
> Wa_14019789679 implementation for MTL, ARL and DG2.
> 
> v2: Corrected condition
> 
> Bspec: 47083
> 
> Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gpu_commands.h |  1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c  | 14 +++++++++++++-
>  2 files changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index 2bd8d98d2110..c143d8133a28 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -220,6 +220,7 @@
>  #define GFX_OP_DESTBUFFER_INFO
> ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
>  #define GFX_OP_DRAWRECT_INFO
> ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
>  #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
> +#define CMD_3DSTATE_MESH_CONTROL
> +((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x77<<16)|(0x3))

I think number of dword should be 0x1!

> 
>  #define XY_CTRL_SURF_INSTR_SIZE		5
>  #define MI_FLUSH_DW_SIZE		3
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 09a287c1aedd..cbc2003886d5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -974,7 +974,12 @@ int intel_engine_emit_ctx_wa(struct i915_request
> *rq)
>  	if (ret)
>  		return ret;
> 
> -	cs = intel_ring_begin(rq, (wal->count * 2 + 2));
> +	if ((GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70) &&
> +			GRAPHICS_VER_FULL(rq->i915) <= IP_VER(12, 74)) ||
> IS_DG2(rq->i915))
> +		cs = intel_ring_begin(rq, (wal->count * 2 + 4));
> +	else
> +		cs = intel_ring_begin(rq, (wal->count * 2 + 2));
> +
>  	if (IS_ERR(cs))
>  		return PTR_ERR(cs);
> 
> @@ -1004,6 +1009,13 @@ int intel_engine_emit_ctx_wa(struct i915_request
> *rq)
>  	}
>  	*cs++ = MI_NOOP;
> 
> +	/* Wa_14019789679 */
> +	if ((GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70) &&
> +			GRAPHICS_VER_FULL(rq->i915) <= IP_VER(12, 74)) ||
> IS_DG2(rq->i915)) {
> +		*cs++ = CMD_3DSTATE_MESH_CONTROL;
> +		*cs++ = MI_NOOP;

I think write dword 0 as asked by WA description. So it will be *cs++ = 0; in place of *cs++ = MI_NOOP;

Tejas
> +	}
> +
>  	intel_uncore_forcewake_put__locked(uncore, fw);
>  	spin_unlock(&uncore->lock);
>  	intel_gt_mcr_unlock(wal->gt, flags);
> --
> 2.25.1

RE: [PATCH v2] drm/i915: Add Wa_14019789679

[Gote, Nitin R]

Hi,

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Tuesday, July 30, 2024 1:14 PM
> To: Gote, Nitin R <nitin.r.gote@intel.com>; intel-gfx@lists.freedesktop.org;
> Upadhyay, Tejas <tejas.upadhyay@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Cc: Shyti, Andi <andi.shyti@intel.com>; Wilson, Chris P
> <chris.p.wilson@intel.com>; Gote, Nitin R <nitin.r.gote@intel.com>
> Subject: Re: [PATCH v2] drm/i915: Add Wa_14019789679
> 
> On Tue, 30 Jul 2024, Nitin Gote <nitin.r.gote@intel.com> wrote:
> > Wa_14019789679 implementation for MTL, ARL and DG2.
> >
> > v2: Corrected condition
> >
> > Bspec: 47083
> >
> > Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_gpu_commands.h |  1 +
> > drivers/gpu/drm/i915/gt/intel_workarounds.c  | 14 +++++++++++++-
> >  2 files changed, 14 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > index 2bd8d98d2110..c143d8133a28 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > @@ -220,6 +220,7 @@
> >  #define GFX_OP_DESTBUFFER_INFO
> ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
> >  #define GFX_OP_DRAWRECT_INFO
> ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
> >  #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
> > +#define CMD_3DSTATE_MESH_CONTROL
> > +((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x77<<16)|(0x3))
> >
> >  #define XY_CTRL_SURF_INSTR_SIZE		5
> >  #define MI_FLUSH_DW_SIZE		3
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 09a287c1aedd..cbc2003886d5 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -974,7 +974,12 @@ int intel_engine_emit_ctx_wa(struct i915_request
> *rq)
> >  	if (ret)
> >  		return ret;
> >
> > -	cs = intel_ring_begin(rq, (wal->count * 2 + 2));
> > +	if ((GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70) &&
> > +			GRAPHICS_VER_FULL(rq->i915) <= IP_VER(12, 74)) ||
> > +IS_DG2(rq->i915))
> 
> Please use checkpatch and get the indentation right.
> 
> BR,
> Jani.

Thank you for review. I will take care indentation in v3 version.

- Nitin

> 
> > +		cs = intel_ring_begin(rq, (wal->count * 2 + 4));
> > +	else
> > +		cs = intel_ring_begin(rq, (wal->count * 2 + 2));
> > +
> >  	if (IS_ERR(cs))
> >  		return PTR_ERR(cs);
> >
> > @@ -1004,6 +1009,13 @@ int intel_engine_emit_ctx_wa(struct
> i915_request *rq)
> >  	}
> >  	*cs++ = MI_NOOP;
> >
> > +	/* Wa_14019789679 */
> > +	if ((GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70) &&
> > +			GRAPHICS_VER_FULL(rq->i915) <= IP_VER(12, 74)) ||
> IS_DG2(rq->i915)) {
> > +		*cs++ = CMD_3DSTATE_MESH_CONTROL;
> > +		*cs++ = MI_NOOP;
> > +	}
> > +
> >  	intel_uncore_forcewake_put__locked(uncore, fw);
> >  	spin_unlock(&uncore->lock);
> >  	intel_gt_mcr_unlock(wal->gt, flags);
> 
> --
> Jani Nikula, Intel

RE: [PATCH v2] drm/i915: Add Wa_14019789679

[Gote, Nitin R]

Hi,

> -----Original Message-----
> From: Upadhyay, Tejas <tejas.upadhyay@intel.com>
> Sent: Tuesday, July 30, 2024 4:21 PM
> To: Gote, Nitin R <nitin.r.gote@intel.com>; intel-gfx@lists.freedesktop.org;
> Roper, Matthew D <matthew.d.roper@intel.com>
> Cc: Shyti, Andi <andi.shyti@intel.com>; Wilson, Chris P
> <chris.p.wilson@intel.com>
> Subject: RE: [PATCH v2] drm/i915: Add Wa_14019789679
> 
> 
> 
> > -----Original Message-----
> > From: Gote, Nitin R <nitin.r.gote@intel.com>
> > Sent: Tuesday, July 30, 2024 1:22 PM
> > To: intel-gfx@lists.freedesktop.org; Upadhyay, Tejas
> > <tejas.upadhyay@intel.com>; Roper, Matthew D
> > <matthew.d.roper@intel.com>
> > Cc: Shyti, Andi <andi.shyti@intel.com>; Wilson, Chris P
> > <chris.p.wilson@intel.com>; Gote, Nitin R <nitin.r.gote@intel.com>
> > Subject: [PATCH v2] drm/i915: Add Wa_14019789679
> >
> > Wa_14019789679 implementation for MTL, ARL and DG2.
> >
> > v2: Corrected condition
> >
> > Bspec: 47083
> >
> > Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_gpu_commands.h |  1 +
> > drivers/gpu/drm/i915/gt/intel_workarounds.c  | 14 +++++++++++++-
> >  2 files changed, 14 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > index 2bd8d98d2110..c143d8133a28 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > @@ -220,6 +220,7 @@
> >  #define GFX_OP_DESTBUFFER_INFO
> > ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
> >  #define GFX_OP_DRAWRECT_INFO
> > ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
> >  #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
> > +#define CMD_3DSTATE_MESH_CONTROL
> > +((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x77<<16)|(0x3))
> 
> I think number of dword should be 0x1!
> 

Correct. I will update accordingly.

> >
> >  #define XY_CTRL_SURF_INSTR_SIZE		5
> >  #define MI_FLUSH_DW_SIZE		3
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 09a287c1aedd..cbc2003886d5 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -974,7 +974,12 @@ int intel_engine_emit_ctx_wa(struct i915_request
> > *rq)
> >  	if (ret)
> >  		return ret;
> >
> > -	cs = intel_ring_begin(rq, (wal->count * 2 + 2));
> > +	if ((GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70) &&
> > +			GRAPHICS_VER_FULL(rq->i915) <= IP_VER(12, 74)) ||
> > IS_DG2(rq->i915))
> > +		cs = intel_ring_begin(rq, (wal->count * 2 + 4));
> > +	else
> > +		cs = intel_ring_begin(rq, (wal->count * 2 + 2));
> > +
> >  	if (IS_ERR(cs))
> >  		return PTR_ERR(cs);
> >
> > @@ -1004,6 +1009,13 @@ int intel_engine_emit_ctx_wa(struct
> > i915_request
> > *rq)
> >  	}
> >  	*cs++ = MI_NOOP;
> >
> > +	/* Wa_14019789679 */
> > +	if ((GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70) &&
> > +			GRAPHICS_VER_FULL(rq->i915) <= IP_VER(12, 74)) ||
> > IS_DG2(rq->i915)) {
> > +		*cs++ = CMD_3DSTATE_MESH_CONTROL;
> > +		*cs++ = MI_NOOP;
> 
> I think write dword 0 as asked by WA description. So it will be *cs++ = 0; in
> place of *cs++ = MI_NOOP;
> 
> Tejas

Agree. I will update in v3 version.

- Nitin

> > +	}
> > +
> >  	intel_uncore_forcewake_put__locked(uncore, fw);
> >  	spin_unlock(&uncore->lock);
> >  	intel_gt_mcr_unlock(wal->gt, flags);
> > --
> > 2.25.1