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From: Tobias Waldekranz <tobias@waldekranz.com>
To: Andrew Lunn <andrew@lunn.ch>, Marek Behun <marek.behun@nic.cz>
Cc: vivien.didelot@gmail.com, f.fainelli@gmail.com,
	olteanv@gmail.com, netdev@vger.kernel.org
Subject: Re: [RFC PATCH 0/4] net: dsa: link aggregation support
Date: Tue, 27 Oct 2020 19:25:16 +0100	[thread overview]
Message-ID: <87k0vbv84z.fsf@waldekranz.com> (raw)
In-Reply-To: <20201027152330.GF878328@lunn.ch>

On Tue, Oct 27, 2020 at 16:23, Andrew Lunn <andrew@lunn.ch> wrote:
> Hi Marek
>
> trunking is something i've looked at once, but never had time to work
> on. There are three different use cases i thought of:
>
> 1) trunk user ports, with team/bonding controlling it
> 2) trunk DSA ports, i.e. the ports between switches in a D in DSA setup
> 3) trunk CPU ports.
>
> What Tobias is implementing here is 1). This seems like a good first
> step.
>
> I'm not sure 3) is even possible. Or it might depend on the switch
> generation. The 6352 for example, the CPU Dest field is a port
> number. It does not appear to allow for a trunk. 6390 moved this
> register, but as far as i know, it did not add trunk support.  It
> might be possible to have multiple SoC interfaces sending frames to
> the Switch using DSA tags, but i don't see a way to have the switch
> send frames to the SoC using multiple ports.

I think that (2) and (3) are essentially the same problem, i.e. creating
LAGs out of DSA links, be they switch-to-switch or switch-to-cpu
connections. I think you are correct that the CPU port can not be a
LAG/trunk, but I believe that limitation only applies to TO_CPU packets.
If the CPU ports configured as a LAG, all FORWARDs, i.e. the bulk
traffic, would benefit from the load-balancing. Something like this:

.-----. TO_CPU, FORWARD .-----. TO_CPU, FORWARD .-----.
|     +-----------------+     +-----------------+     |
| CPU |                 | sw0 |                 | sw1 |
|     +-----------------+     +-----------------+     |
'-----'    FORWARD      '-+-+-'    FORWARD      '-+-+-'
                          | |                     | |
                       swp1 swp2               swp3 swp4

So the links selected as the CPU ports will see a marginally higher load
due to all TO_CPU being sent over it. But the hashing is not that great
on this hardware anyway (DA/SA only) so some imbalance is unavoidable.

In order for this to work on transmit, we need to add forward offloading
to the bridge so that we can, for example, send one FORWARD from the CPU
to send an ARP broadcast to swp1..4 instead of four FROM_CPUs.

	Tobias

  reply	other threads:[~2020-10-27 18:25 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-27 10:51 [RFC PATCH 0/4] net: dsa: link aggregation support Tobias Waldekranz
2020-10-27 10:51 ` [RFC PATCH 1/4] net: dsa: mv88e6xxx: use ethertyped dsa for 6390/6390X Tobias Waldekranz
2020-10-27 14:52   ` Marek Behun
2020-10-27 14:54     ` Marek Behun
2020-10-27 14:58       ` Marek Behun
2020-10-27 10:51 ` [RFC PATCH 2/4] net: dsa: link aggregation support Tobias Waldekranz
2020-10-28  0:58   ` Vladimir Oltean
2020-10-28 14:03     ` Tobias Waldekranz
2020-10-27 10:51 ` [RFC PATCH 3/4] net: dsa: mv88e6xxx: " Tobias Waldekranz
2020-10-29  5:28   ` kernel test robot
2020-10-29 11:54   ` Dan Carpenter
2020-10-29 11:54     ` Dan Carpenter
2020-10-27 10:51 ` [RFC PATCH 4/4] net: dsa: tag_edsa: support reception of packets from lag devices Tobias Waldekranz
2020-10-28 12:05   ` Vladimir Oltean
2020-10-28 15:28     ` Tobias Waldekranz
2020-10-28 18:18       ` Vladimir Oltean
2020-10-28 22:31         ` Tobias Waldekranz
2020-10-28 23:08           ` Vladimir Oltean
2020-10-29  7:47             ` Tobias Waldekranz
2020-10-30  9:21               ` Vladimir Oltean
2020-11-01 11:31         ` Ido Schimmel
2020-10-27 12:27 ` [RFC PATCH 0/4] net: dsa: link aggregation support Vladimir Oltean
2020-10-27 14:29   ` Andrew Lunn
2020-10-27 14:59   ` Tobias Waldekranz
2020-10-27 14:00 ` Andrew Lunn
2020-10-27 15:09   ` Tobias Waldekranz
2020-10-27 15:05 ` Marek Behun
2020-10-27 15:23   ` Andrew Lunn
2020-10-27 18:25     ` Tobias Waldekranz [this message]
2020-10-27 18:33       ` Marek Behun
2020-10-27 19:04         ` Vladimir Oltean
2020-10-27 19:21           ` Tobias Waldekranz
2020-10-27 19:00       ` Vladimir Oltean
2020-10-27 19:37         ` Tobias Waldekranz
2020-10-27 20:02           ` Vladimir Oltean
2020-10-27 20:53             ` Tobias Waldekranz
2020-10-27 22:32               ` Vladimir Oltean
2020-10-28  0:27                 ` Tobias Waldekranz
2020-10-28 22:35       ` Marek Behun
2020-10-27 22:36 ` Andrew Lunn
2020-10-28  0:45   ` Tobias Waldekranz
2020-10-28  1:03     ` Andrew Lunn
2020-11-11  4:28 ` Florian Fainelli
2020-11-19 10:51 ` Vladimir Oltean
2020-11-19 11:52   ` Tobias Waldekranz
2020-11-19 18:12     ` Vladimir Oltean

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