[PATCH 01/20] drm: Let userspace check if driver supports modeset

[PATCH 01/20] drm: Let userspace check if driver supports modeset

[José Roberto de Souza]

GPU accelerators usually don't have display block or the display
driver part can be disabled when building driver(for servers it saves
some resources) so it is important let userspace check this
capability too.

Right now we are checking
drmModeGetResources()/drm_mode_getresources() for a error to detect
if display is enabled but it is a hackish way as it can fail for
other reasons too.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/drm_ioctl.c | 3 +++
 include/uapi/drm/drm.h      | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index ea10e9a26aad..3a8438ae9b51 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -244,6 +244,9 @@ static int drm_getcap(struct drm_device *dev, void *data, struct drm_file *file_
 	case DRM_CAP_SYNCOBJ:
 		req->value = drm_core_check_feature(dev, DRIVER_SYNCOBJ);
 		return 0;
+	case DRM_CAP_MODESET:
+		req->value = drm_core_check_feature(dev, DRIVER_MODESET);
+		return 0;
 	}
 
 	/* Other caps only work with KMS drivers */
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 300f336633f2..85fae6ddbf48 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -649,6 +649,7 @@ struct drm_gem_open {
 #define DRM_CAP_PAGE_FLIP_TARGET	0x11
 #define DRM_CAP_CRTC_IN_VBLANK_EVENT	0x12
 #define DRM_CAP_SYNCOBJ		0x13
+#define DRM_CAP_MODESET		0x14
 
 /** DRM_IOCTL_GET_CAP ioctl argument type */
 struct drm_get_cap {
-- 
2.18.0

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[PATCH 02/20] drm/i915: Set PCH as NOP when display is disabled

[José Roberto de Souza]

num_pipes is set to 0 if disable_display is set inside
intel_device_info_runtime_init() but when that happen PCH will
already be set in intel_detect_pch().

i915_driver_load()
	i915_driver_init_early()
		...
		intel_detect_pch()
		...
	...
	i915_driver_init_hw()
		intel_device_info_runtime_init()

So now setting num_pipes = 0 earlier to avoid this problem.

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c          | 5 +++++
 drivers/gpu/drm/i915/intel_device_info.c | 8 ++------
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9dce55182c3a..7952f5877402 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -917,6 +917,11 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 	if (ret < 0)
 		goto err_workqueues;
 
+	if (i915_modparams.disable_display) {
+		DRM_INFO("Display disabled (module parameter)\n");
+		device_info->num_pipes = 0;
+	}
+
 	/* This must be called before any calls to HAS_PCH_* */
 	intel_detect_pch(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 0ef0c6448d53..67102b481c8f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -776,12 +776,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 			info->num_sprites[pipe] = 1;
 	}
 
-	if (i915_modparams.disable_display) {
-		DRM_INFO("Display disabled (module parameter)\n");
-		info->num_pipes = 0;
-	} else if (info->num_pipes > 0 &&
-		   (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
-		   HAS_PCH_SPLIT(dev_priv)) {
+	if (info->num_pipes > 0 && (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
+	    HAS_PCH_SPLIT(dev_priv)) {
 		u32 fuse_strap = I915_READ(FUSE_STRAP);
 		u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 
-- 
2.18.0

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[PATCH 03/20] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake

[José Roberto de Souza]

Instead of have the same code spread into 4 platforms lets share it.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 25 ++++++++++++-------------
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index e209edbc561d..9575b7402172 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3264,18 +3264,24 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
 	I915_WRITE(MBUS_ABOX_CTL, val);
 }
 
+static void skl_pch_reset_handshake(struct drm_i915_private *dev_priv)
+{
+	u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);
+
+	val |= RESET_PCH_HANDSHAKE_ENABLE;
+	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+}
+
 static void skl_display_core_init(struct drm_i915_private *dev_priv,
 				   bool resume)
 {
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	struct i915_power_well *well;
-	uint32_t val;
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
 	/* enable PCH reset handshake */
-	val = I915_READ(HSW_NDE_RSTWRN_OPT);
-	I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
+	skl_pch_reset_handshake(dev_priv);
 
 	/* enable PG1 and Misc I/O */
 	mutex_lock(&power_domains->lock);
@@ -3331,7 +3337,6 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
 {
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	struct i915_power_well *well;
-	uint32_t val;
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
@@ -3341,9 +3346,7 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
 	 * Move the handshake programming to initialization sequence.
 	 * Previously was left up to BIOS.
 	 */
-	val = I915_READ(HSW_NDE_RSTWRN_OPT);
-	val &= ~RESET_PCH_HANDSHAKE_ENABLE;
-	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+	skl_pch_reset_handshake(dev_priv);
 
 	/* Enable PG1 */
 	mutex_lock(&power_domains->lock);
@@ -3464,9 +3467,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
 	/* 1. Enable PCH Reset Handshake */
-	val = I915_READ(HSW_NDE_RSTWRN_OPT);
-	val |= RESET_PCH_HANDSHAKE_ENABLE;
-	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+	skl_pch_reset_handshake(dev_priv);
 
 	/* 2. Enable Comp */
 	val = I915_READ(CHICKEN_MISC_2);
@@ -3549,9 +3550,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
 	/* 1. Enable PCH reset handshake. */
-	val = I915_READ(HSW_NDE_RSTWRN_OPT);
-	val |= RESET_PCH_HANDSHAKE_ENABLE;
-	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+	skl_pch_reset_handshake(dev_priv);
 
 	for (port = PORT_A; port <= PORT_B; port++) {
 		/* 2. Enable DDI combo PHY comp. */
-- 
2.18.0

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[PATCH 04/20] drm/i915: Move out non-display related calls from display/modeset init/cleanup

[José Roberto de Souza]

i915_load_modeset_init() and intel_modeset_cleanup() was initializing
and cleaning up things that is not display only.
This will make easy initialize driver without display block.

Also moving VLV/CHV/BYT czclk as it is a core clock used as base by
several other GPU blocks not only display, including gem/GT.
Spec: 14370

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c      | 86 ++++++++++++++++++----------
 drivers/gpu/drm/i915/i915_drv.h      |  1 +
 drivers/gpu/drm/i915/intel_display.c | 28 ++-------
 drivers/gpu/drm/i915/intel_pm.c      | 10 ++++
 4 files changed, 72 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7952f5877402..1f784d71f274 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -664,28 +664,15 @@ static int i915_load_modeset_init(struct drm_device *dev)
 	if (ret)
 		goto cleanup_vga_client;
 
-	/* must happen before intel_power_domains_init_hw() on VLV/CHV */
-	intel_update_rawclk(dev_priv);
-
-	intel_power_domains_init_hw(dev_priv, false);
-
 	intel_csr_ucode_init(dev_priv);
 
-	ret = intel_irq_install(dev_priv);
-	if (ret)
-		goto cleanup_csr;
-
 	intel_setup_gmbus(dev_priv);
 
 	/* Important: The output setup functions called by modeset_init need
 	 * working irqs for e.g. gmbus and dp aux transfers. */
 	ret = intel_modeset_init(dev);
 	if (ret)
-		goto cleanup_irq;
-
-	ret = i915_gem_init(dev_priv);
-	if (ret)
-		goto cleanup_modeset;
+		goto cleanup_gmbus;
 
 	intel_setup_overlay(dev_priv);
 
@@ -694,25 +681,18 @@ static int i915_load_modeset_init(struct drm_device *dev)
 
 	ret = intel_fbdev_init(dev);
 	if (ret)
-		goto cleanup_gem;
+		goto cleanup_modeset;
 
 	/* Only enable hotplug handling once the fbdev is fully set up. */
 	intel_hpd_init(dev_priv);
 
 	return 0;
 
-cleanup_gem:
-	if (i915_gem_suspend(dev_priv))
-		DRM_ERROR("failed to idle hardware; continuing to unload!\n");
-	i915_gem_fini(dev_priv);
 cleanup_modeset:
 	intel_modeset_cleanup(dev);
-cleanup_irq:
-	drm_irq_uninstall(dev);
+cleanup_gmbus:
 	intel_teardown_gmbus(dev_priv);
-cleanup_csr:
 	intel_csr_ucode_fini(dev_priv);
-	intel_power_domains_fini_hw(dev_priv);
 	vga_switcheroo_unregister_client(pdev);
 cleanup_vga_client:
 	vga_client_register(pdev, NULL, NULL, NULL);
@@ -1407,9 +1387,25 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 			goto out_cleanup_hw;
 	}
 
+	/* must happen before intel_power_domains_init_hw() on VLV/CHV */
+	intel_update_rawclk(dev_priv);
+
+	/* i915_gem_init() call chain will call
+	 * intel_display_power_put(i915, POWER_DOMAIN_GT_IRQ);
+	 */
+	intel_power_domains_init_hw(dev_priv, false);
+
+	ret = intel_irq_install(dev_priv);
+	if (ret)
+		goto out_cleanup_power;
+
+	ret = i915_gem_init(dev_priv);
+	if (ret)
+		goto cleanup_irq;
+
 	ret = i915_load_modeset_init(&dev_priv->drm);
 	if (ret < 0)
-		goto out_cleanup_hw;
+		goto cleanup_gem;
 
 	i915_driver_register(dev_priv);
 
@@ -1423,6 +1419,15 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 
 	return 0;
 
+cleanup_gem:
+	if (i915_gem_suspend(dev_priv))
+		DRM_ERROR("failed to idle hardware; continuing to unload!\n");
+	intel_cleanup_gt_powersave(dev_priv);
+	i915_gem_fini(dev_priv);
+cleanup_irq:
+	drm_irq_uninstall(&dev_priv->drm);
+out_cleanup_power:
+	intel_power_domains_fini_hw(dev_priv);
 out_cleanup_hw:
 	i915_driver_cleanup_hw(dev_priv);
 out_cleanup_mmio:
@@ -1441,11 +1446,24 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 	return ret;
 }
 
-void i915_driver_unload(struct drm_device *dev)
+/* unload/cleanup the leftover of i915_load_modeset_init() */
+static void i915_modeset_unload(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct pci_dev *pdev = dev_priv->drm.pdev;
 
+	intel_bios_cleanup(dev_priv);
+
+	vga_switcheroo_unregister_client(pdev);
+	vga_client_register(pdev, NULL, NULL, NULL);
+
+	intel_csr_ucode_fini(dev_priv);
+}
+
+void i915_driver_unload(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+
 	i915_driver_unregister(dev_priv);
 
 	if (i915_gem_suspend(dev_priv))
@@ -1457,14 +1475,22 @@ void i915_driver_unload(struct drm_device *dev)
 
 	intel_gvt_cleanup(dev_priv);
 
-	intel_modeset_cleanup(dev);
+	intel_modeset_cleanup_prepare(dev);
 
-	intel_bios_cleanup(dev_priv);
+	intel_disable_gt_powersave(dev_priv);
 
-	vga_switcheroo_unregister_client(pdev);
-	vga_client_register(pdev, NULL, NULL, NULL);
+	/*
+	 * Interrupts and polling as the first thing to avoid creating havoc.
+	 * Too much stuff here (turning of connectors, ...) would
+	 * experience fancy races otherwise.
+	 */
+	intel_irq_uninstall(dev_priv);
 
-	intel_csr_ucode_fini(dev_priv);
+	intel_modeset_cleanup(dev);
+
+	intel_cleanup_gt_powersave(dev_priv);
+
+	i915_modeset_unload(dev);
 
 	/* Free error state after interrupts are fully disabled. */
 	cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0b10a30b7d96..3d956fbdb174 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3439,6 +3439,7 @@ mkwrite_device_info(struct drm_i915_private *dev_priv)
 /* modesetting */
 extern void intel_modeset_init_hw(struct drm_device *dev);
 extern int intel_modeset_init(struct drm_device *dev);
+void intel_modeset_cleanup_prepare(struct drm_device *dev);
 extern void intel_modeset_cleanup(struct drm_device *dev);
 extern int intel_connector_register(struct drm_connector *);
 extern void intel_connector_unregister(struct drm_connector *);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 53e7a7e75384..76d0d2bb3baa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -218,17 +218,6 @@ int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 				 dev_priv->hpll_freq);
 }
 
-static void intel_update_czclk(struct drm_i915_private *dev_priv)
-{
-	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
-		return;
-
-	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
-						      CCK_CZ_CLOCK_CONTROL);
-
-	DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
-}
-
 static inline u32 /* units of 100MHz */
 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 		    const struct intel_crtc_state *pipe_config)
@@ -15267,7 +15256,6 @@ int intel_modeset_init(struct drm_device *dev)
 	intel_shared_dpll_init(dev);
 	intel_update_fdi_pll_freq(dev_priv);
 
-	intel_update_czclk(dev_priv);
 	intel_modeset_init_hw(dev);
 
 	if (dev_priv->max_cdclk_freq == 0)
@@ -15982,7 +15970,7 @@ static void intel_hpd_poll_fini(struct drm_device *dev)
 	drm_connector_list_iter_end(&conn_iter);
 }
 
-void intel_modeset_cleanup(struct drm_device *dev)
+void intel_modeset_cleanup_prepare(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
@@ -15990,15 +15978,11 @@ void intel_modeset_cleanup(struct drm_device *dev)
 
 	flush_work(&dev_priv->atomic_helper.free_work);
 	WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
+}
 
-	intel_disable_gt_powersave(dev_priv);
-
-	/*
-	 * Interrupts and polling as the first thing to avoid creating havoc.
-	 * Too much stuff here (turning of connectors, ...) would
-	 * experience fancy races otherwise.
-	 */
-	intel_irq_uninstall(dev_priv);
+void intel_modeset_cleanup(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
 
 	/*
 	 * Due to the hpd irq storm handling the hotplug work can re-arm the
@@ -16020,8 +16004,6 @@ void intel_modeset_cleanup(struct drm_device *dev)
 
 	intel_cleanup_overlay(dev_priv);
 
-	intel_cleanup_gt_powersave(dev_priv);
-
 	intel_teardown_gmbus(dev_priv);
 
 	destroy_workqueue(dev_priv->modeset_wq);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 03654f5f68c3..30ca77b81b0c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7419,6 +7419,14 @@ static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
 			 dev_priv->gt_pm.rps.gpll_ref_freq);
 }
 
+static void valleyview_update_czclk(struct drm_i915_private *dev_priv)
+{
+	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
+						      CCK_CZ_CLOCK_CONTROL);
+
+	DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
+}
+
 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
 {
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
@@ -7426,6 +7434,7 @@ static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
 
 	valleyview_setup_pctx(dev_priv);
 
+	valleyview_update_czclk(dev_priv);
 	vlv_init_gpll_ref_freq(dev_priv);
 
 	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
@@ -7472,6 +7481,7 @@ static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
 
 	cherryview_setup_pctx(dev_priv);
 
+	valleyview_update_czclk(dev_priv);
 	vlv_init_gpll_ref_freq(dev_priv);
 
 	mutex_lock(&dev_priv->sb_lock);
-- 
2.18.0

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[PATCH 05/20] drm/i915: Release POWER_DOMAIN_INIT reference when display is disabled

[José Roberto de Souza]

When loading the driver
i915_load_modeset_init()->intel_modeset_setup_hw_state() do the
counter part call of intel_power_domains_init_hw() calling
intel_display_set_init_power(false).
The problem is i915_load_modeset_init() is not executed when display
is disabled, so moving it to i915_driver_load().
Also calling intel_display_set_init_power(false) in
__intel_display_resume() as it would be executed by calling
intel_modeset_setup_hw_state().

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c      | 4 ++++
 drivers/gpu/drm/i915/intel_display.c | 8 +++++---
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1f784d71f274..9e2de6d1de3d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1407,6 +1407,10 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 	if (ret < 0)
 		goto cleanup_gem;
 
+	/* intel_power_domains_init_hw() counter part  */
+	intel_display_set_init_power(dev_priv, false);
+	intel_power_domains_verify_state(dev_priv);
+
 	i915_driver_register(dev_priv);
 
 	intel_runtime_pm_enable(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 76d0d2bb3baa..5f0426d6d360 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3664,11 +3664,16 @@ __intel_display_resume(struct drm_device *dev,
 		       struct drm_atomic_state *state,
 		       struct drm_modeset_acquire_ctx *ctx)
 {
+	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct drm_crtc_state *crtc_state;
 	struct drm_crtc *crtc;
 	int i, ret;
 
 	intel_modeset_setup_hw_state(dev, ctx);
+
+	intel_display_set_init_power(dev_priv, false);
+	intel_power_domains_verify_state(dev_priv);
+
 	i915_redisable_vga(to_i915(dev));
 
 	if (!state)
@@ -15888,9 +15893,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
 		if (WARN_ON(put_domains))
 			modeset_put_power_domains(dev_priv, put_domains);
 	}
-	intel_display_set_init_power(dev_priv, false);
-
-	intel_power_domains_verify_state(dev_priv);
 
 	intel_fbc_init_pipe_state(dev_priv);
 }
-- 
2.18.0

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[PATCH 06/20] drm/i915: Move drm_vblank_init() to i915_load_modeset_init()

[José Roberto de Souza]

i915_load_modeset_init() is a more suitable place than
i915_driver_load() as vblank is part of modeset.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 20 +++++++-------------
 1 file changed, 7 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9e2de6d1de3d..bdb41511d375 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -645,6 +645,13 @@ static int i915_load_modeset_init(struct drm_device *dev)
 	if (i915_inject_load_failure())
 		return -ENODEV;
 
+	if (INTEL_INFO(dev_priv)->num_pipes) {
+		ret = drm_vblank_init(&dev_priv->drm,
+				      INTEL_INFO(dev_priv)->num_pipes);
+		if (ret)
+			goto out;
+	}
+
 	intel_bios_init(dev_priv);
 
 	/* If we have > 1 VGA cards, then we need to arbitrate access
@@ -1375,18 +1382,6 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 	if (ret < 0)
 		goto out_cleanup_mmio;
 
-	/*
-	 * TODO: move the vblank init and parts of modeset init steps into one
-	 * of the i915_driver_init_/i915_driver_register functions according
-	 * to the role/effect of the given init step.
-	 */
-	if (INTEL_INFO(dev_priv)->num_pipes) {
-		ret = drm_vblank_init(&dev_priv->drm,
-				      INTEL_INFO(dev_priv)->num_pipes);
-		if (ret)
-			goto out_cleanup_hw;
-	}
-
 	/* must happen before intel_power_domains_init_hw() on VLV/CHV */
 	intel_update_rawclk(dev_priv);
 
@@ -1432,7 +1427,6 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 	drm_irq_uninstall(&dev_priv->drm);
 out_cleanup_power:
 	intel_power_domains_fini_hw(dev_priv);
-out_cleanup_hw:
 	i915_driver_cleanup_hw(dev_priv);
 out_cleanup_mmio:
 	i915_driver_cleanup_mmio(dev_priv);
-- 
2.18.0

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[PATCH 07/20] drm/i915: Move FBC init and cleanup calls to modeset functions

[José Roberto de Souza]

Although FBC helps save power it do not belongs to power management
also the cleanup was placed in i915_driver_unload() also not a good
place. intel_modeset_init()/intel_modeset_cleanup() are better places
also this will help make easy disable features that depends in
display being enabled in driver.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c      | 1 -
 drivers/gpu/drm/i915/intel_display.c | 4 ++++
 drivers/gpu/drm/i915/intel_pm.c      | 2 --
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index bdb41511d375..22323d88734d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1495,7 +1495,6 @@ void i915_driver_unload(struct drm_device *dev)
 	i915_reset_error_state(dev_priv);
 
 	i915_gem_fini(dev_priv);
-	intel_fbc_cleanup_cfb(dev_priv);
 
 	intel_power_domains_fini_hw(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5f0426d6d360..11f720f4228c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15198,6 +15198,8 @@ int intel_modeset_init(struct drm_device *dev)
 
 	intel_init_quirks(dev);
 
+	intel_fbc_init(dev_priv);
+
 	intel_init_pm(dev_priv);
 
 	if (INTEL_INFO(dev_priv)->num_pipes == 0)
@@ -16009,6 +16011,8 @@ void intel_modeset_cleanup(struct drm_device *dev)
 	intel_teardown_gmbus(dev_priv);
 
 	destroy_workqueue(dev_priv->modeset_wq);
+
+	intel_fbc_cleanup_cfb(dev_priv);
 }
 
 void intel_connector_attach_encoder(struct intel_connector *connector,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 30ca77b81b0c..e45ab21e8566 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9309,8 +9309,6 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 /* Set up chip specific power management-related functions */
 void intel_init_pm(struct drm_i915_private *dev_priv)
 {
-	intel_fbc_init(dev_priv);
-
 	/* For cxsr */
 	if (IS_PINEVIEW(dev_priv))
 		i915_pineview_get_mem_freq(dev_priv);
-- 
2.18.0

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[PATCH 08/20] drm/i915: Do not modifiy reserved bit in gens that do not have IPC

[José Roberto de Souza]

IPC was only added in SKL+(actually we don't even enable for SKL due
WA) so without this change, driver was writing to a reserved bit.

Also check for the WA in intel_init_ipc() to avoid further writes to
ipc_enabled.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e45ab21e8566..0ab10a974850 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6107,10 +6107,8 @@ void intel_enable_ipc(struct drm_i915_private *dev_priv)
 	u32 val;
 
 	/* Display WA #0477 WaDisableIPC: skl */
-	if (IS_SKYLAKE(dev_priv)) {
-		dev_priv->ipc_enabled = false;
+	if (!HAS_IPC(dev_priv) || IS_SKYLAKE(dev_priv))
 		return;
-	}
 
 	val = I915_READ(DISP_ARB_CTL2);
 
@@ -6125,7 +6123,9 @@ void intel_enable_ipc(struct drm_i915_private *dev_priv)
 void intel_init_ipc(struct drm_i915_private *dev_priv)
 {
 	dev_priv->ipc_enabled = false;
-	if (!HAS_IPC(dev_priv))
+
+	/* Display WA #0477 WaDisableIPC: skl */
+	if (!HAS_IPC(dev_priv) || IS_SKYLAKE(dev_priv))
 		return;
 
 	dev_priv->ipc_enabled = true;
-- 
2.18.0

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[PATCH 09/20] drm/i915: Move intel_init_ipc() call to i915_load_modeset_init()

[José Roberto de Souza]

IPC(Isochronous Priority Control not Inter-process communication btw)
is a display feature, so i915_load_modeset_init() is the right place
to initialize it.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 22323d88734d..e9a6cc7b3efd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -693,6 +693,8 @@ static int i915_load_modeset_init(struct drm_device *dev)
 	/* Only enable hotplug handling once the fbdev is fully set up. */
 	intel_hpd_init(dev_priv);
 
+	intel_init_ipc(dev_priv);
+
 	return 0;
 
 cleanup_modeset:
@@ -1410,8 +1412,6 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 
 	intel_runtime_pm_enable(dev_priv);
 
-	intel_init_ipc(dev_priv);
-
 	intel_runtime_pm_put(dev_priv);
 
 	i915_welcome_messages(dev_priv);
-- 
2.18.0

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[PATCH 10/20] drm/i915: Do not call modeset related functions when display is disabled

[José Roberto de Souza]

No need to run i915_load_modeset_init() when num_pipes == 0 also
kms depends on things initialized in i915_load_modeset_init() so not
initializing it too. fbdev and audio have guards against
num_pipes == 0 but lets move it to the if block to make it explicit
to readers.

Also as planes, CRTCs, encoders and connectors are not being added
it is necessary to unset the MODESET driver feature otherwise it
will crash when registering driver in drm, also disabling ATOMIC as
do not make sense have ATOMIC and do not have MODESET.

There is more modeset/display calls that still needs to be removed,
this is a initial work.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c         | 157 +++++++++++++++---------
 drivers/gpu/drm/i915/i915_suspend.c     |  24 ++--
 drivers/gpu/drm/i915/intel_runtime_pm.c |   3 +-
 3 files changed, 114 insertions(+), 70 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e9a6cc7b3efd..e93be91a6701 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -917,7 +917,8 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 	intel_wopcm_init_early(&dev_priv->wopcm);
 	intel_uc_init_early(dev_priv);
 	intel_pm_setup(dev_priv);
-	intel_init_dpio(dev_priv);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_init_dpio(dev_priv);
 	ret = intel_power_domains_init(dev_priv);
 	if (ret < 0)
 		goto err_uc;
@@ -925,8 +926,10 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 	intel_hangcheck_init(dev_priv);
 	intel_init_display_hooks(dev_priv);
 	intel_init_clock_gating_hooks(dev_priv);
-	intel_init_audio_hooks(dev_priv);
-	intel_display_crc_init(dev_priv);
+	if (INTEL_INFO(dev_priv)->num_pipes) {
+		intel_init_audio_hooks(dev_priv);
+		intel_display_crc_init(dev_priv);
+	}
 
 	intel_detect_preproduction_hw(dev_priv);
 
@@ -1258,23 +1261,26 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
 	if (IS_GEN5(dev_priv))
 		intel_gpu_ips_init(dev_priv);
 
-	intel_audio_init(dev_priv);
+	if (INTEL_INFO(dev_priv)->num_pipes) {
+		intel_audio_init(dev_priv);
 
-	/*
-	 * Some ports require correctly set-up hpd registers for detection to
-	 * work properly (leading to ghost connected connector status), e.g. VGA
-	 * on gm45.  Hence we can only set up the initial fbdev config after hpd
-	 * irqs are fully enabled. We do it last so that the async config
-	 * cannot run before the connectors are registered.
-	 */
-	intel_fbdev_initial_config_async(dev);
+		/*
+		 * Some ports require correctly set-up hpd registers for
+		 * detection to work properly (leading to ghost connected
+		 * connector status), e.g. VGA on gm45.  Hence we can only set
+		 * up the initial fbdev config after hpd irqs are fully enabled.
+		 * We do it last so that the async config cannot run before the
+		 * connectors are registered.
+		 */
+		intel_fbdev_initial_config_async(dev);
 
-	/*
-	 * We need to coordinate the hotplugs with the asynchronous fbdev
-	 * configuration, for which we use the fbdev->async_cookie.
-	 */
-	if (INTEL_INFO(dev_priv)->num_pipes)
+		/*
+		 * We need to coordinate the hotplugs with the asynchronous
+		 * fbdev configuration, for which we use the
+		 * fbdev->async_cookie.
+		 */
 		drm_kms_helper_poll_init(dev);
+	}
 }
 
 /**
@@ -1283,15 +1289,17 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
  */
 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 {
-	intel_fbdev_unregister(dev_priv);
-	intel_audio_deinit(dev_priv);
+	if (INTEL_INFO(dev_priv)->num_pipes) {
+		intel_fbdev_unregister(dev_priv);
+		intel_audio_deinit(dev_priv);
 
-	/*
-	 * After flushing the fbdev (incl. a late async config which will
-	 * have delayed queuing of a hotplug event), then flush the hotplug
-	 * events.
-	 */
-	drm_kms_helper_poll_fini(&dev_priv->drm);
+		/*
+		 * After flushing the fbdev (incl. a late async config which
+		 * will have delayed queuing of a hotplug event), then flush the
+		 * hotplug events.
+		 */
+		drm_kms_helper_poll_fini(&dev_priv->drm);
+	}
 
 	intel_gpu_ips_teardown();
 	acpi_video_unregister();
@@ -1343,6 +1351,9 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 	if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
 		driver.driver_features &= ~DRIVER_ATOMIC;
 
+	if (i915_modparams.disable_display)
+		driver.driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC);
+
 	ret = -ENOMEM;
 	dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 	if (dev_priv)
@@ -1400,9 +1411,11 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 	if (ret)
 		goto cleanup_irq;
 
-	ret = i915_load_modeset_init(&dev_priv->drm);
-	if (ret < 0)
-		goto cleanup_gem;
+	if (INTEL_INFO(dev_priv)->num_pipes) {
+		ret = i915_load_modeset_init(&dev_priv->drm);
+		if (ret < 0)
+			goto cleanup_gem;
+	}
 
 	/* intel_power_domains_init_hw() counter part  */
 	intel_display_set_init_power(dev_priv, false);
@@ -1469,11 +1482,13 @@ void i915_driver_unload(struct drm_device *dev)
 
 	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 
-	drm_atomic_helper_shutdown(dev);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		drm_atomic_helper_shutdown(dev);
 
 	intel_gvt_cleanup(dev_priv);
 
-	intel_modeset_cleanup_prepare(dev);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_modeset_cleanup_prepare(dev);
 
 	intel_disable_gt_powersave(dev_priv);
 
@@ -1484,11 +1499,13 @@ void i915_driver_unload(struct drm_device *dev)
 	 */
 	intel_irq_uninstall(dev_priv);
 
-	intel_modeset_cleanup(dev);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_modeset_cleanup(dev);
 
 	intel_cleanup_gt_powersave(dev_priv);
 
-	i915_modeset_unload(dev);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		i915_modeset_unload(dev);
 
 	/* Free error state after interrupts are fully disabled. */
 	cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
@@ -1540,8 +1557,12 @@ static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
  */
 static void i915_driver_lastclose(struct drm_device *dev)
 {
-	intel_fbdev_restore_mode(dev);
-	vga_switcheroo_process_delayed_switch();
+	struct drm_i915_private *dev_priv = to_i915(dev);
+
+	if (INTEL_INFO(dev_priv)->num_pipes) {
+		intel_fbdev_restore_mode(dev);
+		vga_switcheroo_process_delayed_switch();
+	}
 }
 
 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
@@ -1611,19 +1632,24 @@ static int i915_drm_suspend(struct drm_device *dev)
 	/* We do a lot of poking in a lot of registers, make sure they work
 	 * properly. */
 	intel_display_set_init_power(dev_priv, true);
-
-	drm_kms_helper_poll_disable(dev);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		drm_kms_helper_poll_disable(dev);
 
 	pci_save_state(pdev);
 
-	intel_display_suspend(dev);
+	if (INTEL_INFO(dev_priv)->num_pipes) {
+		intel_display_suspend(dev);
 
-	intel_dp_mst_suspend(dev_priv);
+		intel_dp_mst_suspend(dev_priv);
+	}
 
 	intel_runtime_pm_disable_interrupts(dev_priv);
-	intel_hpd_cancel_work(dev_priv);
 
-	intel_suspend_encoders(dev_priv);
+	if (INTEL_INFO(dev_priv)->num_pipes) {
+		intel_hpd_cancel_work(dev_priv);
+
+		intel_suspend_encoders(dev_priv);
+	}
 
 	intel_suspend_hw(dev_priv);
 
@@ -1636,11 +1662,13 @@ static int i915_drm_suspend(struct drm_device *dev)
 
 	intel_opregion_unregister(dev_priv);
 
-	intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
 
 	dev_priv->suspend_count++;
 
-	intel_csr_ucode_suspend(dev_priv);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_csr_ucode_suspend(dev_priv);
 
 	enable_rpm_wakeref_asserts(dev_priv);
 
@@ -1751,10 +1779,12 @@ static int i915_drm_resume(struct drm_device *dev)
 	if (ret)
 		DRM_ERROR("failed to re-enable GGTT\n");
 
-	intel_csr_ucode_resume(dev_priv);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_csr_ucode_resume(dev_priv);
 
 	i915_restore_state(dev_priv);
-	intel_pps_unlock_regs_wa(dev_priv);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_pps_unlock_regs_wa(dev_priv);
 	intel_opregion_setup(dev_priv);
 
 	intel_init_pch_refclk(dev_priv);
@@ -1771,7 +1801,8 @@ static int i915_drm_resume(struct drm_device *dev)
 	 */
 	intel_runtime_pm_enable_interrupts(dev_priv);
 
-	drm_mode_config_reset(dev);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		drm_mode_config_reset(dev);
 
 	i915_gem_resume(dev_priv);
 
@@ -1779,27 +1810,30 @@ static int i915_drm_resume(struct drm_device *dev)
 	intel_init_clock_gating(dev_priv);
 
 	spin_lock_irq(&dev_priv->irq_lock);
-	if (dev_priv->display.hpd_irq_setup)
+	if (dev_priv->display.hpd_irq_setup && INTEL_INFO(dev_priv)->num_pipes)
 		dev_priv->display.hpd_irq_setup(dev_priv);
 	spin_unlock_irq(&dev_priv->irq_lock);
 
-	intel_dp_mst_resume(dev_priv);
+	if (INTEL_INFO(dev_priv)->num_pipes) {
+		intel_dp_mst_resume(dev_priv);
 
-	intel_display_resume(dev);
+		intel_display_resume(dev);
 
-	drm_kms_helper_poll_enable(dev);
+		drm_kms_helper_poll_enable(dev);
 
-	/*
-	 * ... but also need to make sure that hotplug processing
-	 * doesn't cause havoc. Like in the driver load code we don't
-	 * bother with the tiny race here where we might lose hotplug
-	 * notifications.
-	 * */
-	intel_hpd_init(dev_priv);
+		/*
+		 * ... but also need to make sure that hotplug processing
+		 * doesn't cause havoc. Like in the driver load code we don't
+		 * bother with the tiny race here where we might lose hotplug
+		 * notifications.
+		 */
+		intel_hpd_init(dev_priv);
+	}
 
 	intel_opregion_register(dev_priv);
 
-	intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
 
 	intel_opregion_notify_adapter(dev_priv, PCI_D0);
 
@@ -2700,7 +2734,8 @@ static int intel_runtime_suspend(struct device *kdev)
 
 	assert_forcewakes_inactive(dev_priv);
 
-	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
+	if (INTEL_INFO(dev_priv)->num_pipes && (!IS_VALLEYVIEW(dev_priv) &&
+						!IS_CHERRYVIEW(dev_priv)))
 		intel_hpd_poll_init(dev_priv);
 
 	DRM_DEBUG_KMS("Device suspended\n");
@@ -2757,10 +2792,12 @@ static int intel_runtime_resume(struct device *kdev)
 	 * power well, so hpd is reinitialized from there. For
 	 * everyone else do it here.
 	 */
-	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
+	if (INTEL_INFO(dev_priv)->num_pipes && (!IS_VALLEYVIEW(dev_priv) &&
+						!IS_CHERRYVIEW(dev_priv)))
 		intel_hpd_init(dev_priv);
 
-	intel_enable_ipc(dev_priv);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_enable_ipc(dev_priv);
 
 	enable_rpm_wakeref_asserts(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 8f3aa4dc0c98..f697865236a6 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -63,11 +63,13 @@ int i915_save_state(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->drm.struct_mutex);
 
-	i915_save_display(dev_priv);
+	if (INTEL_INFO(dev_priv)->num_pipes) {
+		i915_save_display(dev_priv);
 
-	if (IS_GEN4(dev_priv))
-		pci_read_config_word(pdev, GCDGMBUS,
-				     &dev_priv->regfile.saveGCDGMBUS);
+		if (IS_GEN4(dev_priv))
+			pci_read_config_word(pdev, GCDGMBUS,
+					     &dev_priv->regfile.saveGCDGMBUS);
+	}
 
 	/* Cache mode state */
 	if (INTEL_GEN(dev_priv) < 7)
@@ -108,10 +110,13 @@ int i915_restore_state(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->drm.struct_mutex);
 
-	if (IS_GEN4(dev_priv))
-		pci_write_config_word(pdev, GCDGMBUS,
-				      dev_priv->regfile.saveGCDGMBUS);
-	i915_restore_display(dev_priv);
+	if (INTEL_INFO(dev_priv)->num_pipes) {
+		if (IS_GEN4(dev_priv))
+			pci_write_config_word(pdev, GCDGMBUS,
+					      dev_priv->regfile.saveGCDGMBUS);
+
+		i915_restore_display(dev_priv);
+	}
 
 	/* Cache mode state */
 	if (INTEL_GEN(dev_priv) < 7)
@@ -143,7 +148,8 @@ int i915_restore_state(struct drm_i915_private *dev_priv)
 
 	mutex_unlock(&dev_priv->drm.struct_mutex);
 
-	intel_i2c_reset(dev_priv);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_i2c_reset(dev_priv);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 9575b7402172..97178d512852 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1049,7 +1049,8 @@ static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
 	intel_power_sequencer_reset(dev_priv);
 
 	/* Prevent us from re-enabling polling on accident in late suspend */
-	if (!dev_priv->drm.dev->power.is_suspended)
+	if (INTEL_INFO(dev_priv)->num_pipes &&
+	    !dev_priv->drm.dev->power.is_suspended)
 		intel_hpd_poll_init(dev_priv);
 }
 
-- 
2.18.0

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[PATCH 11/20] drm/i915: Grab a runtime pm reference before run live selftests

[José Roberto de Souza]

Now that modeset stuff is not being initialized when display is
disabled nothing is holding a power well or runtime pm reference
when running live selftests. And IGT runs live selftests with
display on and off, causing the below warning:

[  473.586533] Setting dangerous option live_selftests - tainting kernel
[  484.219068] ------------[ cut here ]------------
[  484.219070] RPM wakelock ref not held during HW access
[  484.219126] WARNING: CPU: 3 PID: 4659 at drivers/gpu/drm/i915/intel_drv.h:1986 intel_runtime_pm_get_noresume+0x6c/0x70 [i915]
[  484.219128] Modules linked in: i915(+) amdgpu chash gpu_sched ttm vgem snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic btusb btrtl btbcm x86_pkg_temp_thermal btintel coretemp snd_hda_codec asix crct10dif_pclmul bluetooth crc32_pclmul usbnet snd_hwdep mii snd_hda_core ghash_clmulni_intel e1000e snd_pcm ecdh_generic mei_me mei prime_numbers pinctrl_sunrisepoint pinctrl_intel [last unloaded: i915]
[  484.219173] CPU: 3 PID: 4659 Comm: drv_selftest Tainted: G     U            4.18.0-rc8-CI-Trybot_2696+ #1
[  484.219174] Hardware name: Intel Corporation Kabylake Client platform/Kabylake R DDR4 RVP, BIOS KBLSE2R1.R00.X078.P02.1703030515 03/03/2017
[  484.219205] RIP: 0010:intel_runtime_pm_get_noresume+0x6c/0x70 [i915]
[  484.219206] Code: 94 77 20 00 01 e8 04 bf 53 e0 0f 0b eb c5 80 3d 83 77 20 00 00 75 c6 48 c7 c7 50 b4 ca a0 c6 05 73 77 20 00 01 e8 e4 be 53 e0 <0f> 0b eb af 41 54 55 53 80 bf e4 ab 00 00 00 48 89 fb 48 8b af e0
[  484.219277] RSP: 0018:ffffc900003bfa10 EFLAGS: 00010286
[  484.219279] RAX: 0000000000000000 RBX: ffff88023c160000 RCX: 0000000000000001
[  484.219281] RDX: 0000000080000001 RSI: ffffffff820c708c RDI: 00000000ffffffff
[  484.219282] RBP: ffff8802b4ceb3f8 R08: 00000000afcc94fa R09: 0000000000000000
[  484.219284] R10: ffff8802b5820358 R11: 0000000000000000 R12: ffff88023c160068
[  484.219285] R13: ffffffffa0c80e30 R14: ffffffffa0cce2a0 R15: ffff88023c160000
[  484.219287] FS:  00007f4d95a83980(0000) GS:ffff8802becc0000(0000) knlGS:0000000000000000
[  484.219288] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  484.219290] CR2: 00007f4d953257a0 CR3: 00000001fa1d8001 CR4: 00000000003606e0
[  484.219291] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[  484.219292] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
[  484.219294] Call Trace:
[  484.219328]  i915_gem_unpark+0xb9/0x170 [i915]
[  484.219361]  igt_mmap_offset_exhaustion+0x365/0x6e0 [i915]
[  484.219400]  ? __i915_subtests+0x39/0xf0 [i915]
[  484.219403]  ? ring_buffer_unlock_commit+0x20/0xd0
[  484.219406]  ? trace_vbprintk+0x171/0x220
[  484.219411]  ? __trace_bprintk+0x57/0x80
[  484.219450]  __i915_subtests+0x5e/0xf0 [i915]
[  484.219487]  __run_selftests+0x10b/0x190 [i915]
[  484.219522]  i915_live_selftests+0x2c/0x60 [i915]
[  484.219552]  i915_pci_probe+0x50/0xa0 [i915]
[  484.219556]  pci_device_probe+0xa1/0x130
[  484.219560]  driver_probe_device+0x2f5/0x470

So now grabbing and releasing a runtime pm reference around
i915_live_selftests() call.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e931b48369dd..d43b950c2798 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -695,6 +695,7 @@ static void i915_pci_remove(struct pci_dev *pdev)
 
 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 {
+	struct drm_i915_private *dev_priv;
 	struct intel_device_info *intel_info =
 		(struct intel_device_info *) ent->driver_data;
 	int err;
@@ -730,7 +731,10 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 		return -ENODEV;
 	}
 
+	dev_priv = to_i915(pci_get_drvdata(pdev));
+	intel_runtime_pm_get(dev_priv);
 	err = i915_live_selftests(pdev);
+	intel_runtime_pm_put(dev_priv);
 	if (err) {
 		i915_pci_remove(pdev);
 		return err > 0 ? -ENOTTY : err;
-- 
2.18.0

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[PATCH 12/20] drm/i915: Unset reset pch handshake when PCH is not present in one place

[José Roberto de Souza]

Right now RESET_PCH_HANDSHAKE_ENABLE is enabled all the times inside
of intel_power_domains_init_hw() and if PCH is NOP it is unsed in
i915_gem_init_hw().
So making skl_pch_reset_handshake() handle both cases and calling
it for the missing gens in intel_power_domains_init_hw().
Ivybridge have a different register and bits but with the same
objective so moving it too.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c         | 12 ------------
 drivers/gpu/drm/i915/intel_runtime_pm.c | 16 +++++++++++++++-
 2 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 71502512ac1f..49151d79e3b1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5283,18 +5283,6 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
 			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 
-	if (HAS_PCH_NOP(dev_priv)) {
-		if (IS_IVYBRIDGE(dev_priv)) {
-			u32 temp = I915_READ(GEN7_MSG_CTL);
-			temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
-			I915_WRITE(GEN7_MSG_CTL, temp);
-		} else if (INTEL_GEN(dev_priv) >= 7) {
-			u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
-			temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
-			I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
-		}
-	}
-
 	intel_gt_workarounds_apply(dev_priv);
 
 	i915_gem_init_swizzling(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 97178d512852..43d7f9071ff4 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3265,11 +3265,16 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
 	I915_WRITE(MBUS_ABOX_CTL, val);
 }
 
+/* Actually it is hsw+ but until skl it was not required to set it */
 static void skl_pch_reset_handshake(struct drm_i915_private *dev_priv)
 {
 	u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);
 
-	val |= RESET_PCH_HANDSHAKE_ENABLE;
+	if (HAS_PCH_NOP(dev_priv))
+		val &= ~RESET_PCH_HANDSHAKE_ENABLE;
+	else
+		val |= RESET_PCH_HANDSHAKE_ENABLE;
+
 	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
 }
 
@@ -3773,6 +3778,15 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
 		mutex_lock(&power_domains->lock);
 		vlv_cmnlane_wa(dev_priv);
 		mutex_unlock(&power_domains->lock);
+	} else if (IS_IVYBRIDGE(dev_priv)) {
+		if (HAS_PCH_NOP(dev_priv)) {
+			u32 val = I915_READ(GEN7_MSG_CTL);
+
+			val &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
+			I915_WRITE(GEN7_MSG_CTL, val);
+		}
+	} else if (INTEL_GEN(dev_priv) >= 7) {
+		skl_pch_reset_handshake(dev_priv);
 	}
 
 	/* For now, we need the power well to be always enabled. */
-- 
2.18.0

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[PATCH 13/20] drm/i915: Remove redundant checks for num_pipes == 0

[José Roberto de Souza]

This 'if's will always be false because of previous changes so let's
drop then.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c      | 12 +++---------
 drivers/gpu/drm/i915/intel_audio.c   |  3 ---
 drivers/gpu/drm/i915/intel_display.c |  3 ---
 drivers/gpu/drm/i915/intel_i2c.c     |  3 ---
 4 files changed, 3 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e93be91a6701..7a3794e70187 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -645,12 +645,9 @@ static int i915_load_modeset_init(struct drm_device *dev)
 	if (i915_inject_load_failure())
 		return -ENODEV;
 
-	if (INTEL_INFO(dev_priv)->num_pipes) {
-		ret = drm_vblank_init(&dev_priv->drm,
-				      INTEL_INFO(dev_priv)->num_pipes);
-		if (ret)
-			goto out;
-	}
+	ret = drm_vblank_init(&dev_priv->drm, INTEL_INFO(dev_priv)->num_pipes);
+	if (ret)
+		goto out;
 
 	intel_bios_init(dev_priv);
 
@@ -683,9 +680,6 @@ static int i915_load_modeset_init(struct drm_device *dev)
 
 	intel_setup_overlay(dev_priv);
 
-	if (INTEL_INFO(dev_priv)->num_pipes == 0)
-		return 0;
-
 	ret = intel_fbdev_init(dev);
 	if (ret)
 		goto cleanup_modeset;
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index b725835b47ef..769f3f586661 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -962,9 +962,6 @@ void i915_audio_component_init(struct drm_i915_private *dev_priv)
 {
 	int ret;
 
-	if (INTEL_INFO(dev_priv)->num_pipes == 0)
-		return;
-
 	ret = component_add(dev_priv->drm.dev, &i915_audio_component_bind_ops);
 	if (ret < 0) {
 		DRM_ERROR("failed to add audio component (%d)\n", ret);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 11f720f4228c..d3ce4cb4b2b5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15202,9 +15202,6 @@ int intel_modeset_init(struct drm_device *dev)
 
 	intel_init_pm(dev_priv);
 
-	if (INTEL_INFO(dev_priv)->num_pipes == 0)
-		return 0;
-
 	/*
 	 * There may be no VBT; and if the BIOS enabled SSC we can
 	 * just keep using it to avoid unnecessary flicker.  Whereas if the
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index bef32b7c248e..2f941c5b2e8c 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -819,9 +819,6 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
 	unsigned int pin;
 	int ret;
 
-	if (INTEL_INFO(dev_priv)->num_pipes == 0)
-		return 0;
-
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
 	else if (!HAS_GMCH_DISPLAY(dev_priv))
-- 
2.18.0

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[PATCH 14/20] drm/i915: Keep overlay functions naming consistent

[José Roberto de Souza]

All other overlay functions(almost all other functions in i915) follow
intel_overlay_verb, so renaming the ones that do not match that.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c      | 2 +-
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 drivers/gpu/drm/i915/intel_drv.h     | 4 ++--
 drivers/gpu/drm/i915/intel_overlay.c | 4 ++--
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7a3794e70187..7e948bf30cdd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -678,7 +678,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
 	if (ret)
 		goto cleanup_gmbus;
 
-	intel_setup_overlay(dev_priv);
+	intel_overlay_setup(dev_priv);
 
 	ret = intel_fbdev_init(dev);
 	if (ret)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d3ce4cb4b2b5..266cd482325d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -16003,7 +16003,7 @@ void intel_modeset_cleanup(struct drm_device *dev)
 
 	drm_mode_config_cleanup(dev);
 
-	intel_cleanup_overlay(dev_priv);
+	intel_overlay_cleanup(dev_priv);
 
 	intel_teardown_gmbus(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0601abb8c71f..14545f51b885 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1865,8 +1865,8 @@ void intel_attach_aspect_ratio_property(struct drm_connector *connector);
 
 
 /* intel_overlay.c */
-void intel_setup_overlay(struct drm_i915_private *dev_priv);
-void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
+void intel_overlay_setup(struct drm_i915_private *dev_priv);
+void intel_overlay_cleanup(struct drm_i915_private *dev_priv);
 int intel_overlay_switch_off(struct intel_overlay *overlay);
 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
 				  struct drm_file *file_priv);
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index c2f10d899329..a1daedefa0aa 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -1386,7 +1386,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
 	return ret;
 }
 
-void intel_setup_overlay(struct drm_i915_private *dev_priv)
+void intel_overlay_setup(struct drm_i915_private *dev_priv)
 {
 	struct intel_overlay *overlay;
 	struct drm_i915_gem_object *reg_bo;
@@ -1475,7 +1475,7 @@ void intel_setup_overlay(struct drm_i915_private *dev_priv)
 	return;
 }
 
-void intel_cleanup_overlay(struct drm_i915_private *dev_priv)
+void intel_overlay_cleanup(struct drm_i915_private *dev_priv)
 {
 	if (!dev_priv->overlay)
 		return;
-- 
2.18.0

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[PATCH 15/20] drm/i915: Do not reset display when display is disabled

[José Roberto de Souza]

Display is disabled in the beginning of the reset and re-enabled
afterreset each engine needed but if the display is disabled we
should not do it.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8084e35b25c5..cb82f56cd7dc 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3182,7 +3182,8 @@ static void i915_reset_device(struct drm_i915_private *dev_priv,
 
 	/* Use a watchdog to ensure that our reset completes */
 	i915_wedge_on_timeout(&w, dev_priv, 5*HZ) {
-		intel_prepare_reset(dev_priv);
+		if (INTEL_INFO(dev_priv)->num_pipes)
+			intel_prepare_reset(dev_priv);
 
 		error->reason = reason;
 		error->stalled_mask = engine_mask;
@@ -3208,7 +3209,8 @@ static void i915_reset_device(struct drm_i915_private *dev_priv,
 		error->stalled_mask = 0;
 		error->reason = NULL;
 
-		intel_finish_reset(dev_priv);
+		if (INTEL_INFO(dev_priv)->num_pipes)
+			intel_finish_reset(dev_priv);
 	}
 
 	if (!test_bit(I915_WEDGED, &error->flags))
-- 
2.18.0

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[PATCH 16/20] drm/i915: Do not initialize display clocks when display is disabled

[José Roberto de Souza]

cdclk and rawclk are the 2 display clocks that can now be completed
not initialized when display is disabled.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c         | 9 ++++++---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7e948bf30cdd..743b03d50abb 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -918,7 +918,8 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 		goto err_uc;
 	intel_irq_init(dev_priv);
 	intel_hangcheck_init(dev_priv);
-	intel_init_display_hooks(dev_priv);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_init_display_hooks(dev_priv);
 	intel_init_clock_gating_hooks(dev_priv);
 	if (INTEL_INFO(dev_priv)->num_pipes) {
 		intel_init_audio_hooks(dev_priv);
@@ -1390,7 +1391,8 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 		goto out_cleanup_mmio;
 
 	/* must happen before intel_power_domains_init_hw() on VLV/CHV */
-	intel_update_rawclk(dev_priv);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_update_rawclk(dev_priv);
 
 	/* i915_gem_init() call chain will call
 	 * intel_display_power_put(i915, POWER_DOMAIN_GT_IRQ);
@@ -1800,7 +1802,8 @@ static int i915_drm_resume(struct drm_device *dev)
 
 	i915_gem_resume(dev_priv);
 
-	intel_modeset_init_hw(dev);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_modeset_init_hw(dev);
 	intel_init_clock_gating(dev_priv);
 
 	spin_lock_irq(&dev_priv->irq_lock);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 43d7f9071ff4..01e0c8e82fcf 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -807,6 +807,9 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
+	if (!INTEL_INFO(dev_priv)->num_pipes)
+		return;
+
 	dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
 	/* Can't read out voltage_level so can't use intel_cdclk_changed() */
 	WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
-- 
2.18.0

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[PATCH 17/20] drm/i915: Remove duplicated definition of intel_update_rawclk

[José Roberto de Souza]

A few line above we have another definition of intel_update_rawclk()
keeping that one as the function is implemented in intel_cdclk.c.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 14545f51b885..e1f5605ea68c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1477,7 +1477,6 @@ void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
-void intel_update_rawclk(struct drm_i915_private *dev_priv);
 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 		      const char *name, u32 reg, int ref_freq);
-- 
2.18.0

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[PATCH 18/20] drm/i195: Do not initialize display core when display is disabled

[José Roberto de Souza]

The only thing left from *_display_core_init when display is disabled
is the skl_pch_reset_handshake() that is already handling display
enabled and disabled. And *_display_core_uninit() also was left
to disable DC.

If more power savings is required, we could disable the power wells
that BIOS enable.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 32 +++++++++++++++++++++----
 1 file changed, 28 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 01e0c8e82fcf..8a84c77a1a88 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3292,6 +3292,9 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
 	/* enable PCH reset handshake */
 	skl_pch_reset_handshake(dev_priv);
 
+	if (!INTEL_INFO(dev_priv)->num_pipes)
+		return;
+
 	/* enable PG1 and Misc I/O */
 	mutex_lock(&power_domains->lock);
 
@@ -3318,6 +3321,9 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
+	if (!INTEL_INFO(dev_priv)->num_pipes)
+		return;
+
 	gen9_dbuf_disable(dev_priv);
 
 	skl_uninit_cdclk(dev_priv);
@@ -3357,6 +3363,9 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
 	 */
 	skl_pch_reset_handshake(dev_priv);
 
+	if (!INTEL_INFO(dev_priv)->num_pipes)
+		return;
+
 	/* Enable PG1 */
 	mutex_lock(&power_domains->lock);
 
@@ -3380,6 +3389,9 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
+	if (!INTEL_INFO(dev_priv)->num_pipes)
+		return;
+
 	gen9_dbuf_disable(dev_priv);
 
 	bxt_uninit_cdclk(dev_priv);
@@ -3478,6 +3490,9 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
 	/* 1. Enable PCH Reset Handshake */
 	skl_pch_reset_handshake(dev_priv);
 
+	if (!INTEL_INFO(dev_priv)->num_pipes)
+		return;
+
 	/* 2. Enable Comp */
 	val = I915_READ(CHICKEN_MISC_2);
 	val &= ~CNL_COMP_PWR_DOWN;
@@ -3522,7 +3537,10 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
-	/* 1. Disable all display engine functions -> aready done */
+	if (!INTEL_INFO(dev_priv)->num_pipes)
+		return;
+
+	/* 1. Disable all display engine functions -> already done */
 
 	/* 2. Disable DBUF */
 	gen9_dbuf_disable(dev_priv);
@@ -3561,6 +3579,9 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
 	/* 1. Enable PCH reset handshake. */
 	skl_pch_reset_handshake(dev_priv);
 
+	if (!INTEL_INFO(dev_priv)->num_pipes)
+		return;
+
 	for (port = PORT_A; port <= PORT_B; port++) {
 		/* 2. Enable DDI combo PHY comp. */
 		val = I915_READ(ICL_PHY_MISC(port));
@@ -3607,7 +3628,10 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
-	/* 1. Disable all display engine functions -> aready done */
+	if (!INTEL_INFO(dev_priv)->num_pipes)
+		return;
+
+	/* 1. Disable all display engine functions -> already done */
 
 	/* 2. Disable DBUF */
 	icl_dbuf_disable(dev_priv);
@@ -3773,11 +3797,11 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
 		skl_display_core_init(dev_priv, resume);
 	} else if (IS_GEN9_LP(dev_priv)) {
 		bxt_display_core_init(dev_priv, resume);
-	} else if (IS_CHERRYVIEW(dev_priv)) {
+	} else if (IS_CHERRYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
 		mutex_lock(&power_domains->lock);
 		chv_phy_control_init(dev_priv);
 		mutex_unlock(&power_domains->lock);
-	} else if (IS_VALLEYVIEW(dev_priv)) {
+	} else if (IS_VALLEYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
 		mutex_lock(&power_domains->lock);
 		vlv_cmnlane_wa(dev_priv);
 		mutex_unlock(&power_domains->lock);
-- 
2.18.0

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[PATCH 19/20] drm/i915: Warn when display irq functions is executed when display is disabled

[José Roberto de Souza]

With previous patches any of this warnings shows up but lets add then
so any other patch that breaks that can be caught by CI tests.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c      | 14 ++++++++++++++
 drivers/gpu/drm/i915/intel_hotplug.c |  2 ++
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index cb82f56cd7dc..f785ec61fea8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2511,6 +2511,8 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
 	enum pipe pipe;
 	u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
 
+	WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes);
+
 	if (hotplug_trigger)
 		ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
 
@@ -2557,6 +2559,8 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
 	enum pipe pipe;
 	u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
 
+	WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes);
+
 	if (hotplug_trigger)
 		ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
 
@@ -2725,6 +2729,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 	u32 iir;
 	enum pipe pipe;
 
+	WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes);
+
 	if (master_ctl & GEN8_DE_MISC_IRQ) {
 		iir = I915_READ(GEN8_DE_MISC_IIR);
 		if (iir) {
@@ -3867,6 +3873,8 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug_irqs, enabled_irqs;
 
+	WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes);
+
 	hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
 	enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
 
@@ -3895,6 +3903,8 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug_irqs, enabled_irqs;
 
+	WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes);
+
 	if (INTEL_GEN(dev_priv) >= 8) {
 		hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
 		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
@@ -3957,6 +3967,8 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug_irqs, enabled_irqs;
 
+	WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes);
+
 	enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
 	hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
 
@@ -4674,6 +4686,8 @@ static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug_en;
 
+	WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes);
+
 	lockdep_assert_held(&dev_priv->irq_lock);
 
 	/* Note HDMI and DP share hotplug bits */
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
index 648a13c6043c..908d8e589f9a 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -399,6 +399,8 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
 	if (!pin_mask)
 		return;
 
+	WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes);
+
 	spin_lock(&dev_priv->irq_lock);
 	for_each_intel_encoder(&dev_priv->drm, encoder) {
 		enum hpd_pin pin = encoder->hpd_pin;
-- 
2.18.0

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[PATCH 20/20] drm/i915: Do not enable all power wells when display is disabled

[José Roberto de Souza]

POWER_DOMAIN_INIT is used when doing driver initialization or cleanup
because driver will touch a lot of registers and using
POWER_DOMAIN_INIT as a shortcut to power on or down every power well.

So here skiping the call to the functions that actually power on or
down power wells when domain is POWER_DOMAIN_INIT and display is
disabled but it still grabs and releases the runtime pm reference
to guarantee that hardware will be powered during initialization.

This patch plus the changes in the previous patches is enough to not
enable any power well when display is disabled, the only exception is
POWER_DOMAIN_GT_IRQ that is used by gem to inhibits DC power savings
while using GT.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c         |  8 +++++++-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 10 ++++++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 743b03d50abb..5227cf0683f0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1415,7 +1415,13 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 
 	/* intel_power_domains_init_hw() counter part  */
 	intel_display_set_init_power(dev_priv, false);
-	intel_power_domains_verify_state(dev_priv);
+	/* FIXME: When display is disabled all the power wells enabled by
+	 * BIOS/firmware will still be enabled at this point so skip the
+	 * verify state for now, this will be fixed in future patch disabling
+	 * all the power wells that BIOS/firmware enabled.
+	 */
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_power_domains_verify_state(dev_priv);
 
 	i915_driver_register(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8a84c77a1a88..7f0c10ee475a 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1543,6 +1543,9 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	struct i915_power_well *power_well;
 
+	WARN_ON(!INTEL_INFO(dev_priv)->num_pipes &&
+		domain != POWER_DOMAIN_GT_IRQ);
+
 	for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
 		intel_power_well_get(dev_priv, power_well);
 
@@ -1568,6 +1571,9 @@ void intel_display_power_get(struct drm_i915_private *dev_priv,
 
 	intel_runtime_pm_get(dev_priv);
 
+	if (domain == POWER_DOMAIN_INIT && !INTEL_INFO(dev_priv)->num_pipes)
+		return;
+
 	mutex_lock(&power_domains->lock);
 
 	__intel_display_power_get_domain(dev_priv, domain);
@@ -1628,6 +1634,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	struct i915_power_domains *power_domains;
 	struct i915_power_well *power_well;
 
+	if (domain == POWER_DOMAIN_INIT && !INTEL_INFO(dev_priv)->num_pipes)
+		goto end;
+
 	power_domains = &dev_priv->power_domains;
 
 	mutex_lock(&power_domains->lock);
@@ -1642,6 +1651,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 
 	mutex_unlock(&power_domains->lock);
 
+end:
 	intel_runtime_pm_put(dev_priv);
 }
 
-- 
2.18.0

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✗ Fi.CI.CHECKPATCH: warning for series starting with [01/20] drm: Let userspace check if driver supports modeset

[Patchwork]

== Series Details ==

Series: series starting with [01/20] drm: Let userspace check if driver supports modeset
URL   : https://patchwork.freedesktop.org/series/47917/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
bf1ef1e800de drm: Let userspace check if driver supports modeset
9f0e7c79bc59 drm/i915: Set PCH as NOP when display is disabled
598334e10538 drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake
122c3ac9503e drm/i915: Move out non-display related calls from display/modeset init/cleanup
d2ec830c989d drm/i915: Release POWER_DOMAIN_INIT reference when display is disabled
fe4a5e67d330 drm/i915: Move drm_vblank_init() to i915_load_modeset_init()
b4186ea6f0c7 drm/i915: Move FBC init and cleanup calls to modeset functions
9e2ed46b2794 drm/i915: Do not modifiy reserved bit in gens that do not have IPC
8f6838b45b9a drm/i915: Move intel_init_ipc() call to i915_load_modeset_init()
da72cc4a48be drm/i915: Do not call modeset related functions when display is disabled
-:349: CHECK:CAMELCASE: Avoid CamelCase: <saveGCDGMBUS>
#349: FILE: drivers/gpu/drm/i915/i915_suspend.c:71:
+					     &dev_priv->regfile.saveGCDGMBUS);

total: 0 errors, 0 warnings, 1 checks, 338 lines checked
4c68117a021e drm/i915: Grab a runtime pm reference before run live selftests
6d193c6eaca8 drm/i915: Unset reset pch handshake when PCH is not present in one place
c79c34c7a7f4 drm/i915: Remove redundant checks for num_pipes == 0
bfb38e77a071 drm/i915: Keep overlay functions naming consistent
38bab913e093 drm/i915: Do not reset display when display is disabled
37e3e80ae09a drm/i915: Do not initialize display clocks when display is disabled
5d3eacc063e0 drm/i915: Remove duplicated definition of intel_update_rawclk
faeabdac7948 drm/i195: Do not initialize display core when display is disabled
f8d134458ced drm/i915: Warn when display irq functions is executed when display is disabled
b3ef168cf378 drm/i915: Do not enable all power wells when display is disabled

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✗ Fi.CI.SPARSE: warning for series starting with [01/20] drm: Let userspace check if driver supports modeset

[Patchwork]

== Series Details ==

Series: series starting with [01/20] drm: Let userspace check if driver supports modeset
URL   : https://patchwork.freedesktop.org/series/47917/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm: Let userspace check if driver supports modeset
Okay!

Commit: drm/i915: Set PCH as NOP when display is disabled
Okay!

Commit: drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake
Okay!

Commit: drm/i915: Move out non-display related calls from display/modeset init/cleanup
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3675:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3676:16: warning: expression using sizeof(void)

Commit: drm/i915: Release POWER_DOMAIN_INIT reference when display is disabled
Okay!

Commit: drm/i915: Move drm_vblank_init() to i915_load_modeset_init()
Okay!

Commit: drm/i915: Move FBC init and cleanup calls to modeset functions
Okay!

Commit: drm/i915: Do not modifiy reserved bit in gens that do not have IPC
Okay!

Commit: drm/i915: Move intel_init_ipc() call to i915_load_modeset_init()
Okay!

Commit: drm/i915: Do not call modeset related functions when display is disabled
Okay!

Commit: drm/i915: Grab a runtime pm reference before run live selftests
Okay!

Commit: drm/i915: Unset reset pch handshake when PCH is not present in one place
Okay!

Commit: drm/i915: Remove redundant checks for num_pipes == 0
Okay!

Commit: drm/i915: Keep overlay functions naming consistent
Okay!

Commit: drm/i915: Do not reset display when display is disabled
Okay!

Commit: drm/i915: Do not initialize display clocks when display is disabled
Okay!

Commit: drm/i915: Remove duplicated definition of intel_update_rawclk
Okay!

Commit: drm/i195: Do not initialize display core when display is disabled
Okay!

Commit: drm/i915: Warn when display irq functions is executed when display is disabled
Okay!

Commit: drm/i915: Do not enable all power wells when display is disabled
Okay!

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✓ Fi.CI.BAT: success for series starting with [01/20] drm: Let userspace check if driver supports modeset

[Patchwork]

== Series Details ==

Series: series starting with [01/20] drm: Let userspace check if driver supports modeset
URL   : https://patchwork.freedesktop.org/series/47917/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4635 -> Patchwork_9896 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/47917/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9896 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_module_reload@basic-reload:
      fi-glk-j4005:       PASS -> DMESG-WARN (fdo#106725, fdo#106248)

    igt@drv_selftest@live_hangcheck:
      fi-cfl-s3:          PASS -> DMESG-FAIL (fdo#106560)

    igt@drv_selftest@live_workarounds:
      fi-skl-6700hq:      PASS -> DMESG-FAIL (fdo#107292)
      fi-cnl-psr:         PASS -> DMESG-FAIL (fdo#107292)

    igt@kms_chamelium@dp-edid-read:
      fi-kbl-7500u:       PASS -> FAIL (fdo#103841)

    
    ==== Possible fixes ====

    igt@drv_selftest@live_hangcheck:
      fi-cnl-psr:         DMESG-FAIL (fdo#106560) -> PASS
      fi-skl-guc:         DMESG-FAIL (fdo#107174) -> PASS

    igt@kms_pipe_crc_basic@read-crc-pipe-b:
      {fi-byt-clapper}:   FAIL (fdo#107362) -> PASS

    
    ==== Warnings ====

    {igt@kms_psr@primary_page_flip}:
      fi-cnl-psr:         DMESG-FAIL (fdo#107372) -> DMESG-WARN (fdo#107372)

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725
  fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
  fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372


== Participating hosts (50 -> 46) ==

  Additional (1): fi-hsw-peppy 
  Missing    (5): fi-byt-squawks fi-ilk-m540 fi-bxt-dsi fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4635 -> Patchwork_9896

  CI_DRM_4635: a9f34f7e3bab765e2b1320a1b154a76be38602a7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4589: 779d2d42f9db6a2797d1ef50036af6fac4e62e73 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9896: b3ef168cf378f3302a530145c7f4aa5b9226e7c3 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

b3ef168cf378 drm/i915: Do not enable all power wells when display is disabled
f8d134458ced drm/i915: Warn when display irq functions is executed when display is disabled
faeabdac7948 drm/i195: Do not initialize display core when display is disabled
5d3eacc063e0 drm/i915: Remove duplicated definition of intel_update_rawclk
37e3e80ae09a drm/i915: Do not initialize display clocks when display is disabled
38bab913e093 drm/i915: Do not reset display when display is disabled
bfb38e77a071 drm/i915: Keep overlay functions naming consistent
c79c34c7a7f4 drm/i915: Remove redundant checks for num_pipes == 0
6d193c6eaca8 drm/i915: Unset reset pch handshake when PCH is not present in one place
4c68117a021e drm/i915: Grab a runtime pm reference before run live selftests
da72cc4a48be drm/i915: Do not call modeset related functions when display is disabled
8f6838b45b9a drm/i915: Move intel_init_ipc() call to i915_load_modeset_init()
9e2ed46b2794 drm/i915: Do not modifiy reserved bit in gens that do not have IPC
b4186ea6f0c7 drm/i915: Move FBC init and cleanup calls to modeset functions
fe4a5e67d330 drm/i915: Move drm_vblank_init() to i915_load_modeset_init()
d2ec830c989d drm/i915: Release POWER_DOMAIN_INIT reference when display is disabled
122c3ac9503e drm/i915: Move out non-display related calls from display/modeset init/cleanup
598334e10538 drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake
9f0e7c79bc59 drm/i915: Set PCH as NOP when display is disabled
bf1ef1e800de drm: Let userspace check if driver supports modeset

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9896/issues.html
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✓ Fi.CI.IGT: success for series starting with [01/20] drm: Let userspace check if driver supports modeset

[Patchwork]

== Series Details ==

Series: series starting with [01/20] drm: Let userspace check if driver supports modeset
URL   : https://patchwork.freedesktop.org/series/47917/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4635_full -> Patchwork_9896_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9896_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9896_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9896_full:

  === IGT changes ===

    ==== Warnings ====

    igt@pm_rc6_residency@rc6-accuracy:
      shard-snb:          SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_9896_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_rotation_crc@sprite-rotation-180:
      shard-hsw:          PASS -> FAIL (fdo#103925)

    igt@perf_pmu@rc6-runtime-pm:
      shard-apl:          PASS -> FAIL (fdo#105010)

    
    ==== Possible fixes ====

    igt@gem_exec_await@wide-contexts:
      shard-apl:          FAIL (fdo#106680, fdo#105900) -> PASS

    igt@gem_exec_reuse@single:
      shard-snb:          INCOMPLETE (fdo#105411) -> PASS

    igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
      shard-glk:          FAIL (fdo#105363) -> PASS

    
  fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
  fdo#105010 https://bugs.freedesktop.org/show_bug.cgi?id=105010
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900
  fdo#106680 https://bugs.freedesktop.org/show_bug.cgi?id=106680


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4635 -> Patchwork_9896

  CI_DRM_4635: a9f34f7e3bab765e2b1320a1b154a76be38602a7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4589: 779d2d42f9db6a2797d1ef50036af6fac4e62e73 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9896: b3ef168cf378f3302a530145c7f4aa5b9226e7c3 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9896/shards.html
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Re: [PATCH 02/20] drm/i915: Set PCH as NOP when display is disabled

[Jani Nikula]

On Wed, 08 Aug 2018, José Roberto de Souza <jose.souza@intel.com> wrote:
> num_pipes is set to 0 if disable_display is set inside
> intel_device_info_runtime_init() but when that happen PCH will
> already be set in intel_detect_pch().
>
> i915_driver_load()
> 	i915_driver_init_early()
> 		...
> 		intel_detect_pch()
> 		...
> 	...
> 	i915_driver_init_hw()
> 		intel_device_info_runtime_init()
>
> So now setting num_pipes = 0 earlier to avoid this problem.

Okay, this gets confusing. There are other paths in
intel_device_info_runtime_init() that set num_pipes = 0 and depend on
PCH having been detected. :(

>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c          | 5 +++++
>  drivers/gpu/drm/i915/intel_device_info.c | 8 ++------
>  2 files changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 9dce55182c3a..7952f5877402 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -917,6 +917,11 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
>  	if (ret < 0)
>  		goto err_workqueues;
>  
> +	if (i915_modparams.disable_display) {
> +		DRM_INFO("Display disabled (module parameter)\n");
> +		device_info->num_pipes = 0;
> +	}
> +

Please look at the function as a whole, and note that this feels like a
random thing to add in the middle. Needs to be stowed away somewhere
deeper.

Overall, I think we need to be more accurate about the relationship of
num_pipes = 0 and PCH_NOP.


BR,
Jani.

>  	/* This must be called before any calls to HAS_PCH_* */
>  	intel_detect_pch(dev_priv);
>  
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 0ef0c6448d53..67102b481c8f 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -776,12 +776,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>  			info->num_sprites[pipe] = 1;
>  	}
>  
> -	if (i915_modparams.disable_display) {
> -		DRM_INFO("Display disabled (module parameter)\n");
> -		info->num_pipes = 0;
> -	} else if (info->num_pipes > 0 &&
> -		   (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
> -		   HAS_PCH_SPLIT(dev_priv)) {
> +	if (info->num_pipes > 0 && (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
> +	    HAS_PCH_SPLIT(dev_priv)) {
>  		u32 fuse_strap = I915_READ(FUSE_STRAP);
>  		u32 sfuse_strap = I915_READ(SFUSE_STRAP);

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH 01/20] drm: Let userspace check if driver supports modeset

[Chris Wilson]

Quoting José Roberto de Souza (2018-08-09 01:15:47)
> GPU accelerators usually don't have display block or the display
> driver part can be disabled when building driver(for servers it saves
> some resources) so it is important let userspace check this
> capability too.
> 
> Right now we are checking
> drmModeGetResources()/drm_mode_getresources() for a error to detect
> if display is enabled but it is a hackish way as it can fail for
> other reasons too.

Literally there are no other ways to fail. It reports -EINVAL if
!MODESET and the counts otherwise. No allocations, no pointer chasing.
-Chris
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Re: [PATCH 02/20] drm/i915: Set PCH as NOP when display is disabled

[Chris Wilson]

Quoting José Roberto de Souza (2018-08-09 01:15:48)
> num_pipes is set to 0 if disable_display is set inside
> intel_device_info_runtime_init() but when that happen PCH will
> already be set in intel_detect_pch().

One major thing missed is that if you disable the displays via modparam,
you need to reap all the BIOS enabled displays and stolen memory that
conflict with our usage. (We ignore the conflict so that means the BIOS
can write into memory we are using elsewhere.) The same bug exists for
outputs we don't recover from the BIOS, which is a regression from
circa 3.2.
-Chris
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Re: [PATCH 02/20] drm/i915: Set PCH as NOP when display is disabled

[Souza, Jose]

On Thu, 2018-08-09 at 11:16 +0300, Jani Nikula wrote:
> On Wed, 08 Aug 2018, José Roberto de Souza <jose.souza@intel.com>
> wrote:
> > num_pipes is set to 0 if disable_display is set inside
> > intel_device_info_runtime_init() but when that happen PCH will
> > already be set in intel_detect_pch().
> > 
> > i915_driver_load()
> > 	i915_driver_init_early()
> > 		...
> > 		intel_detect_pch()
> > 		...
> > 	...
> > 	i915_driver_init_hw()
> > 		intel_device_info_runtime_init()
> > 
> > So now setting num_pipes = 0 earlier to avoid this problem.
> 
> Okay, this gets confusing. There are other paths in
> intel_device_info_runtime_init() that set num_pipes = 0 and depend on
> PCH having been detected. :(
> 
> > 
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.c          | 5 +++++
> >  drivers/gpu/drm/i915/intel_device_info.c | 8 ++------
> >  2 files changed, 7 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index 9dce55182c3a..7952f5877402 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -917,6 +917,11 @@ static int i915_driver_init_early(struct
> > drm_i915_private *dev_priv,
> >  	if (ret < 0)
> >  		goto err_workqueues;
> >  
> > +	if (i915_modparams.disable_display) {
> > +		DRM_INFO("Display disabled (module parameter)\n");
> > +		device_info->num_pipes = 0;
> > +	}
> > +
> 
> Please look at the function as a whole, and note that this feels like
> a
> random thing to add in the middle. Needs to be stowed away somewhere
> deeper.

I can move it to right after:

/* Setup the write-once "constant" device info */
device_info = mkwrite_device_info(dev_priv);
memcpy(device_info, match_info, sizeof(*device_info));
device_info->device_id = dev_priv->drm.pdev->device;

> 
> Overall, I think we need to be more accurate about the relationship
> of
> num_pipes = 0 and PCH_NOP.

The path in intel_device_info_runtime_init() that now sets num_pipes =
0 is when the display(I guess it is the whole GPU) is fused off so user
can't use it at all.

The other path changing num_pipes is one for IVB there is disables the
last pipe.

I guess with this changes we have a good relationship between num_pipes
and PCH_NOP or do you have another suggestion.

> 
> 
> BR,
> Jani.
> 
> >  	/* This must be called before any calls to HAS_PCH_* */
> >  	intel_detect_pch(dev_priv);
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > b/drivers/gpu/drm/i915/intel_device_info.c
> > index 0ef0c6448d53..67102b481c8f 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -776,12 +776,8 @@ void intel_device_info_runtime_init(struct
> > intel_device_info *info)
> >  			info->num_sprites[pipe] = 1;
> >  	}
> >  
> > -	if (i915_modparams.disable_display) {
> > -		DRM_INFO("Display disabled (module parameter)\n");
> > -		info->num_pipes = 0;
> > -	} else if (info->num_pipes > 0 &&
> > -		   (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
> > -		   HAS_PCH_SPLIT(dev_priv)) {
> > +	if (info->num_pipes > 0 && (IS_GEN7(dev_priv) ||
> > IS_GEN8(dev_priv)) &&
> > +	    HAS_PCH_SPLIT(dev_priv)) {
> >  		u32 fuse_strap = I915_READ(FUSE_STRAP);
> >  		u32 sfuse_strap = I915_READ(SFUSE_STRAP);
> 
> 
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Re: [PATCH 02/20] drm/i915: Set PCH as NOP when display is disabled

[Souza, Jose]

On Thu, 2018-08-09 at 09:36 +0100, Chris Wilson wrote:
> Quoting José Roberto de Souza (2018-08-09 01:15:48)
> > num_pipes is set to 0 if disable_display is set inside
> > intel_device_info_runtime_init() but when that happen PCH will
> > already be set in intel_detect_pch().
> 
> One major thing missed is that if you disable the displays via
> modparam,
> you need to reap all the BIOS enabled displays and stolen memory that
> conflict with our usage. (We ignore the conflict so that means the
> BIOS
> can write into memory we are using elsewhere.) The same bug exists
> for
> outputs we don't recover from the BIOS, which is a regression from
> circa 3.2.

I have a working in progress patch on top of this ones that complete
power down all power wells, fixing this issue but for now you are
right.

> -Chris
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Re: [PATCH 01/20] drm: Let userspace check if driver supports modeset

[Souza, Jose]

Ping series review

On Wed, 2018-08-08 at 17:15 -0700, José Roberto de Souza wrote:
> GPU accelerators usually don't have display block or the display
> driver part can be disabled when building driver(for servers it saves
> some resources) so it is important let userspace check this
> capability too.
> 
> Right now we are checking
> drmModeGetResources()/drm_mode_getresources() for a error to detect
> if display is enabled but it is a hackish way as it can fail for
> other reasons too.
> 
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/drm_ioctl.c | 3 +++
>  include/uapi/drm/drm.h      | 1 +
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_ioctl.c
> b/drivers/gpu/drm/drm_ioctl.c
> index ea10e9a26aad..3a8438ae9b51 100644
> --- a/drivers/gpu/drm/drm_ioctl.c
> +++ b/drivers/gpu/drm/drm_ioctl.c
> @@ -244,6 +244,9 @@ static int drm_getcap(struct drm_device *dev,
> void *data, struct drm_file *file_
>  	case DRM_CAP_SYNCOBJ:
>  		req->value = drm_core_check_feature(dev,
> DRIVER_SYNCOBJ);
>  		return 0;
> +	case DRM_CAP_MODESET:
> +		req->value = drm_core_check_feature(dev,
> DRIVER_MODESET);
> +		return 0;
>  	}
>  
>  	/* Other caps only work with KMS drivers */
> diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
> index 300f336633f2..85fae6ddbf48 100644
> --- a/include/uapi/drm/drm.h
> +++ b/include/uapi/drm/drm.h
> @@ -649,6 +649,7 @@ struct drm_gem_open {
>  #define DRM_CAP_PAGE_FLIP_TARGET	0x11
>  #define DRM_CAP_CRTC_IN_VBLANK_EVENT	0x12
>  #define DRM_CAP_SYNCOBJ		0x13
> +#define DRM_CAP_MODESET		0x14
>  
>  /** DRM_IOCTL_GET_CAP ioctl argument type */
>  struct drm_get_cap {
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