[PATCH 00/14] DSI Command mode(DBI mode) enabling on CHT

[PATCH 00/14] DSI Command mode(DBI mode) enabling on CHT

[Gaurav K Singh]

Hi,

These set of patches are for enabling DSI command mode on CHT. Command Mode refers to
an operation in which transactions primarily take the form of sending commands
and data to a peripheral that incorporates a display controller. The display
controller may include local registers and a frame buffer. The host processor
indirectly controls activity at the peripheral by sending commands, parameters
and data to the display controller.

Sink refreshes from its local frame buffer. Image updates require Source to write
new data into the frame buffer which Source sends in the form of command + payload.

The command mode panel we have here is 1080 x 1920. For this panel, features like support of
i2c transactions for sending backlight on sequence, VBT version 3 patches, GPIO configuration
changes for CHT are required. The same has been floated as part of different patch series.
Floating the command mode enabling patches separately to start with the review. These patches
have been rebased on top of BXT MIPI, BXT dual link changes.

Regards
Gaurav

Gaurav K Singh (14):
  drm/i915: allocate DMA region for mipi dbi cmd buffer
  drm/i915: Add support for TEAR ON Sequence
  drm/i915: Add functions for dcs memory write cmd
  drm/i915: Calculate bw timer for mipi DBI interface
  drm/i915: Use the bpp value wrt the pixel format
  drm/i915: Disable vlank interrupt for disabling MIPI cmd mode
  drm/i915: Disable MIPI display self refresh mode
  drm/i915: Disable Tearing effect trigger by GPIO pin
  drm/i915: Changes for command mode preparation
  drm/i915: Enable Tearing effect trigger by GPIO pin
  drm/i915: Enable MIPI display self refresh mode
  drm/i915: Generalize DSI enable function
  drm/i915: Reset the display hw if vid mode to cmd mode
  drm/i915: send one frame after enabling mipi cmd mode

 drivers/gpu/drm/i915/i915_drv.h            |    1 +
 drivers/gpu/drm/i915/i915_reg.h            |    1 +
 drivers/gpu/drm/i915/intel_bios.h          |    2 +
 drivers/gpu/drm/i915/intel_display.c       |   98 ++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h           |   10 +++
 drivers/gpu/drm/i915/intel_dsi.c           |  121 +++++++++++++++++++++++++---
 drivers/gpu/drm/i915/intel_dsi.h           |    3 +
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   34 +++++++-
 8 files changed, 255 insertions(+), 15 deletions(-)

-- 
1.7.9.5

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[PATCH 01/14] drm/i915: allocate DMA region for mipi dbi cmd buffer

[Gaurav K Singh]

Allocate DMA region for MIPI DBI command buffer. This memory
will be used when sending command via DBI interface.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |   17 +++++++++++++++++
 drivers/gpu/drm/i915/intel_dsi.h |    2 ++
 2 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index d7e2118..6483d7f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -32,6 +32,7 @@
 #include <drm/drm_mipi_dsi.h>
 #include <linux/slab.h>
 #include <linux/gpio/consumer.h>
+#include <linux/dma-mapping.h>
 #include "i915_drv.h"
 #include "intel_drv.h"
 #include "intel_dsi.h"
@@ -468,12 +469,22 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+	dma_addr_t dma_handle;
 	enum pipe pipe = intel_crtc->pipe;
 	enum port port;
 	u32 tmp;
 
 	DRM_DEBUG_KMS("\n");
 
+	if (IS_CHERRYVIEW(dev))
+		intel_dsi->cmd_buff_virt_addr = dma_alloc_coherent(dev, 4096,
+								&dma_handle, GFP_KERNEL);
+		if (!intel_dsi->cmd_buff_virt_addr)
+			return -ENOMEM;
+
+		intel_dsi->dma_handle = dma_handle;
+	}
+
 	/* Panel Enable over CRC PMIC */
 	if (intel_dsi->gpio_panel)
 		gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
@@ -661,6 +672,10 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder)
 	msleep(intel_dsi->panel_off_delay);
 	msleep(intel_dsi->panel_pwr_cycle_delay);
 
+	if (IS_CHERRYVIEW(dev_priv->dev) && intel_dsi->dma_handle)
+		dma_free_coherent(dev, 4096,
+				intel_dsi->cmd_buff_virt_addr, intel_dsi->dma_handle);
+
 	/* Panel Disable over CRC PMIC */
 	if (intel_dsi->gpio_panel)
 		gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
@@ -1198,6 +1213,8 @@ void intel_dsi_init(struct drm_device *dev)
 		intel_encoder->crtc_mask = (1 << PIPE_B);
 		intel_dsi->ports = (1 << PORT_C);
 	}
+	intel_dsi->cmd_buff_virt_addr = NULL;
+	intel_dsi->dma_handle = 0;
 
 	/* Create a DSI host (and a device) for each port. */
 	for_each_dsi_port(port, intel_dsi->ports) {
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index e6cb252..81b321f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -46,6 +46,8 @@ struct intel_dsi {
 	struct gpio_desc *gpio_panel;
 
 	struct intel_connector *attached_connector;
+	void *cmd_buff_virt_addr;
+	dma_addr_t dma_handle;
 
 	/* bit mask of ports being driven */
 	u16 ports;
-- 
1.7.9.5

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[PATCH 02/14] drm/i915: Add support for TEAR ON Sequence

[Gaurav K Singh]

For command mode panel, panel's fb enabling and tearing configuration
is done as part of TEAR ON sequence. This patch parses and executes
TEAR ON sequence for MIPI command mode.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_bios.h          |    2 ++
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    9 ++++++++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index 1b7417e..d7fdb10 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -948,6 +948,8 @@ enum mipi_seq {
 	MIPI_SEQ_DISPLAY_ON,
 	MIPI_SEQ_DISPLAY_OFF,
 	MIPI_SEQ_DEASSERT_RESET,
+	MIPI_SEQ_TEAR_ON,
+	MIPI_SEQ_TEAR_OFF,
 	MIPI_SEQ_MAX
 };
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index feeca59..cacd5b8 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -251,7 +251,9 @@ static const char * const seq_name[] = {
 	"MIPI_SEQ_INIT_OTP",
 	"MIPI_SEQ_DISPLAY_ON",
 	"MIPI_SEQ_DISPLAY_OFF",
-	"MIPI_SEQ_DEASSERT_RESET"
+	"MIPI_SEQ_DEASSERT_RESET",
+	"MIPI_SEQ_TEAR_ON",
+	"MIPI_SEQ_TEAR_OFF"
 };
 
 static void generic_exec_sequence(struct intel_dsi *intel_dsi, const u8 *data)
@@ -320,6 +322,11 @@ static int vbt_panel_prepare(struct drm_panel *panel)
 	sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
 	generic_exec_sequence(intel_dsi, sequence);
 
+	if (intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE) {
+		sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_TEAR_ON];
+		generic_exec_sequence(intel_dsi, sequence);
+	}
+
 	return 0;
 }
 
-- 
1.7.9.5

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[PATCH 03/14] drm/i915: Add functions for dcs memory write cmd

[Gaurav K Singh]

Add functions for DCS memory write command. The mem write
command to send fb data to panel is sent using this function.

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |    1 +
 drivers/gpu/drm/i915/intel_drv.h |    1 +
 drivers/gpu/drm/i915/intel_dsi.c |   41 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4e5c0bb..ccba984 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4334,6 +4334,7 @@ enum skl_disp_power_wells {
 #define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */
 #define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */
 #define   PIPECONF_INTERLACE_MODE_MASK		(7 << 21)
+#define   PIPECONF_MIPI_DSR_ENABLE		(1 << 20)
 #define   PIPECONF_EDP_RR_MODE_SWITCH		(1 << 20)
 #define   PIPECONF_CXSR_DOWNCLOCK	(1<<16)
 #define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	(1 << 14)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index dae3cfd..b3d16ce 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1219,6 +1219,7 @@ void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
 /* intel_dsi.c */
 void intel_dsi_init(struct drm_device *dev);
 
+void intel_dsi_update_panel_fb(struct intel_encoder *encoder);
 
 /* intel_dvo.c */
 void intel_dvo_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 6483d7f..8d018d0 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -33,6 +33,7 @@
 #include <linux/slab.h>
 #include <linux/gpio/consumer.h>
 #include <linux/dma-mapping.h>
+#include <video/mipi_display.h>
 #include "i915_drv.h"
 #include "intel_drv.h"
 #include "intel_dsi.h"
@@ -204,6 +205,38 @@ static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
 	return host;
 }
 
+int dsi_send_dcs_cmd(struct intel_dsi *intel_dsi, int channel, const u8 *data,
+		     int len, bool pipe_render)
+{
+	struct drm_encoder *encoder = &intel_dsi->base.base;
+	struct drm_device *dev = encoder->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	enum port port;
+	u32 cmd_addr;
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (I915_READ(MIPI_COMMAND_ADDRESS(port)) & COMMAND_VALID)
+			return -EBUSY;
+
+		if ((I915_READ(PIPECONF(port)) & PIPECONF_MIPI_DSR_ENABLE) == 0)
+			return -EBUSY;
+
+		if (IS_CHERRYVIEW(dev)) {
+			cmd_addr = intel_dsi->dma_handle &
+							COMMAND_MEM_ADDRESS_MASK;
+			cmd_addr |= COMMAND_VALID;
+
+			if (pipe_render)
+				cmd_addr |= MEMORY_WRITE_DATA_FROM_PIPE_RENDERING;
+		}
+
+		I915_WRITE(MIPI_COMMAND_LENGTH(port), len);
+		I915_WRITE(MIPI_COMMAND_ADDRESS(port), cmd_addr);
+	}
+
+	return 0;
+}
+
 /*
  * send a video mode command
  *
@@ -748,6 +781,14 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
 	pipe_config->port_clock = pclk;
 }
 
+void intel_dsi_update_panel_fb(struct intel_encoder *encoder)
+{
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	unsigned char uc_data[] = {MIPI_DCS_WRITE_MEMORY_START};
+
+	dsi_send_dcs_cmd(intel_dsi, 0, uc_data, sizeof(uc_data), true);
+}
+
 static enum drm_mode_status
 intel_dsi_mode_valid(struct drm_connector *connector,
 		     struct drm_display_mode *mode)
-- 
1.7.9.5

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Re: [PATCH 03/14] drm/i915: Add functions for dcs memory write cmd

[Jani Nikula]

On Wed, 30 Sep 2015, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> Add functions for DCS memory write command. The mem write
> command to send fb data to panel is sent using this function.

All DSI commands should be handled via intel_dsi_host_ops and its
.transfer function, i.e. intel_dsi_host_transfer. See all the mipi_dsi_*
functions in drm_mipi_dsi.h to do all this stuff given a mipi_dsi_device
handle.

If intel_dsi_host_transfer doesn't do what you want, you need to fix
it. But we'll need to use the framework instead of bypassing it. It may
feel silly "because we could just do it directly", but in the long run
we will need to be able to better separate the drivers for the host and
the device. It's not unlike using i2c devices to do i2c over dp aux.

BR,
Jani.


>
> Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |    1 +
>  drivers/gpu/drm/i915/intel_drv.h |    1 +
>  drivers/gpu/drm/i915/intel_dsi.c |   41 ++++++++++++++++++++++++++++++++++++++
>  3 files changed, 43 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4e5c0bb..ccba984 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4334,6 +4334,7 @@ enum skl_disp_power_wells {
>  #define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */
>  #define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */
>  #define   PIPECONF_INTERLACE_MODE_MASK		(7 << 21)
> +#define   PIPECONF_MIPI_DSR_ENABLE		(1 << 20)
>  #define   PIPECONF_EDP_RR_MODE_SWITCH		(1 << 20)
>  #define   PIPECONF_CXSR_DOWNCLOCK	(1<<16)
>  #define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	(1 << 14)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index dae3cfd..b3d16ce 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1219,6 +1219,7 @@ void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
>  /* intel_dsi.c */
>  void intel_dsi_init(struct drm_device *dev);
>  
> +void intel_dsi_update_panel_fb(struct intel_encoder *encoder);
>  
>  /* intel_dvo.c */
>  void intel_dvo_init(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 6483d7f..8d018d0 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -33,6 +33,7 @@
>  #include <linux/slab.h>
>  #include <linux/gpio/consumer.h>
>  #include <linux/dma-mapping.h>
> +#include <video/mipi_display.h>
>  #include "i915_drv.h"
>  #include "intel_drv.h"
>  #include "intel_dsi.h"
> @@ -204,6 +205,38 @@ static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
>  	return host;
>  }
>  
> +int dsi_send_dcs_cmd(struct intel_dsi *intel_dsi, int channel, const u8 *data,
> +		     int len, bool pipe_render)
> +{
> +	struct drm_encoder *encoder = &intel_dsi->base.base;
> +	struct drm_device *dev = encoder->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	enum port port;
> +	u32 cmd_addr;
> +
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (I915_READ(MIPI_COMMAND_ADDRESS(port)) & COMMAND_VALID)
> +			return -EBUSY;
> +
> +		if ((I915_READ(PIPECONF(port)) & PIPECONF_MIPI_DSR_ENABLE) == 0)
> +			return -EBUSY;
> +
> +		if (IS_CHERRYVIEW(dev)) {
> +			cmd_addr = intel_dsi->dma_handle &
> +							COMMAND_MEM_ADDRESS_MASK;
> +			cmd_addr |= COMMAND_VALID;
> +
> +			if (pipe_render)
> +				cmd_addr |= MEMORY_WRITE_DATA_FROM_PIPE_RENDERING;
> +		}
> +
> +		I915_WRITE(MIPI_COMMAND_LENGTH(port), len);
> +		I915_WRITE(MIPI_COMMAND_ADDRESS(port), cmd_addr);
> +	}
> +
> +	return 0;
> +}
> +
>  /*
>   * send a video mode command
>   *
> @@ -748,6 +781,14 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
>  	pipe_config->port_clock = pclk;
>  }
>  
> +void intel_dsi_update_panel_fb(struct intel_encoder *encoder)
> +{
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	unsigned char uc_data[] = {MIPI_DCS_WRITE_MEMORY_START};
> +
> +	dsi_send_dcs_cmd(intel_dsi, 0, uc_data, sizeof(uc_data), true);
> +}
> +
>  static enum drm_mode_status
>  intel_dsi_mode_valid(struct drm_connector *connector,
>  		     struct drm_display_mode *mode)
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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[PATCH 04/14] drm/i915: Calculate bw timer for mipi DBI interface

[Gaurav K Singh]

This patch will calculate the bandwidth timer for MIPI DBI interface.
If the BW timer value is available from VBT, then value from VBT
will be used.

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index cacd5b8..7d9094a 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -56,6 +56,11 @@ static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
 #define CLK_ZERO_CNT_MAX	0xFF
 #define TRAIL_CNT_MAX		0x1F
 
+#define LP_HDR_FOOT_SIZE	6
+#define BW_LP_NUM_OF_PKT	16
+#define BW_LP_LOAD_SIZE		252
+#define EXTRA_ONE_BYTE		1
+
 #define NS_KHZ_RATIO 1000000
 
 #define GPI0_NC_0_HV_DDI0_HPD           0x4130
@@ -443,7 +448,6 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
 	intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
 	intel_dsi->init_count = mipi_config->master_init_timer;
-	intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
 	intel_dsi->video_frmt_cfg_bits =
 		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
 
@@ -601,6 +605,24 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
 						clk_zero_cnt << 8 | prepare_cnt;
 
+	if (mipi_config->dbi_bw_timer) {
+		intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
+	} else {
+		/*
+		 * bw timer should be more than 16 longs packets containing
+		 * 252 bytes + 2 blanking packets.
+		 * bw timer = 16 long packets * (252 bytes payload for each
+		 *            long packet + 6 bytes for long packet header and
+		 *            footer) + 12 bytes for 2 blanking packets + 1
+		 *            byte for having more of the above.
+		 */
+		intel_dsi->bw_timer = DIV_ROUND_UP(BW_LP_NUM_OF_PKT *
+					(BW_LP_LOAD_SIZE + LP_HDR_FOOT_SIZE),
+					intel_dsi->lane_count);
+
+		intel_dsi->bw_timer += (extra_byte_count + EXTRA_ONE_BYTE);
+	}
+
 	/*
 	 * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2
 	 *					+ 10UI + Extra Byte Count
-- 
1.7.9.5

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[PATCH 05/14] drm/i915: Use the bpp value wrt the pixel format

[Gaurav K Singh]

The bpp value which is used while calulating the txbyteclkhs values
should be wrt the pixel format value. Currently bpp is coming
from pipe config to calculate txbyteclkhs.

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c           |    5 ++---
 drivers/gpu/drm/i915/intel_dsi.h           |    1 +
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    1 +
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 8d018d0..41f988c 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -843,10 +843,9 @@ static void set_dsi_timings(struct drm_encoder *encoder,
 {
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 	enum port port;
-	unsigned int bpp = intel_crtc->config->pipe_bpp;
+	unsigned int bpp = intel_dsi->dsi_bpp;
 	unsigned int lane_count = intel_dsi->lane_count;
 
 	u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
@@ -918,7 +917,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 	struct drm_display_mode *adjusted_mode =
 		&intel_crtc->config->base.adjusted_mode;
 	enum port port;
-	unsigned int bpp = intel_crtc->config->pipe_bpp;
+	unsigned int bpp = intel_dsi->dsi_bpp;
 	u32 val, tmp;
 	u16 mode_hdisplay;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 81b321f..31dc216 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -66,6 +66,7 @@ struct intel_dsi {
 
 	/* video mode pixel format for MIPI_DSI_FUNC_PRG register */
 	u32 pixel_format;
+	u32 dsi_bpp;
 
 	/* video mode format for MIPI_VIDEO_MODE_FORMAT register */
 	u32 video_mode_format;
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 7d9094a..2abe9e8 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -450,6 +450,7 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	intel_dsi->init_count = mipi_config->master_init_timer;
 	intel_dsi->video_frmt_cfg_bits =
 		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
+	intel_dsi->dsi_bpp = bits_per_pixel;
 
 	pclk = mode->clock;
 
-- 
1.7.9.5

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[PATCH 06/14] drm/i915: Disable vlank interrupt for disabling MIPI

[Gaurav K Singh]

vblank interrupt should be disabled before starting the disable
sequence for MIPI command mode. Otherwise when pipe is disabled
TE interurpt will be still handled and one memory write command
will be sent with pipe disabled. This makes the pipe hw to get
stuck and it doesn't recover in the next enable sequence causing
display blank out.

v2: Use drm_blank_off instead of platform specific disable vblank functions (Daniel)

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |   15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 41f988c..d2b5d49 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -568,13 +568,28 @@ static void intel_dsi_enable_nop(struct intel_encoder *encoder)
 
 static void intel_dsi_pre_disable(struct intel_encoder *encoder)
 {
+	struct drm_device *dev = encoder->base.dev;
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+	int pipe = intel_crtc->pipe;
+
 	enum port port;
 
 	DRM_DEBUG_KMS("\n");
 
 	intel_panel_disable_backlight(intel_dsi->attached_connector);
 
+	if (is_cmd_mode(intel_dsi)) {
+		drm_vblank_off(dev, pipe);
+
+		/*
+		 * Make sure that the last frame is sent otherwise pipe can get
+		 * stuck. Currently providing delay time for ~2 vblanks
+		 * assuming 60fps.
+		 */
+		mdelay(40);
+	}
+
 	if (is_vid_mode(intel_dsi)) {
 		/* Send Shutdown command to the panel in LP mode */
 		for_each_dsi_port(port, intel_dsi->ports)
-- 
1.7.9.5

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[PATCH 07/14] drm/i915: Disable MIPI display self refresh mode

[Gaurav K Singh]

During disable sequence for MIPI encoder in command mode, disable
MIPI display self-refresh mode bit in Pipe Ctrl reg.

v2: Use crtc state flag instead of loop over encoders (Daniel)

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    3 +++
 drivers/gpu/drm/i915/intel_drv.h     |    3 +++
 drivers/gpu/drm/i915/intel_dsi.c     |    3 +++
 3 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0285af9..c2a5cdf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2159,6 +2159,9 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
 	if ((val & PIPECONF_ENABLE) == 0)
 		return;
 
+	if (crtc->config->dsi_self_refresh)
+		val = val & ~PIPECONF_MIPI_DSR_ENABLE;
+
 	/*
 	 * Double wide has implications for planes
 	 * so best keep it disabled when not needed.
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b3d16ce..58fcd7d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -452,6 +452,9 @@ struct intel_crtc_state {
 	bool double_wide;
 
 	bool dp_encoder_is_mst;
+
+	bool dsi_self_refresh;
+
 	int pbn;
 
 	struct intel_crtc_scaler_state scaler_state;
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index d2b5d49..d812e07 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -307,6 +307,9 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 
 	DRM_DEBUG_KMS("\n");
 
+	if (is_cmd_mode(intel_dsi))
+		config->dsi_self_refresh = true;
+
 	if (fixed_mode)
 		intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 
-- 
1.7.9.5

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[PATCH 08/14] drm/i915: Disable Tearing effect trigger by GPIO pin

[Gaurav K Singh]

While disabling MIPI Port in command mode, disable TE trigger by GPIO pin.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |    8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index d812e07..4a5905e 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -463,8 +463,12 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
 		/* de-assert ip_tg_enable signal */
 		port_ctrl = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
 						MIPI_PORT_CTRL(port);
-		temp = I915_READ(port_ctrl);
-		I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
+		if (is_cmd_mode(intel_dsi)) {
+			I915_WRITE(port_ctrl, 0);
+		} else {
+			temp = I915_READ(port_ctrl);
+			I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
+		}
 		POSTING_READ(port_ctrl);
 	}
 }
-- 
1.7.9.5

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[PATCH 09/14] drm/i915: Changes for command mode preparation

[Gaurav K Singh]

Changes done in preparation of command mode-

1. Set DBI HS LS Switch bit for DBI packets to be tramitted in HS mode.
2. Set DBI FIFO watermark.
3. Timing regs need not be programmmed for command mode.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |   13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 4a5905e..70c4e56 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -999,12 +999,16 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 			mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
 	}
 
-	set_dsi_timings(encoder, adjusted_mode);
+	if (is_vid_mode(intel_dsi))
+		set_dsi_timings(encoder, adjusted_mode);
 
 	val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
 	if (is_cmd_mode(intel_dsi)) {
 		val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
-		val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
+		val |= CMD_MODE_DATA_WIDTH_OPTION2;
+		I915_WRITE(MIPI_DBI_FIFO_THROTTLE(port),
+			   DBI_FIFO_EMPTY_QUARTER);
+		I915_WRITE(MIPI_HS_LP_DBI_ENABLE(port), 0);
 	} else {
 		val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
 
@@ -1117,6 +1121,11 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 				intel_dsi->video_mode_format |
 				IP_TG_CONFIG |
 				RANDOM_DPI_DISPLAY_RESOLUTION);
+		else
+			I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
+				   intel_dsi->video_frmt_cfg_bits |
+				   IP_TG_CONFIG |
+				   RANDOM_DPI_DISPLAY_RESOLUTION);
 	}
 }
 
-- 
1.7.9.5

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[PATCH 10/14] drm/i915: Enable Tearing effect trigger by GPIO pin

[Gaurav K Singh]

While enabling MIPI Port in command mode, enable tearing effect
by GPIO pin.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 70c4e56..0f1bec4 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -445,7 +445,10 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
 				temp |= LANE_CONFIGURATION_DUAL_LINK_ENABLE;
 		}
 		/* assert ip_tg_enable signal */
-		I915_WRITE(port_ctrl, temp | DPI_ENABLE);
+		if (is_cmd_mode(intel_dsi))
+			I915_WRITE(port_ctrl, temp | TEARING_EFFECT_GPIO);
+		else
+			I915_WRITE(port_ctrl, temp | DPI_ENABLE);
 		POSTING_READ(port_ctrl);
 	}
 }
-- 
1.7.9.5

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[PATCH 11/14] drm/i915: Enable MIPI display self refresh mode

[Gaurav K Singh]

During enable sequence for MIPI encoder in command mode, enable
MIPI display self-refresh mode bit in Pipe Ctrl reg.

v2: Use crtc state flag instead of loop over encoders (Daniel)

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c2a5cdf..0a6676f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2122,6 +2122,11 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
 		return;
 	}
 
+	if (crtc->config->dsi_self_refresh) {
+		val = val | PIPECONF_MIPI_DSR_ENABLE;
+		I915_WRITE(reg, val);
+	}
+
 	I915_WRITE(reg, val | PIPECONF_ENABLE);
 	POSTING_READ(reg);
 }
-- 
1.7.9.5

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[PATCH 12/14] drm/i915: Generalize DSI enable function

[Gaurav K Singh]

For command mode and video mode, panel prepare, wait for FIFO
checks are required. Making these changes generic across command
mode and video mode.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |   10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 0f1bec4..2279859 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -494,14 +494,14 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
 		for_each_dsi_port(port, intel_dsi->ports)
 			dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 		msleep(100);
+	}
 
-		drm_panel_enable(intel_dsi->panel);
+	drm_panel_enable(intel_dsi->panel);
 
-		for_each_dsi_port(port, intel_dsi->ports)
-			wait_for_dsi_fifo_empty(intel_dsi, port);
+	for_each_dsi_port(port, intel_dsi->ports)
+		wait_for_dsi_fifo_empty(intel_dsi, port);
 
-		intel_dsi_port_enable(encoder);
-	}
+	intel_dsi_port_enable(encoder);
 
 	intel_panel_enable_backlight(intel_dsi->attached_connector);
 }
-- 
1.7.9.5

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[PATCH 13/14] drm/i915: Reset the display hw if vid mode to cmd mode

[Gaurav K Singh]

Reset the display hardware if video mode to command mode transition
has to be done in MIPI display. otherwise command mode will not work.

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |    1 +
 drivers/gpu/drm/i915/intel_display.c |   43 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dsi.c     |    4 ++++
 3 files changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3d1700f..7538197 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1954,6 +1954,7 @@ struct drm_i915_private {
 	} gt;
 
 	bool edp_low_vswing;
+	bool video_disabled;
 
 	/*
 	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0a6676f..5911a333 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6149,6 +6149,8 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
+	bool all_pipe_disabled;
+	u32 val;
 
 	/*
 	 * On gen2 planes are double buffered but the pipe isn't, so we must
@@ -15444,6 +15446,47 @@ void intel_modeset_cleanup(struct drm_device *dev)
 	mutex_lock(&dev->struct_mutex);
 	intel_cleanup_gt_powersave(dev);
 	mutex_unlock(&dev->struct_mutex);
+
+	all_pipe_disabled = true;
+	for_each_pipe(dev_priv, pipe) {
+		if ((I915_READ(PIPECONF(pipe)) &
+				PIPECONF_ENABLE) == PIPECONF_ENABLE)
+			all_pipe_disabled = false;
+	}
+
+	if ((all_pipe_disabled == true) &&
+				(dev_priv->video_disabled == true)) {
+
+		/*
+		 * to switch from video mode to command mode, need to reset
+		 * the display.
+		 * FIXME: Even after resetting the display, the first modeset
+		 * works sporadically(2 out of 3 times). Need to fix this.
+		 * FIXME: Need to find a better way of doing this, because
+		 * resetting the display resets all the registers in the
+		 * display controller. Need to save and restore some of these
+		 * required registers.
+		 */
+		DRM_DEBUG_KMS("vid mode to cmd mode, reset display\n");
+		if (IS_CHERRYVIEW(dev)) {
+			val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
+			val = val | DP_SSC_PWR_GATE(0);
+			vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
+
+			/* delay to power gate display controller */
+			mdelay(5);
+
+			val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
+			val = val & ~((u32)DP_SSC_MASK(0));
+			vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
+
+			/* delay to power on display controller */
+			mdelay(10);
+		} else
+			DRM_ERROR("vid mode to cmd mode reset is not done.\n");
+
+		i915_disable_vga(dev_priv->dev);
+	}
 }
 
 /*
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 2279859..da8526c 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -462,11 +462,15 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
 	u32 temp;
 	u32 port_ctrl;
 
+	dev_priv->video_disabled = false;
+
 	for_each_dsi_port(port, intel_dsi->ports) {
 		/* de-assert ip_tg_enable signal */
 		port_ctrl = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
 						MIPI_PORT_CTRL(port);
 		if (is_cmd_mode(intel_dsi)) {
+			if (I915_READ(MIPI_PORT_CTRL(port)) & DPI_ENABLE)
+				dev_priv->video_disabled = true;
 			I915_WRITE(port_ctrl, 0);
 		} else {
 			temp = I915_READ(port_ctrl);
-- 
1.7.9.5

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[PATCH 14/14] drm/i915: send one frame after enabling mipi cmd mode

[Gaurav K Singh]

If MIPI is operated in command mode, and after display reset. if
not even one frame is sent after enabling the pipe and then if it
is disabled, pipe is getting stuck. This patch will fix this issue
by sending one frame after enabling the pipe.

Ideally,there should not be a case where there is mode set and no frames
are sent.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   47 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h     |    6 +++++
 2 files changed, 53 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5911a333..37757bb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -44,6 +44,7 @@
 #include <drm/drm_plane_helper.h>
 #include <drm/drm_rect.h>
 #include <linux/dma_remapping.h>
+#include "intel_dsi.h"
 
 /* Primary plane formats for gen <= 3 */
 static const uint32_t i8xx_primary_formats[] = {
@@ -6016,6 +6017,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
+	struct intel_dsi *intel_dsi;
 	int pipe = intel_crtc->pipe;
 	bool is_dsi;
 
@@ -6071,6 +6073,25 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		encoder->enable(encoder);
+
+	for_each_encoder_on_crtc(dev, crtc, encoder) {
+		if (encoder->type != INTEL_OUTPUT_DSI)
+			continue;
+
+		intel_dsi = enc_to_intel_dsi(&encoder->base);
+		if (intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE) {
+			/*
+			 * save the current pipe counter. During disable use
+			 * this variable to check if at least one frame has
+			 * been sent. If no frame is sent and MIPI is disabled
+			 * in command mode, then pipe gets stuck.
+			 */
+			intel_crtc->hw_frm_cnt_at_enable =
+						I915_READ(PIPEFRAME(pipe));
+		}
+		break;
+	}
+
 }
 
 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
@@ -6148,10 +6169,36 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
+	struct intel_dsi *intel_dsi;
 	int pipe = intel_crtc->pipe;
 	bool all_pipe_disabled;
 	u32 val;
 
+	for_each_encoder_on_crtc(dev, crtc, encoder) {
+		if (encoder->type != INTEL_OUTPUT_DSI)
+			continue;
+
+		intel_dsi = enc_to_intel_dsi(&encoder->base);
+		if ((intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE) &&
+				(intel_crtc->hw_frm_cnt_at_enable ==
+						I915_READ(PIPEFRAME(pipe)))) {
+
+			intel_dsi_update_panel_fb(encoder);
+
+			/*
+			 * wait for ~2 frames for TE interrupt and sending one
+			 * frame.
+			 */
+			msleep(40);
+
+			if (intel_crtc->hw_frm_cnt_at_enable ==
+						I915_READ(PIPEFRAME(pipe)))
+				DRM_ERROR("Pipe is stuck for DSI cmd mode.");
+		}
+
+		break;
+	}
+
 	/*
 	 * On gen2 planes are double buffered but the pipe isn't, so we must
 	 * wait for planes to fully turn off before disabling the pipe.
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 58fcd7d..9013f93 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -576,6 +576,12 @@ struct intel_crtc {
 	/* scalers available on this crtc */
 	int num_scalers;
 
+	/*
+	 * save the frame counter at enable sequence to make sure one frame has
+	 * been sent before disable sequence.
+	 */
+	u32 hw_frm_cnt_at_enable;
+
 	struct vlv_wm_state wm_state;
 };
 
-- 
1.7.9.5

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