From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/6] drm/i915/vga: Extract intel_vga_regs.h
Date: Thu, 17 Apr 2025 15:52:36 +0300 [thread overview]
Message-ID: <87ldrzne5n.fsf@intel.com> (raw)
In-Reply-To: <20250417114454.12836-4-ville.syrjala@linux.intel.com>
On Thu, 17 Apr 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract the VGACNTR register definitions into their own
> header file, to declutter i915_reg.h a bit.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vga.c | 1 +
> drivers/gpu/drm/i915/display/intel_vga_regs.h | 38 +++++++++++++++++++
> drivers/gpu/drm/i915/gvt/handlers.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 30 ---------------
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
> 5 files changed, 41 insertions(+), 30 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_vga_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c
> index 684b5d1bc87c..56047f701798 100644
> --- a/drivers/gpu/drm/i915/display/intel_vga.c
> +++ b/drivers/gpu/drm/i915/display/intel_vga.c
> @@ -13,6 +13,7 @@
> #include "i915_reg.h"
> #include "intel_de.h"
> #include "intel_vga.h"
> +#include "intel_vga_regs.h"
>
> static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_vga_regs.h b/drivers/gpu/drm/i915/display/intel_vga_regs.h
> new file mode 100644
> index 000000000000..031da94cab79
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_vga_regs.h
> @@ -0,0 +1,38 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __INTEL_VGA_REGS_H__
> +#define __INTEL_VGA_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +#define VGACNTRL _MMIO(0x71400)
> +#define VGA_DISP_DISABLE REG_BIT(31)
> +#define VGA_2X_MODE REG_BIT(30) /* pre-ilk */
> +#define VGA_PIPE_SEL_MASK REG_BIT(29) /* pre-ivb */
> +#define VGA_PIPE_SEL(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK, (pipe))
> +#define VGA_PIPE_SEL_MASK_CHV REG_GENMASK(29, 28) /* chv */
> +#define VGA_PIPE_SEL_CHV(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK_CHV, (pipe))
> +#define VGA_BORDER_ENABLE REG_BIT(26)
> +#define VGA_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
> +#define VGA_CENTERING_ENABLE_MASK REG_GENMASK(25, 24) /* pre-ilk */
> +#define VGA_PALETTE_READ_SEL REG_BIT(23) /* pre-ivb */
> +#define VGA_PALETTE_A_WRITE_DISABLE REG_BIT(22) /* pre-ivb */
> +#define VGA_PALETTE_B_WRITE_DISABLE REG_BIT(21) /* pre-ivb */
> +#define VGA_LEGACY_8BIT_PALETTE_ENABLE REG_BIT(20)
> +#define VGA_PALETTE_BYPASS REG_BIT(19)
> +#define VGA_NINE_DOT_DISABLE REG_BIT(18)
> +#define VGA_PALETTE_READ_SEL_HI_CHV REG_BIT(15) /* chv */
> +#define VGA_PALETTE_C_WRITE_DISABLE_CHV REG_BIT(14) /* chv */
> +#define VGA_ACTIVE_THROTTLING_MASK REG_GENMASK(15, 12) /* ilk+ */
> +#define VGA_BLANK_THROTTLING_MASK REG_GENMASK(11, 8) /* ilk+ */
> +#define VGA_BLINK_DUTY_CYCLE_MASK REG_GENMASK(7, 6)
> +#define VGA_VSYNC_BLINK_RATE_MASK REG_GENMASK(5, 0)
> +
> +#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
> +
> +#define CPU_VGACNTRL _MMIO(0x41000)
I guess the register offset definitions could be together above the
contents, but no big deal.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> +
> +#endif /* __INTEL_VGA_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index e6e9010462e3..1344e6d20a34 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -56,6 +56,7 @@
> #include "display/intel_pps_regs.h"
> #include "display/intel_psr_regs.h"
> #include "display/intel_sprite_regs.h"
> +#include "display/intel_vga_regs.h"
> #include "display/skl_universal_plane_regs.h"
> #include "display/skl_watermark_regs.h"
> #include "display/vlv_dsi_pll_regs.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a533889c2793..38fd44cff5e8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1812,36 +1812,6 @@
> #define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
> #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
>
> -/* VBIOS regs */
> -#define VGACNTRL _MMIO(0x71400)
> -#define VGA_DISP_DISABLE REG_BIT(31)
> -#define VGA_2X_MODE REG_BIT(30) /* pre-ilk */
> -#define VGA_PIPE_SEL_MASK REG_BIT(29) /* pre-ivb */
> -#define VGA_PIPE_SEL(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK, (pipe))
> -#define VGA_PIPE_SEL_MASK_CHV REG_GENMASK(29, 28) /* chv */
> -#define VGA_PIPE_SEL_CHV(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK_CHV, (pipe))
> -#define VGA_BORDER_ENABLE REG_BIT(26)
> -#define VGA_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
> -#define VGA_CENTERING_ENABLE_MASK REG_GENMASK(25, 24) /* pre-ilk */
> -#define VGA_PALETTE_READ_SEL REG_BIT(23) /* pre-ivb */
> -#define VGA_PALETTE_A_WRITE_DISABLE REG_BIT(22) /* pre-ivb */
> -#define VGA_PALETTE_B_WRITE_DISABLE REG_BIT(21) /* pre-ivb */
> -#define VGA_LEGACY_8BIT_PALETTE_ENABLE REG_BIT(20)
> -#define VGA_PALETTE_BYPASS REG_BIT(19)
> -#define VGA_NINE_DOT_DISABLE REG_BIT(18)
> -#define VGA_PALETTE_READ_SEL_HI_CHV REG_BIT(15) /* chv */
> -#define VGA_PALETTE_C_WRITE_DISABLE_CHV REG_BIT(14) /* chv */
> -#define VGA_ACTIVE_THROTTLING_MASK REG_GENMASK(15, 12) /* ilk+ */
> -#define VGA_BLANK_THROTTLING_MASK REG_GENMASK(11, 8) /* ilk+ */
> -#define VGA_BLINK_DUTY_CYCLE_MASK REG_GENMASK(7, 6)
> -#define VGA_VSYNC_BLINK_RATE_MASK REG_GENMASK(5, 0)
> -
> -#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
> -
> -/* Ironlake */
> -
> -#define CPU_VGACNTRL _MMIO(0x41000)
> -
> #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
> #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
> #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 76d84cbb8361..d581a9d2c063 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -21,6 +21,7 @@
> #include "display/intel_pfit_regs.h"
> #include "display/intel_psr_regs.h"
> #include "display/intel_sprite_regs.h"
> +#include "display/intel_vga_regs.h"
> #include "display/skl_universal_plane_regs.h"
> #include "display/skl_watermark_regs.h"
> #include "display/vlv_dsi_pll_regs.h"
--
Jani Nikula, Intel
next prev parent reply other threads:[~2025-04-17 12:52 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-17 11:44 [PATCH 0/6] drm/i915/vga: Clean up VGA plane handling Ville Syrjala
2025-04-17 11:44 ` [PATCH 1/6] drm/i915/vga: Clean up VGACNTRL bits Ville Syrjala
2025-04-17 12:45 ` Jani Nikula
2025-04-17 11:44 ` [PATCH 2/6] drm/i915/vga: Add more " Ville Syrjala
2025-04-17 12:50 ` Jani Nikula
2025-04-17 11:44 ` [PATCH 3/6] drm/i915/vga: Extract intel_vga_regs.h Ville Syrjala
2025-04-17 12:52 ` Jani Nikula [this message]
2025-04-17 11:44 ` [PATCH 4/6] drm/i915/vga: Include the current pipe in the VGA disable debug message Ville Syrjala
2025-04-17 12:53 ` Jani Nikula
2025-04-17 11:44 ` [PATCH 5/6] drm/i915/vga: Nuke vga_redisable_power_on() Ville Syrjala
2025-04-17 13:05 ` Jani Nikula
2025-04-17 11:44 ` [PATCH 6/6] drm/i915/vga: Consolidate intel_vga_disable() calls Ville Syrjala
2025-04-17 13:32 ` Jani Nikula
2025-04-17 12:41 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/vga: Clean up VGA plane handling Patchwork
2025-04-17 12:41 ` ✗ Fi.CI.SPARSE: " Patchwork
2025-04-17 13:11 ` ✓ i915.CI.BAT: success " Patchwork
2025-04-18 0:14 ` ✗ i915.CI.Full: failure " Patchwork
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