* [Intel-gfx] [PATCH v4 01/30] drm/i915/dp_mst: Fix race between connector registration and setup
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-31 9:23 ` Lisovskiy, Stanislav
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 02/30] drm/dp_mst: Fix fractional DSC bpp handling Imre Deak
` (38 subsequent siblings)
39 siblings, 1 reply; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
After drm_connector_init() is called the connector is visible to the
rest of the kernel via the drm_mode_config::connector_list. Make
sure that the DSC AUX device and capabilities are setup by that time.
Another race condition is adding the connector to the connector list
before drm_connector_helper_add() sets the connector helper functions.
That's an unrelated issue, for which the fix is for a follow-up. One
solution would be adding the connector to the connector list only
during its registration in drm_connector_register().
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fixes: 808b43fa7e56 ("drm/i915/dp_mst: Set connector DSC capabilities and decompression AUX")
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 7b4628f4f1240..851b312bd8449 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1161,6 +1161,14 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
intel_connector->port = port;
drm_dp_mst_get_port_malloc(port);
+ /*
+ * TODO: set the AUX for the actual MST port decompressing the stream.
+ * At the moment the driver only supports enabling this globally in the
+ * first downstream MST branch, via intel_dp's (root port) AUX.
+ */
+ intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
+ intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);
+
connector = &intel_connector->base;
ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs,
DRM_MODE_CONNECTOR_DisplayPort);
@@ -1172,14 +1180,6 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs);
- /*
- * TODO: set the AUX for the actual MST port decompressing the stream.
- * At the moment the driver only supports enabling this globally in the
- * first downstream MST branch, via intel_dp's (root port) AUX.
- */
- intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
- intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);
-
for_each_pipe(dev_priv, pipe) {
struct drm_encoder *enc =
&intel_dp->mst_encoders[pipe]->base.base;
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v4 01/30] drm/i915/dp_mst: Fix race between connector registration and setup
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 01/30] drm/i915/dp_mst: Fix race between connector registration and setup Imre Deak
@ 2023-10-31 9:23 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 94+ messages in thread
From: Lisovskiy, Stanislav @ 2023-10-31 9:23 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Mon, Oct 30, 2023 at 05:58:14PM +0200, Imre Deak wrote:
> After drm_connector_init() is called the connector is visible to the
> rest of the kernel via the drm_mode_config::connector_list. Make
> sure that the DSC AUX device and capabilities are setup by that time.
>
> Another race condition is adding the connector to the connector list
> before drm_connector_helper_add() sets the connector helper functions.
> That's an unrelated issue, for which the fix is for a follow-up. One
> solution would be adding the connector to the connector list only
> during its registration in drm_connector_register().
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Fixes: 808b43fa7e56 ("drm/i915/dp_mst: Set connector DSC capabilities and decompression AUX")
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 7b4628f4f1240..851b312bd8449 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -1161,6 +1161,14 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
> intel_connector->port = port;
> drm_dp_mst_get_port_malloc(port);
>
> + /*
> + * TODO: set the AUX for the actual MST port decompressing the stream.
> + * At the moment the driver only supports enabling this globally in the
> + * first downstream MST branch, via intel_dp's (root port) AUX.
> + */
> + intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
> + intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);
> +
> connector = &intel_connector->base;
> ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs,
> DRM_MODE_CONNECTOR_DisplayPort);
> @@ -1172,14 +1180,6 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
>
> drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs);
>
> - /*
> - * TODO: set the AUX for the actual MST port decompressing the stream.
> - * At the moment the driver only supports enabling this globally in the
> - * first downstream MST branch, via intel_dp's (root port) AUX.
> - */
> - intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
> - intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);
> -
> for_each_pipe(dev_priv, pipe) {
> struct drm_encoder *enc =
> &intel_dp->mst_encoders[pipe]->base.base;
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 94+ messages in thread
* [Intel-gfx] [PATCH v4 02/30] drm/dp_mst: Fix fractional DSC bpp handling
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 01/30] drm/i915/dp_mst: Fix race between connector registration and setup Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-31 19:52 ` Imre Deak
` (2 more replies)
2023-10-30 15:58 ` Imre Deak
` (37 subsequent siblings)
39 siblings, 3 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
Cc: David Francis, Manasi Navare, Alex Deucher, Mikita Lipski,
Harry Wentland
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The current code does '(bpp << 4) / 16' in the MST PBN
calculation, but that is just the same as 'bpp' so the
DSC codepath achieves absolutely nothing. Fix it up so that
the fractional part of the bpp value is actually used instead
of truncated away. 64*1006 has enough zero lsbs that we can
just shift that down in the dividend and thus still manage
to stick to a 32bit divisor.
And while touching this, let's just make the whole thing more
straightforward by making the passed in bpp value .4 binary
fixed point always, instead of having to pass in different
things based on whether DSC is enabled or not.
v2:
- Fix DSC kunit test cases.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Lyude Paul <lyude@redhat.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: David Francis <David.Francis@amd.com>
Cc: Mikita Lipski <mikita.lipski@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Fixes: dc48529fb14e ("drm/dp_mst: Add PBN calculation for DSC modes")
Reviewed-by: Lyude Paul <lyude@redhat.com> (v1)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[Imre: Fix kunit test cases]
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
drivers/gpu/drm/display/drm_dp_mst_topology.c | 20 +++++--------------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 3 +--
.../gpu/drm/tests/drm_dp_mst_helper_test.c | 6 +++---
include/drm/display/drm_dp_mst_helper.h | 2 +-
7 files changed, 14 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 9a712791f309f..ada3773869ff0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6918,7 +6918,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
max_bpc);
bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
clock = adjusted_mode->clock;
- dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
+ dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4);
}
dm_new_connector_state->vcpi_slots =
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index d3b13d362edac..9a58e1a4c5f49 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1642,7 +1642,7 @@ enum dc_status dm_dp_mst_is_port_support_mode(
} else {
/* check if mode could be supported within full_pbn */
bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
- pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
+ pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp << 4);
if (pbn > aconnector->mst_output_port->full_pbn)
return DC_FAIL_BANDWIDTH_VALIDATE;
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 0e0d0e76de065..772b00ebd57bd 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -4718,13 +4718,12 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
/**
* drm_dp_calc_pbn_mode() - Calculate the PBN for a mode.
- * @clock: dot clock for the mode
- * @bpp: bpp for the mode.
- * @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel
+ * @clock: dot clock
+ * @bpp: bpp as .4 binary fixed point
*
* This uses the formula in the spec to calculate the PBN value for a mode.
*/
-int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
+int drm_dp_calc_pbn_mode(int clock, int bpp)
{
/*
* margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
@@ -4735,18 +4734,9 @@ int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
* peak_kbps *= (1006/1000)
* peak_kbps *= (64/54)
* peak_kbps *= 8 convert to bytes
- *
- * If the bpp is in units of 1/16, further divide by 16. Put this
- * factor in the numerator rather than the denominator to avoid
- * integer overflow
*/
-
- if (dsc)
- return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006),
- 8 * 54 * 1000 * 1000);
-
- return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
- 8 * 54 * 1000 * 1000);
+ return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
+ 1000 * 8 * 54 * 1000);
}
EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 851b312bd8449..5bf45a2a85b0e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -106,8 +106,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
continue;
crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
- dsc ? bpp << 4 : bpp,
- dsc);
+ bpp << 4);
slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
connector->port,
@@ -975,7 +974,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
return ret;
if (mode_rate > max_rate || mode->clock > max_dotclk ||
- drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) {
+ drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
*status = MODE_CLOCK_HIGH;
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index d2be40337b92e..153717e1df1a2 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -982,8 +982,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
const int clock = crtc_state->adjusted_mode.clock;
asyh->or.bpc = connector->display_info.bpc;
- asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
- false);
+ asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3 << 4);
}
mst_state = drm_atomic_get_mst_topology_state(state, &mstm->mgr);
diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
index 545beea33e8c7..e3c818dfc0e6d 100644
--- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
+++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
@@ -42,13 +42,13 @@ static const struct drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases
.clock = 332880,
.bpp = 24,
.dsc = true,
- .expected = 50
+ .expected = 1191
},
{
.clock = 324540,
.bpp = 24,
.dsc = true,
- .expected = 49
+ .expected = 1161
},
};
@@ -56,7 +56,7 @@ static void drm_test_dp_mst_calc_pbn_mode(struct kunit *test)
{
const struct drm_dp_mst_calc_pbn_mode_test *params = test->param_value;
- KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp, params->dsc),
+ KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp << 4),
params->expected);
}
diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
index 4429d3b1745b6..655862b3d2a49 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -842,7 +842,7 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector,
int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
int link_rate, int link_lane_count);
-int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
+int drm_dp_calc_pbn_mode(int clock, int bpp);
void drm_dp_mst_update_slots(struct drm_dp_mst_topology_state *mst_state, uint8_t link_encoding_cap);
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v4 02/30] drm/dp_mst: Fix fractional DSC bpp handling
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 02/30] drm/dp_mst: Fix fractional DSC bpp handling Imre Deak
@ 2023-10-31 19:52 ` Imre Deak
2023-11-01 12:59 ` Jani Nikula
2023-11-07 22:45 ` Lyude Paul
2023-11-08 14:40 ` Harry Wentland
2 siblings, 1 reply; 94+ messages in thread
From: Imre Deak @ 2023-10-31 19:52 UTC (permalink / raw)
To: Lyude Paul, Wayne Lin, Alex Deucher, Harry Wentland
Cc: Jani Nikula, Daniel Vetter, intel-gfx, Dave Airlie, Mikita Lipski,
David Francis
On Mon, Oct 30, 2023 at 05:58:15PM +0200, Imre Deak wrote:
Hi Lyude, AMD folks et al,
could you ack patches 2-9 in this patchset if they are ok and it's ok to
merge them via the i915 tree?
Thanks,
Imre
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The current code does '(bpp << 4) / 16' in the MST PBN
> calculation, but that is just the same as 'bpp' so the
> DSC codepath achieves absolutely nothing. Fix it up so that
> the fractional part of the bpp value is actually used instead
> of truncated away. 64*1006 has enough zero lsbs that we can
> just shift that down in the dividend and thus still manage
> to stick to a 32bit divisor.
>
> And while touching this, let's just make the whole thing more
> straightforward by making the passed in bpp value .4 binary
> fixed point always, instead of having to pass in different
> things based on whether DSC is enabled or not.
>
> v2:
> - Fix DSC kunit test cases.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: David Francis <David.Francis@amd.com>
> Cc: Mikita Lipski <mikita.lipski@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Fixes: dc48529fb14e ("drm/dp_mst: Add PBN calculation for DSC modes")
> Reviewed-by: Lyude Paul <lyude@redhat.com> (v1)
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> [Imre: Fix kunit test cases]
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
> drivers/gpu/drm/display/drm_dp_mst_topology.c | 20 +++++--------------
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++---
> drivers/gpu/drm/nouveau/dispnv50/disp.c | 3 +--
> .../gpu/drm/tests/drm_dp_mst_helper_test.c | 6 +++---
> include/drm/display/drm_dp_mst_helper.h | 2 +-
> 7 files changed, 14 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 9a712791f309f..ada3773869ff0 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -6918,7 +6918,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
> max_bpc);
> bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
> clock = adjusted_mode->clock;
> - dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
> + dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4);
> }
>
> dm_new_connector_state->vcpi_slots =
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> index d3b13d362edac..9a58e1a4c5f49 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> @@ -1642,7 +1642,7 @@ enum dc_status dm_dp_mst_is_port_support_mode(
> } else {
> /* check if mode could be supported within full_pbn */
> bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
> - pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
> + pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp << 4);
>
> if (pbn > aconnector->mst_output_port->full_pbn)
> return DC_FAIL_BANDWIDTH_VALIDATE;
> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> index 0e0d0e76de065..772b00ebd57bd 100644
> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> @@ -4718,13 +4718,12 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
>
> /**
> * drm_dp_calc_pbn_mode() - Calculate the PBN for a mode.
> - * @clock: dot clock for the mode
> - * @bpp: bpp for the mode.
> - * @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel
> + * @clock: dot clock
> + * @bpp: bpp as .4 binary fixed point
> *
> * This uses the formula in the spec to calculate the PBN value for a mode.
> */
> -int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
> +int drm_dp_calc_pbn_mode(int clock, int bpp)
> {
> /*
> * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
> @@ -4735,18 +4734,9 @@ int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
> * peak_kbps *= (1006/1000)
> * peak_kbps *= (64/54)
> * peak_kbps *= 8 convert to bytes
> - *
> - * If the bpp is in units of 1/16, further divide by 16. Put this
> - * factor in the numerator rather than the denominator to avoid
> - * integer overflow
> */
> -
> - if (dsc)
> - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006),
> - 8 * 54 * 1000 * 1000);
> -
> - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
> - 8 * 54 * 1000 * 1000);
> + return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
> + 1000 * 8 * 54 * 1000);
> }
> EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 851b312bd8449..5bf45a2a85b0e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -106,8 +106,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> continue;
>
> crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
> - dsc ? bpp << 4 : bpp,
> - dsc);
> + bpp << 4);
>
> slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
> connector->port,
> @@ -975,7 +974,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
> return ret;
>
> if (mode_rate > max_rate || mode->clock > max_dotclk ||
> - drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) {
> + drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
> *status = MODE_CLOCK_HIGH;
> return 0;
> }
> diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> index d2be40337b92e..153717e1df1a2 100644
> --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> @@ -982,8 +982,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
> const int clock = crtc_state->adjusted_mode.clock;
>
> asyh->or.bpc = connector->display_info.bpc;
> - asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
> - false);
> + asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3 << 4);
> }
>
> mst_state = drm_atomic_get_mst_topology_state(state, &mstm->mgr);
> diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> index 545beea33e8c7..e3c818dfc0e6d 100644
> --- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> +++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> @@ -42,13 +42,13 @@ static const struct drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases
> .clock = 332880,
> .bpp = 24,
> .dsc = true,
> - .expected = 50
> + .expected = 1191
> },
> {
> .clock = 324540,
> .bpp = 24,
> .dsc = true,
> - .expected = 49
> + .expected = 1161
> },
> };
>
> @@ -56,7 +56,7 @@ static void drm_test_dp_mst_calc_pbn_mode(struct kunit *test)
> {
> const struct drm_dp_mst_calc_pbn_mode_test *params = test->param_value;
>
> - KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp, params->dsc),
> + KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp << 4),
> params->expected);
> }
>
> diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
> index 4429d3b1745b6..655862b3d2a49 100644
> --- a/include/drm/display/drm_dp_mst_helper.h
> +++ b/include/drm/display/drm_dp_mst_helper.h
> @@ -842,7 +842,7 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector,
> int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
> int link_rate, int link_lane_count);
>
> -int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
> +int drm_dp_calc_pbn_mode(int clock, int bpp);
>
> void drm_dp_mst_update_slots(struct drm_dp_mst_topology_state *mst_state, uint8_t link_encoding_cap);
>
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v4 02/30] drm/dp_mst: Fix fractional DSC bpp handling
2023-10-31 19:52 ` Imre Deak
@ 2023-11-01 12:59 ` Jani Nikula
2023-11-06 8:16 ` Maxime Ripard
0 siblings, 1 reply; 94+ messages in thread
From: Jani Nikula @ 2023-11-01 12:59 UTC (permalink / raw)
To: imre.deak, Lyude Paul, Wayne Lin, Alex Deucher, Harry Wentland
Cc: Daniel Vetter, intel-gfx, Maxime Ripard, Thomas Zimmermann,
Dave Airlie, Mikita Lipski, David Francis
On Tue, 31 Oct 2023, Imre Deak <imre.deak@intel.com> wrote:
> On Mon, Oct 30, 2023 at 05:58:15PM +0200, Imre Deak wrote:
> Hi Lyude, AMD folks et al,
>
> could you ack patches 2-9 in this patchset if they are ok and it's ok to
> merge them via the i915 tree?
Need acks from drm-misc maintainers too!
Cc: Maxime, Thomas, Maarten
>
> Thanks,
> Imre
>
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> The current code does '(bpp << 4) / 16' in the MST PBN
>> calculation, but that is just the same as 'bpp' so the
>> DSC codepath achieves absolutely nothing. Fix it up so that
>> the fractional part of the bpp value is actually used instead
>> of truncated away. 64*1006 has enough zero lsbs that we can
>> just shift that down in the dividend and thus still manage
>> to stick to a 32bit divisor.
>>
>> And while touching this, let's just make the whole thing more
>> straightforward by making the passed in bpp value .4 binary
>> fixed point always, instead of having to pass in different
>> things based on whether DSC is enabled or not.
>>
>> v2:
>> - Fix DSC kunit test cases.
>>
>> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> Cc: Lyude Paul <lyude@redhat.com>
>> Cc: Harry Wentland <harry.wentland@amd.com>
>> Cc: David Francis <David.Francis@amd.com>
>> Cc: Mikita Lipski <mikita.lipski@amd.com>
>> Cc: Alex Deucher <alexander.deucher@amd.com>
>> Fixes: dc48529fb14e ("drm/dp_mst: Add PBN calculation for DSC modes")
>> Reviewed-by: Lyude Paul <lyude@redhat.com> (v1)
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> [Imre: Fix kunit test cases]
>> Signed-off-by: Imre Deak <imre.deak@intel.com>
>> ---
>> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
>> .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
>> drivers/gpu/drm/display/drm_dp_mst_topology.c | 20 +++++--------------
>> drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++---
>> drivers/gpu/drm/nouveau/dispnv50/disp.c | 3 +--
>> .../gpu/drm/tests/drm_dp_mst_helper_test.c | 6 +++---
>> include/drm/display/drm_dp_mst_helper.h | 2 +-
>> 7 files changed, 14 insertions(+), 26 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> index 9a712791f309f..ada3773869ff0 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> @@ -6918,7 +6918,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
>> max_bpc);
>> bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
>> clock = adjusted_mode->clock;
>> - dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
>> + dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4);
>> }
>>
>> dm_new_connector_state->vcpi_slots =
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
>> index d3b13d362edac..9a58e1a4c5f49 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
>> @@ -1642,7 +1642,7 @@ enum dc_status dm_dp_mst_is_port_support_mode(
>> } else {
>> /* check if mode could be supported within full_pbn */
>> bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
>> - pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
>> + pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp << 4);
>>
>> if (pbn > aconnector->mst_output_port->full_pbn)
>> return DC_FAIL_BANDWIDTH_VALIDATE;
>> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
>> index 0e0d0e76de065..772b00ebd57bd 100644
>> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
>> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
>> @@ -4718,13 +4718,12 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
>>
>> /**
>> * drm_dp_calc_pbn_mode() - Calculate the PBN for a mode.
>> - * @clock: dot clock for the mode
>> - * @bpp: bpp for the mode.
>> - * @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel
>> + * @clock: dot clock
>> + * @bpp: bpp as .4 binary fixed point
>> *
>> * This uses the formula in the spec to calculate the PBN value for a mode.
>> */
>> -int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
>> +int drm_dp_calc_pbn_mode(int clock, int bpp)
>> {
>> /*
>> * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
>> @@ -4735,18 +4734,9 @@ int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
>> * peak_kbps *= (1006/1000)
>> * peak_kbps *= (64/54)
>> * peak_kbps *= 8 convert to bytes
>> - *
>> - * If the bpp is in units of 1/16, further divide by 16. Put this
>> - * factor in the numerator rather than the denominator to avoid
>> - * integer overflow
>> */
>> -
>> - if (dsc)
>> - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006),
>> - 8 * 54 * 1000 * 1000);
>> -
>> - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
>> - 8 * 54 * 1000 * 1000);
>> + return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
>> + 1000 * 8 * 54 * 1000);
>> }
>> EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> index 851b312bd8449..5bf45a2a85b0e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> @@ -106,8 +106,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
>> continue;
>>
>> crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
>> - dsc ? bpp << 4 : bpp,
>> - dsc);
>> + bpp << 4);
>>
>> slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
>> connector->port,
>> @@ -975,7 +974,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
>> return ret;
>>
>> if (mode_rate > max_rate || mode->clock > max_dotclk ||
>> - drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) {
>> + drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
>> *status = MODE_CLOCK_HIGH;
>> return 0;
>> }
>> diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
>> index d2be40337b92e..153717e1df1a2 100644
>> --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
>> +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
>> @@ -982,8 +982,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
>> const int clock = crtc_state->adjusted_mode.clock;
>>
>> asyh->or.bpc = connector->display_info.bpc;
>> - asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
>> - false);
>> + asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3 << 4);
>> }
>>
>> mst_state = drm_atomic_get_mst_topology_state(state, &mstm->mgr);
>> diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
>> index 545beea33e8c7..e3c818dfc0e6d 100644
>> --- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
>> +++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
>> @@ -42,13 +42,13 @@ static const struct drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases
>> .clock = 332880,
>> .bpp = 24,
>> .dsc = true,
>> - .expected = 50
>> + .expected = 1191
>> },
>> {
>> .clock = 324540,
>> .bpp = 24,
>> .dsc = true,
>> - .expected = 49
>> + .expected = 1161
>> },
>> };
>>
>> @@ -56,7 +56,7 @@ static void drm_test_dp_mst_calc_pbn_mode(struct kunit *test)
>> {
>> const struct drm_dp_mst_calc_pbn_mode_test *params = test->param_value;
>>
>> - KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp, params->dsc),
>> + KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp << 4),
>> params->expected);
>> }
>>
>> diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
>> index 4429d3b1745b6..655862b3d2a49 100644
>> --- a/include/drm/display/drm_dp_mst_helper.h
>> +++ b/include/drm/display/drm_dp_mst_helper.h
>> @@ -842,7 +842,7 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector,
>> int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
>> int link_rate, int link_lane_count);
>>
>> -int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
>> +int drm_dp_calc_pbn_mode(int clock, int bpp);
>>
>> void drm_dp_mst_update_slots(struct drm_dp_mst_topology_state *mst_state, uint8_t link_encoding_cap);
>>
>> --
>> 2.39.2
>>
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v4 02/30] drm/dp_mst: Fix fractional DSC bpp handling
2023-11-01 12:59 ` Jani Nikula
@ 2023-11-06 8:16 ` Maxime Ripard
0 siblings, 0 replies; 94+ messages in thread
From: Maxime Ripard @ 2023-11-06 8:16 UTC (permalink / raw)
To: Jani Nikula
Cc: Dave Airlie, Daniel Vetter, Thomas Zimmermann, Wayne Lin,
Alex Deucher, David Francis, Mikita Lipski, Harry Wentland,
intel-gfx
[-- Attachment #1: Type: text/plain, Size: 480 bytes --]
On Wed, Nov 01, 2023 at 02:59:50PM +0200, Jani Nikula wrote:
> On Tue, 31 Oct 2023, Imre Deak <imre.deak@intel.com> wrote:
> > On Mon, Oct 30, 2023 at 05:58:15PM +0200, Imre Deak wrote:
> > Hi Lyude, AMD folks et al,
> >
> > could you ack patches 2-9 in this patchset if they are ok and it's ok to
> > merge them via the i915 tree?
>
> Need acks from drm-misc maintainers too!
>
> Cc: Maxime, Thomas, Maarten
Acked-by: Maxime Ripard <mripard@kernel.org>
Maxime
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [Intel-gfx] [PATCH v4 02/30] drm/dp_mst: Fix fractional DSC bpp handling
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 02/30] drm/dp_mst: Fix fractional DSC bpp handling Imre Deak
2023-10-31 19:52 ` Imre Deak
@ 2023-11-07 22:45 ` Lyude Paul
2023-11-08 14:40 ` Harry Wentland
2 siblings, 0 replies; 94+ messages in thread
From: Lyude Paul @ 2023-11-07 22:45 UTC (permalink / raw)
To: Imre Deak, intel-gfx
Cc: David Francis, Manasi Navare, Alex Deucher, Mikita Lipski,
Harry Wentland
Reviewed-by: Lyude Paul <lyude@redhat.com>
On Mon, 2023-10-30 at 17:58 +0200, Imre Deak wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The current code does '(bpp << 4) / 16' in the MST PBN
> calculation, but that is just the same as 'bpp' so the
> DSC codepath achieves absolutely nothing. Fix it up so that
> the fractional part of the bpp value is actually used instead
> of truncated away. 64*1006 has enough zero lsbs that we can
> just shift that down in the dividend and thus still manage
> to stick to a 32bit divisor.
>
> And while touching this, let's just make the whole thing more
> straightforward by making the passed in bpp value .4 binary
> fixed point always, instead of having to pass in different
> things based on whether DSC is enabled or not.
>
> v2:
> - Fix DSC kunit test cases.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: David Francis <David.Francis@amd.com>
> Cc: Mikita Lipski <mikita.lipski@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Fixes: dc48529fb14e ("drm/dp_mst: Add PBN calculation for DSC modes")
> Reviewed-by: Lyude Paul <lyude@redhat.com> (v1)
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> [Imre: Fix kunit test cases]
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
> drivers/gpu/drm/display/drm_dp_mst_topology.c | 20 +++++--------------
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++---
> drivers/gpu/drm/nouveau/dispnv50/disp.c | 3 +--
> .../gpu/drm/tests/drm_dp_mst_helper_test.c | 6 +++---
> include/drm/display/drm_dp_mst_helper.h | 2 +-
> 7 files changed, 14 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 9a712791f309f..ada3773869ff0 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -6918,7 +6918,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
> max_bpc);
> bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
> clock = adjusted_mode->clock;
> - dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
> + dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4);
> }
>
> dm_new_connector_state->vcpi_slots =
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> index d3b13d362edac..9a58e1a4c5f49 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> @@ -1642,7 +1642,7 @@ enum dc_status dm_dp_mst_is_port_support_mode(
> } else {
> /* check if mode could be supported within full_pbn */
> bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
> - pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
> + pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp << 4);
>
> if (pbn > aconnector->mst_output_port->full_pbn)
> return DC_FAIL_BANDWIDTH_VALIDATE;
> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> index 0e0d0e76de065..772b00ebd57bd 100644
> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> @@ -4718,13 +4718,12 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
>
> /**
> * drm_dp_calc_pbn_mode() - Calculate the PBN for a mode.
> - * @clock: dot clock for the mode
> - * @bpp: bpp for the mode.
> - * @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel
> + * @clock: dot clock
> + * @bpp: bpp as .4 binary fixed point
> *
> * This uses the formula in the spec to calculate the PBN value for a mode.
> */
> -int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
> +int drm_dp_calc_pbn_mode(int clock, int bpp)
> {
> /*
> * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
> @@ -4735,18 +4734,9 @@ int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
> * peak_kbps *= (1006/1000)
> * peak_kbps *= (64/54)
> * peak_kbps *= 8 convert to bytes
> - *
> - * If the bpp is in units of 1/16, further divide by 16. Put this
> - * factor in the numerator rather than the denominator to avoid
> - * integer overflow
> */
> -
> - if (dsc)
> - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006),
> - 8 * 54 * 1000 * 1000);
> -
> - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
> - 8 * 54 * 1000 * 1000);
> + return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
> + 1000 * 8 * 54 * 1000);
> }
> EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 851b312bd8449..5bf45a2a85b0e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -106,8 +106,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> continue;
>
> crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
> - dsc ? bpp << 4 : bpp,
> - dsc);
> + bpp << 4);
>
> slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
> connector->port,
> @@ -975,7 +974,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
> return ret;
>
> if (mode_rate > max_rate || mode->clock > max_dotclk ||
> - drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) {
> + drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
> *status = MODE_CLOCK_HIGH;
> return 0;
> }
> diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> index d2be40337b92e..153717e1df1a2 100644
> --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> @@ -982,8 +982,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
> const int clock = crtc_state->adjusted_mode.clock;
>
> asyh->or.bpc = connector->display_info.bpc;
> - asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
> - false);
> + asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3 << 4);
> }
>
> mst_state = drm_atomic_get_mst_topology_state(state, &mstm->mgr);
> diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> index 545beea33e8c7..e3c818dfc0e6d 100644
> --- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> +++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> @@ -42,13 +42,13 @@ static const struct drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases
> .clock = 332880,
> .bpp = 24,
> .dsc = true,
> - .expected = 50
> + .expected = 1191
> },
> {
> .clock = 324540,
> .bpp = 24,
> .dsc = true,
> - .expected = 49
> + .expected = 1161
> },
> };
>
> @@ -56,7 +56,7 @@ static void drm_test_dp_mst_calc_pbn_mode(struct kunit *test)
> {
> const struct drm_dp_mst_calc_pbn_mode_test *params = test->param_value;
>
> - KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp, params->dsc),
> + KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp << 4),
> params->expected);
> }
>
> diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
> index 4429d3b1745b6..655862b3d2a49 100644
> --- a/include/drm/display/drm_dp_mst_helper.h
> +++ b/include/drm/display/drm_dp_mst_helper.h
> @@ -842,7 +842,7 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector,
> int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
> int link_rate, int link_lane_count);
>
> -int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
> +int drm_dp_calc_pbn_mode(int clock, int bpp);
>
> void drm_dp_mst_update_slots(struct drm_dp_mst_topology_state *mst_state, uint8_t link_encoding_cap);
>
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v4 02/30] drm/dp_mst: Fix fractional DSC bpp handling
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 02/30] drm/dp_mst: Fix fractional DSC bpp handling Imre Deak
2023-10-31 19:52 ` Imre Deak
2023-11-07 22:45 ` Lyude Paul
@ 2023-11-08 14:40 ` Harry Wentland
2023-11-08 17:01 ` Deucher, Alexander
2 siblings, 1 reply; 94+ messages in thread
From: Harry Wentland @ 2023-11-08 14:40 UTC (permalink / raw)
To: Imre Deak, intel-gfx
Cc: David Francis, Manasi Navare, Alex Deucher, Mikita Lipski
On 2023-10-30 11:58, Imre Deak wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The current code does '(bpp << 4) / 16' in the MST PBN
> calculation, but that is just the same as 'bpp' so the
> DSC codepath achieves absolutely nothing. Fix it up so that
> the fractional part of the bpp value is actually used instead
> of truncated away. 64*1006 has enough zero lsbs that we can
> just shift that down in the dividend and thus still manage
> to stick to a 32bit divisor.
>
> And while touching this, let's just make the whole thing more
> straightforward by making the passed in bpp value .4 binary
> fixed point always, instead of having to pass in different
> things based on whether DSC is enabled or not.
>
> v2:
> - Fix DSC kunit test cases.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: David Francis <David.Francis@amd.com>
> Cc: Mikita Lipski <mikita.lipski@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Fixes: dc48529fb14e ("drm/dp_mst: Add PBN calculation for DSC modes")
> Reviewed-by: Lyude Paul <lyude@redhat.com> (v1)
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> [Imre: Fix kunit test cases]
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Harry
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
> drivers/gpu/drm/display/drm_dp_mst_topology.c | 20 +++++--------------
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++---
> drivers/gpu/drm/nouveau/dispnv50/disp.c | 3 +--
> .../gpu/drm/tests/drm_dp_mst_helper_test.c | 6 +++---
> include/drm/display/drm_dp_mst_helper.h | 2 +-
> 7 files changed, 14 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 9a712791f309f..ada3773869ff0 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -6918,7 +6918,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
> max_bpc);
> bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
> clock = adjusted_mode->clock;
> - dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
> + dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4);
> }
>
> dm_new_connector_state->vcpi_slots =
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> index d3b13d362edac..9a58e1a4c5f49 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> @@ -1642,7 +1642,7 @@ enum dc_status dm_dp_mst_is_port_support_mode(
> } else {
> /* check if mode could be supported within full_pbn */
> bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
> - pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
> + pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp << 4);
>
> if (pbn > aconnector->mst_output_port->full_pbn)
> return DC_FAIL_BANDWIDTH_VALIDATE;
> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> index 0e0d0e76de065..772b00ebd57bd 100644
> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> @@ -4718,13 +4718,12 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
>
> /**
> * drm_dp_calc_pbn_mode() - Calculate the PBN for a mode.
> - * @clock: dot clock for the mode
> - * @bpp: bpp for the mode.
> - * @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel
> + * @clock: dot clock
> + * @bpp: bpp as .4 binary fixed point
> *
> * This uses the formula in the spec to calculate the PBN value for a mode.
> */
> -int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
> +int drm_dp_calc_pbn_mode(int clock, int bpp)
> {
> /*
> * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
> @@ -4735,18 +4734,9 @@ int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
> * peak_kbps *= (1006/1000)
> * peak_kbps *= (64/54)
> * peak_kbps *= 8 convert to bytes
> - *
> - * If the bpp is in units of 1/16, further divide by 16. Put this
> - * factor in the numerator rather than the denominator to avoid
> - * integer overflow
> */
> -
> - if (dsc)
> - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006),
> - 8 * 54 * 1000 * 1000);
> -
> - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
> - 8 * 54 * 1000 * 1000);
> + return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
> + 1000 * 8 * 54 * 1000);
> }
> EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 851b312bd8449..5bf45a2a85b0e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -106,8 +106,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> continue;
>
> crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
> - dsc ? bpp << 4 : bpp,
> - dsc);
> + bpp << 4);
>
> slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
> connector->port,
> @@ -975,7 +974,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
> return ret;
>
> if (mode_rate > max_rate || mode->clock > max_dotclk ||
> - drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) {
> + drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
> *status = MODE_CLOCK_HIGH;
> return 0;
> }
> diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> index d2be40337b92e..153717e1df1a2 100644
> --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> @@ -982,8 +982,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
> const int clock = crtc_state->adjusted_mode.clock;
>
> asyh->or.bpc = connector->display_info.bpc;
> - asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
> - false);
> + asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3 << 4);
> }
>
> mst_state = drm_atomic_get_mst_topology_state(state, &mstm->mgr);
> diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> index 545beea33e8c7..e3c818dfc0e6d 100644
> --- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> +++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> @@ -42,13 +42,13 @@ static const struct drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases
> .clock = 332880,
> .bpp = 24,
> .dsc = true,
> - .expected = 50
> + .expected = 1191
> },
> {
> .clock = 324540,
> .bpp = 24,
> .dsc = true,
> - .expected = 49
> + .expected = 1161
> },
> };
>
> @@ -56,7 +56,7 @@ static void drm_test_dp_mst_calc_pbn_mode(struct kunit *test)
> {
> const struct drm_dp_mst_calc_pbn_mode_test *params = test->param_value;
>
> - KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp, params->dsc),
> + KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp << 4),
> params->expected);
> }
>
> diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
> index 4429d3b1745b6..655862b3d2a49 100644
> --- a/include/drm/display/drm_dp_mst_helper.h
> +++ b/include/drm/display/drm_dp_mst_helper.h
> @@ -842,7 +842,7 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector,
> int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
> int link_rate, int link_lane_count);
>
> -int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
> +int drm_dp_calc_pbn_mode(int clock, int bpp);
>
> void drm_dp_mst_update_slots(struct drm_dp_mst_topology_state *mst_state, uint8_t link_encoding_cap);
>
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v4 02/30] drm/dp_mst: Fix fractional DSC bpp handling
2023-11-08 14:40 ` Harry Wentland
@ 2023-11-08 17:01 ` Deucher, Alexander
0 siblings, 0 replies; 94+ messages in thread
From: Deucher, Alexander @ 2023-11-08 17:01 UTC (permalink / raw)
To: Wentland, Harry, Imre Deak, intel-gfx@lists.freedesktop.org
Cc: Manasi Navare, Francis, David, Mikita Lipski
[Public]
> -----Original Message-----
> From: Wentland, Harry <Harry.Wentland@amd.com>
> Sent: Wednesday, November 8, 2023 9:40 AM
> To: Imre Deak <imre.deak@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>; Manasi Navare
> <manasi.d.navare@intel.com>; Lyude Paul <lyude@redhat.com>; Francis,
> David <David.Francis@amd.com>; Mikita Lipski <mikita.lipski@amd.com>;
> Deucher, Alexander <Alexander.Deucher@amd.com>
> Subject: Re: [PATCH v4 02/30] drm/dp_mst: Fix fractional DSC bpp handling
>
>
>
> On 2023-10-30 11:58, Imre Deak wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The current code does '(bpp << 4) / 16' in the MST PBN calculation,
> > but that is just the same as 'bpp' so the DSC codepath achieves
> > absolutely nothing. Fix it up so that the fractional part of the bpp
> > value is actually used instead of truncated away. 64*1006 has enough
> > zero lsbs that we can just shift that down in the dividend and thus
> > still manage to stick to a 32bit divisor.
> >
> > And while touching this, let's just make the whole thing more
> > straightforward by making the passed in bpp value .4 binary fixed
> > point always, instead of having to pass in different things based on
> > whether DSC is enabled or not.
> >
> > v2:
> > - Fix DSC kunit test cases.
> >
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Cc: Lyude Paul <lyude@redhat.com>
> > Cc: Harry Wentland <harry.wentland@amd.com>
> > Cc: David Francis <David.Francis@amd.com>
> > Cc: Mikita Lipski <mikita.lipski@amd.com>
> > Cc: Alex Deucher <alexander.deucher@amd.com>
> > Fixes: dc48529fb14e ("drm/dp_mst: Add PBN calculation for DSC modes")
> > Reviewed-by: Lyude Paul <lyude@redhat.com> (v1)
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > [Imre: Fix kunit test cases]
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>
> Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
>
> Harry
>
> > ---
> > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> > .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
> > drivers/gpu/drm/display/drm_dp_mst_topology.c | 20 +++++--------------
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++---
> > drivers/gpu/drm/nouveau/dispnv50/disp.c | 3 +--
> > .../gpu/drm/tests/drm_dp_mst_helper_test.c | 6 +++---
> > include/drm/display/drm_dp_mst_helper.h | 2 +-
> > 7 files changed, 14 insertions(+), 26 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index 9a712791f309f..ada3773869ff0 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -6918,7 +6918,7 @@ static int
> dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
> > max_bpc);
> > bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
> > clock = adjusted_mode->clock;
> > - dm_new_connector_state->pbn =
> drm_dp_calc_pbn_mode(clock, bpp, false);
> > + dm_new_connector_state->pbn =
> drm_dp_calc_pbn_mode(clock, bpp <<
> > +4);
> > }
> >
> > dm_new_connector_state->vcpi_slots = diff --git
> > a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> > index d3b13d362edac..9a58e1a4c5f49 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> > +++
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> > @@ -1642,7 +1642,7 @@ enum dc_status
> dm_dp_mst_is_port_support_mode(
> > } else {
> > /* check if mode could be supported within full_pbn */
> > bpp = convert_dc_color_depth_into_bpc(stream-
> >timing.display_color_depth) * 3;
> > - pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz
> / 10, bpp, false);
> > + pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz
> / 10, bpp
> > +<< 4);
> >
> > if (pbn > aconnector->mst_output_port->full_pbn)
> > return DC_FAIL_BANDWIDTH_VALIDATE; diff --git
> > a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > index 0e0d0e76de065..772b00ebd57bd 100644
> > --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > @@ -4718,13 +4718,12 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
> >
> > /**
> > * drm_dp_calc_pbn_mode() - Calculate the PBN for a mode.
> > - * @clock: dot clock for the mode
> > - * @bpp: bpp for the mode.
> > - * @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel
> > + * @clock: dot clock
> > + * @bpp: bpp as .4 binary fixed point
> > *
> > * This uses the formula in the spec to calculate the PBN value for a mode.
> > */
> > -int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
> > +int drm_dp_calc_pbn_mode(int clock, int bpp)
> > {
> > /*
> > * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006 @@
> > -4735,18 +4734,9 @@ int drm_dp_calc_pbn_mode(int clock, int bpp, bool
> dsc)
> > * peak_kbps *= (1006/1000)
> > * peak_kbps *= (64/54)
> > * peak_kbps *= 8 convert to bytes
> > - *
> > - * If the bpp is in units of 1/16, further divide by 16. Put this
> > - * factor in the numerator rather than the denominator to avoid
> > - * integer overflow
> > */
> > -
> > - if (dsc)
> > - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp /
> 16), 64 * 1006),
> > - 8 * 54 * 1000 * 1000);
> > -
> > - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
> > - 8 * 54 * 1000 * 1000);
> > + return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >>
> 4),
> > + 1000 * 8 * 54 * 1000);
> > }
> > EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 851b312bd8449..5bf45a2a85b0e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -106,8 +106,7 @@ static int
> intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> > continue;
> >
> > crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode-
> >crtc_clock,
> > - dsc ? bpp << 4 : bpp,
> > - dsc);
> > + bpp << 4);
> >
> > slots = drm_dp_atomic_find_time_slots(state, &intel_dp-
> >mst_mgr,
> > connector->port,
> > @@ -975,7 +974,7 @@ intel_dp_mst_mode_valid_ctx(struct
> drm_connector *connector,
> > return ret;
> >
> > if (mode_rate > max_rate || mode->clock > max_dotclk ||
> > - drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port-
> >full_pbn) {
> > + drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) >
> > +port->full_pbn) {
> > *status = MODE_CLOCK_HIGH;
> > return 0;
> > }
> > diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> > b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> > index d2be40337b92e..153717e1df1a2 100644
> > --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> > +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> > @@ -982,8 +982,7 @@ nv50_msto_atomic_check(struct drm_encoder
> *encoder,
> > const int clock = crtc_state->adjusted_mode.clock;
> >
> > asyh->or.bpc = connector->display_info.bpc;
> > - asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc
> * 3,
> > - false);
> > + asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc
> * 3 << 4);
> > }
> >
> > mst_state = drm_atomic_get_mst_topology_state(state, &mstm-
> >mgr);
> > diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> > b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> > index 545beea33e8c7..e3c818dfc0e6d 100644
> > --- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> > +++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> > @@ -42,13 +42,13 @@ static const struct
> drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases
> > .clock = 332880,
> > .bpp = 24,
> > .dsc = true,
> > - .expected = 50
> > + .expected = 1191
> > },
> > {
> > .clock = 324540,
> > .bpp = 24,
> > .dsc = true,
> > - .expected = 49
> > + .expected = 1161
> > },
> > };
> >
> > @@ -56,7 +56,7 @@ static void drm_test_dp_mst_calc_pbn_mode(struct
> > kunit *test) {
> > const struct drm_dp_mst_calc_pbn_mode_test *params =
> > test->param_value;
> >
> > - KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock,
> params->bpp, params->dsc),
> > + KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock,
> > +params->bpp << 4),
> > params->expected);
> > }
> >
> > diff --git a/include/drm/display/drm_dp_mst_helper.h
> > b/include/drm/display/drm_dp_mst_helper.h
> > index 4429d3b1745b6..655862b3d2a49 100644
> > --- a/include/drm/display/drm_dp_mst_helper.h
> > +++ b/include/drm/display/drm_dp_mst_helper.h
> > @@ -842,7 +842,7 @@ struct edid *drm_dp_mst_get_edid(struct
> > drm_connector *connector, int drm_dp_get_vc_payload_bw(const struct
> drm_dp_mst_topology_mgr *mgr,
> > int link_rate, int link_lane_count);
> >
> > -int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
> > +int drm_dp_calc_pbn_mode(int clock, int bpp);
> >
> > void drm_dp_mst_update_slots(struct drm_dp_mst_topology_state
> > *mst_state, uint8_t link_encoding_cap);
> >
^ permalink raw reply [flat|nested] 94+ messages in thread
* [Intel-gfx] [PATCH v4 03/30] drm/dp_mst: Add helper to determine if an MST port is downstream of another port
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 02/30] drm/dp_mst: Fix fractional DSC bpp handling Imre Deak
` (38 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Add drm_dp_mst_port_downstream_of_parent() required by the i915
driver in a follow-up patch to resolve a BW overallocation of MST
streams going through a given MST port.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 52 +++++++++++++++++++
include/drm/display/drm_dp_mst_helper.h | 3 ++
2 files changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 772b00ebd57bd..f733f620347f6 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5126,6 +5126,58 @@ static bool drm_dp_mst_port_downstream_of_branch(struct drm_dp_mst_port *port,
return false;
}
+static bool
+drm_dp_mst_port_downstream_of_parent_locked(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_mst_port *parent)
+{
+ if (!mgr->mst_primary)
+ return false;
+
+ port = drm_dp_mst_topology_get_port_validated_locked(mgr->mst_primary,
+ port);
+ if (!port)
+ return false;
+
+ if (!parent)
+ return true;
+
+ parent = drm_dp_mst_topology_get_port_validated_locked(mgr->mst_primary,
+ parent);
+ if (!parent)
+ return false;
+
+ if (!parent->mstb)
+ return false;
+
+ return drm_dp_mst_port_downstream_of_branch(port, parent->mstb);
+}
+
+/**
+ * drm_dp_mst_port_downstream_of_parent - check if a port is downstream of a parent port
+ * @mgr: MST topology manager
+ * @port: the port being looked up
+ * @parent: the parent port
+ *
+ * The function returns %true if @port is downstream of @parent. If @parent is
+ * %NULL - denoting the root port - the function returns %true if @port is in
+ * @mgr's topology.
+ */
+bool
+drm_dp_mst_port_downstream_of_parent(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_mst_port *parent)
+{
+ bool ret;
+
+ mutex_lock(&mgr->lock);
+ ret = drm_dp_mst_port_downstream_of_parent_locked(mgr, port, parent);
+ mutex_unlock(&mgr->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(drm_dp_mst_port_downstream_of_parent);
+
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
struct drm_dp_mst_topology_state *state);
diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
index 655862b3d2a49..e44485aa74e94 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -892,6 +892,9 @@ drm_atomic_get_new_mst_topology_state(struct drm_atomic_state *state,
struct drm_dp_mst_atomic_payload *
drm_atomic_get_mst_payload_state(struct drm_dp_mst_topology_state *state,
struct drm_dp_mst_port *port);
+bool drm_dp_mst_port_downstream_of_parent(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_mst_port *parent);
int __must_check
drm_dp_atomic_find_time_slots(struct drm_atomic_state *state,
struct drm_dp_mst_topology_mgr *mgr,
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PATCH v4 03/30] drm/dp_mst: Add helper to determine if an MST port is downstream of another port
@ 2023-10-30 15:58 ` Imre Deak
0 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Add drm_dp_mst_port_downstream_of_parent() required by the i915
driver in a follow-up patch to resolve a BW overallocation of MST
streams going through a given MST port.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 52 +++++++++++++++++++
include/drm/display/drm_dp_mst_helper.h | 3 ++
2 files changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 772b00ebd57bd..f733f620347f6 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5126,6 +5126,58 @@ static bool drm_dp_mst_port_downstream_of_branch(struct drm_dp_mst_port *port,
return false;
}
+static bool
+drm_dp_mst_port_downstream_of_parent_locked(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_mst_port *parent)
+{
+ if (!mgr->mst_primary)
+ return false;
+
+ port = drm_dp_mst_topology_get_port_validated_locked(mgr->mst_primary,
+ port);
+ if (!port)
+ return false;
+
+ if (!parent)
+ return true;
+
+ parent = drm_dp_mst_topology_get_port_validated_locked(mgr->mst_primary,
+ parent);
+ if (!parent)
+ return false;
+
+ if (!parent->mstb)
+ return false;
+
+ return drm_dp_mst_port_downstream_of_branch(port, parent->mstb);
+}
+
+/**
+ * drm_dp_mst_port_downstream_of_parent - check if a port is downstream of a parent port
+ * @mgr: MST topology manager
+ * @port: the port being looked up
+ * @parent: the parent port
+ *
+ * The function returns %true if @port is downstream of @parent. If @parent is
+ * %NULL - denoting the root port - the function returns %true if @port is in
+ * @mgr's topology.
+ */
+bool
+drm_dp_mst_port_downstream_of_parent(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_mst_port *parent)
+{
+ bool ret;
+
+ mutex_lock(&mgr->lock);
+ ret = drm_dp_mst_port_downstream_of_parent_locked(mgr, port, parent);
+ mutex_unlock(&mgr->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(drm_dp_mst_port_downstream_of_parent);
+
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
struct drm_dp_mst_topology_state *state);
diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
index 655862b3d2a49..e44485aa74e94 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -892,6 +892,9 @@ drm_atomic_get_new_mst_topology_state(struct drm_atomic_state *state,
struct drm_dp_mst_atomic_payload *
drm_atomic_get_mst_payload_state(struct drm_dp_mst_topology_state *state,
struct drm_dp_mst_port *port);
+bool drm_dp_mst_port_downstream_of_parent(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_mst_port *parent);
int __must_check
drm_dp_atomic_find_time_slots(struct drm_atomic_state *state,
struct drm_dp_mst_topology_mgr *mgr,
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread
* [Intel-gfx] [PATCH v4 04/30] drm/dp_mst: Factor out a helper to check the atomic state of a topology manager
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 02/30] drm/dp_mst: Fix fractional DSC bpp handling Imre Deak
` (38 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Factor out a helper to check the atomic state for one MST topology
manager, returning the MST port where the BW limit check has failed.
This will be used in a follow-up patch by the i915 driver to improve the
BW sharing between MST streams.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 93 +++++++++++++++----
include/drm/display/drm_dp_mst_helper.h | 4 +
2 files changed, 78 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index f733f620347f6..a86a67d3516ff 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5180,11 +5180,13 @@ EXPORT_SYMBOL(drm_dp_mst_port_downstream_of_parent);
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
- struct drm_dp_mst_topology_state *state);
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port);
static int
drm_dp_mst_atomic_check_mstb_bw_limit(struct drm_dp_mst_branch *mstb,
- struct drm_dp_mst_topology_state *state)
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port)
{
struct drm_dp_mst_atomic_payload *payload;
struct drm_dp_mst_port *port;
@@ -5213,7 +5215,7 @@ drm_dp_mst_atomic_check_mstb_bw_limit(struct drm_dp_mst_branch *mstb,
drm_dbg_atomic(mstb->mgr->dev, "[MSTB:%p] Checking bandwidth limits\n", mstb);
list_for_each_entry(port, &mstb->ports, next) {
- ret = drm_dp_mst_atomic_check_port_bw_limit(port, state);
+ ret = drm_dp_mst_atomic_check_port_bw_limit(port, state, failing_port);
if (ret < 0)
return ret;
@@ -5225,7 +5227,8 @@ drm_dp_mst_atomic_check_mstb_bw_limit(struct drm_dp_mst_branch *mstb,
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
- struct drm_dp_mst_topology_state *state)
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port)
{
struct drm_dp_mst_atomic_payload *payload;
int pbn_used = 0;
@@ -5246,13 +5249,15 @@ drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
drm_dbg_atomic(port->mgr->dev,
"[MSTB:%p] [MST PORT:%p] no BW available for the port\n",
port->parent, port);
+ *failing_port = port;
return -EINVAL;
}
pbn_used = payload->pbn;
} else {
pbn_used = drm_dp_mst_atomic_check_mstb_bw_limit(port->mstb,
- state);
+ state,
+ failing_port);
if (pbn_used <= 0)
return pbn_used;
}
@@ -5261,6 +5266,7 @@ drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
drm_dbg_atomic(port->mgr->dev,
"[MSTB:%p] [MST PORT:%p] required PBN of %d exceeds port limit of %d\n",
port->parent, port, pbn_used, port->full_pbn);
+ *failing_port = port;
return -ENOSPC;
}
@@ -5438,20 +5444,79 @@ int drm_dp_mst_atomic_enable_dsc(struct drm_atomic_state *state,
}
EXPORT_SYMBOL(drm_dp_mst_atomic_enable_dsc);
+/**
+ * drm_dp_mst_atomic_check_mgr - Check the atomic state of an MST topology manager
+ * @state: The global atomic state
+ * @mgr: Manager to check
+ * @mst_state: The MST atomic state for @mgr
+ * @failing_port: Returns the port with a BW limitation
+ *
+ * Checks the given MST manager's topology state for an atomic update to ensure
+ * that it's valid. This includes checking whether there's enough bandwidth to
+ * support the new timeslot allocations in the atomic update.
+ *
+ * Any atomic drivers supporting DP MST must make sure to call this or
+ * the drm_dp_mst_atomic_check() function after checking the rest of their state
+ * in their &drm_mode_config_funcs.atomic_check() callback.
+ *
+ * See also:
+ * drm_dp_mst_atomic_check()
+ * drm_dp_atomic_find_time_slots()
+ * drm_dp_atomic_release_time_slots()
+ *
+ * Returns:
+ * - 0 if the new state is valid
+ * - %-ENOSPC, if the new state is invalid, because of BW limitation
+ * @failing_port is set to:
+ * - The non-root port where a BW limit check failed
+ * The returned port pointer is valid until at least
+ * one payload downstream of it exists.
+ * - %NULL if the BW limit check failed at the root port
+ * - %-EINVAL, if the new state is invalid, because the root port has
+ * too many payloads.
+ */
+int drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_topology_state *mst_state,
+ struct drm_dp_mst_port **failing_port)
+{
+ int ret;
+
+ *failing_port = NULL;
+
+ if (!mgr->mst_state)
+ return 0;
+
+ ret = drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
+ if (ret)
+ return ret;
+
+ mutex_lock(&mgr->lock);
+ ret = drm_dp_mst_atomic_check_mstb_bw_limit(mgr->mst_primary,
+ mst_state,
+ failing_port);
+ mutex_unlock(&mgr->lock);
+
+ return ret < 0 ? ret : 0;
+}
+EXPORT_SYMBOL(drm_dp_mst_atomic_check_mgr);
+
/**
* drm_dp_mst_atomic_check - Check that the new state of an MST topology in an
* atomic update is valid
* @state: Pointer to the new &struct drm_dp_mst_topology_state
*
* Checks the given topology state for an atomic update to ensure that it's
- * valid. This includes checking whether there's enough bandwidth to support
- * the new timeslot allocations in the atomic update.
+ * valid, calling drm_dp_mst_atomic_check_mgr() for all MST manager in the
+ * atomic state. This includes checking whether there's enough bandwidth to
+ * support the new timeslot allocations in the atomic update.
*
* Any atomic drivers supporting DP MST must make sure to call this after
* checking the rest of their state in their
* &drm_mode_config_funcs.atomic_check() callback.
*
* See also:
+ * drm_dp_mst_atomic_check_mgr()
* drm_dp_atomic_find_time_slots()
* drm_dp_atomic_release_time_slots()
*
@@ -5466,21 +5531,11 @@ int drm_dp_mst_atomic_check(struct drm_atomic_state *state)
int i, ret = 0;
for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
- if (!mgr->mst_state)
- continue;
+ struct drm_dp_mst_port *tmp_port;
- ret = drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
+ ret = drm_dp_mst_atomic_check_mgr(state, mgr, mst_state, &tmp_port);
if (ret)
break;
-
- mutex_lock(&mgr->lock);
- ret = drm_dp_mst_atomic_check_mstb_bw_limit(mgr->mst_primary,
- mst_state);
- mutex_unlock(&mgr->lock);
- if (ret < 0)
- break;
- else
- ret = 0;
}
return ret;
diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
index e44485aa74e94..a4aad6df71f18 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -916,6 +916,10 @@ int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr,
int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_port *port,
struct drm_dp_query_stream_enc_status_ack_reply *status);
+int __must_check drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_topology_state *mst_state,
+ struct drm_dp_mst_port **failing_port);
int __must_check drm_dp_mst_atomic_check(struct drm_atomic_state *state);
int __must_check drm_dp_mst_root_conn_atomic_check(struct drm_connector_state *new_conn_state,
struct drm_dp_mst_topology_mgr *mgr);
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PATCH v4 04/30] drm/dp_mst: Factor out a helper to check the atomic state of a topology manager
@ 2023-10-30 15:58 ` Imre Deak
0 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Factor out a helper to check the atomic state for one MST topology
manager, returning the MST port where the BW limit check has failed.
This will be used in a follow-up patch by the i915 driver to improve the
BW sharing between MST streams.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 93 +++++++++++++++----
include/drm/display/drm_dp_mst_helper.h | 4 +
2 files changed, 78 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index f733f620347f6..a86a67d3516ff 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5180,11 +5180,13 @@ EXPORT_SYMBOL(drm_dp_mst_port_downstream_of_parent);
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
- struct drm_dp_mst_topology_state *state);
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port);
static int
drm_dp_mst_atomic_check_mstb_bw_limit(struct drm_dp_mst_branch *mstb,
- struct drm_dp_mst_topology_state *state)
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port)
{
struct drm_dp_mst_atomic_payload *payload;
struct drm_dp_mst_port *port;
@@ -5213,7 +5215,7 @@ drm_dp_mst_atomic_check_mstb_bw_limit(struct drm_dp_mst_branch *mstb,
drm_dbg_atomic(mstb->mgr->dev, "[MSTB:%p] Checking bandwidth limits\n", mstb);
list_for_each_entry(port, &mstb->ports, next) {
- ret = drm_dp_mst_atomic_check_port_bw_limit(port, state);
+ ret = drm_dp_mst_atomic_check_port_bw_limit(port, state, failing_port);
if (ret < 0)
return ret;
@@ -5225,7 +5227,8 @@ drm_dp_mst_atomic_check_mstb_bw_limit(struct drm_dp_mst_branch *mstb,
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
- struct drm_dp_mst_topology_state *state)
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port)
{
struct drm_dp_mst_atomic_payload *payload;
int pbn_used = 0;
@@ -5246,13 +5249,15 @@ drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
drm_dbg_atomic(port->mgr->dev,
"[MSTB:%p] [MST PORT:%p] no BW available for the port\n",
port->parent, port);
+ *failing_port = port;
return -EINVAL;
}
pbn_used = payload->pbn;
} else {
pbn_used = drm_dp_mst_atomic_check_mstb_bw_limit(port->mstb,
- state);
+ state,
+ failing_port);
if (pbn_used <= 0)
return pbn_used;
}
@@ -5261,6 +5266,7 @@ drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
drm_dbg_atomic(port->mgr->dev,
"[MSTB:%p] [MST PORT:%p] required PBN of %d exceeds port limit of %d\n",
port->parent, port, pbn_used, port->full_pbn);
+ *failing_port = port;
return -ENOSPC;
}
@@ -5438,20 +5444,79 @@ int drm_dp_mst_atomic_enable_dsc(struct drm_atomic_state *state,
}
EXPORT_SYMBOL(drm_dp_mst_atomic_enable_dsc);
+/**
+ * drm_dp_mst_atomic_check_mgr - Check the atomic state of an MST topology manager
+ * @state: The global atomic state
+ * @mgr: Manager to check
+ * @mst_state: The MST atomic state for @mgr
+ * @failing_port: Returns the port with a BW limitation
+ *
+ * Checks the given MST manager's topology state for an atomic update to ensure
+ * that it's valid. This includes checking whether there's enough bandwidth to
+ * support the new timeslot allocations in the atomic update.
+ *
+ * Any atomic drivers supporting DP MST must make sure to call this or
+ * the drm_dp_mst_atomic_check() function after checking the rest of their state
+ * in their &drm_mode_config_funcs.atomic_check() callback.
+ *
+ * See also:
+ * drm_dp_mst_atomic_check()
+ * drm_dp_atomic_find_time_slots()
+ * drm_dp_atomic_release_time_slots()
+ *
+ * Returns:
+ * - 0 if the new state is valid
+ * - %-ENOSPC, if the new state is invalid, because of BW limitation
+ * @failing_port is set to:
+ * - The non-root port where a BW limit check failed
+ * The returned port pointer is valid until at least
+ * one payload downstream of it exists.
+ * - %NULL if the BW limit check failed at the root port
+ * - %-EINVAL, if the new state is invalid, because the root port has
+ * too many payloads.
+ */
+int drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_topology_state *mst_state,
+ struct drm_dp_mst_port **failing_port)
+{
+ int ret;
+
+ *failing_port = NULL;
+
+ if (!mgr->mst_state)
+ return 0;
+
+ ret = drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
+ if (ret)
+ return ret;
+
+ mutex_lock(&mgr->lock);
+ ret = drm_dp_mst_atomic_check_mstb_bw_limit(mgr->mst_primary,
+ mst_state,
+ failing_port);
+ mutex_unlock(&mgr->lock);
+
+ return ret < 0 ? ret : 0;
+}
+EXPORT_SYMBOL(drm_dp_mst_atomic_check_mgr);
+
/**
* drm_dp_mst_atomic_check - Check that the new state of an MST topology in an
* atomic update is valid
* @state: Pointer to the new &struct drm_dp_mst_topology_state
*
* Checks the given topology state for an atomic update to ensure that it's
- * valid. This includes checking whether there's enough bandwidth to support
- * the new timeslot allocations in the atomic update.
+ * valid, calling drm_dp_mst_atomic_check_mgr() for all MST manager in the
+ * atomic state. This includes checking whether there's enough bandwidth to
+ * support the new timeslot allocations in the atomic update.
*
* Any atomic drivers supporting DP MST must make sure to call this after
* checking the rest of their state in their
* &drm_mode_config_funcs.atomic_check() callback.
*
* See also:
+ * drm_dp_mst_atomic_check_mgr()
* drm_dp_atomic_find_time_slots()
* drm_dp_atomic_release_time_slots()
*
@@ -5466,21 +5531,11 @@ int drm_dp_mst_atomic_check(struct drm_atomic_state *state)
int i, ret = 0;
for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
- if (!mgr->mst_state)
- continue;
+ struct drm_dp_mst_port *tmp_port;
- ret = drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
+ ret = drm_dp_mst_atomic_check_mgr(state, mgr, mst_state, &tmp_port);
if (ret)
break;
-
- mutex_lock(&mgr->lock);
- ret = drm_dp_mst_atomic_check_mstb_bw_limit(mgr->mst_primary,
- mst_state);
- mutex_unlock(&mgr->lock);
- if (ret < 0)
- break;
- else
- ret = 0;
}
return ret;
diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
index e44485aa74e94..a4aad6df71f18 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -916,6 +916,10 @@ int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr,
int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_port *port,
struct drm_dp_query_stream_enc_status_ack_reply *status);
+int __must_check drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_topology_state *mst_state,
+ struct drm_dp_mst_port **failing_port);
int __must_check drm_dp_mst_atomic_check(struct drm_atomic_state *state);
int __must_check drm_dp_mst_root_conn_atomic_check(struct drm_connector_state *new_conn_state,
struct drm_dp_mst_topology_mgr *mgr);
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread
* [Intel-gfx] [PATCH v4 05/30] drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 02/30] drm/dp_mst: Fix fractional DSC bpp handling Imre Deak
` (38 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
drm_dp_mst_atomic_check_mgr() should check for BW limitation starting
from sink ports continuing towards the root port, so that drivers can
use the @failing_port returned to resolve a BW overallocation in an
ideal way. For instance from streams A,B,C in a topology A,B going
through @failing_port and C not going through it, a BW overallocation of
A,B due to a limit of the port must be resolved first before considering
the limits of other ports closer to the root port. This way can avoid
reducing the BW of stream C unnecessarily due to a BW limit closer to the
root port.
Based on the above swap the order of the BW check for the root port and
the check for all the ports downstream of it (the latter going through
the topology already in the sink->root port direction).
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index a86a67d3516ff..5972c93615f18 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5469,9 +5469,13 @@ EXPORT_SYMBOL(drm_dp_mst_atomic_enable_dsc);
* - %-ENOSPC, if the new state is invalid, because of BW limitation
* @failing_port is set to:
* - The non-root port where a BW limit check failed
+ * with all the ports downstream of @failing_port passing
+ * the BW limit check.
* The returned port pointer is valid until at least
* one payload downstream of it exists.
* - %NULL if the BW limit check failed at the root port
+ * with all the ports downstream of the root port passing
+ * the BW limit check.
* - %-EINVAL, if the new state is invalid, because the root port has
* too many payloads.
*/
@@ -5487,17 +5491,16 @@ int drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state,
if (!mgr->mst_state)
return 0;
- ret = drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
- if (ret)
- return ret;
-
mutex_lock(&mgr->lock);
ret = drm_dp_mst_atomic_check_mstb_bw_limit(mgr->mst_primary,
mst_state,
failing_port);
mutex_unlock(&mgr->lock);
- return ret < 0 ? ret : 0;
+ if (ret < 0)
+ return ret;
+
+ return drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
}
EXPORT_SYMBOL(drm_dp_mst_atomic_check_mgr);
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PATCH v4 05/30] drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations
@ 2023-10-30 15:58 ` Imre Deak
0 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
drm_dp_mst_atomic_check_mgr() should check for BW limitation starting
from sink ports continuing towards the root port, so that drivers can
use the @failing_port returned to resolve a BW overallocation in an
ideal way. For instance from streams A,B,C in a topology A,B going
through @failing_port and C not going through it, a BW overallocation of
A,B due to a limit of the port must be resolved first before considering
the limits of other ports closer to the root port. This way can avoid
reducing the BW of stream C unnecessarily due to a BW limit closer to the
root port.
Based on the above swap the order of the BW check for the root port and
the check for all the ports downstream of it (the latter going through
the topology already in the sink->root port direction).
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index a86a67d3516ff..5972c93615f18 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5469,9 +5469,13 @@ EXPORT_SYMBOL(drm_dp_mst_atomic_enable_dsc);
* - %-ENOSPC, if the new state is invalid, because of BW limitation
* @failing_port is set to:
* - The non-root port where a BW limit check failed
+ * with all the ports downstream of @failing_port passing
+ * the BW limit check.
* The returned port pointer is valid until at least
* one payload downstream of it exists.
* - %NULL if the BW limit check failed at the root port
+ * with all the ports downstream of the root port passing
+ * the BW limit check.
* - %-EINVAL, if the new state is invalid, because the root port has
* too many payloads.
*/
@@ -5487,17 +5491,16 @@ int drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state,
if (!mgr->mst_state)
return 0;
- ret = drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
- if (ret)
- return ret;
-
mutex_lock(&mgr->lock);
ret = drm_dp_mst_atomic_check_mstb_bw_limit(mgr->mst_primary,
mst_state,
failing_port);
mutex_unlock(&mgr->lock);
- return ret < 0 ? ret : 0;
+ if (ret < 0)
+ return ret;
+
+ return drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
}
EXPORT_SYMBOL(drm_dp_mst_atomic_check_mgr);
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread
* [Intel-gfx] [PATCH v4 06/30] drm/dp_mst: Allow DSC in any Synaptics last branch device
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 02/30] drm/dp_mst: Fix fractional DSC bpp handling Imre Deak
` (38 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
The Synaptics MST branch devices support DSC decompression on all their
output ports, provided that they are last branch devices (with their
output ports connected to the sinks). The Thinkpad 40B0 TBT dock for
instance has two such branch devices, a secondary one connected to one
of the output ports of the primary; hence the decompression needs to be
enabled in both branch devices to enable decompression for all the
sinks.
Based on the above add support for enabling decompression in last
Synaptics branch devices.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 21 ++++++++++++-------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 5972c93615f18..cc0a8fe84d290 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5994,6 +5994,7 @@ static bool drm_dp_mst_is_virtual_dpcd(struct drm_dp_mst_port *port)
struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port)
{
struct drm_dp_mst_port *immediate_upstream_port;
+ struct drm_dp_aux *immediate_upstream_aux;
struct drm_dp_mst_port *fec_port;
struct drm_dp_desc desc = {};
u8 endpoint_fec;
@@ -6058,21 +6059,25 @@ struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port)
* - Port is on primary branch device
* - Not a VGA adapter (DP_DWN_STRM_PORT_TYPE_ANALOG)
*/
- if (drm_dp_read_desc(port->mgr->aux, &desc, true))
+ if (immediate_upstream_port)
+ immediate_upstream_aux = &immediate_upstream_port->aux;
+ else
+ immediate_upstream_aux = port->mgr->aux;
+
+ if (drm_dp_read_desc(immediate_upstream_aux, &desc, true))
return NULL;
- if (drm_dp_has_quirk(&desc, DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) &&
- port->mgr->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14 &&
- port->parent == port->mgr->mst_primary) {
+ if (drm_dp_has_quirk(&desc, DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD)) {
u8 dpcd_ext[DP_RECEIVER_CAP_SIZE];
- if (drm_dp_read_dpcd_caps(port->mgr->aux, dpcd_ext) < 0)
+ if (drm_dp_read_dpcd_caps(immediate_upstream_aux, dpcd_ext) < 0)
return NULL;
- if ((dpcd_ext[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT) &&
+ if (dpcd_ext[DP_DPCD_REV] >= DP_DPCD_REV_14 &&
+ ((dpcd_ext[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT) &&
((dpcd_ext[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK)
- != DP_DWN_STRM_PORT_TYPE_ANALOG))
- return port->mgr->aux;
+ != DP_DWN_STRM_PORT_TYPE_ANALOG)))
+ return immediate_upstream_aux;
}
/*
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PATCH v4 06/30] drm/dp_mst: Allow DSC in any Synaptics last branch device
@ 2023-10-30 15:58 ` Imre Deak
0 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Stanislav Lisovskiy, dri-devel
The Synaptics MST branch devices support DSC decompression on all their
output ports, provided that they are last branch devices (with their
output ports connected to the sinks). The Thinkpad 40B0 TBT dock for
instance has two such branch devices, a secondary one connected to one
of the output ports of the primary; hence the decompression needs to be
enabled in both branch devices to enable decompression for all the
sinks.
Based on the above add support for enabling decompression in last
Synaptics branch devices.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 21 ++++++++++++-------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 5972c93615f18..cc0a8fe84d290 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5994,6 +5994,7 @@ static bool drm_dp_mst_is_virtual_dpcd(struct drm_dp_mst_port *port)
struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port)
{
struct drm_dp_mst_port *immediate_upstream_port;
+ struct drm_dp_aux *immediate_upstream_aux;
struct drm_dp_mst_port *fec_port;
struct drm_dp_desc desc = {};
u8 endpoint_fec;
@@ -6058,21 +6059,25 @@ struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port)
* - Port is on primary branch device
* - Not a VGA adapter (DP_DWN_STRM_PORT_TYPE_ANALOG)
*/
- if (drm_dp_read_desc(port->mgr->aux, &desc, true))
+ if (immediate_upstream_port)
+ immediate_upstream_aux = &immediate_upstream_port->aux;
+ else
+ immediate_upstream_aux = port->mgr->aux;
+
+ if (drm_dp_read_desc(immediate_upstream_aux, &desc, true))
return NULL;
- if (drm_dp_has_quirk(&desc, DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) &&
- port->mgr->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14 &&
- port->parent == port->mgr->mst_primary) {
+ if (drm_dp_has_quirk(&desc, DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD)) {
u8 dpcd_ext[DP_RECEIVER_CAP_SIZE];
- if (drm_dp_read_dpcd_caps(port->mgr->aux, dpcd_ext) < 0)
+ if (drm_dp_read_dpcd_caps(immediate_upstream_aux, dpcd_ext) < 0)
return NULL;
- if ((dpcd_ext[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT) &&
+ if (dpcd_ext[DP_DPCD_REV] >= DP_DPCD_REV_14 &&
+ ((dpcd_ext[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT) &&
((dpcd_ext[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK)
- != DP_DWN_STRM_PORT_TYPE_ANALOG))
- return port->mgr->aux;
+ != DP_DWN_STRM_PORT_TYPE_ANALOG)))
+ return immediate_upstream_aux;
}
/*
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v4 06/30] drm/dp_mst: Allow DSC in any Synaptics last branch device
2023-10-30 15:58 ` Imre Deak
@ 2023-11-07 22:35 ` Lyude Paul
-1 siblings, 0 replies; 94+ messages in thread
From: Lyude Paul @ 2023-11-07 22:35 UTC (permalink / raw)
To: Imre Deak, intel-gfx; +Cc: dri-devel
Reviewed-by: Lyude Paul <lyude@redhat.com>
On Mon, 2023-10-30 at 17:58 +0200, Imre Deak wrote:
> The Synaptics MST branch devices support DSC decompression on all their
> output ports, provided that they are last branch devices (with their
> output ports connected to the sinks). The Thinkpad 40B0 TBT dock for
> instance has two such branch devices, a secondary one connected to one
> of the output ports of the primary; hence the decompression needs to be
> enabled in both branch devices to enable decompression for all the
> sinks.
>
> Based on the above add support for enabling decompression in last
> Synaptics branch devices.
>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: dri-devel@lists.freedesktop.org
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_mst_topology.c | 21 ++++++++++++-------
> 1 file changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> index 5972c93615f18..cc0a8fe84d290 100644
> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> @@ -5994,6 +5994,7 @@ static bool drm_dp_mst_is_virtual_dpcd(struct drm_dp_mst_port *port)
> struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port)
> {
> struct drm_dp_mst_port *immediate_upstream_port;
> + struct drm_dp_aux *immediate_upstream_aux;
> struct drm_dp_mst_port *fec_port;
> struct drm_dp_desc desc = {};
> u8 endpoint_fec;
> @@ -6058,21 +6059,25 @@ struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port)
> * - Port is on primary branch device
> * - Not a VGA adapter (DP_DWN_STRM_PORT_TYPE_ANALOG)
> */
> - if (drm_dp_read_desc(port->mgr->aux, &desc, true))
> + if (immediate_upstream_port)
> + immediate_upstream_aux = &immediate_upstream_port->aux;
> + else
> + immediate_upstream_aux = port->mgr->aux;
> +
> + if (drm_dp_read_desc(immediate_upstream_aux, &desc, true))
> return NULL;
>
> - if (drm_dp_has_quirk(&desc, DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) &&
> - port->mgr->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14 &&
> - port->parent == port->mgr->mst_primary) {
> + if (drm_dp_has_quirk(&desc, DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD)) {
> u8 dpcd_ext[DP_RECEIVER_CAP_SIZE];
>
> - if (drm_dp_read_dpcd_caps(port->mgr->aux, dpcd_ext) < 0)
> + if (drm_dp_read_dpcd_caps(immediate_upstream_aux, dpcd_ext) < 0)
> return NULL;
>
> - if ((dpcd_ext[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT) &&
> + if (dpcd_ext[DP_DPCD_REV] >= DP_DPCD_REV_14 &&
> + ((dpcd_ext[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT) &&
> ((dpcd_ext[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK)
> - != DP_DWN_STRM_PORT_TYPE_ANALOG))
> - return port->mgr->aux;
> + != DP_DWN_STRM_PORT_TYPE_ANALOG)))
> + return immediate_upstream_aux;
> }
>
> /*
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 06/30] drm/dp_mst: Allow DSC in any Synaptics last branch device
@ 2023-11-07 22:35 ` Lyude Paul
0 siblings, 0 replies; 94+ messages in thread
From: Lyude Paul @ 2023-11-07 22:35 UTC (permalink / raw)
To: Imre Deak, intel-gfx; +Cc: Stanislav Lisovskiy, dri-devel
Reviewed-by: Lyude Paul <lyude@redhat.com>
On Mon, 2023-10-30 at 17:58 +0200, Imre Deak wrote:
> The Synaptics MST branch devices support DSC decompression on all their
> output ports, provided that they are last branch devices (with their
> output ports connected to the sinks). The Thinkpad 40B0 TBT dock for
> instance has two such branch devices, a secondary one connected to one
> of the output ports of the primary; hence the decompression needs to be
> enabled in both branch devices to enable decompression for all the
> sinks.
>
> Based on the above add support for enabling decompression in last
> Synaptics branch devices.
>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: dri-devel@lists.freedesktop.org
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_mst_topology.c | 21 ++++++++++++-------
> 1 file changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> index 5972c93615f18..cc0a8fe84d290 100644
> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> @@ -5994,6 +5994,7 @@ static bool drm_dp_mst_is_virtual_dpcd(struct drm_dp_mst_port *port)
> struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port)
> {
> struct drm_dp_mst_port *immediate_upstream_port;
> + struct drm_dp_aux *immediate_upstream_aux;
> struct drm_dp_mst_port *fec_port;
> struct drm_dp_desc desc = {};
> u8 endpoint_fec;
> @@ -6058,21 +6059,25 @@ struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port)
> * - Port is on primary branch device
> * - Not a VGA adapter (DP_DWN_STRM_PORT_TYPE_ANALOG)
> */
> - if (drm_dp_read_desc(port->mgr->aux, &desc, true))
> + if (immediate_upstream_port)
> + immediate_upstream_aux = &immediate_upstream_port->aux;
> + else
> + immediate_upstream_aux = port->mgr->aux;
> +
> + if (drm_dp_read_desc(immediate_upstream_aux, &desc, true))
> return NULL;
>
> - if (drm_dp_has_quirk(&desc, DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) &&
> - port->mgr->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14 &&
> - port->parent == port->mgr->mst_primary) {
> + if (drm_dp_has_quirk(&desc, DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD)) {
> u8 dpcd_ext[DP_RECEIVER_CAP_SIZE];
>
> - if (drm_dp_read_dpcd_caps(port->mgr->aux, dpcd_ext) < 0)
> + if (drm_dp_read_dpcd_caps(immediate_upstream_aux, dpcd_ext) < 0)
> return NULL;
>
> - if ((dpcd_ext[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT) &&
> + if (dpcd_ext[DP_DPCD_REV] >= DP_DPCD_REV_14 &&
> + ((dpcd_ext[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT) &&
> ((dpcd_ext[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK)
> - != DP_DWN_STRM_PORT_TYPE_ANALOG))
> - return port->mgr->aux;
> + != DP_DWN_STRM_PORT_TYPE_ANALOG)))
> + return immediate_upstream_aux;
> }
>
> /*
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
^ permalink raw reply [flat|nested] 94+ messages in thread
* [Intel-gfx] [PATCH v4 07/30] drm/dp: Add DP_HBLANK_EXPANSION_CAPABLE and DSC_PASSTHROUGH_EN DPCD flags
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 02/30] drm/dp_mst: Fix fractional DSC bpp handling Imre Deak
` (38 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Add the DPCD flag to enable DSC passthrough in a last branch device,
used in a follow-up i915 patch.
Also add a flag to detect HBLANK expansion support in a branch device,
used by a workaround in a follow-up i915 patch.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
include/drm/display/drm_dp.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index e69cece404b3c..763d45a612f35 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -148,6 +148,7 @@
#define DP_RECEIVE_PORT_0_CAP_0 0x008
# define DP_LOCAL_EDID_PRESENT (1 << 1)
# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
+# define DP_HBLANK_EXPANSION_CAPABLE (1 << 3)
#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
@@ -699,6 +700,7 @@
#define DP_DSC_ENABLE 0x160 /* DP 1.4 */
# define DP_DECOMPRESSION_EN (1 << 0)
+# define DP_DSC_PASSTHROUGH_EN (1 << 1)
#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PATCH v4 07/30] drm/dp: Add DP_HBLANK_EXPANSION_CAPABLE and DSC_PASSTHROUGH_EN DPCD flags
@ 2023-10-30 15:58 ` Imre Deak
0 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Stanislav Lisovskiy, dri-devel
Add the DPCD flag to enable DSC passthrough in a last branch device,
used in a follow-up i915 patch.
Also add a flag to detect HBLANK expansion support in a branch device,
used by a workaround in a follow-up i915 patch.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
include/drm/display/drm_dp.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index e69cece404b3c..763d45a612f35 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -148,6 +148,7 @@
#define DP_RECEIVE_PORT_0_CAP_0 0x008
# define DP_LOCAL_EDID_PRESENT (1 << 1)
# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
+# define DP_HBLANK_EXPANSION_CAPABLE (1 << 3)
#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
@@ -699,6 +700,7 @@
#define DP_DSC_ENABLE 0x160 /* DP 1.4 */
# define DP_DECOMPRESSION_EN (1 << 0)
+# define DP_DSC_PASSTHROUGH_EN (1 << 1)
#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread
* Re: [Intel-gfx] [PATCH v4 07/30] drm/dp: Add DP_HBLANK_EXPANSION_CAPABLE and DSC_PASSTHROUGH_EN DPCD flags
2023-10-30 15:58 ` Imre Deak
@ 2023-11-07 22:35 ` Lyude Paul
-1 siblings, 0 replies; 94+ messages in thread
From: Lyude Paul @ 2023-11-07 22:35 UTC (permalink / raw)
To: Imre Deak, intel-gfx; +Cc: dri-devel
Reviewed-by: Lyude Paul <lyude@redhat.com>
On Mon, 2023-10-30 at 17:58 +0200, Imre Deak wrote:
> Add the DPCD flag to enable DSC passthrough in a last branch device,
> used in a follow-up i915 patch.
>
> Also add a flag to detect HBLANK expansion support in a branch device,
> used by a workaround in a follow-up i915 patch.
>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: dri-devel@lists.freedesktop.org
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> include/drm/display/drm_dp.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index e69cece404b3c..763d45a612f35 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -148,6 +148,7 @@
> #define DP_RECEIVE_PORT_0_CAP_0 0x008
> # define DP_LOCAL_EDID_PRESENT (1 << 1)
> # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
> +# define DP_HBLANK_EXPANSION_CAPABLE (1 << 3)
>
> #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
>
> @@ -699,6 +700,7 @@
>
> #define DP_DSC_ENABLE 0x160 /* DP 1.4 */
> # define DP_DECOMPRESSION_EN (1 << 0)
> +# define DP_DSC_PASSTHROUGH_EN (1 << 1)
> #define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
>
> #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 07/30] drm/dp: Add DP_HBLANK_EXPANSION_CAPABLE and DSC_PASSTHROUGH_EN DPCD flags
@ 2023-11-07 22:35 ` Lyude Paul
0 siblings, 0 replies; 94+ messages in thread
From: Lyude Paul @ 2023-11-07 22:35 UTC (permalink / raw)
To: Imre Deak, intel-gfx; +Cc: Stanislav Lisovskiy, dri-devel
Reviewed-by: Lyude Paul <lyude@redhat.com>
On Mon, 2023-10-30 at 17:58 +0200, Imre Deak wrote:
> Add the DPCD flag to enable DSC passthrough in a last branch device,
> used in a follow-up i915 patch.
>
> Also add a flag to detect HBLANK expansion support in a branch device,
> used by a workaround in a follow-up i915 patch.
>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: dri-devel@lists.freedesktop.org
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> include/drm/display/drm_dp.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index e69cece404b3c..763d45a612f35 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -148,6 +148,7 @@
> #define DP_RECEIVE_PORT_0_CAP_0 0x008
> # define DP_LOCAL_EDID_PRESENT (1 << 1)
> # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
> +# define DP_HBLANK_EXPANSION_CAPABLE (1 << 3)
>
> #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
>
> @@ -699,6 +700,7 @@
>
> #define DP_DSC_ENABLE 0x160 /* DP 1.4 */
> # define DP_DECOMPRESSION_EN (1 << 0)
> +# define DP_DSC_PASSTHROUGH_EN (1 << 1)
> #define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
>
> #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
^ permalink raw reply [flat|nested] 94+ messages in thread
* [Intel-gfx] [PATCH v4 08/30] drm/dp_mst: Add HBLANK expansion quirk for Synaptics MST hubs
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 02/30] drm/dp_mst: Fix fractional DSC bpp handling Imre Deak
` (38 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Add a quirk for Synaptics MST hubs, which require a workaround - at leat
on i915 - for some modes, on which the hub applies HBLANK expansion.
These modes will only work by enabling DSC decompression for them, a
follow-up patch will do this in i915.
v2:
- Fix the quirk name in its DocBook description.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_helper.c | 2 ++
include/drm/display/drm_dp_helper.h | 7 +++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index f3680f4e69708..e5d7970a9ddd0 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2245,6 +2245,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
{ OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
/* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
+ /* Synaptics DP1.4 MST hubs require DSC for some modes on which it applies HBLANK expansion. */
+ { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
/* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
{ OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
};
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index 3d74b2cec72fd..da94932f4262b 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -632,6 +632,13 @@ enum drm_dp_quirk {
* the DP_MAX_LINK_RATE register reporting a lower max multiplier.
*/
DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
+ /**
+ * @DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC:
+ *
+ * The device applies HBLANK expansion for some modes, but this
+ * requires enabling DSC.
+ */
+ DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC,
};
/**
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PATCH v4 08/30] drm/dp_mst: Add HBLANK expansion quirk for Synaptics MST hubs
@ 2023-10-30 15:58 ` Imre Deak
0 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Stanislav Lisovskiy, dri-devel
Add a quirk for Synaptics MST hubs, which require a workaround - at leat
on i915 - for some modes, on which the hub applies HBLANK expansion.
These modes will only work by enabling DSC decompression for them, a
follow-up patch will do this in i915.
v2:
- Fix the quirk name in its DocBook description.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_helper.c | 2 ++
include/drm/display/drm_dp_helper.h | 7 +++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index f3680f4e69708..e5d7970a9ddd0 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2245,6 +2245,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
{ OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
/* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
+ /* Synaptics DP1.4 MST hubs require DSC for some modes on which it applies HBLANK expansion. */
+ { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
/* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
{ OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
};
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index 3d74b2cec72fd..da94932f4262b 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -632,6 +632,13 @@ enum drm_dp_quirk {
* the DP_MAX_LINK_RATE register reporting a lower max multiplier.
*/
DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
+ /**
+ * @DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC:
+ *
+ * The device applies HBLANK expansion for some modes, but this
+ * requires enabling DSC.
+ */
+ DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC,
};
/**
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v4 08/30] drm/dp_mst: Add HBLANK expansion quirk for Synaptics MST hubs
2023-10-30 15:58 ` Imre Deak
@ 2023-11-07 22:37 ` Lyude Paul
-1 siblings, 0 replies; 94+ messages in thread
From: Lyude Paul @ 2023-11-07 22:37 UTC (permalink / raw)
To: Imre Deak, intel-gfx; +Cc: dri-devel
Reviewed-by: Lyude Paul <lyude@redhat.com>
On Mon, 2023-10-30 at 17:58 +0200, Imre Deak wrote:
> Add a quirk for Synaptics MST hubs, which require a workaround - at leat
> on i915 - for some modes, on which the hub applies HBLANK expansion.
> These modes will only work by enabling DSC decompression for them, a
> follow-up patch will do this in i915.
>
> v2:
> - Fix the quirk name in its DocBook description.
>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: dri-devel@lists.freedesktop.org
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 2 ++
> include/drm/display/drm_dp_helper.h | 7 +++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> index f3680f4e69708..e5d7970a9ddd0 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -2245,6 +2245,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
> { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
> /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
> { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
> + /* Synaptics DP1.4 MST hubs require DSC for some modes on which it applies HBLANK expansion. */
> + { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
> /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
> { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
> };
> diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> index 3d74b2cec72fd..da94932f4262b 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -632,6 +632,13 @@ enum drm_dp_quirk {
> * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
> */
> DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
> + /**
> + * @DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC:
> + *
> + * The device applies HBLANK expansion for some modes, but this
> + * requires enabling DSC.
> + */
> + DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC,
> };
>
> /**
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 08/30] drm/dp_mst: Add HBLANK expansion quirk for Synaptics MST hubs
@ 2023-11-07 22:37 ` Lyude Paul
0 siblings, 0 replies; 94+ messages in thread
From: Lyude Paul @ 2023-11-07 22:37 UTC (permalink / raw)
To: Imre Deak, intel-gfx; +Cc: Stanislav Lisovskiy, dri-devel
Reviewed-by: Lyude Paul <lyude@redhat.com>
On Mon, 2023-10-30 at 17:58 +0200, Imre Deak wrote:
> Add a quirk for Synaptics MST hubs, which require a workaround - at leat
> on i915 - for some modes, on which the hub applies HBLANK expansion.
> These modes will only work by enabling DSC decompression for them, a
> follow-up patch will do this in i915.
>
> v2:
> - Fix the quirk name in its DocBook description.
>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: dri-devel@lists.freedesktop.org
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 2 ++
> include/drm/display/drm_dp_helper.h | 7 +++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> index f3680f4e69708..e5d7970a9ddd0 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -2245,6 +2245,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
> { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
> /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
> { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
> + /* Synaptics DP1.4 MST hubs require DSC for some modes on which it applies HBLANK expansion. */
> + { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
> /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
> { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
> };
> diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> index 3d74b2cec72fd..da94932f4262b 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -632,6 +632,13 @@ enum drm_dp_quirk {
> * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
> */
> DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
> + /**
> + * @DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC:
> + *
> + * The device applies HBLANK expansion for some modes, but this
> + * requires enabling DSC.
> + */
> + DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC,
> };
>
> /**
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
^ permalink raw reply [flat|nested] 94+ messages in thread
* [Intel-gfx] [PATCH v4 09/30] drm/dp: Add helpers to calculate the link BW overhead
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 02/30] drm/dp_mst: Fix fractional DSC bpp handling Imre Deak
` (38 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Add helpers drivers can use to calculate the BW allocation overhead -
due to SSC, FEC, DSC and data alignment on symbol cycles - and the
channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On
128b/132b links the FEC overhead is part of the coding efficiency, so
not accounted for in the BW allocation overhead.
The drivers can use these functions to calculate a ratio, controlling
the stream symbol insertion rate of the source device in each SST TU
or MST MTP frame. Drivers can calculate this
m/n = (pixel_data_rate * drm_dp_bw_overhead()) /
(link_data_rate * drm_dp_bw_channel_coding_efficiency())
ratio for a given link and pixel stream and with that the
mtp_count = CEIL(64 * m / n)
allocated MTPs for the stream in a link frame and
pbn = CEIL(64 * dm_mst_get_pbn_divider() * m / n)
allocated PBNs for the stream on the MST link path.
Take drm_dp_bw_overhead() into use in drm_dp_calc_pbn_mode(), for
drivers calculating the PBN value directly.
v2:
- Add dockbook description to drm_dp_bw_channel_coding_efficiency().
(LKP).
- Clarify the way m/n ratio is calculated in the commit log.
v3:
- Fix compile breakage for !CONFIG_BACKLIGHT_CLASS_DEVICE. (LKP)
- Account for FEC_PM overhead (+ 0.0015625 %), add comment
with the formula to calculate the total FEC overhead. (Ville)
v4:
- Rename DRM_DP_OVERHEAD_SSC to DRM_DP_OVERHEAD_SSC_REF_CLK. (Ville)
Cc: Lyude Paul <lyude@redhat.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: kernel test robot <lkp@intel.com>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_helper.c | 132 ++++++++++++++++++
drivers/gpu/drm/display/drm_dp_mst_topology.c | 23 ++-
include/drm/display/drm_dp_helper.h | 11 ++
3 files changed, 160 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index e5d7970a9ddd0..72ba9ae89f862 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -3900,3 +3900,135 @@ int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
#endif
+
+/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
+static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
+ int symbol_size, bool is_mst)
+{
+ int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
+ int align = is_mst ? 4 / lane_count : 1;
+
+ return ALIGN(cycles, align);
+}
+
+static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,
+ int bpp_x16, int symbol_size, bool is_mst)
+{
+ int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
+ int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,
+ bpp_x16, symbol_size, is_mst);
+ int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
+
+ return slice_count * (slice_data_cycles + slice_eoc_cycles);
+}
+
+/**
+ * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
+ * @lane_count: DP link lane count
+ * @hactive: pixel count of the active period in one scanline of the stream
+ * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set
+ * @bpp_x16: bits per pixel in .4 binary fixed point
+ * @flags: DRM_DP_OVERHEAD_x flags
+ *
+ * Calculate the BW allocation overhead of a DP link stream, depending
+ * on the link's
+ * - @lane_count
+ * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
+ * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
+ * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
+ * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
+ * as well as the stream's
+ * - @hactive timing
+ * - @bpp_x16 color depth
+ * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).
+ * Note that this overhead doesn't account for the 8b/10b, 128b/132b
+ * channel coding efficiency, for that see
+ * @drm_dp_link_bw_channel_coding_efficiency().
+ *
+ * Returns the overhead as 100% + overhead% in 1ppm units.
+ */
+int drm_dp_bw_overhead(int lane_count, int hactive,
+ int dsc_slice_count,
+ int bpp_x16, unsigned long flags)
+{
+ int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8;
+ bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;
+ u32 overhead = 1000000;
+ int symbol_cycles;
+
+ /*
+ * DP Standard v2.1 2.6.4.1
+ * SSC downspread and ref clock variation margin:
+ * 5300ppm + 300ppm ~ 0.6%
+ */
+ if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK)
+ overhead += 6000;
+
+ /*
+ * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4:
+ * FEC symbol insertions for 8b/10b channel coding:
+ * After each 250 data symbols on 2-4 lanes:
+ * 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block)
+ * After each 2 x 250 data symbols on 1 lane:
+ * 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block)
+ * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks:
+ * 256 * 256 bytes + 1 FEC_PM
+ * or
+ * 128 * 512 bytes + 1 FEC_PM
+ * (256 * 6 + 1) / (256 * 250) = 2.4015625 %
+ */
+ if (flags & DRM_DP_BW_OVERHEAD_FEC)
+ overhead += 24016;
+
+ /*
+ * DP Standard v2.1 2.7.9, 5.9.7
+ * The FEC overhead for UHBR is accounted for in its 96.71% channel
+ * coding efficiency.
+ */
+ WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
+ (flags & DRM_DP_BW_OVERHEAD_FEC));
+
+ if (flags & DRM_DP_BW_OVERHEAD_DSC)
+ symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,
+ dsc_slice_count,
+ bpp_x16, symbol_size,
+ is_mst);
+ else
+ symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
+ bpp_x16, symbol_size,
+ is_mst);
+
+ return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
+ overhead * 16),
+ hactive * bpp_x16);
+}
+EXPORT_SYMBOL(drm_dp_bw_overhead);
+
+/**
+ * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
+ * @is_uhbr: Whether the link has a 128b/132b channel coding
+ *
+ * Return the channel coding efficiency of the given DP link type, which is
+ * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes
+ * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
+ * and for 128b/132b any link or PHY level control symbol insertion overhead
+ * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the
+ * corresponding FEC overhead is BW allocation specific, included in the value
+ * returned by drm_dp_bw_overhead().
+ *
+ * Returns the efficiency in the 100%/coding-overhead% ratio in
+ * 1ppm units.
+ */
+int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
+{
+ if (is_uhbr)
+ return 967100;
+ else
+ /*
+ * Note that on 8b/10b MST the efficiency is only
+ * 78.75% due to the 1 out of 64 MTPH packet overhead,
+ * not accounted for here.
+ */
+ return 800000;
+}
+EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index cc0a8fe84d290..4d72c9a32026e 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -4726,17 +4726,28 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
int drm_dp_calc_pbn_mode(int clock, int bpp)
{
/*
- * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
* The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
* common multiplier to render an integer PBN for all link rate/lane
* counts combinations
* calculate
- * peak_kbps *= (1006/1000)
- * peak_kbps *= (64/54)
- * peak_kbps *= 8 convert to bytes
+ * peak_kbps = clock * bpp / 16
+ * peak_kbps *= SSC overhead / 1000000
+ * peak_kbps /= 8 convert to Kbytes
+ * peak_kBps *= (64/54) / 1000 convert to PBN
*/
- return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
- 1000 * 8 * 54 * 1000);
+ /*
+ * TODO: Use the actual link and mode parameters to calculate
+ * the overhead. For now it's assumed that these are
+ * 4 link lanes, 4096 hactive pixels, which don't add any
+ * significant data padding overhead and that there is no DSC
+ * or FEC overhead.
+ */
+ int overhead = drm_dp_bw_overhead(4, 4096, 0, bpp,
+ DRM_DP_BW_OVERHEAD_MST |
+ DRM_DP_BW_OVERHEAD_SSC_REF_CLK);
+
+ return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),
+ 1000000ULL * 8 * 54 * 1000);
}
EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index da94932f4262b..caee29d28463c 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -788,4 +788,15 @@ bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZ
const u8 port_cap[4], u8 color_spc);
int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
+#define DRM_DP_BW_OVERHEAD_MST BIT(0)
+#define DRM_DP_BW_OVERHEAD_UHBR BIT(1)
+#define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2)
+#define DRM_DP_BW_OVERHEAD_FEC BIT(3)
+#define DRM_DP_BW_OVERHEAD_DSC BIT(4)
+
+int drm_dp_bw_overhead(int lane_count, int hactive,
+ int dsc_slice_count,
+ int bpp_x16, unsigned long flags);
+int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
+
#endif /* _DRM_DP_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PATCH v4 09/30] drm/dp: Add helpers to calculate the link BW overhead
@ 2023-10-30 15:58 ` Imre Deak
0 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Stanislav Lisovskiy, dri-devel, kernel test robot
Add helpers drivers can use to calculate the BW allocation overhead -
due to SSC, FEC, DSC and data alignment on symbol cycles - and the
channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On
128b/132b links the FEC overhead is part of the coding efficiency, so
not accounted for in the BW allocation overhead.
The drivers can use these functions to calculate a ratio, controlling
the stream symbol insertion rate of the source device in each SST TU
or MST MTP frame. Drivers can calculate this
m/n = (pixel_data_rate * drm_dp_bw_overhead()) /
(link_data_rate * drm_dp_bw_channel_coding_efficiency())
ratio for a given link and pixel stream and with that the
mtp_count = CEIL(64 * m / n)
allocated MTPs for the stream in a link frame and
pbn = CEIL(64 * dm_mst_get_pbn_divider() * m / n)
allocated PBNs for the stream on the MST link path.
Take drm_dp_bw_overhead() into use in drm_dp_calc_pbn_mode(), for
drivers calculating the PBN value directly.
v2:
- Add dockbook description to drm_dp_bw_channel_coding_efficiency().
(LKP).
- Clarify the way m/n ratio is calculated in the commit log.
v3:
- Fix compile breakage for !CONFIG_BACKLIGHT_CLASS_DEVICE. (LKP)
- Account for FEC_PM overhead (+ 0.0015625 %), add comment
with the formula to calculate the total FEC overhead. (Ville)
v4:
- Rename DRM_DP_OVERHEAD_SSC to DRM_DP_OVERHEAD_SSC_REF_CLK. (Ville)
Cc: Lyude Paul <lyude@redhat.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: kernel test robot <lkp@intel.com>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_helper.c | 132 ++++++++++++++++++
drivers/gpu/drm/display/drm_dp_mst_topology.c | 23 ++-
include/drm/display/drm_dp_helper.h | 11 ++
3 files changed, 160 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index e5d7970a9ddd0..72ba9ae89f862 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -3900,3 +3900,135 @@ int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
#endif
+
+/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
+static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
+ int symbol_size, bool is_mst)
+{
+ int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
+ int align = is_mst ? 4 / lane_count : 1;
+
+ return ALIGN(cycles, align);
+}
+
+static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,
+ int bpp_x16, int symbol_size, bool is_mst)
+{
+ int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
+ int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,
+ bpp_x16, symbol_size, is_mst);
+ int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
+
+ return slice_count * (slice_data_cycles + slice_eoc_cycles);
+}
+
+/**
+ * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
+ * @lane_count: DP link lane count
+ * @hactive: pixel count of the active period in one scanline of the stream
+ * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set
+ * @bpp_x16: bits per pixel in .4 binary fixed point
+ * @flags: DRM_DP_OVERHEAD_x flags
+ *
+ * Calculate the BW allocation overhead of a DP link stream, depending
+ * on the link's
+ * - @lane_count
+ * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
+ * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
+ * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
+ * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
+ * as well as the stream's
+ * - @hactive timing
+ * - @bpp_x16 color depth
+ * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).
+ * Note that this overhead doesn't account for the 8b/10b, 128b/132b
+ * channel coding efficiency, for that see
+ * @drm_dp_link_bw_channel_coding_efficiency().
+ *
+ * Returns the overhead as 100% + overhead% in 1ppm units.
+ */
+int drm_dp_bw_overhead(int lane_count, int hactive,
+ int dsc_slice_count,
+ int bpp_x16, unsigned long flags)
+{
+ int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8;
+ bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;
+ u32 overhead = 1000000;
+ int symbol_cycles;
+
+ /*
+ * DP Standard v2.1 2.6.4.1
+ * SSC downspread and ref clock variation margin:
+ * 5300ppm + 300ppm ~ 0.6%
+ */
+ if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK)
+ overhead += 6000;
+
+ /*
+ * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4:
+ * FEC symbol insertions for 8b/10b channel coding:
+ * After each 250 data symbols on 2-4 lanes:
+ * 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block)
+ * After each 2 x 250 data symbols on 1 lane:
+ * 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block)
+ * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks:
+ * 256 * 256 bytes + 1 FEC_PM
+ * or
+ * 128 * 512 bytes + 1 FEC_PM
+ * (256 * 6 + 1) / (256 * 250) = 2.4015625 %
+ */
+ if (flags & DRM_DP_BW_OVERHEAD_FEC)
+ overhead += 24016;
+
+ /*
+ * DP Standard v2.1 2.7.9, 5.9.7
+ * The FEC overhead for UHBR is accounted for in its 96.71% channel
+ * coding efficiency.
+ */
+ WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
+ (flags & DRM_DP_BW_OVERHEAD_FEC));
+
+ if (flags & DRM_DP_BW_OVERHEAD_DSC)
+ symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,
+ dsc_slice_count,
+ bpp_x16, symbol_size,
+ is_mst);
+ else
+ symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
+ bpp_x16, symbol_size,
+ is_mst);
+
+ return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
+ overhead * 16),
+ hactive * bpp_x16);
+}
+EXPORT_SYMBOL(drm_dp_bw_overhead);
+
+/**
+ * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
+ * @is_uhbr: Whether the link has a 128b/132b channel coding
+ *
+ * Return the channel coding efficiency of the given DP link type, which is
+ * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes
+ * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
+ * and for 128b/132b any link or PHY level control symbol insertion overhead
+ * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the
+ * corresponding FEC overhead is BW allocation specific, included in the value
+ * returned by drm_dp_bw_overhead().
+ *
+ * Returns the efficiency in the 100%/coding-overhead% ratio in
+ * 1ppm units.
+ */
+int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
+{
+ if (is_uhbr)
+ return 967100;
+ else
+ /*
+ * Note that on 8b/10b MST the efficiency is only
+ * 78.75% due to the 1 out of 64 MTPH packet overhead,
+ * not accounted for here.
+ */
+ return 800000;
+}
+EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index cc0a8fe84d290..4d72c9a32026e 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -4726,17 +4726,28 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
int drm_dp_calc_pbn_mode(int clock, int bpp)
{
/*
- * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
* The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
* common multiplier to render an integer PBN for all link rate/lane
* counts combinations
* calculate
- * peak_kbps *= (1006/1000)
- * peak_kbps *= (64/54)
- * peak_kbps *= 8 convert to bytes
+ * peak_kbps = clock * bpp / 16
+ * peak_kbps *= SSC overhead / 1000000
+ * peak_kbps /= 8 convert to Kbytes
+ * peak_kBps *= (64/54) / 1000 convert to PBN
*/
- return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
- 1000 * 8 * 54 * 1000);
+ /*
+ * TODO: Use the actual link and mode parameters to calculate
+ * the overhead. For now it's assumed that these are
+ * 4 link lanes, 4096 hactive pixels, which don't add any
+ * significant data padding overhead and that there is no DSC
+ * or FEC overhead.
+ */
+ int overhead = drm_dp_bw_overhead(4, 4096, 0, bpp,
+ DRM_DP_BW_OVERHEAD_MST |
+ DRM_DP_BW_OVERHEAD_SSC_REF_CLK);
+
+ return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),
+ 1000000ULL * 8 * 54 * 1000);
}
EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index da94932f4262b..caee29d28463c 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -788,4 +788,15 @@ bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZ
const u8 port_cap[4], u8 color_spc);
int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
+#define DRM_DP_BW_OVERHEAD_MST BIT(0)
+#define DRM_DP_BW_OVERHEAD_UHBR BIT(1)
+#define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2)
+#define DRM_DP_BW_OVERHEAD_FEC BIT(3)
+#define DRM_DP_BW_OVERHEAD_DSC BIT(4)
+
+int drm_dp_bw_overhead(int lane_count, int hactive,
+ int dsc_slice_count,
+ int bpp_x16, unsigned long flags);
+int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
+
#endif /* _DRM_DP_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v4 09/30] drm/dp: Add helpers to calculate the link BW overhead
2023-10-30 15:58 ` Imre Deak
@ 2023-11-06 21:31 ` Ville Syrjälä
-1 siblings, 0 replies; 94+ messages in thread
From: Ville Syrjälä @ 2023-11-06 21:31 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, dri-devel
On Mon, Oct 30, 2023 at 05:58:22PM +0200, Imre Deak wrote:
> Add helpers drivers can use to calculate the BW allocation overhead -
> due to SSC, FEC, DSC and data alignment on symbol cycles - and the
> channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On
> 128b/132b links the FEC overhead is part of the coding efficiency, so
> not accounted for in the BW allocation overhead.
>
> The drivers can use these functions to calculate a ratio, controlling
> the stream symbol insertion rate of the source device in each SST TU
> or MST MTP frame. Drivers can calculate this
>
> m/n = (pixel_data_rate * drm_dp_bw_overhead()) /
> (link_data_rate * drm_dp_bw_channel_coding_efficiency())
>
> ratio for a given link and pixel stream and with that the
>
> mtp_count = CEIL(64 * m / n)
>
> allocated MTPs for the stream in a link frame and
>
> pbn = CEIL(64 * dm_mst_get_pbn_divider() * m / n)
>
> allocated PBNs for the stream on the MST link path.
>
> Take drm_dp_bw_overhead() into use in drm_dp_calc_pbn_mode(), for
> drivers calculating the PBN value directly.
>
> v2:
> - Add dockbook description to drm_dp_bw_channel_coding_efficiency().
> (LKP).
> - Clarify the way m/n ratio is calculated in the commit log.
> v3:
> - Fix compile breakage for !CONFIG_BACKLIGHT_CLASS_DEVICE. (LKP)
> - Account for FEC_PM overhead (+ 0.0015625 %), add comment
> with the formula to calculate the total FEC overhead. (Ville)
> v4:
> - Rename DRM_DP_OVERHEAD_SSC to DRM_DP_OVERHEAD_SSC_REF_CLK. (Ville)
>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: kernel test robot <lkp@intel.com>
> Cc: dri-devel@lists.freedesktop.org
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v2)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 132 ++++++++++++++++++
> drivers/gpu/drm/display/drm_dp_mst_topology.c | 23 ++-
> include/drm/display/drm_dp_helper.h | 11 ++
> 3 files changed, 160 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> index e5d7970a9ddd0..72ba9ae89f862 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -3900,3 +3900,135 @@ int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
> EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
>
> #endif
> +
> +/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
> +static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
> + int symbol_size, bool is_mst)
> +{
> + int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
> + int align = is_mst ? 4 / lane_count : 1;
> +
> + return ALIGN(cycles, align);
> +}
> +
> +static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,
> + int bpp_x16, int symbol_size, bool is_mst)
> +{
> + int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
> + int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,
> + bpp_x16, symbol_size, is_mst);
> + int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
> +
> + return slice_count * (slice_data_cycles + slice_eoc_cycles);
> +}
> +
> +/**
> + * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
> + * @lane_count: DP link lane count
> + * @hactive: pixel count of the active period in one scanline of the stream
> + * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set
> + * @bpp_x16: bits per pixel in .4 binary fixed point
> + * @flags: DRM_DP_OVERHEAD_x flags
> + *
> + * Calculate the BW allocation overhead of a DP link stream, depending
> + * on the link's
> + * - @lane_count
> + * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
> + * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
> + * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
> + * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
> + * as well as the stream's
> + * - @hactive timing
> + * - @bpp_x16 color depth
> + * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).
> + * Note that this overhead doesn't account for the 8b/10b, 128b/132b
> + * channel coding efficiency, for that see
> + * @drm_dp_link_bw_channel_coding_efficiency().
> + *
> + * Returns the overhead as 100% + overhead% in 1ppm units.
> + */
> +int drm_dp_bw_overhead(int lane_count, int hactive,
> + int dsc_slice_count,
> + int bpp_x16, unsigned long flags)
> +{
> + int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8;
> + bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;
> + u32 overhead = 1000000;
> + int symbol_cycles;
> +
> + /*
> + * DP Standard v2.1 2.6.4.1
> + * SSC downspread and ref clock variation margin:
> + * 5300ppm + 300ppm ~ 0.6%
> + */
> + if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK)
> + overhead += 6000;
> +
> + /*
> + * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4:
> + * FEC symbol insertions for 8b/10b channel coding:
> + * After each 250 data symbols on 2-4 lanes:
> + * 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block)
> + * After each 2 x 250 data symbols on 1 lane:
> + * 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block)
> + * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks:
> + * 256 * 256 bytes + 1 FEC_PM
> + * or
> + * 128 * 512 bytes + 1 FEC_PM
> + * (256 * 6 + 1) / (256 * 250) = 2.4015625 %
> + */
> + if (flags & DRM_DP_BW_OVERHEAD_FEC)
> + overhead += 24016;
Hmm. Shouldn't we be multiplying the overheads, not add them up?
Though I suppose in this case the error won't be huge.
> +
> + /*
> + * DP Standard v2.1 2.7.9, 5.9.7
> + * The FEC overhead for UHBR is accounted for in its 96.71% channel
> + * coding efficiency.
> + */
> + WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
> + (flags & DRM_DP_BW_OVERHEAD_FEC));
> +
> + if (flags & DRM_DP_BW_OVERHEAD_DSC)
> + symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,
> + dsc_slice_count,
> + bpp_x16, symbol_size,
> + is_mst);
> + else
> + symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
> + bpp_x16, symbol_size,
> + is_mst);
> +
> + return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
> + overhead * 16),
> + hactive * bpp_x16);
> +}
> +EXPORT_SYMBOL(drm_dp_bw_overhead);
> +
> +/**
> + * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
> + * @is_uhbr: Whether the link has a 128b/132b channel coding
> + *
> + * Return the channel coding efficiency of the given DP link type, which is
> + * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes
> + * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
> + * and for 128b/132b any link or PHY level control symbol insertion overhead
> + * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the
> + * corresponding FEC overhead is BW allocation specific, included in the value
> + * returned by drm_dp_bw_overhead().
> + *
> + * Returns the efficiency in the 100%/coding-overhead% ratio in
> + * 1ppm units.
> + */
> +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
> +{
> + if (is_uhbr)
> + return 967100;
> + else
> + /*
> + * Note that on 8b/10b MST the efficiency is only
> + * 78.75% due to the 1 out of 64 MTPH packet overhead,
> + * not accounted for here.
> + */
> + return 800000;
> +}
> +EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> index cc0a8fe84d290..4d72c9a32026e 100644
> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> @@ -4726,17 +4726,28 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
> int drm_dp_calc_pbn_mode(int clock, int bpp)
> {
> /*
> - * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
> * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
> * common multiplier to render an integer PBN for all link rate/lane
> * counts combinations
> * calculate
> - * peak_kbps *= (1006/1000)
> - * peak_kbps *= (64/54)
> - * peak_kbps *= 8 convert to bytes
> + * peak_kbps = clock * bpp / 16
> + * peak_kbps *= SSC overhead / 1000000
> + * peak_kbps /= 8 convert to Kbytes
> + * peak_kBps *= (64/54) / 1000 convert to PBN
> */
> - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
> - 1000 * 8 * 54 * 1000);
> + /*
> + * TODO: Use the actual link and mode parameters to calculate
> + * the overhead. For now it's assumed that these are
> + * 4 link lanes, 4096 hactive pixels, which don't add any
> + * significant data padding overhead and that there is no DSC
> + * or FEC overhead.
> + */
> + int overhead = drm_dp_bw_overhead(4, 4096, 0, bpp,
> + DRM_DP_BW_OVERHEAD_MST |
> + DRM_DP_BW_OVERHEAD_SSC_REF_CLK);
> +
> + return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),
> + 1000000ULL * 8 * 54 * 1000);
> }
> EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
>
> diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> index da94932f4262b..caee29d28463c 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -788,4 +788,15 @@ bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZ
> const u8 port_cap[4], u8 color_spc);
> int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
>
> +#define DRM_DP_BW_OVERHEAD_MST BIT(0)
> +#define DRM_DP_BW_OVERHEAD_UHBR BIT(1)
> +#define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2)
> +#define DRM_DP_BW_OVERHEAD_FEC BIT(3)
> +#define DRM_DP_BW_OVERHEAD_DSC BIT(4)
> +
> +int drm_dp_bw_overhead(int lane_count, int hactive,
> + int dsc_slice_count,
> + int bpp_x16, unsigned long flags);
> +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
> +
> #endif /* _DRM_DP_HELPER_H_ */
> --
> 2.39.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 09/30] drm/dp: Add helpers to calculate the link BW overhead
@ 2023-11-06 21:31 ` Ville Syrjälä
0 siblings, 0 replies; 94+ messages in thread
From: Ville Syrjälä @ 2023-11-06 21:31 UTC (permalink / raw)
To: Imre Deak; +Cc: Stanislav Lisovskiy, intel-gfx, kernel test robot, dri-devel
On Mon, Oct 30, 2023 at 05:58:22PM +0200, Imre Deak wrote:
> Add helpers drivers can use to calculate the BW allocation overhead -
> due to SSC, FEC, DSC and data alignment on symbol cycles - and the
> channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On
> 128b/132b links the FEC overhead is part of the coding efficiency, so
> not accounted for in the BW allocation overhead.
>
> The drivers can use these functions to calculate a ratio, controlling
> the stream symbol insertion rate of the source device in each SST TU
> or MST MTP frame. Drivers can calculate this
>
> m/n = (pixel_data_rate * drm_dp_bw_overhead()) /
> (link_data_rate * drm_dp_bw_channel_coding_efficiency())
>
> ratio for a given link and pixel stream and with that the
>
> mtp_count = CEIL(64 * m / n)
>
> allocated MTPs for the stream in a link frame and
>
> pbn = CEIL(64 * dm_mst_get_pbn_divider() * m / n)
>
> allocated PBNs for the stream on the MST link path.
>
> Take drm_dp_bw_overhead() into use in drm_dp_calc_pbn_mode(), for
> drivers calculating the PBN value directly.
>
> v2:
> - Add dockbook description to drm_dp_bw_channel_coding_efficiency().
> (LKP).
> - Clarify the way m/n ratio is calculated in the commit log.
> v3:
> - Fix compile breakage for !CONFIG_BACKLIGHT_CLASS_DEVICE. (LKP)
> - Account for FEC_PM overhead (+ 0.0015625 %), add comment
> with the formula to calculate the total FEC overhead. (Ville)
> v4:
> - Rename DRM_DP_OVERHEAD_SSC to DRM_DP_OVERHEAD_SSC_REF_CLK. (Ville)
>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: kernel test robot <lkp@intel.com>
> Cc: dri-devel@lists.freedesktop.org
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v2)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 132 ++++++++++++++++++
> drivers/gpu/drm/display/drm_dp_mst_topology.c | 23 ++-
> include/drm/display/drm_dp_helper.h | 11 ++
> 3 files changed, 160 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> index e5d7970a9ddd0..72ba9ae89f862 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -3900,3 +3900,135 @@ int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
> EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
>
> #endif
> +
> +/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
> +static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
> + int symbol_size, bool is_mst)
> +{
> + int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
> + int align = is_mst ? 4 / lane_count : 1;
> +
> + return ALIGN(cycles, align);
> +}
> +
> +static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,
> + int bpp_x16, int symbol_size, bool is_mst)
> +{
> + int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
> + int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,
> + bpp_x16, symbol_size, is_mst);
> + int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
> +
> + return slice_count * (slice_data_cycles + slice_eoc_cycles);
> +}
> +
> +/**
> + * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
> + * @lane_count: DP link lane count
> + * @hactive: pixel count of the active period in one scanline of the stream
> + * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set
> + * @bpp_x16: bits per pixel in .4 binary fixed point
> + * @flags: DRM_DP_OVERHEAD_x flags
> + *
> + * Calculate the BW allocation overhead of a DP link stream, depending
> + * on the link's
> + * - @lane_count
> + * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
> + * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
> + * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
> + * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
> + * as well as the stream's
> + * - @hactive timing
> + * - @bpp_x16 color depth
> + * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).
> + * Note that this overhead doesn't account for the 8b/10b, 128b/132b
> + * channel coding efficiency, for that see
> + * @drm_dp_link_bw_channel_coding_efficiency().
> + *
> + * Returns the overhead as 100% + overhead% in 1ppm units.
> + */
> +int drm_dp_bw_overhead(int lane_count, int hactive,
> + int dsc_slice_count,
> + int bpp_x16, unsigned long flags)
> +{
> + int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8;
> + bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;
> + u32 overhead = 1000000;
> + int symbol_cycles;
> +
> + /*
> + * DP Standard v2.1 2.6.4.1
> + * SSC downspread and ref clock variation margin:
> + * 5300ppm + 300ppm ~ 0.6%
> + */
> + if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK)
> + overhead += 6000;
> +
> + /*
> + * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4:
> + * FEC symbol insertions for 8b/10b channel coding:
> + * After each 250 data symbols on 2-4 lanes:
> + * 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block)
> + * After each 2 x 250 data symbols on 1 lane:
> + * 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block)
> + * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks:
> + * 256 * 256 bytes + 1 FEC_PM
> + * or
> + * 128 * 512 bytes + 1 FEC_PM
> + * (256 * 6 + 1) / (256 * 250) = 2.4015625 %
> + */
> + if (flags & DRM_DP_BW_OVERHEAD_FEC)
> + overhead += 24016;
Hmm. Shouldn't we be multiplying the overheads, not add them up?
Though I suppose in this case the error won't be huge.
> +
> + /*
> + * DP Standard v2.1 2.7.9, 5.9.7
> + * The FEC overhead for UHBR is accounted for in its 96.71% channel
> + * coding efficiency.
> + */
> + WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
> + (flags & DRM_DP_BW_OVERHEAD_FEC));
> +
> + if (flags & DRM_DP_BW_OVERHEAD_DSC)
> + symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,
> + dsc_slice_count,
> + bpp_x16, symbol_size,
> + is_mst);
> + else
> + symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
> + bpp_x16, symbol_size,
> + is_mst);
> +
> + return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
> + overhead * 16),
> + hactive * bpp_x16);
> +}
> +EXPORT_SYMBOL(drm_dp_bw_overhead);
> +
> +/**
> + * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
> + * @is_uhbr: Whether the link has a 128b/132b channel coding
> + *
> + * Return the channel coding efficiency of the given DP link type, which is
> + * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes
> + * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
> + * and for 128b/132b any link or PHY level control symbol insertion overhead
> + * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the
> + * corresponding FEC overhead is BW allocation specific, included in the value
> + * returned by drm_dp_bw_overhead().
> + *
> + * Returns the efficiency in the 100%/coding-overhead% ratio in
> + * 1ppm units.
> + */
> +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
> +{
> + if (is_uhbr)
> + return 967100;
> + else
> + /*
> + * Note that on 8b/10b MST the efficiency is only
> + * 78.75% due to the 1 out of 64 MTPH packet overhead,
> + * not accounted for here.
> + */
> + return 800000;
> +}
> +EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> index cc0a8fe84d290..4d72c9a32026e 100644
> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> @@ -4726,17 +4726,28 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
> int drm_dp_calc_pbn_mode(int clock, int bpp)
> {
> /*
> - * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
> * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
> * common multiplier to render an integer PBN for all link rate/lane
> * counts combinations
> * calculate
> - * peak_kbps *= (1006/1000)
> - * peak_kbps *= (64/54)
> - * peak_kbps *= 8 convert to bytes
> + * peak_kbps = clock * bpp / 16
> + * peak_kbps *= SSC overhead / 1000000
> + * peak_kbps /= 8 convert to Kbytes
> + * peak_kBps *= (64/54) / 1000 convert to PBN
> */
> - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
> - 1000 * 8 * 54 * 1000);
> + /*
> + * TODO: Use the actual link and mode parameters to calculate
> + * the overhead. For now it's assumed that these are
> + * 4 link lanes, 4096 hactive pixels, which don't add any
> + * significant data padding overhead and that there is no DSC
> + * or FEC overhead.
> + */
> + int overhead = drm_dp_bw_overhead(4, 4096, 0, bpp,
> + DRM_DP_BW_OVERHEAD_MST |
> + DRM_DP_BW_OVERHEAD_SSC_REF_CLK);
> +
> + return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),
> + 1000000ULL * 8 * 54 * 1000);
> }
> EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
>
> diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> index da94932f4262b..caee29d28463c 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -788,4 +788,15 @@ bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZ
> const u8 port_cap[4], u8 color_spc);
> int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
>
> +#define DRM_DP_BW_OVERHEAD_MST BIT(0)
> +#define DRM_DP_BW_OVERHEAD_UHBR BIT(1)
> +#define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2)
> +#define DRM_DP_BW_OVERHEAD_FEC BIT(3)
> +#define DRM_DP_BW_OVERHEAD_DSC BIT(4)
> +
> +int drm_dp_bw_overhead(int lane_count, int hactive,
> + int dsc_slice_count,
> + int bpp_x16, unsigned long flags);
> +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
> +
> #endif /* _DRM_DP_HELPER_H_ */
> --
> 2.39.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v4 09/30] drm/dp: Add helpers to calculate the link BW overhead
2023-11-06 21:31 ` Ville Syrjälä
@ 2023-11-06 22:28 ` Imre Deak
-1 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-11-06 22:28 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, dri-devel
On Mon, Nov 06, 2023 at 11:31:51PM +0200, Ville Syrjälä wrote:
> On Mon, Oct 30, 2023 at 05:58:22PM +0200, Imre Deak wrote:
> > Add helpers drivers can use to calculate the BW allocation overhead -
> > due to SSC, FEC, DSC and data alignment on symbol cycles - and the
> > channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On
> > 128b/132b links the FEC overhead is part of the coding efficiency, so
> > not accounted for in the BW allocation overhead.
> >
> > The drivers can use these functions to calculate a ratio, controlling
> > the stream symbol insertion rate of the source device in each SST TU
> > or MST MTP frame. Drivers can calculate this
> >
> > m/n = (pixel_data_rate * drm_dp_bw_overhead()) /
> > (link_data_rate * drm_dp_bw_channel_coding_efficiency())
> >
> > ratio for a given link and pixel stream and with that the
> >
> > mtp_count = CEIL(64 * m / n)
> >
> > allocated MTPs for the stream in a link frame and
> >
> > pbn = CEIL(64 * dm_mst_get_pbn_divider() * m / n)
> >
> > allocated PBNs for the stream on the MST link path.
> >
> > Take drm_dp_bw_overhead() into use in drm_dp_calc_pbn_mode(), for
> > drivers calculating the PBN value directly.
> >
> > v2:
> > - Add dockbook description to drm_dp_bw_channel_coding_efficiency().
> > (LKP).
> > - Clarify the way m/n ratio is calculated in the commit log.
> > v3:
> > - Fix compile breakage for !CONFIG_BACKLIGHT_CLASS_DEVICE. (LKP)
> > - Account for FEC_PM overhead (+ 0.0015625 %), add comment
> > with the formula to calculate the total FEC overhead. (Ville)
> > v4:
> > - Rename DRM_DP_OVERHEAD_SSC to DRM_DP_OVERHEAD_SSC_REF_CLK. (Ville)
> >
> > Cc: Lyude Paul <lyude@redhat.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: kernel test robot <lkp@intel.com>
> > Cc: dri-devel@lists.freedesktop.org
> > Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v2)
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/display/drm_dp_helper.c | 132 ++++++++++++++++++
> > drivers/gpu/drm/display/drm_dp_mst_topology.c | 23 ++-
> > include/drm/display/drm_dp_helper.h | 11 ++
> > 3 files changed, 160 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> > index e5d7970a9ddd0..72ba9ae89f862 100644
> > --- a/drivers/gpu/drm/display/drm_dp_helper.c
> > +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> > @@ -3900,3 +3900,135 @@ int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
> > EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
> >
> > #endif
> > +
> > +/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
> > +static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
> > + int symbol_size, bool is_mst)
> > +{
> > + int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
> > + int align = is_mst ? 4 / lane_count : 1;
> > +
> > + return ALIGN(cycles, align);
> > +}
> > +
> > +static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,
> > + int bpp_x16, int symbol_size, bool is_mst)
> > +{
> > + int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
> > + int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,
> > + bpp_x16, symbol_size, is_mst);
> > + int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
> > +
> > + return slice_count * (slice_data_cycles + slice_eoc_cycles);
> > +}
> > +
> > +/**
> > + * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
> > + * @lane_count: DP link lane count
> > + * @hactive: pixel count of the active period in one scanline of the stream
> > + * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set
> > + * @bpp_x16: bits per pixel in .4 binary fixed point
> > + * @flags: DRM_DP_OVERHEAD_x flags
> > + *
> > + * Calculate the BW allocation overhead of a DP link stream, depending
> > + * on the link's
> > + * - @lane_count
> > + * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
> > + * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
> > + * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
> > + * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
> > + * as well as the stream's
> > + * - @hactive timing
> > + * - @bpp_x16 color depth
> > + * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).
> > + * Note that this overhead doesn't account for the 8b/10b, 128b/132b
> > + * channel coding efficiency, for that see
> > + * @drm_dp_link_bw_channel_coding_efficiency().
> > + *
> > + * Returns the overhead as 100% + overhead% in 1ppm units.
> > + */
> > +int drm_dp_bw_overhead(int lane_count, int hactive,
> > + int dsc_slice_count,
> > + int bpp_x16, unsigned long flags)
> > +{
> > + int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8;
> > + bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;
> > + u32 overhead = 1000000;
> > + int symbol_cycles;
> > +
> > + /*
> > + * DP Standard v2.1 2.6.4.1
> > + * SSC downspread and ref clock variation margin:
> > + * 5300ppm + 300ppm ~ 0.6%
> > + */
> > + if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK)
> > + overhead += 6000;
> > +
> > + /*
> > + * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4:
> > + * FEC symbol insertions for 8b/10b channel coding:
> > + * After each 250 data symbols on 2-4 lanes:
> > + * 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block)
> > + * After each 2 x 250 data symbols on 1 lane:
> > + * 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block)
> > + * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks:
> > + * 256 * 256 bytes + 1 FEC_PM
> > + * or
> > + * 128 * 512 bytes + 1 FEC_PM
> > + * (256 * 6 + 1) / (256 * 250) = 2.4015625 %
> > + */
> > + if (flags & DRM_DP_BW_OVERHEAD_FEC)
> > + overhead += 24016;
>
> Hmm. Shouldn't we be multiplying the overheads, not add them up?
> Though I suppose in this case the error won't be huge.
Yes logically these should be multiplied. I added them here, because
that's what the spec does with explicitly mentioning the 3% total
overhead. I presume it's a simplification, maybe because the 0.6%
SSC+REF_CLK overhead is already a rounded-up value, the exact one being
only 0.53% for SSC and 0.03% for REF_CLK.
> > +
> > + /*
> > + * DP Standard v2.1 2.7.9, 5.9.7
> > + * The FEC overhead for UHBR is accounted for in its 96.71% channel
> > + * coding efficiency.
> > + */
> > + WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
> > + (flags & DRM_DP_BW_OVERHEAD_FEC));
> > +
> > + if (flags & DRM_DP_BW_OVERHEAD_DSC)
> > + symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,
> > + dsc_slice_count,
> > + bpp_x16, symbol_size,
> > + is_mst);
> > + else
> > + symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
> > + bpp_x16, symbol_size,
> > + is_mst);
> > +
> > + return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
> > + overhead * 16),
> > + hactive * bpp_x16);
> > +}
> > +EXPORT_SYMBOL(drm_dp_bw_overhead);
> > +
> > +/**
> > + * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
> > + * @is_uhbr: Whether the link has a 128b/132b channel coding
> > + *
> > + * Return the channel coding efficiency of the given DP link type, which is
> > + * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes
> > + * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
> > + * and for 128b/132b any link or PHY level control symbol insertion overhead
> > + * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the
> > + * corresponding FEC overhead is BW allocation specific, included in the value
> > + * returned by drm_dp_bw_overhead().
> > + *
> > + * Returns the efficiency in the 100%/coding-overhead% ratio in
> > + * 1ppm units.
> > + */
> > +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
> > +{
> > + if (is_uhbr)
> > + return 967100;
> > + else
> > + /*
> > + * Note that on 8b/10b MST the efficiency is only
> > + * 78.75% due to the 1 out of 64 MTPH packet overhead,
> > + * not accounted for here.
> > + */
> > + return 800000;
> > +}
> > +EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
> > diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > index cc0a8fe84d290..4d72c9a32026e 100644
> > --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > @@ -4726,17 +4726,28 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
> > int drm_dp_calc_pbn_mode(int clock, int bpp)
> > {
> > /*
> > - * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
> > * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
> > * common multiplier to render an integer PBN for all link rate/lane
> > * counts combinations
> > * calculate
> > - * peak_kbps *= (1006/1000)
> > - * peak_kbps *= (64/54)
> > - * peak_kbps *= 8 convert to bytes
> > + * peak_kbps = clock * bpp / 16
> > + * peak_kbps *= SSC overhead / 1000000
> > + * peak_kbps /= 8 convert to Kbytes
> > + * peak_kBps *= (64/54) / 1000 convert to PBN
> > */
> > - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
> > - 1000 * 8 * 54 * 1000);
> > + /*
> > + * TODO: Use the actual link and mode parameters to calculate
> > + * the overhead. For now it's assumed that these are
> > + * 4 link lanes, 4096 hactive pixels, which don't add any
> > + * significant data padding overhead and that there is no DSC
> > + * or FEC overhead.
> > + */
> > + int overhead = drm_dp_bw_overhead(4, 4096, 0, bpp,
> > + DRM_DP_BW_OVERHEAD_MST |
> > + DRM_DP_BW_OVERHEAD_SSC_REF_CLK);
> > +
> > + return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),
> > + 1000000ULL * 8 * 54 * 1000);
> > }
> > EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
> >
> > diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> > index da94932f4262b..caee29d28463c 100644
> > --- a/include/drm/display/drm_dp_helper.h
> > +++ b/include/drm/display/drm_dp_helper.h
> > @@ -788,4 +788,15 @@ bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZ
> > const u8 port_cap[4], u8 color_spc);
> > int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
> >
> > +#define DRM_DP_BW_OVERHEAD_MST BIT(0)
> > +#define DRM_DP_BW_OVERHEAD_UHBR BIT(1)
> > +#define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2)
> > +#define DRM_DP_BW_OVERHEAD_FEC BIT(3)
> > +#define DRM_DP_BW_OVERHEAD_DSC BIT(4)
> > +
> > +int drm_dp_bw_overhead(int lane_count, int hactive,
> > + int dsc_slice_count,
> > + int bpp_x16, unsigned long flags);
> > +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
> > +
> > #endif /* _DRM_DP_HELPER_H_ */
> > --
> > 2.39.2
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 09/30] drm/dp: Add helpers to calculate the link BW overhead
@ 2023-11-06 22:28 ` Imre Deak
0 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-11-06 22:28 UTC (permalink / raw)
To: Ville Syrjälä
Cc: Stanislav Lisovskiy, intel-gfx, kernel test robot, dri-devel
On Mon, Nov 06, 2023 at 11:31:51PM +0200, Ville Syrjälä wrote:
> On Mon, Oct 30, 2023 at 05:58:22PM +0200, Imre Deak wrote:
> > Add helpers drivers can use to calculate the BW allocation overhead -
> > due to SSC, FEC, DSC and data alignment on symbol cycles - and the
> > channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On
> > 128b/132b links the FEC overhead is part of the coding efficiency, so
> > not accounted for in the BW allocation overhead.
> >
> > The drivers can use these functions to calculate a ratio, controlling
> > the stream symbol insertion rate of the source device in each SST TU
> > or MST MTP frame. Drivers can calculate this
> >
> > m/n = (pixel_data_rate * drm_dp_bw_overhead()) /
> > (link_data_rate * drm_dp_bw_channel_coding_efficiency())
> >
> > ratio for a given link and pixel stream and with that the
> >
> > mtp_count = CEIL(64 * m / n)
> >
> > allocated MTPs for the stream in a link frame and
> >
> > pbn = CEIL(64 * dm_mst_get_pbn_divider() * m / n)
> >
> > allocated PBNs for the stream on the MST link path.
> >
> > Take drm_dp_bw_overhead() into use in drm_dp_calc_pbn_mode(), for
> > drivers calculating the PBN value directly.
> >
> > v2:
> > - Add dockbook description to drm_dp_bw_channel_coding_efficiency().
> > (LKP).
> > - Clarify the way m/n ratio is calculated in the commit log.
> > v3:
> > - Fix compile breakage for !CONFIG_BACKLIGHT_CLASS_DEVICE. (LKP)
> > - Account for FEC_PM overhead (+ 0.0015625 %), add comment
> > with the formula to calculate the total FEC overhead. (Ville)
> > v4:
> > - Rename DRM_DP_OVERHEAD_SSC to DRM_DP_OVERHEAD_SSC_REF_CLK. (Ville)
> >
> > Cc: Lyude Paul <lyude@redhat.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: kernel test robot <lkp@intel.com>
> > Cc: dri-devel@lists.freedesktop.org
> > Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v2)
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/display/drm_dp_helper.c | 132 ++++++++++++++++++
> > drivers/gpu/drm/display/drm_dp_mst_topology.c | 23 ++-
> > include/drm/display/drm_dp_helper.h | 11 ++
> > 3 files changed, 160 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> > index e5d7970a9ddd0..72ba9ae89f862 100644
> > --- a/drivers/gpu/drm/display/drm_dp_helper.c
> > +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> > @@ -3900,3 +3900,135 @@ int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
> > EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
> >
> > #endif
> > +
> > +/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
> > +static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
> > + int symbol_size, bool is_mst)
> > +{
> > + int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
> > + int align = is_mst ? 4 / lane_count : 1;
> > +
> > + return ALIGN(cycles, align);
> > +}
> > +
> > +static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,
> > + int bpp_x16, int symbol_size, bool is_mst)
> > +{
> > + int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
> > + int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,
> > + bpp_x16, symbol_size, is_mst);
> > + int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
> > +
> > + return slice_count * (slice_data_cycles + slice_eoc_cycles);
> > +}
> > +
> > +/**
> > + * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
> > + * @lane_count: DP link lane count
> > + * @hactive: pixel count of the active period in one scanline of the stream
> > + * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set
> > + * @bpp_x16: bits per pixel in .4 binary fixed point
> > + * @flags: DRM_DP_OVERHEAD_x flags
> > + *
> > + * Calculate the BW allocation overhead of a DP link stream, depending
> > + * on the link's
> > + * - @lane_count
> > + * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
> > + * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
> > + * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
> > + * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
> > + * as well as the stream's
> > + * - @hactive timing
> > + * - @bpp_x16 color depth
> > + * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).
> > + * Note that this overhead doesn't account for the 8b/10b, 128b/132b
> > + * channel coding efficiency, for that see
> > + * @drm_dp_link_bw_channel_coding_efficiency().
> > + *
> > + * Returns the overhead as 100% + overhead% in 1ppm units.
> > + */
> > +int drm_dp_bw_overhead(int lane_count, int hactive,
> > + int dsc_slice_count,
> > + int bpp_x16, unsigned long flags)
> > +{
> > + int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8;
> > + bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;
> > + u32 overhead = 1000000;
> > + int symbol_cycles;
> > +
> > + /*
> > + * DP Standard v2.1 2.6.4.1
> > + * SSC downspread and ref clock variation margin:
> > + * 5300ppm + 300ppm ~ 0.6%
> > + */
> > + if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK)
> > + overhead += 6000;
> > +
> > + /*
> > + * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4:
> > + * FEC symbol insertions for 8b/10b channel coding:
> > + * After each 250 data symbols on 2-4 lanes:
> > + * 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block)
> > + * After each 2 x 250 data symbols on 1 lane:
> > + * 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block)
> > + * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks:
> > + * 256 * 256 bytes + 1 FEC_PM
> > + * or
> > + * 128 * 512 bytes + 1 FEC_PM
> > + * (256 * 6 + 1) / (256 * 250) = 2.4015625 %
> > + */
> > + if (flags & DRM_DP_BW_OVERHEAD_FEC)
> > + overhead += 24016;
>
> Hmm. Shouldn't we be multiplying the overheads, not add them up?
> Though I suppose in this case the error won't be huge.
Yes logically these should be multiplied. I added them here, because
that's what the spec does with explicitly mentioning the 3% total
overhead. I presume it's a simplification, maybe because the 0.6%
SSC+REF_CLK overhead is already a rounded-up value, the exact one being
only 0.53% for SSC and 0.03% for REF_CLK.
> > +
> > + /*
> > + * DP Standard v2.1 2.7.9, 5.9.7
> > + * The FEC overhead for UHBR is accounted for in its 96.71% channel
> > + * coding efficiency.
> > + */
> > + WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
> > + (flags & DRM_DP_BW_OVERHEAD_FEC));
> > +
> > + if (flags & DRM_DP_BW_OVERHEAD_DSC)
> > + symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,
> > + dsc_slice_count,
> > + bpp_x16, symbol_size,
> > + is_mst);
> > + else
> > + symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
> > + bpp_x16, symbol_size,
> > + is_mst);
> > +
> > + return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
> > + overhead * 16),
> > + hactive * bpp_x16);
> > +}
> > +EXPORT_SYMBOL(drm_dp_bw_overhead);
> > +
> > +/**
> > + * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
> > + * @is_uhbr: Whether the link has a 128b/132b channel coding
> > + *
> > + * Return the channel coding efficiency of the given DP link type, which is
> > + * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes
> > + * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
> > + * and for 128b/132b any link or PHY level control symbol insertion overhead
> > + * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the
> > + * corresponding FEC overhead is BW allocation specific, included in the value
> > + * returned by drm_dp_bw_overhead().
> > + *
> > + * Returns the efficiency in the 100%/coding-overhead% ratio in
> > + * 1ppm units.
> > + */
> > +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
> > +{
> > + if (is_uhbr)
> > + return 967100;
> > + else
> > + /*
> > + * Note that on 8b/10b MST the efficiency is only
> > + * 78.75% due to the 1 out of 64 MTPH packet overhead,
> > + * not accounted for here.
> > + */
> > + return 800000;
> > +}
> > +EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
> > diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > index cc0a8fe84d290..4d72c9a32026e 100644
> > --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > @@ -4726,17 +4726,28 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
> > int drm_dp_calc_pbn_mode(int clock, int bpp)
> > {
> > /*
> > - * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
> > * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
> > * common multiplier to render an integer PBN for all link rate/lane
> > * counts combinations
> > * calculate
> > - * peak_kbps *= (1006/1000)
> > - * peak_kbps *= (64/54)
> > - * peak_kbps *= 8 convert to bytes
> > + * peak_kbps = clock * bpp / 16
> > + * peak_kbps *= SSC overhead / 1000000
> > + * peak_kbps /= 8 convert to Kbytes
> > + * peak_kBps *= (64/54) / 1000 convert to PBN
> > */
> > - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
> > - 1000 * 8 * 54 * 1000);
> > + /*
> > + * TODO: Use the actual link and mode parameters to calculate
> > + * the overhead. For now it's assumed that these are
> > + * 4 link lanes, 4096 hactive pixels, which don't add any
> > + * significant data padding overhead and that there is no DSC
> > + * or FEC overhead.
> > + */
> > + int overhead = drm_dp_bw_overhead(4, 4096, 0, bpp,
> > + DRM_DP_BW_OVERHEAD_MST |
> > + DRM_DP_BW_OVERHEAD_SSC_REF_CLK);
> > +
> > + return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),
> > + 1000000ULL * 8 * 54 * 1000);
> > }
> > EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
> >
> > diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> > index da94932f4262b..caee29d28463c 100644
> > --- a/include/drm/display/drm_dp_helper.h
> > +++ b/include/drm/display/drm_dp_helper.h
> > @@ -788,4 +788,15 @@ bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZ
> > const u8 port_cap[4], u8 color_spc);
> > int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
> >
> > +#define DRM_DP_BW_OVERHEAD_MST BIT(0)
> > +#define DRM_DP_BW_OVERHEAD_UHBR BIT(1)
> > +#define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2)
> > +#define DRM_DP_BW_OVERHEAD_FEC BIT(3)
> > +#define DRM_DP_BW_OVERHEAD_DSC BIT(4)
> > +
> > +int drm_dp_bw_overhead(int lane_count, int hactive,
> > + int dsc_slice_count,
> > + int bpp_x16, unsigned long flags);
> > +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
> > +
> > #endif /* _DRM_DP_HELPER_H_ */
> > --
> > 2.39.2
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v4 09/30] drm/dp: Add helpers to calculate the link BW overhead
2023-11-06 22:28 ` Imre Deak
@ 2023-11-07 16:24 ` Ville Syrjälä
-1 siblings, 0 replies; 94+ messages in thread
From: Ville Syrjälä @ 2023-11-07 16:24 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, dri-devel
On Tue, Nov 07, 2023 at 12:28:24AM +0200, Imre Deak wrote:
> On Mon, Nov 06, 2023 at 11:31:51PM +0200, Ville Syrjälä wrote:
> > On Mon, Oct 30, 2023 at 05:58:22PM +0200, Imre Deak wrote:
> > > Add helpers drivers can use to calculate the BW allocation overhead -
> > > due to SSC, FEC, DSC and data alignment on symbol cycles - and the
> > > channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On
> > > 128b/132b links the FEC overhead is part of the coding efficiency, so
> > > not accounted for in the BW allocation overhead.
> > >
> > > The drivers can use these functions to calculate a ratio, controlling
> > > the stream symbol insertion rate of the source device in each SST TU
> > > or MST MTP frame. Drivers can calculate this
> > >
> > > m/n = (pixel_data_rate * drm_dp_bw_overhead()) /
> > > (link_data_rate * drm_dp_bw_channel_coding_efficiency())
> > >
> > > ratio for a given link and pixel stream and with that the
> > >
> > > mtp_count = CEIL(64 * m / n)
> > >
> > > allocated MTPs for the stream in a link frame and
> > >
> > > pbn = CEIL(64 * dm_mst_get_pbn_divider() * m / n)
> > >
> > > allocated PBNs for the stream on the MST link path.
> > >
> > > Take drm_dp_bw_overhead() into use in drm_dp_calc_pbn_mode(), for
> > > drivers calculating the PBN value directly.
> > >
> > > v2:
> > > - Add dockbook description to drm_dp_bw_channel_coding_efficiency().
> > > (LKP).
> > > - Clarify the way m/n ratio is calculated in the commit log.
> > > v3:
> > > - Fix compile breakage for !CONFIG_BACKLIGHT_CLASS_DEVICE. (LKP)
> > > - Account for FEC_PM overhead (+ 0.0015625 %), add comment
> > > with the formula to calculate the total FEC overhead. (Ville)
> > > v4:
> > > - Rename DRM_DP_OVERHEAD_SSC to DRM_DP_OVERHEAD_SSC_REF_CLK. (Ville)
> > >
> > > Cc: Lyude Paul <lyude@redhat.com>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Cc: kernel test robot <lkp@intel.com>
> > > Cc: dri-devel@lists.freedesktop.org
> > > Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v2)
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > drivers/gpu/drm/display/drm_dp_helper.c | 132 ++++++++++++++++++
> > > drivers/gpu/drm/display/drm_dp_mst_topology.c | 23 ++-
> > > include/drm/display/drm_dp_helper.h | 11 ++
> > > 3 files changed, 160 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> > > index e5d7970a9ddd0..72ba9ae89f862 100644
> > > --- a/drivers/gpu/drm/display/drm_dp_helper.c
> > > +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> > > @@ -3900,3 +3900,135 @@ int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
> > > EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
> > >
> > > #endif
> > > +
> > > +/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
> > > +static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
> > > + int symbol_size, bool is_mst)
> > > +{
> > > + int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
> > > + int align = is_mst ? 4 / lane_count : 1;
> > > +
> > > + return ALIGN(cycles, align);
> > > +}
> > > +
> > > +static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,
> > > + int bpp_x16, int symbol_size, bool is_mst)
> > > +{
> > > + int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
> > > + int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,
> > > + bpp_x16, symbol_size, is_mst);
> > > + int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
> > > +
> > > + return slice_count * (slice_data_cycles + slice_eoc_cycles);
> > > +}
> > > +
> > > +/**
> > > + * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
> > > + * @lane_count: DP link lane count
> > > + * @hactive: pixel count of the active period in one scanline of the stream
> > > + * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set
> > > + * @bpp_x16: bits per pixel in .4 binary fixed point
> > > + * @flags: DRM_DP_OVERHEAD_x flags
> > > + *
> > > + * Calculate the BW allocation overhead of a DP link stream, depending
> > > + * on the link's
> > > + * - @lane_count
> > > + * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
> > > + * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
> > > + * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
> > > + * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
> > > + * as well as the stream's
> > > + * - @hactive timing
> > > + * - @bpp_x16 color depth
> > > + * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).
> > > + * Note that this overhead doesn't account for the 8b/10b, 128b/132b
> > > + * channel coding efficiency, for that see
> > > + * @drm_dp_link_bw_channel_coding_efficiency().
> > > + *
> > > + * Returns the overhead as 100% + overhead% in 1ppm units.
> > > + */
> > > +int drm_dp_bw_overhead(int lane_count, int hactive,
> > > + int dsc_slice_count,
> > > + int bpp_x16, unsigned long flags)
> > > +{
> > > + int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8;
> > > + bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;
> > > + u32 overhead = 1000000;
> > > + int symbol_cycles;
> > > +
> > > + /*
> > > + * DP Standard v2.1 2.6.4.1
> > > + * SSC downspread and ref clock variation margin:
> > > + * 5300ppm + 300ppm ~ 0.6%
> > > + */
> > > + if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK)
> > > + overhead += 6000;
> > > +
> > > + /*
> > > + * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4:
> > > + * FEC symbol insertions for 8b/10b channel coding:
> > > + * After each 250 data symbols on 2-4 lanes:
> > > + * 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block)
> > > + * After each 2 x 250 data symbols on 1 lane:
> > > + * 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block)
> > > + * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks:
> > > + * 256 * 256 bytes + 1 FEC_PM
> > > + * or
> > > + * 128 * 512 bytes + 1 FEC_PM
> > > + * (256 * 6 + 1) / (256 * 250) = 2.4015625 %
> > > + */
> > > + if (flags & DRM_DP_BW_OVERHEAD_FEC)
> > > + overhead += 24016;
> >
> > Hmm. Shouldn't we be multiplying the overheads, not add them up?
> > Though I suppose in this case the error won't be huge.
>
> Yes logically these should be multiplied. I added them here, because
> that's what the spec does with explicitly mentioning the 3% total
> overhead.
>
> I presume it's a simplification, maybe because the 0.6%
> SSC+REF_CLK overhead is already a rounded-up value, the exact one being
> only 0.53% for SSC and 0.03% for REF_CLK.
Yeah, they also didn't bother multiplying those two together
and just added them together. But for the rest they rather just
give rough estimates instead of exact numbers.
However
((256*256+1)/(256*250))*1.0053 = ~1.02944
vs.
1.0+0.006+0.024016 = 1.030016
so yeah, it does look like we should be safe with just
adding them up (and the rough 3% total the spec mentions
would also be safe).
>
> > > +
> > > + /*
> > > + * DP Standard v2.1 2.7.9, 5.9.7
> > > + * The FEC overhead for UHBR is accounted for in its 96.71% channel
> > > + * coding efficiency.
> > > + */
> > > + WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
> > > + (flags & DRM_DP_BW_OVERHEAD_FEC));
> > > +
> > > + if (flags & DRM_DP_BW_OVERHEAD_DSC)
> > > + symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,
> > > + dsc_slice_count,
> > > + bpp_x16, symbol_size,
> > > + is_mst);
> > > + else
> > > + symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
> > > + bpp_x16, symbol_size,
> > > + is_mst);
> > > +
> > > + return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
> > > + overhead * 16),
> > > + hactive * bpp_x16);
> > > +}
> > > +EXPORT_SYMBOL(drm_dp_bw_overhead);
> > > +
> > > +/**
> > > + * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
> > > + * @is_uhbr: Whether the link has a 128b/132b channel coding
> > > + *
> > > + * Return the channel coding efficiency of the given DP link type, which is
> > > + * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes
> > > + * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
> > > + * and for 128b/132b any link or PHY level control symbol insertion overhead
> > > + * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the
> > > + * corresponding FEC overhead is BW allocation specific, included in the value
> > > + * returned by drm_dp_bw_overhead().
> > > + *
> > > + * Returns the efficiency in the 100%/coding-overhead% ratio in
> > > + * 1ppm units.
> > > + */
> > > +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
> > > +{
> > > + if (is_uhbr)
> > > + return 967100;
> > > + else
> > > + /*
> > > + * Note that on 8b/10b MST the efficiency is only
> > > + * 78.75% due to the 1 out of 64 MTPH packet overhead,
> > > + * not accounted for here.
> > > + */
> > > + return 800000;
> > > +}
> > > +EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
> > > diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > index cc0a8fe84d290..4d72c9a32026e 100644
> > > --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > @@ -4726,17 +4726,28 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
> > > int drm_dp_calc_pbn_mode(int clock, int bpp)
> > > {
> > > /*
> > > - * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
> > > * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
> > > * common multiplier to render an integer PBN for all link rate/lane
> > > * counts combinations
> > > * calculate
> > > - * peak_kbps *= (1006/1000)
> > > - * peak_kbps *= (64/54)
> > > - * peak_kbps *= 8 convert to bytes
> > > + * peak_kbps = clock * bpp / 16
> > > + * peak_kbps *= SSC overhead / 1000000
> > > + * peak_kbps /= 8 convert to Kbytes
> > > + * peak_kBps *= (64/54) / 1000 convert to PBN
> > > */
> > > - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
> > > - 1000 * 8 * 54 * 1000);
> > > + /*
> > > + * TODO: Use the actual link and mode parameters to calculate
> > > + * the overhead. For now it's assumed that these are
> > > + * 4 link lanes, 4096 hactive pixels, which don't add any
> > > + * significant data padding overhead and that there is no DSC
> > > + * or FEC overhead.
> > > + */
> > > + int overhead = drm_dp_bw_overhead(4, 4096, 0, bpp,
> > > + DRM_DP_BW_OVERHEAD_MST |
> > > + DRM_DP_BW_OVERHEAD_SSC_REF_CLK);
> > > +
> > > + return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),
> > > + 1000000ULL * 8 * 54 * 1000);
> > > }
> > > EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
> > >
> > > diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> > > index da94932f4262b..caee29d28463c 100644
> > > --- a/include/drm/display/drm_dp_helper.h
> > > +++ b/include/drm/display/drm_dp_helper.h
> > > @@ -788,4 +788,15 @@ bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZ
> > > const u8 port_cap[4], u8 color_spc);
> > > int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
> > >
> > > +#define DRM_DP_BW_OVERHEAD_MST BIT(0)
> > > +#define DRM_DP_BW_OVERHEAD_UHBR BIT(1)
> > > +#define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2)
> > > +#define DRM_DP_BW_OVERHEAD_FEC BIT(3)
> > > +#define DRM_DP_BW_OVERHEAD_DSC BIT(4)
> > > +
> > > +int drm_dp_bw_overhead(int lane_count, int hactive,
> > > + int dsc_slice_count,
> > > + int bpp_x16, unsigned long flags);
> > > +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
> > > +
> > > #endif /* _DRM_DP_HELPER_H_ */
> > > --
> > > 2.39.2
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 09/30] drm/dp: Add helpers to calculate the link BW overhead
@ 2023-11-07 16:24 ` Ville Syrjälä
0 siblings, 0 replies; 94+ messages in thread
From: Ville Syrjälä @ 2023-11-07 16:24 UTC (permalink / raw)
To: Imre Deak; +Cc: Stanislav Lisovskiy, intel-gfx, kernel test robot, dri-devel
On Tue, Nov 07, 2023 at 12:28:24AM +0200, Imre Deak wrote:
> On Mon, Nov 06, 2023 at 11:31:51PM +0200, Ville Syrjälä wrote:
> > On Mon, Oct 30, 2023 at 05:58:22PM +0200, Imre Deak wrote:
> > > Add helpers drivers can use to calculate the BW allocation overhead -
> > > due to SSC, FEC, DSC and data alignment on symbol cycles - and the
> > > channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On
> > > 128b/132b links the FEC overhead is part of the coding efficiency, so
> > > not accounted for in the BW allocation overhead.
> > >
> > > The drivers can use these functions to calculate a ratio, controlling
> > > the stream symbol insertion rate of the source device in each SST TU
> > > or MST MTP frame. Drivers can calculate this
> > >
> > > m/n = (pixel_data_rate * drm_dp_bw_overhead()) /
> > > (link_data_rate * drm_dp_bw_channel_coding_efficiency())
> > >
> > > ratio for a given link and pixel stream and with that the
> > >
> > > mtp_count = CEIL(64 * m / n)
> > >
> > > allocated MTPs for the stream in a link frame and
> > >
> > > pbn = CEIL(64 * dm_mst_get_pbn_divider() * m / n)
> > >
> > > allocated PBNs for the stream on the MST link path.
> > >
> > > Take drm_dp_bw_overhead() into use in drm_dp_calc_pbn_mode(), for
> > > drivers calculating the PBN value directly.
> > >
> > > v2:
> > > - Add dockbook description to drm_dp_bw_channel_coding_efficiency().
> > > (LKP).
> > > - Clarify the way m/n ratio is calculated in the commit log.
> > > v3:
> > > - Fix compile breakage for !CONFIG_BACKLIGHT_CLASS_DEVICE. (LKP)
> > > - Account for FEC_PM overhead (+ 0.0015625 %), add comment
> > > with the formula to calculate the total FEC overhead. (Ville)
> > > v4:
> > > - Rename DRM_DP_OVERHEAD_SSC to DRM_DP_OVERHEAD_SSC_REF_CLK. (Ville)
> > >
> > > Cc: Lyude Paul <lyude@redhat.com>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Cc: kernel test robot <lkp@intel.com>
> > > Cc: dri-devel@lists.freedesktop.org
> > > Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v2)
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > drivers/gpu/drm/display/drm_dp_helper.c | 132 ++++++++++++++++++
> > > drivers/gpu/drm/display/drm_dp_mst_topology.c | 23 ++-
> > > include/drm/display/drm_dp_helper.h | 11 ++
> > > 3 files changed, 160 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> > > index e5d7970a9ddd0..72ba9ae89f862 100644
> > > --- a/drivers/gpu/drm/display/drm_dp_helper.c
> > > +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> > > @@ -3900,3 +3900,135 @@ int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
> > > EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
> > >
> > > #endif
> > > +
> > > +/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
> > > +static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
> > > + int symbol_size, bool is_mst)
> > > +{
> > > + int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
> > > + int align = is_mst ? 4 / lane_count : 1;
> > > +
> > > + return ALIGN(cycles, align);
> > > +}
> > > +
> > > +static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,
> > > + int bpp_x16, int symbol_size, bool is_mst)
> > > +{
> > > + int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
> > > + int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,
> > > + bpp_x16, symbol_size, is_mst);
> > > + int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
> > > +
> > > + return slice_count * (slice_data_cycles + slice_eoc_cycles);
> > > +}
> > > +
> > > +/**
> > > + * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
> > > + * @lane_count: DP link lane count
> > > + * @hactive: pixel count of the active period in one scanline of the stream
> > > + * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set
> > > + * @bpp_x16: bits per pixel in .4 binary fixed point
> > > + * @flags: DRM_DP_OVERHEAD_x flags
> > > + *
> > > + * Calculate the BW allocation overhead of a DP link stream, depending
> > > + * on the link's
> > > + * - @lane_count
> > > + * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
> > > + * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
> > > + * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
> > > + * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
> > > + * as well as the stream's
> > > + * - @hactive timing
> > > + * - @bpp_x16 color depth
> > > + * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).
> > > + * Note that this overhead doesn't account for the 8b/10b, 128b/132b
> > > + * channel coding efficiency, for that see
> > > + * @drm_dp_link_bw_channel_coding_efficiency().
> > > + *
> > > + * Returns the overhead as 100% + overhead% in 1ppm units.
> > > + */
> > > +int drm_dp_bw_overhead(int lane_count, int hactive,
> > > + int dsc_slice_count,
> > > + int bpp_x16, unsigned long flags)
> > > +{
> > > + int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8;
> > > + bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;
> > > + u32 overhead = 1000000;
> > > + int symbol_cycles;
> > > +
> > > + /*
> > > + * DP Standard v2.1 2.6.4.1
> > > + * SSC downspread and ref clock variation margin:
> > > + * 5300ppm + 300ppm ~ 0.6%
> > > + */
> > > + if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK)
> > > + overhead += 6000;
> > > +
> > > + /*
> > > + * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4:
> > > + * FEC symbol insertions for 8b/10b channel coding:
> > > + * After each 250 data symbols on 2-4 lanes:
> > > + * 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block)
> > > + * After each 2 x 250 data symbols on 1 lane:
> > > + * 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block)
> > > + * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks:
> > > + * 256 * 256 bytes + 1 FEC_PM
> > > + * or
> > > + * 128 * 512 bytes + 1 FEC_PM
> > > + * (256 * 6 + 1) / (256 * 250) = 2.4015625 %
> > > + */
> > > + if (flags & DRM_DP_BW_OVERHEAD_FEC)
> > > + overhead += 24016;
> >
> > Hmm. Shouldn't we be multiplying the overheads, not add them up?
> > Though I suppose in this case the error won't be huge.
>
> Yes logically these should be multiplied. I added them here, because
> that's what the spec does with explicitly mentioning the 3% total
> overhead.
>
> I presume it's a simplification, maybe because the 0.6%
> SSC+REF_CLK overhead is already a rounded-up value, the exact one being
> only 0.53% for SSC and 0.03% for REF_CLK.
Yeah, they also didn't bother multiplying those two together
and just added them together. But for the rest they rather just
give rough estimates instead of exact numbers.
However
((256*256+1)/(256*250))*1.0053 = ~1.02944
vs.
1.0+0.006+0.024016 = 1.030016
so yeah, it does look like we should be safe with just
adding them up (and the rough 3% total the spec mentions
would also be safe).
>
> > > +
> > > + /*
> > > + * DP Standard v2.1 2.7.9, 5.9.7
> > > + * The FEC overhead for UHBR is accounted for in its 96.71% channel
> > > + * coding efficiency.
> > > + */
> > > + WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
> > > + (flags & DRM_DP_BW_OVERHEAD_FEC));
> > > +
> > > + if (flags & DRM_DP_BW_OVERHEAD_DSC)
> > > + symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,
> > > + dsc_slice_count,
> > > + bpp_x16, symbol_size,
> > > + is_mst);
> > > + else
> > > + symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
> > > + bpp_x16, symbol_size,
> > > + is_mst);
> > > +
> > > + return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
> > > + overhead * 16),
> > > + hactive * bpp_x16);
> > > +}
> > > +EXPORT_SYMBOL(drm_dp_bw_overhead);
> > > +
> > > +/**
> > > + * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
> > > + * @is_uhbr: Whether the link has a 128b/132b channel coding
> > > + *
> > > + * Return the channel coding efficiency of the given DP link type, which is
> > > + * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes
> > > + * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
> > > + * and for 128b/132b any link or PHY level control symbol insertion overhead
> > > + * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the
> > > + * corresponding FEC overhead is BW allocation specific, included in the value
> > > + * returned by drm_dp_bw_overhead().
> > > + *
> > > + * Returns the efficiency in the 100%/coding-overhead% ratio in
> > > + * 1ppm units.
> > > + */
> > > +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
> > > +{
> > > + if (is_uhbr)
> > > + return 967100;
> > > + else
> > > + /*
> > > + * Note that on 8b/10b MST the efficiency is only
> > > + * 78.75% due to the 1 out of 64 MTPH packet overhead,
> > > + * not accounted for here.
> > > + */
> > > + return 800000;
> > > +}
> > > +EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
> > > diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > index cc0a8fe84d290..4d72c9a32026e 100644
> > > --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > @@ -4726,17 +4726,28 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
> > > int drm_dp_calc_pbn_mode(int clock, int bpp)
> > > {
> > > /*
> > > - * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
> > > * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
> > > * common multiplier to render an integer PBN for all link rate/lane
> > > * counts combinations
> > > * calculate
> > > - * peak_kbps *= (1006/1000)
> > > - * peak_kbps *= (64/54)
> > > - * peak_kbps *= 8 convert to bytes
> > > + * peak_kbps = clock * bpp / 16
> > > + * peak_kbps *= SSC overhead / 1000000
> > > + * peak_kbps /= 8 convert to Kbytes
> > > + * peak_kBps *= (64/54) / 1000 convert to PBN
> > > */
> > > - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
> > > - 1000 * 8 * 54 * 1000);
> > > + /*
> > > + * TODO: Use the actual link and mode parameters to calculate
> > > + * the overhead. For now it's assumed that these are
> > > + * 4 link lanes, 4096 hactive pixels, which don't add any
> > > + * significant data padding overhead and that there is no DSC
> > > + * or FEC overhead.
> > > + */
> > > + int overhead = drm_dp_bw_overhead(4, 4096, 0, bpp,
> > > + DRM_DP_BW_OVERHEAD_MST |
> > > + DRM_DP_BW_OVERHEAD_SSC_REF_CLK);
> > > +
> > > + return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),
> > > + 1000000ULL * 8 * 54 * 1000);
> > > }
> > > EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
> > >
> > > diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> > > index da94932f4262b..caee29d28463c 100644
> > > --- a/include/drm/display/drm_dp_helper.h
> > > +++ b/include/drm/display/drm_dp_helper.h
> > > @@ -788,4 +788,15 @@ bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZ
> > > const u8 port_cap[4], u8 color_spc);
> > > int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
> > >
> > > +#define DRM_DP_BW_OVERHEAD_MST BIT(0)
> > > +#define DRM_DP_BW_OVERHEAD_UHBR BIT(1)
> > > +#define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2)
> > > +#define DRM_DP_BW_OVERHEAD_FEC BIT(3)
> > > +#define DRM_DP_BW_OVERHEAD_DSC BIT(4)
> > > +
> > > +int drm_dp_bw_overhead(int lane_count, int hactive,
> > > + int dsc_slice_count,
> > > + int bpp_x16, unsigned long flags);
> > > +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
> > > +
> > > #endif /* _DRM_DP_HELPER_H_ */
> > > --
> > > 2.39.2
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 94+ messages in thread
* [Intel-gfx] [PATCH v5 09/30] drm/dp: Add helpers to calculate the link BW overhead
2023-10-30 15:58 ` Imre Deak
@ 2023-11-07 0:14 ` Imre Deak
-1 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-11-07 0:14 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Maxime Ripard
Add helpers drivers can use to calculate the BW allocation overhead -
due to SSC, FEC, DSC and data alignment on symbol cycles - and the
channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On
128b/132b links the FEC overhead is part of the coding efficiency, so
not accounted for in the BW allocation overhead.
The drivers can use these functions to calculate a ratio, controlling
the stream symbol insertion rate of the source device in each SST TU
or MST MTP frame. Drivers can calculate this
m/n = (pixel_data_rate * drm_dp_bw_overhead()) /
(link_data_rate * drm_dp_bw_channel_coding_efficiency())
ratio for a given link and pixel stream and with that the
slots_per_mtp = CEIL(64 * m / n)
allocated slots per MTP for the stream in a link frame and with
that the
pbn = slots_per_mtp * drm_mst_get_pbn_divider()
allocated PBNs for the stream on the MST link path.
Take drm_dp_bw_overhead() into use in drm_dp_calc_pbn_mode(), for
drivers calculating the PBN value directly.
v2:
- Add dockbook description to drm_dp_bw_channel_coding_efficiency().
(LKP).
- Clarify the way m/n ratio is calculated in the commit log.
v3:
- Fix compile breakage for !CONFIG_BACKLIGHT_CLASS_DEVICE. (LKP)
- Account for FEC_PM overhead (+ 0.0015625 %), add comment
with the formula to calculate the total FEC overhead. (Ville)
v4:
- Rename DRM_DP_OVERHEAD_SSC to DRM_DP_OVERHEAD_SSC_REF_CLK. (Ville)
v5:
- Clarify in the commit log what MTP means.
- Simplify the commit log's formula to calculate PBN.
Cc: Lyude Paul <lyude@redhat.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: kernel test robot <lkp@intel.com>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v2)
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_helper.c | 132 ++++++++++++++++++
drivers/gpu/drm/display/drm_dp_mst_topology.c | 23 ++-
include/drm/display/drm_dp_helper.h | 11 ++
3 files changed, 160 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index e5d7970a9ddd0..72ba9ae89f862 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -3900,3 +3900,135 @@ int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
#endif
+
+/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
+static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
+ int symbol_size, bool is_mst)
+{
+ int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
+ int align = is_mst ? 4 / lane_count : 1;
+
+ return ALIGN(cycles, align);
+}
+
+static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,
+ int bpp_x16, int symbol_size, bool is_mst)
+{
+ int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
+ int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,
+ bpp_x16, symbol_size, is_mst);
+ int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
+
+ return slice_count * (slice_data_cycles + slice_eoc_cycles);
+}
+
+/**
+ * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
+ * @lane_count: DP link lane count
+ * @hactive: pixel count of the active period in one scanline of the stream
+ * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set
+ * @bpp_x16: bits per pixel in .4 binary fixed point
+ * @flags: DRM_DP_OVERHEAD_x flags
+ *
+ * Calculate the BW allocation overhead of a DP link stream, depending
+ * on the link's
+ * - @lane_count
+ * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
+ * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
+ * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
+ * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
+ * as well as the stream's
+ * - @hactive timing
+ * - @bpp_x16 color depth
+ * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).
+ * Note that this overhead doesn't account for the 8b/10b, 128b/132b
+ * channel coding efficiency, for that see
+ * @drm_dp_link_bw_channel_coding_efficiency().
+ *
+ * Returns the overhead as 100% + overhead% in 1ppm units.
+ */
+int drm_dp_bw_overhead(int lane_count, int hactive,
+ int dsc_slice_count,
+ int bpp_x16, unsigned long flags)
+{
+ int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8;
+ bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;
+ u32 overhead = 1000000;
+ int symbol_cycles;
+
+ /*
+ * DP Standard v2.1 2.6.4.1
+ * SSC downspread and ref clock variation margin:
+ * 5300ppm + 300ppm ~ 0.6%
+ */
+ if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK)
+ overhead += 6000;
+
+ /*
+ * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4:
+ * FEC symbol insertions for 8b/10b channel coding:
+ * After each 250 data symbols on 2-4 lanes:
+ * 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block)
+ * After each 2 x 250 data symbols on 1 lane:
+ * 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block)
+ * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks:
+ * 256 * 256 bytes + 1 FEC_PM
+ * or
+ * 128 * 512 bytes + 1 FEC_PM
+ * (256 * 6 + 1) / (256 * 250) = 2.4015625 %
+ */
+ if (flags & DRM_DP_BW_OVERHEAD_FEC)
+ overhead += 24016;
+
+ /*
+ * DP Standard v2.1 2.7.9, 5.9.7
+ * The FEC overhead for UHBR is accounted for in its 96.71% channel
+ * coding efficiency.
+ */
+ WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
+ (flags & DRM_DP_BW_OVERHEAD_FEC));
+
+ if (flags & DRM_DP_BW_OVERHEAD_DSC)
+ symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,
+ dsc_slice_count,
+ bpp_x16, symbol_size,
+ is_mst);
+ else
+ symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
+ bpp_x16, symbol_size,
+ is_mst);
+
+ return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
+ overhead * 16),
+ hactive * bpp_x16);
+}
+EXPORT_SYMBOL(drm_dp_bw_overhead);
+
+/**
+ * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
+ * @is_uhbr: Whether the link has a 128b/132b channel coding
+ *
+ * Return the channel coding efficiency of the given DP link type, which is
+ * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes
+ * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
+ * and for 128b/132b any link or PHY level control symbol insertion overhead
+ * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the
+ * corresponding FEC overhead is BW allocation specific, included in the value
+ * returned by drm_dp_bw_overhead().
+ *
+ * Returns the efficiency in the 100%/coding-overhead% ratio in
+ * 1ppm units.
+ */
+int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
+{
+ if (is_uhbr)
+ return 967100;
+ else
+ /*
+ * Note that on 8b/10b MST the efficiency is only
+ * 78.75% due to the 1 out of 64 MTPH packet overhead,
+ * not accounted for here.
+ */
+ return 800000;
+}
+EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index cc0a8fe84d290..4d72c9a32026e 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -4726,17 +4726,28 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
int drm_dp_calc_pbn_mode(int clock, int bpp)
{
/*
- * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
* The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
* common multiplier to render an integer PBN for all link rate/lane
* counts combinations
* calculate
- * peak_kbps *= (1006/1000)
- * peak_kbps *= (64/54)
- * peak_kbps *= 8 convert to bytes
+ * peak_kbps = clock * bpp / 16
+ * peak_kbps *= SSC overhead / 1000000
+ * peak_kbps /= 8 convert to Kbytes
+ * peak_kBps *= (64/54) / 1000 convert to PBN
*/
- return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
- 1000 * 8 * 54 * 1000);
+ /*
+ * TODO: Use the actual link and mode parameters to calculate
+ * the overhead. For now it's assumed that these are
+ * 4 link lanes, 4096 hactive pixels, which don't add any
+ * significant data padding overhead and that there is no DSC
+ * or FEC overhead.
+ */
+ int overhead = drm_dp_bw_overhead(4, 4096, 0, bpp,
+ DRM_DP_BW_OVERHEAD_MST |
+ DRM_DP_BW_OVERHEAD_SSC_REF_CLK);
+
+ return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),
+ 1000000ULL * 8 * 54 * 1000);
}
EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index da94932f4262b..caee29d28463c 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -788,4 +788,15 @@ bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZ
const u8 port_cap[4], u8 color_spc);
int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
+#define DRM_DP_BW_OVERHEAD_MST BIT(0)
+#define DRM_DP_BW_OVERHEAD_UHBR BIT(1)
+#define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2)
+#define DRM_DP_BW_OVERHEAD_FEC BIT(3)
+#define DRM_DP_BW_OVERHEAD_DSC BIT(4)
+
+int drm_dp_bw_overhead(int lane_count, int hactive,
+ int dsc_slice_count,
+ int bpp_x16, unsigned long flags);
+int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
+
#endif /* _DRM_DP_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PATCH v5 09/30] drm/dp: Add helpers to calculate the link BW overhead
@ 2023-11-07 0:14 ` Imre Deak
0 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-11-07 0:14 UTC (permalink / raw)
To: intel-gfx
Cc: kernel test robot, dri-devel, Stanislav Lisovskiy, Maxime Ripard
Add helpers drivers can use to calculate the BW allocation overhead -
due to SSC, FEC, DSC and data alignment on symbol cycles - and the
channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On
128b/132b links the FEC overhead is part of the coding efficiency, so
not accounted for in the BW allocation overhead.
The drivers can use these functions to calculate a ratio, controlling
the stream symbol insertion rate of the source device in each SST TU
or MST MTP frame. Drivers can calculate this
m/n = (pixel_data_rate * drm_dp_bw_overhead()) /
(link_data_rate * drm_dp_bw_channel_coding_efficiency())
ratio for a given link and pixel stream and with that the
slots_per_mtp = CEIL(64 * m / n)
allocated slots per MTP for the stream in a link frame and with
that the
pbn = slots_per_mtp * drm_mst_get_pbn_divider()
allocated PBNs for the stream on the MST link path.
Take drm_dp_bw_overhead() into use in drm_dp_calc_pbn_mode(), for
drivers calculating the PBN value directly.
v2:
- Add dockbook description to drm_dp_bw_channel_coding_efficiency().
(LKP).
- Clarify the way m/n ratio is calculated in the commit log.
v3:
- Fix compile breakage for !CONFIG_BACKLIGHT_CLASS_DEVICE. (LKP)
- Account for FEC_PM overhead (+ 0.0015625 %), add comment
with the formula to calculate the total FEC overhead. (Ville)
v4:
- Rename DRM_DP_OVERHEAD_SSC to DRM_DP_OVERHEAD_SSC_REF_CLK. (Ville)
v5:
- Clarify in the commit log what MTP means.
- Simplify the commit log's formula to calculate PBN.
Cc: Lyude Paul <lyude@redhat.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: kernel test robot <lkp@intel.com>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v2)
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_helper.c | 132 ++++++++++++++++++
drivers/gpu/drm/display/drm_dp_mst_topology.c | 23 ++-
include/drm/display/drm_dp_helper.h | 11 ++
3 files changed, 160 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index e5d7970a9ddd0..72ba9ae89f862 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -3900,3 +3900,135 @@ int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
#endif
+
+/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
+static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
+ int symbol_size, bool is_mst)
+{
+ int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
+ int align = is_mst ? 4 / lane_count : 1;
+
+ return ALIGN(cycles, align);
+}
+
+static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,
+ int bpp_x16, int symbol_size, bool is_mst)
+{
+ int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
+ int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,
+ bpp_x16, symbol_size, is_mst);
+ int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
+
+ return slice_count * (slice_data_cycles + slice_eoc_cycles);
+}
+
+/**
+ * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
+ * @lane_count: DP link lane count
+ * @hactive: pixel count of the active period in one scanline of the stream
+ * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set
+ * @bpp_x16: bits per pixel in .4 binary fixed point
+ * @flags: DRM_DP_OVERHEAD_x flags
+ *
+ * Calculate the BW allocation overhead of a DP link stream, depending
+ * on the link's
+ * - @lane_count
+ * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
+ * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
+ * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
+ * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
+ * as well as the stream's
+ * - @hactive timing
+ * - @bpp_x16 color depth
+ * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).
+ * Note that this overhead doesn't account for the 8b/10b, 128b/132b
+ * channel coding efficiency, for that see
+ * @drm_dp_link_bw_channel_coding_efficiency().
+ *
+ * Returns the overhead as 100% + overhead% in 1ppm units.
+ */
+int drm_dp_bw_overhead(int lane_count, int hactive,
+ int dsc_slice_count,
+ int bpp_x16, unsigned long flags)
+{
+ int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8;
+ bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;
+ u32 overhead = 1000000;
+ int symbol_cycles;
+
+ /*
+ * DP Standard v2.1 2.6.4.1
+ * SSC downspread and ref clock variation margin:
+ * 5300ppm + 300ppm ~ 0.6%
+ */
+ if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK)
+ overhead += 6000;
+
+ /*
+ * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4:
+ * FEC symbol insertions for 8b/10b channel coding:
+ * After each 250 data symbols on 2-4 lanes:
+ * 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block)
+ * After each 2 x 250 data symbols on 1 lane:
+ * 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block)
+ * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks:
+ * 256 * 256 bytes + 1 FEC_PM
+ * or
+ * 128 * 512 bytes + 1 FEC_PM
+ * (256 * 6 + 1) / (256 * 250) = 2.4015625 %
+ */
+ if (flags & DRM_DP_BW_OVERHEAD_FEC)
+ overhead += 24016;
+
+ /*
+ * DP Standard v2.1 2.7.9, 5.9.7
+ * The FEC overhead for UHBR is accounted for in its 96.71% channel
+ * coding efficiency.
+ */
+ WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
+ (flags & DRM_DP_BW_OVERHEAD_FEC));
+
+ if (flags & DRM_DP_BW_OVERHEAD_DSC)
+ symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,
+ dsc_slice_count,
+ bpp_x16, symbol_size,
+ is_mst);
+ else
+ symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
+ bpp_x16, symbol_size,
+ is_mst);
+
+ return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
+ overhead * 16),
+ hactive * bpp_x16);
+}
+EXPORT_SYMBOL(drm_dp_bw_overhead);
+
+/**
+ * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
+ * @is_uhbr: Whether the link has a 128b/132b channel coding
+ *
+ * Return the channel coding efficiency of the given DP link type, which is
+ * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes
+ * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
+ * and for 128b/132b any link or PHY level control symbol insertion overhead
+ * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the
+ * corresponding FEC overhead is BW allocation specific, included in the value
+ * returned by drm_dp_bw_overhead().
+ *
+ * Returns the efficiency in the 100%/coding-overhead% ratio in
+ * 1ppm units.
+ */
+int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
+{
+ if (is_uhbr)
+ return 967100;
+ else
+ /*
+ * Note that on 8b/10b MST the efficiency is only
+ * 78.75% due to the 1 out of 64 MTPH packet overhead,
+ * not accounted for here.
+ */
+ return 800000;
+}
+EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index cc0a8fe84d290..4d72c9a32026e 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -4726,17 +4726,28 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
int drm_dp_calc_pbn_mode(int clock, int bpp)
{
/*
- * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
* The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
* common multiplier to render an integer PBN for all link rate/lane
* counts combinations
* calculate
- * peak_kbps *= (1006/1000)
- * peak_kbps *= (64/54)
- * peak_kbps *= 8 convert to bytes
+ * peak_kbps = clock * bpp / 16
+ * peak_kbps *= SSC overhead / 1000000
+ * peak_kbps /= 8 convert to Kbytes
+ * peak_kBps *= (64/54) / 1000 convert to PBN
*/
- return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
- 1000 * 8 * 54 * 1000);
+ /*
+ * TODO: Use the actual link and mode parameters to calculate
+ * the overhead. For now it's assumed that these are
+ * 4 link lanes, 4096 hactive pixels, which don't add any
+ * significant data padding overhead and that there is no DSC
+ * or FEC overhead.
+ */
+ int overhead = drm_dp_bw_overhead(4, 4096, 0, bpp,
+ DRM_DP_BW_OVERHEAD_MST |
+ DRM_DP_BW_OVERHEAD_SSC_REF_CLK);
+
+ return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),
+ 1000000ULL * 8 * 54 * 1000);
}
EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index da94932f4262b..caee29d28463c 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -788,4 +788,15 @@ bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZ
const u8 port_cap[4], u8 color_spc);
int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
+#define DRM_DP_BW_OVERHEAD_MST BIT(0)
+#define DRM_DP_BW_OVERHEAD_UHBR BIT(1)
+#define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2)
+#define DRM_DP_BW_OVERHEAD_FEC BIT(3)
+#define DRM_DP_BW_OVERHEAD_DSC BIT(4)
+
+int drm_dp_bw_overhead(int lane_count, int hactive,
+ int dsc_slice_count,
+ int bpp_x16, unsigned long flags);
+int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
+
#endif /* _DRM_DP_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v5 09/30] drm/dp: Add helpers to calculate the link BW overhead
2023-11-07 0:14 ` Imre Deak
@ 2023-11-07 22:45 ` Lyude Paul
-1 siblings, 0 replies; 94+ messages in thread
From: Lyude Paul @ 2023-11-07 22:45 UTC (permalink / raw)
To: Imre Deak, intel-gfx; +Cc: dri-devel, Maxime Ripard
Reviewed-by: Lyude Paul <lyude@redhat.com>
On Tue, 2023-11-07 at 02:14 +0200, Imre Deak wrote:
> Add helpers drivers can use to calculate the BW allocation overhead -
> due to SSC, FEC, DSC and data alignment on symbol cycles - and the
> channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On
> 128b/132b links the FEC overhead is part of the coding efficiency, so
> not accounted for in the BW allocation overhead.
>
> The drivers can use these functions to calculate a ratio, controlling
> the stream symbol insertion rate of the source device in each SST TU
> or MST MTP frame. Drivers can calculate this
>
> m/n = (pixel_data_rate * drm_dp_bw_overhead()) /
> (link_data_rate * drm_dp_bw_channel_coding_efficiency())
>
> ratio for a given link and pixel stream and with that the
>
> slots_per_mtp = CEIL(64 * m / n)
>
> allocated slots per MTP for the stream in a link frame and with
> that the
>
> pbn = slots_per_mtp * drm_mst_get_pbn_divider()
>
> allocated PBNs for the stream on the MST link path.
>
> Take drm_dp_bw_overhead() into use in drm_dp_calc_pbn_mode(), for
> drivers calculating the PBN value directly.
>
> v2:
> - Add dockbook description to drm_dp_bw_channel_coding_efficiency().
> (LKP).
> - Clarify the way m/n ratio is calculated in the commit log.
> v3:
> - Fix compile breakage for !CONFIG_BACKLIGHT_CLASS_DEVICE. (LKP)
> - Account for FEC_PM overhead (+ 0.0015625 %), add comment
> with the formula to calculate the total FEC overhead. (Ville)
> v4:
> - Rename DRM_DP_OVERHEAD_SSC to DRM_DP_OVERHEAD_SSC_REF_CLK. (Ville)
> v5:
> - Clarify in the commit log what MTP means.
> - Simplify the commit log's formula to calculate PBN.
>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: kernel test robot <lkp@intel.com>
> Cc: dri-devel@lists.freedesktop.org
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v2)
> Acked-by: Maxime Ripard <mripard@kernel.org>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 132 ++++++++++++++++++
> drivers/gpu/drm/display/drm_dp_mst_topology.c | 23 ++-
> include/drm/display/drm_dp_helper.h | 11 ++
> 3 files changed, 160 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> index e5d7970a9ddd0..72ba9ae89f862 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -3900,3 +3900,135 @@ int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
> EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
>
> #endif
> +
> +/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
> +static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
> + int symbol_size, bool is_mst)
> +{
> + int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
> + int align = is_mst ? 4 / lane_count : 1;
> +
> + return ALIGN(cycles, align);
> +}
> +
> +static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,
> + int bpp_x16, int symbol_size, bool is_mst)
> +{
> + int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
> + int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,
> + bpp_x16, symbol_size, is_mst);
> + int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
> +
> + return slice_count * (slice_data_cycles + slice_eoc_cycles);
> +}
> +
> +/**
> + * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
> + * @lane_count: DP link lane count
> + * @hactive: pixel count of the active period in one scanline of the stream
> + * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set
> + * @bpp_x16: bits per pixel in .4 binary fixed point
> + * @flags: DRM_DP_OVERHEAD_x flags
> + *
> + * Calculate the BW allocation overhead of a DP link stream, depending
> + * on the link's
> + * - @lane_count
> + * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
> + * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
> + * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
> + * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
> + * as well as the stream's
> + * - @hactive timing
> + * - @bpp_x16 color depth
> + * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).
> + * Note that this overhead doesn't account for the 8b/10b, 128b/132b
> + * channel coding efficiency, for that see
> + * @drm_dp_link_bw_channel_coding_efficiency().
> + *
> + * Returns the overhead as 100% + overhead% in 1ppm units.
> + */
> +int drm_dp_bw_overhead(int lane_count, int hactive,
> + int dsc_slice_count,
> + int bpp_x16, unsigned long flags)
> +{
> + int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8;
> + bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;
> + u32 overhead = 1000000;
> + int symbol_cycles;
> +
> + /*
> + * DP Standard v2.1 2.6.4.1
> + * SSC downspread and ref clock variation margin:
> + * 5300ppm + 300ppm ~ 0.6%
> + */
> + if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK)
> + overhead += 6000;
> +
> + /*
> + * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4:
> + * FEC symbol insertions for 8b/10b channel coding:
> + * After each 250 data symbols on 2-4 lanes:
> + * 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block)
> + * After each 2 x 250 data symbols on 1 lane:
> + * 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block)
> + * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks:
> + * 256 * 256 bytes + 1 FEC_PM
> + * or
> + * 128 * 512 bytes + 1 FEC_PM
> + * (256 * 6 + 1) / (256 * 250) = 2.4015625 %
> + */
> + if (flags & DRM_DP_BW_OVERHEAD_FEC)
> + overhead += 24016;
> +
> + /*
> + * DP Standard v2.1 2.7.9, 5.9.7
> + * The FEC overhead for UHBR is accounted for in its 96.71% channel
> + * coding efficiency.
> + */
> + WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
> + (flags & DRM_DP_BW_OVERHEAD_FEC));
> +
> + if (flags & DRM_DP_BW_OVERHEAD_DSC)
> + symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,
> + dsc_slice_count,
> + bpp_x16, symbol_size,
> + is_mst);
> + else
> + symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
> + bpp_x16, symbol_size,
> + is_mst);
> +
> + return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
> + overhead * 16),
> + hactive * bpp_x16);
> +}
> +EXPORT_SYMBOL(drm_dp_bw_overhead);
> +
> +/**
> + * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
> + * @is_uhbr: Whether the link has a 128b/132b channel coding
> + *
> + * Return the channel coding efficiency of the given DP link type, which is
> + * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes
> + * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
> + * and for 128b/132b any link or PHY level control symbol insertion overhead
> + * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the
> + * corresponding FEC overhead is BW allocation specific, included in the value
> + * returned by drm_dp_bw_overhead().
> + *
> + * Returns the efficiency in the 100%/coding-overhead% ratio in
> + * 1ppm units.
> + */
> +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
> +{
> + if (is_uhbr)
> + return 967100;
> + else
> + /*
> + * Note that on 8b/10b MST the efficiency is only
> + * 78.75% due to the 1 out of 64 MTPH packet overhead,
> + * not accounted for here.
> + */
> + return 800000;
> +}
> +EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> index cc0a8fe84d290..4d72c9a32026e 100644
> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> @@ -4726,17 +4726,28 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
> int drm_dp_calc_pbn_mode(int clock, int bpp)
> {
> /*
> - * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
> * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
> * common multiplier to render an integer PBN for all link rate/lane
> * counts combinations
> * calculate
> - * peak_kbps *= (1006/1000)
> - * peak_kbps *= (64/54)
> - * peak_kbps *= 8 convert to bytes
> + * peak_kbps = clock * bpp / 16
> + * peak_kbps *= SSC overhead / 1000000
> + * peak_kbps /= 8 convert to Kbytes
> + * peak_kBps *= (64/54) / 1000 convert to PBN
> */
> - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
> - 1000 * 8 * 54 * 1000);
> + /*
> + * TODO: Use the actual link and mode parameters to calculate
> + * the overhead. For now it's assumed that these are
> + * 4 link lanes, 4096 hactive pixels, which don't add any
> + * significant data padding overhead and that there is no DSC
> + * or FEC overhead.
> + */
> + int overhead = drm_dp_bw_overhead(4, 4096, 0, bpp,
> + DRM_DP_BW_OVERHEAD_MST |
> + DRM_DP_BW_OVERHEAD_SSC_REF_CLK);
> +
> + return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),
> + 1000000ULL * 8 * 54 * 1000);
> }
> EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
>
> diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> index da94932f4262b..caee29d28463c 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -788,4 +788,15 @@ bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZ
> const u8 port_cap[4], u8 color_spc);
> int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
>
> +#define DRM_DP_BW_OVERHEAD_MST BIT(0)
> +#define DRM_DP_BW_OVERHEAD_UHBR BIT(1)
> +#define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2)
> +#define DRM_DP_BW_OVERHEAD_FEC BIT(3)
> +#define DRM_DP_BW_OVERHEAD_DSC BIT(4)
> +
> +int drm_dp_bw_overhead(int lane_count, int hactive,
> + int dsc_slice_count,
> + int bpp_x16, unsigned long flags);
> +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
> +
> #endif /* _DRM_DP_HELPER_H_ */
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v5 09/30] drm/dp: Add helpers to calculate the link BW overhead
@ 2023-11-07 22:45 ` Lyude Paul
0 siblings, 0 replies; 94+ messages in thread
From: Lyude Paul @ 2023-11-07 22:45 UTC (permalink / raw)
To: Imre Deak, intel-gfx
Cc: Stanislav Lisovskiy, dri-devel, kernel test robot, Maxime Ripard
Reviewed-by: Lyude Paul <lyude@redhat.com>
On Tue, 2023-11-07 at 02:14 +0200, Imre Deak wrote:
> Add helpers drivers can use to calculate the BW allocation overhead -
> due to SSC, FEC, DSC and data alignment on symbol cycles - and the
> channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On
> 128b/132b links the FEC overhead is part of the coding efficiency, so
> not accounted for in the BW allocation overhead.
>
> The drivers can use these functions to calculate a ratio, controlling
> the stream symbol insertion rate of the source device in each SST TU
> or MST MTP frame. Drivers can calculate this
>
> m/n = (pixel_data_rate * drm_dp_bw_overhead()) /
> (link_data_rate * drm_dp_bw_channel_coding_efficiency())
>
> ratio for a given link and pixel stream and with that the
>
> slots_per_mtp = CEIL(64 * m / n)
>
> allocated slots per MTP for the stream in a link frame and with
> that the
>
> pbn = slots_per_mtp * drm_mst_get_pbn_divider()
>
> allocated PBNs for the stream on the MST link path.
>
> Take drm_dp_bw_overhead() into use in drm_dp_calc_pbn_mode(), for
> drivers calculating the PBN value directly.
>
> v2:
> - Add dockbook description to drm_dp_bw_channel_coding_efficiency().
> (LKP).
> - Clarify the way m/n ratio is calculated in the commit log.
> v3:
> - Fix compile breakage for !CONFIG_BACKLIGHT_CLASS_DEVICE. (LKP)
> - Account for FEC_PM overhead (+ 0.0015625 %), add comment
> with the formula to calculate the total FEC overhead. (Ville)
> v4:
> - Rename DRM_DP_OVERHEAD_SSC to DRM_DP_OVERHEAD_SSC_REF_CLK. (Ville)
> v5:
> - Clarify in the commit log what MTP means.
> - Simplify the commit log's formula to calculate PBN.
>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: kernel test robot <lkp@intel.com>
> Cc: dri-devel@lists.freedesktop.org
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v2)
> Acked-by: Maxime Ripard <mripard@kernel.org>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 132 ++++++++++++++++++
> drivers/gpu/drm/display/drm_dp_mst_topology.c | 23 ++-
> include/drm/display/drm_dp_helper.h | 11 ++
> 3 files changed, 160 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> index e5d7970a9ddd0..72ba9ae89f862 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -3900,3 +3900,135 @@ int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
> EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
>
> #endif
> +
> +/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
> +static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
> + int symbol_size, bool is_mst)
> +{
> + int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
> + int align = is_mst ? 4 / lane_count : 1;
> +
> + return ALIGN(cycles, align);
> +}
> +
> +static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,
> + int bpp_x16, int symbol_size, bool is_mst)
> +{
> + int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
> + int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,
> + bpp_x16, symbol_size, is_mst);
> + int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
> +
> + return slice_count * (slice_data_cycles + slice_eoc_cycles);
> +}
> +
> +/**
> + * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
> + * @lane_count: DP link lane count
> + * @hactive: pixel count of the active period in one scanline of the stream
> + * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set
> + * @bpp_x16: bits per pixel in .4 binary fixed point
> + * @flags: DRM_DP_OVERHEAD_x flags
> + *
> + * Calculate the BW allocation overhead of a DP link stream, depending
> + * on the link's
> + * - @lane_count
> + * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
> + * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
> + * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
> + * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
> + * as well as the stream's
> + * - @hactive timing
> + * - @bpp_x16 color depth
> + * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).
> + * Note that this overhead doesn't account for the 8b/10b, 128b/132b
> + * channel coding efficiency, for that see
> + * @drm_dp_link_bw_channel_coding_efficiency().
> + *
> + * Returns the overhead as 100% + overhead% in 1ppm units.
> + */
> +int drm_dp_bw_overhead(int lane_count, int hactive,
> + int dsc_slice_count,
> + int bpp_x16, unsigned long flags)
> +{
> + int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8;
> + bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;
> + u32 overhead = 1000000;
> + int symbol_cycles;
> +
> + /*
> + * DP Standard v2.1 2.6.4.1
> + * SSC downspread and ref clock variation margin:
> + * 5300ppm + 300ppm ~ 0.6%
> + */
> + if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK)
> + overhead += 6000;
> +
> + /*
> + * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4:
> + * FEC symbol insertions for 8b/10b channel coding:
> + * After each 250 data symbols on 2-4 lanes:
> + * 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block)
> + * After each 2 x 250 data symbols on 1 lane:
> + * 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block)
> + * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks:
> + * 256 * 256 bytes + 1 FEC_PM
> + * or
> + * 128 * 512 bytes + 1 FEC_PM
> + * (256 * 6 + 1) / (256 * 250) = 2.4015625 %
> + */
> + if (flags & DRM_DP_BW_OVERHEAD_FEC)
> + overhead += 24016;
> +
> + /*
> + * DP Standard v2.1 2.7.9, 5.9.7
> + * The FEC overhead for UHBR is accounted for in its 96.71% channel
> + * coding efficiency.
> + */
> + WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
> + (flags & DRM_DP_BW_OVERHEAD_FEC));
> +
> + if (flags & DRM_DP_BW_OVERHEAD_DSC)
> + symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,
> + dsc_slice_count,
> + bpp_x16, symbol_size,
> + is_mst);
> + else
> + symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
> + bpp_x16, symbol_size,
> + is_mst);
> +
> + return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
> + overhead * 16),
> + hactive * bpp_x16);
> +}
> +EXPORT_SYMBOL(drm_dp_bw_overhead);
> +
> +/**
> + * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
> + * @is_uhbr: Whether the link has a 128b/132b channel coding
> + *
> + * Return the channel coding efficiency of the given DP link type, which is
> + * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes
> + * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
> + * and for 128b/132b any link or PHY level control symbol insertion overhead
> + * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the
> + * corresponding FEC overhead is BW allocation specific, included in the value
> + * returned by drm_dp_bw_overhead().
> + *
> + * Returns the efficiency in the 100%/coding-overhead% ratio in
> + * 1ppm units.
> + */
> +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
> +{
> + if (is_uhbr)
> + return 967100;
> + else
> + /*
> + * Note that on 8b/10b MST the efficiency is only
> + * 78.75% due to the 1 out of 64 MTPH packet overhead,
> + * not accounted for here.
> + */
> + return 800000;
> +}
> +EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> index cc0a8fe84d290..4d72c9a32026e 100644
> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> @@ -4726,17 +4726,28 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
> int drm_dp_calc_pbn_mode(int clock, int bpp)
> {
> /*
> - * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
> * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
> * common multiplier to render an integer PBN for all link rate/lane
> * counts combinations
> * calculate
> - * peak_kbps *= (1006/1000)
> - * peak_kbps *= (64/54)
> - * peak_kbps *= 8 convert to bytes
> + * peak_kbps = clock * bpp / 16
> + * peak_kbps *= SSC overhead / 1000000
> + * peak_kbps /= 8 convert to Kbytes
> + * peak_kBps *= (64/54) / 1000 convert to PBN
> */
> - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
> - 1000 * 8 * 54 * 1000);
> + /*
> + * TODO: Use the actual link and mode parameters to calculate
> + * the overhead. For now it's assumed that these are
> + * 4 link lanes, 4096 hactive pixels, which don't add any
> + * significant data padding overhead and that there is no DSC
> + * or FEC overhead.
> + */
> + int overhead = drm_dp_bw_overhead(4, 4096, 0, bpp,
> + DRM_DP_BW_OVERHEAD_MST |
> + DRM_DP_BW_OVERHEAD_SSC_REF_CLK);
> +
> + return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),
> + 1000000ULL * 8 * 54 * 1000);
> }
> EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
>
> diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> index da94932f4262b..caee29d28463c 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -788,4 +788,15 @@ bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZ
> const u8 port_cap[4], u8 color_spc);
> int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
>
> +#define DRM_DP_BW_OVERHEAD_MST BIT(0)
> +#define DRM_DP_BW_OVERHEAD_UHBR BIT(1)
> +#define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2)
> +#define DRM_DP_BW_OVERHEAD_FEC BIT(3)
> +#define DRM_DP_BW_OVERHEAD_DSC BIT(4)
> +
> +int drm_dp_bw_overhead(int lane_count, int hactive,
> + int dsc_slice_count,
> + int bpp_x16, unsigned long flags);
> +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
> +
> #endif /* _DRM_DP_HELPER_H_ */
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [Intel-gfx] [PATCH v4 09/30] drm/dp: Add helpers to calculate the link BW overhead
2023-10-30 15:58 ` Imre Deak
@ 2023-11-07 22:42 ` Lyude Paul
-1 siblings, 0 replies; 94+ messages in thread
From: Lyude Paul @ 2023-11-07 22:42 UTC (permalink / raw)
To: Imre Deak, intel-gfx; +Cc: dri-devel
Reviewed-by: Lyude Paul <lyude@redhat.com>
On Mon, 2023-10-30 at 17:58 +0200, Imre Deak wrote:
> Add helpers drivers can use to calculate the BW allocation overhead -
> due to SSC, FEC, DSC and data alignment on symbol cycles - and the
> channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On
> 128b/132b links the FEC overhead is part of the coding efficiency, so
> not accounted for in the BW allocation overhead.
>
> The drivers can use these functions to calculate a ratio, controlling
> the stream symbol insertion rate of the source device in each SST TU
> or MST MTP frame. Drivers can calculate this
>
> m/n = (pixel_data_rate * drm_dp_bw_overhead()) /
> (link_data_rate * drm_dp_bw_channel_coding_efficiency())
>
> ratio for a given link and pixel stream and with that the
>
> mtp_count = CEIL(64 * m / n)
>
> allocated MTPs for the stream in a link frame and
>
> pbn = CEIL(64 * dm_mst_get_pbn_divider() * m / n)
>
> allocated PBNs for the stream on the MST link path.
>
> Take drm_dp_bw_overhead() into use in drm_dp_calc_pbn_mode(), for
> drivers calculating the PBN value directly.
>
> v2:
> - Add dockbook description to drm_dp_bw_channel_coding_efficiency().
> (LKP).
> - Clarify the way m/n ratio is calculated in the commit log.
> v3:
> - Fix compile breakage for !CONFIG_BACKLIGHT_CLASS_DEVICE. (LKP)
> - Account for FEC_PM overhead (+ 0.0015625 %), add comment
> with the formula to calculate the total FEC overhead. (Ville)
> v4:
> - Rename DRM_DP_OVERHEAD_SSC to DRM_DP_OVERHEAD_SSC_REF_CLK. (Ville)
>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: kernel test robot <lkp@intel.com>
> Cc: dri-devel@lists.freedesktop.org
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v2)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 132 ++++++++++++++++++
> drivers/gpu/drm/display/drm_dp_mst_topology.c | 23 ++-
> include/drm/display/drm_dp_helper.h | 11 ++
> 3 files changed, 160 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> index e5d7970a9ddd0..72ba9ae89f862 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -3900,3 +3900,135 @@ int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
> EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
>
> #endif
> +
> +/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
> +static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
> + int symbol_size, bool is_mst)
> +{
> + int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
> + int align = is_mst ? 4 / lane_count : 1;
> +
> + return ALIGN(cycles, align);
> +}
> +
> +static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,
> + int bpp_x16, int symbol_size, bool is_mst)
> +{
> + int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
> + int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,
> + bpp_x16, symbol_size, is_mst);
> + int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
> +
> + return slice_count * (slice_data_cycles + slice_eoc_cycles);
> +}
> +
> +/**
> + * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
> + * @lane_count: DP link lane count
> + * @hactive: pixel count of the active period in one scanline of the stream
> + * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set
> + * @bpp_x16: bits per pixel in .4 binary fixed point
> + * @flags: DRM_DP_OVERHEAD_x flags
> + *
> + * Calculate the BW allocation overhead of a DP link stream, depending
> + * on the link's
> + * - @lane_count
> + * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
> + * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
> + * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
> + * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
> + * as well as the stream's
> + * - @hactive timing
> + * - @bpp_x16 color depth
> + * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).
> + * Note that this overhead doesn't account for the 8b/10b, 128b/132b
> + * channel coding efficiency, for that see
> + * @drm_dp_link_bw_channel_coding_efficiency().
> + *
> + * Returns the overhead as 100% + overhead% in 1ppm units.
> + */
> +int drm_dp_bw_overhead(int lane_count, int hactive,
> + int dsc_slice_count,
> + int bpp_x16, unsigned long flags)
> +{
> + int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8;
> + bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;
> + u32 overhead = 1000000;
> + int symbol_cycles;
> +
> + /*
> + * DP Standard v2.1 2.6.4.1
> + * SSC downspread and ref clock variation margin:
> + * 5300ppm + 300ppm ~ 0.6%
> + */
> + if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK)
> + overhead += 6000;
> +
> + /*
> + * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4:
> + * FEC symbol insertions for 8b/10b channel coding:
> + * After each 250 data symbols on 2-4 lanes:
> + * 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block)
> + * After each 2 x 250 data symbols on 1 lane:
> + * 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block)
> + * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks:
> + * 256 * 256 bytes + 1 FEC_PM
> + * or
> + * 128 * 512 bytes + 1 FEC_PM
> + * (256 * 6 + 1) / (256 * 250) = 2.4015625 %
> + */
> + if (flags & DRM_DP_BW_OVERHEAD_FEC)
> + overhead += 24016;
> +
> + /*
> + * DP Standard v2.1 2.7.9, 5.9.7
> + * The FEC overhead for UHBR is accounted for in its 96.71% channel
> + * coding efficiency.
> + */
> + WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
> + (flags & DRM_DP_BW_OVERHEAD_FEC));
> +
> + if (flags & DRM_DP_BW_OVERHEAD_DSC)
> + symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,
> + dsc_slice_count,
> + bpp_x16, symbol_size,
> + is_mst);
> + else
> + symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
> + bpp_x16, symbol_size,
> + is_mst);
> +
> + return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
> + overhead * 16),
> + hactive * bpp_x16);
> +}
> +EXPORT_SYMBOL(drm_dp_bw_overhead);
> +
> +/**
> + * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
> + * @is_uhbr: Whether the link has a 128b/132b channel coding
> + *
> + * Return the channel coding efficiency of the given DP link type, which is
> + * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes
> + * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
> + * and for 128b/132b any link or PHY level control symbol insertion overhead
> + * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the
> + * corresponding FEC overhead is BW allocation specific, included in the value
> + * returned by drm_dp_bw_overhead().
> + *
> + * Returns the efficiency in the 100%/coding-overhead% ratio in
> + * 1ppm units.
> + */
> +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
> +{
> + if (is_uhbr)
> + return 967100;
> + else
> + /*
> + * Note that on 8b/10b MST the efficiency is only
> + * 78.75% due to the 1 out of 64 MTPH packet overhead,
> + * not accounted for here.
> + */
> + return 800000;
> +}
> +EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> index cc0a8fe84d290..4d72c9a32026e 100644
> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> @@ -4726,17 +4726,28 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
> int drm_dp_calc_pbn_mode(int clock, int bpp)
> {
> /*
> - * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
> * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
> * common multiplier to render an integer PBN for all link rate/lane
> * counts combinations
> * calculate
> - * peak_kbps *= (1006/1000)
> - * peak_kbps *= (64/54)
> - * peak_kbps *= 8 convert to bytes
> + * peak_kbps = clock * bpp / 16
> + * peak_kbps *= SSC overhead / 1000000
> + * peak_kbps /= 8 convert to Kbytes
> + * peak_kBps *= (64/54) / 1000 convert to PBN
> */
> - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
> - 1000 * 8 * 54 * 1000);
> + /*
> + * TODO: Use the actual link and mode parameters to calculate
> + * the overhead. For now it's assumed that these are
> + * 4 link lanes, 4096 hactive pixels, which don't add any
> + * significant data padding overhead and that there is no DSC
> + * or FEC overhead.
> + */
> + int overhead = drm_dp_bw_overhead(4, 4096, 0, bpp,
> + DRM_DP_BW_OVERHEAD_MST |
> + DRM_DP_BW_OVERHEAD_SSC_REF_CLK);
> +
> + return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),
> + 1000000ULL * 8 * 54 * 1000);
> }
> EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
>
> diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> index da94932f4262b..caee29d28463c 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -788,4 +788,15 @@ bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZ
> const u8 port_cap[4], u8 color_spc);
> int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
>
> +#define DRM_DP_BW_OVERHEAD_MST BIT(0)
> +#define DRM_DP_BW_OVERHEAD_UHBR BIT(1)
> +#define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2)
> +#define DRM_DP_BW_OVERHEAD_FEC BIT(3)
> +#define DRM_DP_BW_OVERHEAD_DSC BIT(4)
> +
> +int drm_dp_bw_overhead(int lane_count, int hactive,
> + int dsc_slice_count,
> + int bpp_x16, unsigned long flags);
> +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
> +
> #endif /* _DRM_DP_HELPER_H_ */
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 09/30] drm/dp: Add helpers to calculate the link BW overhead
@ 2023-11-07 22:42 ` Lyude Paul
0 siblings, 0 replies; 94+ messages in thread
From: Lyude Paul @ 2023-11-07 22:42 UTC (permalink / raw)
To: Imre Deak, intel-gfx; +Cc: Stanislav Lisovskiy, dri-devel, kernel test robot
Reviewed-by: Lyude Paul <lyude@redhat.com>
On Mon, 2023-10-30 at 17:58 +0200, Imre Deak wrote:
> Add helpers drivers can use to calculate the BW allocation overhead -
> due to SSC, FEC, DSC and data alignment on symbol cycles - and the
> channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On
> 128b/132b links the FEC overhead is part of the coding efficiency, so
> not accounted for in the BW allocation overhead.
>
> The drivers can use these functions to calculate a ratio, controlling
> the stream symbol insertion rate of the source device in each SST TU
> or MST MTP frame. Drivers can calculate this
>
> m/n = (pixel_data_rate * drm_dp_bw_overhead()) /
> (link_data_rate * drm_dp_bw_channel_coding_efficiency())
>
> ratio for a given link and pixel stream and with that the
>
> mtp_count = CEIL(64 * m / n)
>
> allocated MTPs for the stream in a link frame and
>
> pbn = CEIL(64 * dm_mst_get_pbn_divider() * m / n)
>
> allocated PBNs for the stream on the MST link path.
>
> Take drm_dp_bw_overhead() into use in drm_dp_calc_pbn_mode(), for
> drivers calculating the PBN value directly.
>
> v2:
> - Add dockbook description to drm_dp_bw_channel_coding_efficiency().
> (LKP).
> - Clarify the way m/n ratio is calculated in the commit log.
> v3:
> - Fix compile breakage for !CONFIG_BACKLIGHT_CLASS_DEVICE. (LKP)
> - Account for FEC_PM overhead (+ 0.0015625 %), add comment
> with the formula to calculate the total FEC overhead. (Ville)
> v4:
> - Rename DRM_DP_OVERHEAD_SSC to DRM_DP_OVERHEAD_SSC_REF_CLK. (Ville)
>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: kernel test robot <lkp@intel.com>
> Cc: dri-devel@lists.freedesktop.org
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v2)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 132 ++++++++++++++++++
> drivers/gpu/drm/display/drm_dp_mst_topology.c | 23 ++-
> include/drm/display/drm_dp_helper.h | 11 ++
> 3 files changed, 160 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> index e5d7970a9ddd0..72ba9ae89f862 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -3900,3 +3900,135 @@ int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
> EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
>
> #endif
> +
> +/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
> +static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
> + int symbol_size, bool is_mst)
> +{
> + int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
> + int align = is_mst ? 4 / lane_count : 1;
> +
> + return ALIGN(cycles, align);
> +}
> +
> +static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,
> + int bpp_x16, int symbol_size, bool is_mst)
> +{
> + int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
> + int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,
> + bpp_x16, symbol_size, is_mst);
> + int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
> +
> + return slice_count * (slice_data_cycles + slice_eoc_cycles);
> +}
> +
> +/**
> + * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
> + * @lane_count: DP link lane count
> + * @hactive: pixel count of the active period in one scanline of the stream
> + * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set
> + * @bpp_x16: bits per pixel in .4 binary fixed point
> + * @flags: DRM_DP_OVERHEAD_x flags
> + *
> + * Calculate the BW allocation overhead of a DP link stream, depending
> + * on the link's
> + * - @lane_count
> + * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
> + * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
> + * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
> + * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
> + * as well as the stream's
> + * - @hactive timing
> + * - @bpp_x16 color depth
> + * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).
> + * Note that this overhead doesn't account for the 8b/10b, 128b/132b
> + * channel coding efficiency, for that see
> + * @drm_dp_link_bw_channel_coding_efficiency().
> + *
> + * Returns the overhead as 100% + overhead% in 1ppm units.
> + */
> +int drm_dp_bw_overhead(int lane_count, int hactive,
> + int dsc_slice_count,
> + int bpp_x16, unsigned long flags)
> +{
> + int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8;
> + bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;
> + u32 overhead = 1000000;
> + int symbol_cycles;
> +
> + /*
> + * DP Standard v2.1 2.6.4.1
> + * SSC downspread and ref clock variation margin:
> + * 5300ppm + 300ppm ~ 0.6%
> + */
> + if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK)
> + overhead += 6000;
> +
> + /*
> + * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4:
> + * FEC symbol insertions for 8b/10b channel coding:
> + * After each 250 data symbols on 2-4 lanes:
> + * 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block)
> + * After each 2 x 250 data symbols on 1 lane:
> + * 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block)
> + * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks:
> + * 256 * 256 bytes + 1 FEC_PM
> + * or
> + * 128 * 512 bytes + 1 FEC_PM
> + * (256 * 6 + 1) / (256 * 250) = 2.4015625 %
> + */
> + if (flags & DRM_DP_BW_OVERHEAD_FEC)
> + overhead += 24016;
> +
> + /*
> + * DP Standard v2.1 2.7.9, 5.9.7
> + * The FEC overhead for UHBR is accounted for in its 96.71% channel
> + * coding efficiency.
> + */
> + WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
> + (flags & DRM_DP_BW_OVERHEAD_FEC));
> +
> + if (flags & DRM_DP_BW_OVERHEAD_DSC)
> + symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,
> + dsc_slice_count,
> + bpp_x16, symbol_size,
> + is_mst);
> + else
> + symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
> + bpp_x16, symbol_size,
> + is_mst);
> +
> + return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
> + overhead * 16),
> + hactive * bpp_x16);
> +}
> +EXPORT_SYMBOL(drm_dp_bw_overhead);
> +
> +/**
> + * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
> + * @is_uhbr: Whether the link has a 128b/132b channel coding
> + *
> + * Return the channel coding efficiency of the given DP link type, which is
> + * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes
> + * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
> + * and for 128b/132b any link or PHY level control symbol insertion overhead
> + * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the
> + * corresponding FEC overhead is BW allocation specific, included in the value
> + * returned by drm_dp_bw_overhead().
> + *
> + * Returns the efficiency in the 100%/coding-overhead% ratio in
> + * 1ppm units.
> + */
> +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
> +{
> + if (is_uhbr)
> + return 967100;
> + else
> + /*
> + * Note that on 8b/10b MST the efficiency is only
> + * 78.75% due to the 1 out of 64 MTPH packet overhead,
> + * not accounted for here.
> + */
> + return 800000;
> +}
> +EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> index cc0a8fe84d290..4d72c9a32026e 100644
> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> @@ -4726,17 +4726,28 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
> int drm_dp_calc_pbn_mode(int clock, int bpp)
> {
> /*
> - * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
> * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
> * common multiplier to render an integer PBN for all link rate/lane
> * counts combinations
> * calculate
> - * peak_kbps *= (1006/1000)
> - * peak_kbps *= (64/54)
> - * peak_kbps *= 8 convert to bytes
> + * peak_kbps = clock * bpp / 16
> + * peak_kbps *= SSC overhead / 1000000
> + * peak_kbps /= 8 convert to Kbytes
> + * peak_kBps *= (64/54) / 1000 convert to PBN
> */
> - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
> - 1000 * 8 * 54 * 1000);
> + /*
> + * TODO: Use the actual link and mode parameters to calculate
> + * the overhead. For now it's assumed that these are
> + * 4 link lanes, 4096 hactive pixels, which don't add any
> + * significant data padding overhead and that there is no DSC
> + * or FEC overhead.
> + */
> + int overhead = drm_dp_bw_overhead(4, 4096, 0, bpp,
> + DRM_DP_BW_OVERHEAD_MST |
> + DRM_DP_BW_OVERHEAD_SSC_REF_CLK);
> +
> + return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),
> + 1000000ULL * 8 * 54 * 1000);
> }
> EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
>
> diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> index da94932f4262b..caee29d28463c 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -788,4 +788,15 @@ bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZ
> const u8 port_cap[4], u8 color_spc);
> int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
>
> +#define DRM_DP_BW_OVERHEAD_MST BIT(0)
> +#define DRM_DP_BW_OVERHEAD_UHBR BIT(1)
> +#define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2)
> +#define DRM_DP_BW_OVERHEAD_FEC BIT(3)
> +#define DRM_DP_BW_OVERHEAD_DSC BIT(4)
> +
> +int drm_dp_bw_overhead(int lane_count, int hactive,
> + int dsc_slice_count,
> + int bpp_x16, unsigned long flags);
> +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
> +
> #endif /* _DRM_DP_HELPER_H_ */
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
^ permalink raw reply [flat|nested] 94+ messages in thread
* [Intel-gfx] [PATCH v4 10/30] drm/i915/dp_mst: Enable FEC early once it's known DSC is needed
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (8 preceding siblings ...)
2023-10-30 15:58 ` Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 11/30] drm/i915/dp: Specify the FEC overhead as an increment vs. a remainder Imre Deak
` (29 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
Enable FEC in crtc_state, as soon as it's known it will be needed by
DSC. This fixes the calculation of BW allocation overhead, in case DSC
is enabled by falling back to it during the encoder compute config
phase (vs. enabling FEC due to DSC being enabled on other streams).
v2:
- Enable FEC only in intel_dp_mst_find_vcpi_slots_for_bpp(), since
only by that will crtc_state->port_clock be set, which in turn is
needed by intel_dp_is_uhbr().
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
drivers/gpu/drm/i915/display/intel_dp.h | 5 +++++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 +++++++
3 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f43536d49c49d..b747fda960e49 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1369,9 +1369,9 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
return false;
}
-static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
- const struct intel_connector *connector,
- const struct intel_crtc_state *pipe_config)
+bool intel_dp_supports_fec(struct intel_dp *intel_dp,
+ const struct intel_connector *connector,
+ const struct intel_crtc_state *pipe_config)
{
return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
drm_dp_sink_supports_fec(connector->dp.fec_capability);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 484aea215a251..0258580a6aadc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -137,6 +137,11 @@ static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
}
u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
+
+bool intel_dp_supports_fec(struct intel_dp *intel_dp,
+ const struct intel_connector *connector,
+ const struct intel_crtc_state *pipe_config);
+
u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp);
void intel_ddi_update_pipe(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 5bf45a2a85b0e..8177e19e53ac8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -94,6 +94,13 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
crtc_state->lane_count = limits->max_lane_count;
crtc_state->port_clock = limits->max_rate;
+ if (dsc) {
+ if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))
+ return -EINVAL;
+
+ crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
+ }
+
mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
crtc_state->port_clock,
crtc_state->lane_count);
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [Intel-gfx] [PATCH v4 11/30] drm/i915/dp: Specify the FEC overhead as an increment vs. a remainder
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (9 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 10/30] drm/i915/dp_mst: Enable FEC early once it's known DSC is needed Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 12/30] drm/i915/dp: Pass actual BW overhead to m_n calculation Imre Deak
` (28 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
A follow-up patch will add up all the overheads on a DP link, where it
makes more sense to specify each overhead factor in terms of the added
overhead amount vs. the reciprocal remainder (of usable BW remaining
after deducting the overhead). Prepare for that here, keeping the
existing behavior.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b747fda960e49..4d8f068218ea3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -85,8 +85,8 @@
#define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
#define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
-/* DP DSC FEC Overhead factor = 1/(0.972261) */
-#define DP_DSC_FEC_OVERHEAD_FACTOR 972261
+/* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
+#define DP_DSC_FEC_OVERHEAD_FACTOR 1028530
/* Compliance test status bits */
#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
@@ -680,8 +680,8 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
{
- return div_u64(mul_u32_u32(mode_clock, 1000000U),
- DP_DSC_FEC_OVERHEAD_FACTOR);
+ return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
+ 1000000U);
}
static int
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [Intel-gfx] [PATCH v4 12/30] drm/i915/dp: Pass actual BW overhead to m_n calculation
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (10 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 11/30] drm/i915/dp: Specify the FEC overhead as an increment vs. a remainder Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 13/30] drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation Imre Deak
` (27 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
A follow-up MST patch will need to specify the total BW allocation
overhead, prepare for that here by passing the amount of overhead
to intel_link_compute_m_n(), keeping the existing behavior.
v2:
- Fix passing the correct crtc_state->fec_enable param in
intel_dp_mst_compute_link_config() /
intel_dp_dsc_mst_compute_link_config().
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 40 +++++++++++++++++---
drivers/gpu/drm/i915/display/intel_display.h | 4 +-
drivers/gpu/drm/i915/display/intel_dp.c | 30 ++++++++++++---
drivers/gpu/drm/i915/display/intel_dp.h | 2 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++--
drivers/gpu/drm/i915/display/intel_fdi.c | 5 ++-
6 files changed, 71 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1caf46e3e5692..1133c2893bb38 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2396,17 +2396,45 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
intel_reduce_m_n_ratio(ret_m, ret_n);
}
+static void
+add_bw_alloc_overhead(int link_clock, int bw_overhead,
+ int pixel_data_rate, int link_data_rate,
+ u32 *data_m, u32 *data_n)
+{
+ bool is_uhbr = intel_dp_is_uhbr_rate(link_clock);
+ int ch_coding_efficiency =
+ drm_dp_bw_channel_coding_efficiency(is_uhbr);
+
+ /*
+ * TODO: adjust for actual UHBR channel coding efficiency and BW
+ * overhead.
+ */
+ if (is_uhbr) {
+ *data_m = pixel_data_rate;
+ *data_n = link_data_rate * 8 / 10;
+ return;
+ }
+
+ *data_m = DIV_ROUND_UP_ULL(mul_u32_u32(pixel_data_rate, bw_overhead),
+ 1000000);
+ *data_n = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_data_rate, ch_coding_efficiency),
+ 1000000);
+}
+
void
intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
int pixel_clock, int link_clock,
- struct intel_link_m_n *m_n,
- bool fec_enable)
+ int bw_overhead,
+ struct intel_link_m_n *m_n)
{
u32 data_clock = bits_per_pixel * pixel_clock;
+ u32 data_m;
+ u32 data_n;
- if (fec_enable)
- data_clock = intel_dp_mode_to_fec_clock(data_clock);
-
+ add_bw_alloc_overhead(link_clock, bw_overhead,
+ data_clock,
+ link_clock * 10 * nlanes,
+ &data_m, &data_n);
/*
* Windows/BIOS uses fixed M/N values always. Follow suit.
*
@@ -2416,7 +2444,7 @@ intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
*/
m_n->tu = 64;
compute_m_n(&m_n->data_m, &m_n->data_n,
- data_clock, link_clock * nlanes * 8,
+ data_m, data_n,
0x8000000);
compute_m_n(&m_n->link_m, &m_n->link_n,
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index cae2a3b12e20d..6d0636acb7250 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -394,8 +394,8 @@ u8 intel_calc_active_pipes(struct intel_atomic_state *state,
u8 active_pipes);
void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
- struct intel_link_m_n *m_n,
- bool fec_enable);
+ int bw_overhead,
+ struct intel_link_m_n *m_n);
u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier);
enum drm_mode_status
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4d8f068218ea3..34da403fa512b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -121,10 +121,15 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
+bool intel_dp_is_uhbr_rate(int rate)
+{
+ return rate >= 1000000;
+}
+
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
{
- return crtc_state->port_clock >= 1000000;
+ return intel_dp_is_uhbr_rate(crtc_state->port_clock);
}
static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
@@ -684,6 +689,20 @@ u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
1000000U);
}
+int intel_dp_bw_fec_overhead(bool fec_enabled)
+{
+ /*
+ * TODO: Calculate the actual overhead for a given mode.
+ * The hard-coded 1/0.972261=2.853% overhead factor
+ * corresponds (for instance) to the 8b/10b DP FEC 2.4% +
+ * 0.453% DSC overhead. This is enough for a 3840 width mode,
+ * which has a DSC overhead of up to ~0.2%, but may not be
+ * enough for a 1024 width mode where this is ~0.8% (on a 4
+ * lane DP link, with 2 DSC slices and 8 bpp color depth).
+ */
+ return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000;
+}
+
static int
small_joiner_ram_size_bits(struct drm_i915_private *i915)
{
@@ -2655,8 +2674,9 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
pixel_clock /= pipe_config->splitter.link_count;
intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock,
- pipe_config->port_clock, &pipe_config->dp_m2_n2,
- pipe_config->fec_enable);
+ pipe_config->port_clock,
+ intel_dp_bw_fec_overhead(pipe_config->fec_enable),
+ &pipe_config->dp_m2_n2);
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
@@ -2837,8 +2857,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
pipe_config->lane_count,
adjusted_mode->crtc_clock,
pipe_config->port_clock,
- &pipe_config->dp_m_n,
- pipe_config->fec_enable);
+ intel_dp_bw_fec_overhead(pipe_config->fec_enable),
+ &pipe_config->dp_m_n);
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 0258580a6aadc..2080575fef69a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -77,6 +77,7 @@ void intel_dp_audio_compute_config(struct intel_encoder *encoder,
struct drm_connector_state *conn_state);
bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);
bool intel_dp_is_edp(struct intel_dp *intel_dp);
+bool intel_dp_is_uhbr_rate(int rate);
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
@@ -137,6 +138,7 @@ static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
}
u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
+int intel_dp_bw_fec_overhead(bool fec_enabled);
bool intel_dp_supports_fec(struct intel_dp *intel_dp,
const struct intel_connector *connector,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 8177e19e53ac8..dcbc5d3aa7bc3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -179,8 +179,8 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
crtc_state->lane_count,
adjusted_mode->crtc_clock,
crtc_state->port_clock,
- &crtc_state->dp_m_n,
- crtc_state->fec_enable);
+ intel_dp_bw_fec_overhead(crtc_state->fec_enable),
+ &crtc_state->dp_m_n);
crtc_state->dp_m_n.tu = slots;
return 0;
@@ -274,8 +274,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
crtc_state->lane_count,
adjusted_mode->crtc_clock,
crtc_state->port_clock,
- &crtc_state->dp_m_n,
- crtc_state->fec_enable);
+ intel_dp_bw_fec_overhead(crtc_state->fec_enable),
+ &crtc_state->dp_m_n);
crtc_state->dp_m_n.tu = slots;
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index e6429dfebe159..1d87fbc1e8138 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -10,6 +10,7 @@
#include "intel_crtc.h"
#include "intel_ddi.h"
#include "intel_de.h"
+#include "intel_dp.h"
#include "intel_display_types.h"
#include "intel_fdi.h"
#include "intel_fdi_regs.h"
@@ -339,7 +340,9 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
pipe_config->fdi_lanes = lane;
intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
- link_bw, &pipe_config->fdi_m_n, false);
+ link_bw,
+ intel_dp_bw_fec_overhead(false),
+ &pipe_config->fdi_m_n);
return 0;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [Intel-gfx] [PATCH v4 13/30] drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (11 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 12/30] drm/i915/dp: Pass actual BW overhead to m_n calculation Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-11-06 20:39 ` Ville Syrjälä
` (2 more replies)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 14/30] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms Imre Deak
` (26 subsequent siblings)
39 siblings, 3 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
Atm, the BW allocated for an MST stream doesn't take into account the
DSC control symbol (EOC) and data alignment overhead on the local (first
downstream) MST link (reflected by the data M/N/TU values) and - besides
the above overheads - the FEC symbol overhead on 8b/10b remote
(after a downstream branch device) MST links.
In addition the FEC overhead used on the local link is a fixed amount,
which only applies to certain modes, but not enough for all modes; add a
code comment clarifying this.
Fix the above by calculating the data M/N values with the total BW
overhead (not including the SSC overhead, since this isn't enabled by
the source device) and using this the PBN and TU values for the local
link and PBN for remote links (including SSC, since this is mandatory
for links after downstream branch devices).
For now keep the current fixed FEC overhead as a minimum, since this is
what bspec requires for audio functionality.
Calculate the effective link BW in a clearer way, applying the channel
coding efficiency based on the coding type. The calculation was correct
for 8b/10b, but not for 128b/132b links; this patch leaves the behavior
for this unchanged, leaving the fix for a follow-up.
v2:
- Fix TU size programmed to the HW, making it match the payload size
programmed to the payload table.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 107 +++++++++++++++-----
1 file changed, 82 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index dcbc5d3aa7bc3..05b2d5d547c85 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -66,6 +66,63 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp
return 0;
}
+static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
+ const struct intel_connector *connector,
+ bool ssc, bool dsc, int bpp)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+ unsigned long flags = DRM_DP_BW_OVERHEAD_MST;
+ int dsc_slice_count = 0;
+ int overhead;
+
+ flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0;
+ flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
+ flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
+
+ if (dsc) {
+ flags |= DRM_DP_BW_OVERHEAD_DSC;
+ /* TODO: add support for bigjoiner */
+ dsc_slice_count = intel_dp_dsc_get_slice_count(connector,
+ adjusted_mode->clock,
+ adjusted_mode->hdisplay,
+ false);
+ }
+
+ overhead = drm_dp_bw_overhead(crtc_state->lane_count,
+ adjusted_mode->hdisplay,
+ dsc_slice_count,
+ to_bpp_x16(bpp),
+ flags);
+
+ /*
+ * TODO: clarify whether a minimum required by the fixed FEC overhead
+ * in the bspec audio programming sequence is required here.
+ */
+ return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable));
+}
+
+static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
+ const struct intel_connector *connector,
+ bool ssc, bool dsc,
+ int bpp,
+ struct intel_link_m_n *m_n)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+ int overhead = intel_dp_mst_bw_overhead(crtc_state,
+ connector,
+ ssc, dsc, bpp);
+
+ intel_link_compute_m_n(bpp, crtc_state->lane_count,
+ adjusted_mode->crtc_clock,
+ crtc_state->port_clock,
+ overhead,
+ m_n);
+
+ m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n);
+}
+
static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
int max_bpp,
@@ -106,14 +163,34 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
crtc_state->lane_count);
for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
+ struct intel_link_m_n remote_m_n;
+ int link_bpp;
+
drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, crtc_state, dsc);
if (ret)
continue;
- crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
- bpp << 4);
+ link_bpp = dsc ? bpp :
+ intel_dp_output_bpp(crtc_state->output_format, bpp);
+
+ intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc, link_bpp,
+ &crtc_state->dp_m_n);
+ intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc, link_bpp,
+ &remote_m_n);
+
+ /*
+ * The TU size programmed to the HW determines which slots in
+ * an MTP frame are used for this stream, which needs to match
+ * the payload size programmed to the first downstream branch
+ * device's payload table.
+ */
+ crtc_state->dp_m_n.tu = remote_m_n.tu;
+
+ crtc_state->pbn = DIV_ROUND_UP_ULL(mul_u32_u32(mst_state->pbn_div * 64,
+ remote_m_n.data_m),
+ remote_m_n.data_n);
slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
connector->port,
@@ -122,6 +199,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
return slots;
if (slots >= 0) {
+ drm_WARN_ON(&i915->drm, slots != remote_m_n.tu);
+
ret = drm_dp_mst_atomic_check(state);
/*
* If we got slots >= 0 and we can fit those based on check
@@ -155,10 +234,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
struct drm_connector_state *conn_state,
struct link_config_limits *limits)
{
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
int slots = -EINVAL;
- int link_bpp;
/*
* FIXME: allocate the BW according to link_bpp, which in the case of
@@ -173,16 +249,6 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
if (slots < 0)
return slots;
- link_bpp = intel_dp_output_bpp(crtc_state->output_format, crtc_state->pipe_bpp);
-
- intel_link_compute_m_n(link_bpp,
- crtc_state->lane_count,
- adjusted_mode->crtc_clock,
- crtc_state->port_clock,
- intel_dp_bw_fec_overhead(crtc_state->fec_enable),
- &crtc_state->dp_m_n);
- crtc_state->dp_m_n.tu = slots;
-
return 0;
}
@@ -194,8 +260,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
int slots = -EINVAL;
int i, num_bpc;
u8 dsc_bpc[3] = {};
@@ -270,14 +334,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
return slots;
}
- intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
- crtc_state->lane_count,
- adjusted_mode->crtc_clock,
- crtc_state->port_clock,
- intel_dp_bw_fec_overhead(crtc_state->fec_enable),
- &crtc_state->dp_m_n);
- crtc_state->dp_m_n.tu = slots;
-
return 0;
}
static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
@@ -980,6 +1036,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
if (ret)
return ret;
+ /* TODO: also check if compression would allow for the mode */
if (mode_rate > max_rate || mode->clock > max_dotclk ||
drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
*status = MODE_CLOCK_HIGH;
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v4 13/30] drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 13/30] drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation Imre Deak
@ 2023-11-06 20:39 ` Ville Syrjälä
2023-11-06 21:02 ` Imre Deak
2023-11-06 20:49 ` Ville Syrjälä
2023-11-07 0:14 ` [Intel-gfx] [PATCH v5 " Imre Deak
2 siblings, 1 reply; 94+ messages in thread
From: Ville Syrjälä @ 2023-11-06 20:39 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Mon, Oct 30, 2023 at 05:58:26PM +0200, Imre Deak wrote:
> Atm, the BW allocated for an MST stream doesn't take into account the
> DSC control symbol (EOC) and data alignment overhead on the local (first
> downstream) MST link (reflected by the data M/N/TU values) and - besides
> the above overheads - the FEC symbol overhead on 8b/10b remote
> (after a downstream branch device) MST links.
>
> In addition the FEC overhead used on the local link is a fixed amount,
> which only applies to certain modes, but not enough for all modes; add a
> code comment clarifying this.
>
> Fix the above by calculating the data M/N values with the total BW
> overhead (not including the SSC overhead, since this isn't enabled by
> the source device) and using this the PBN and TU values for the local
> link and PBN for remote links (including SSC, since this is mandatory
> for links after downstream branch devices).
>
> For now keep the current fixed FEC overhead as a minimum, since this is
> what bspec requires for audio functionality.
>
> Calculate the effective link BW in a clearer way, applying the channel
> coding efficiency based on the coding type. The calculation was correct
> for 8b/10b, but not for 128b/132b links; this patch leaves the behavior
> for this unchanged, leaving the fix for a follow-up.
>
> v2:
> - Fix TU size programmed to the HW, making it match the payload size
> programmed to the payload table.
>
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 107 +++++++++++++++-----
> 1 file changed, 82 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index dcbc5d3aa7bc3..05b2d5d547c85 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -66,6 +66,63 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp
> return 0;
> }
>
> +static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
> + const struct intel_connector *connector,
> + bool ssc, bool dsc, int bpp)
> +{
> + const struct drm_display_mode *adjusted_mode =
> + &crtc_state->hw.adjusted_mode;
> + unsigned long flags = DRM_DP_BW_OVERHEAD_MST;
> + int dsc_slice_count = 0;
> + int overhead;
> +
> + flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0;
> + flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
> + flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
> +
> + if (dsc) {
> + flags |= DRM_DP_BW_OVERHEAD_DSC;
> + /* TODO: add support for bigjoiner */
> + dsc_slice_count = intel_dp_dsc_get_slice_count(connector,
> + adjusted_mode->clock,
> + adjusted_mode->hdisplay,
> + false);
> + }
> +
> + overhead = drm_dp_bw_overhead(crtc_state->lane_count,
> + adjusted_mode->hdisplay,
> + dsc_slice_count,
> + to_bpp_x16(bpp),
> + flags);
> +
> + /*
> + * TODO: clarify whether a minimum required by the fixed FEC overhead
> + * in the bspec audio programming sequence is required here.
> + */
> + return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable));
> +}
> +
> +static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
> + const struct intel_connector *connector,
> + bool ssc, bool dsc,
> + int bpp,
> + struct intel_link_m_n *m_n)
> +{
> + const struct drm_display_mode *adjusted_mode =
> + &crtc_state->hw.adjusted_mode;
> + int overhead = intel_dp_mst_bw_overhead(crtc_state,
> + connector,
> + ssc, dsc, bpp);
> +
> + intel_link_compute_m_n(bpp, crtc_state->lane_count,
> + adjusted_mode->crtc_clock,
> + crtc_state->port_clock,
> + overhead,
> + m_n);
> +
> + m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n);
> +}
> +
> static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state,
> int max_bpp,
> @@ -106,14 +163,34 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> crtc_state->lane_count);
>
> for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
> + struct intel_link_m_n remote_m_n;
> + int link_bpp;
> +
> drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
>
> ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, crtc_state, dsc);
> if (ret)
> continue;
>
> - crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
> - bpp << 4);
> + link_bpp = dsc ? bpp :
> + intel_dp_output_bpp(crtc_state->output_format, bpp);
> +
> + intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc, link_bpp,
> + &crtc_state->dp_m_n);
> + intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc, link_bpp,
> + &remote_m_n);
> +
> + /*
> + * The TU size programmed to the HW determines which slots in
> + * an MTP frame are used for this stream, which needs to match
> + * the payload size programmed to the first downstream branch
> + * device's payload table.
> + */
> + crtc_state->dp_m_n.tu = remote_m_n.tu;
The fact we use the "remote" value here is because the mst manager code
assumes the two numbers are the same, right? Should perhaps highlight
that fact a bit better.
Maybe we want a WARN_ON(remote_m_n.tu < dp_m_n.tu) here as well?
> +
> + crtc_state->pbn = DIV_ROUND_UP_ULL(mul_u32_u32(mst_state->pbn_div * 64,
> + remote_m_n.data_m),
> + remote_m_n.data_n);
>
> slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
> connector->port,
> @@ -122,6 +199,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> return slots;
>
> if (slots >= 0) {
> + drm_WARN_ON(&i915->drm, slots != remote_m_n.tu);
> +
> ret = drm_dp_mst_atomic_check(state);
> /*
> * If we got slots >= 0 and we can fit those based on check
> @@ -155,10 +234,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
> struct drm_connector_state *conn_state,
> struct link_config_limits *limits)
> {
> - const struct drm_display_mode *adjusted_mode =
> - &crtc_state->hw.adjusted_mode;
> int slots = -EINVAL;
> - int link_bpp;
>
> /*
> * FIXME: allocate the BW according to link_bpp, which in the case of
> @@ -173,16 +249,6 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
> if (slots < 0)
> return slots;
>
> - link_bpp = intel_dp_output_bpp(crtc_state->output_format, crtc_state->pipe_bpp);
> -
> - intel_link_compute_m_n(link_bpp,
> - crtc_state->lane_count,
> - adjusted_mode->crtc_clock,
> - crtc_state->port_clock,
> - intel_dp_bw_fec_overhead(crtc_state->fec_enable),
> - &crtc_state->dp_m_n);
> - crtc_state->dp_m_n.tu = slots;
> -
> return 0;
> }
>
> @@ -194,8 +260,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> struct intel_connector *connector =
> to_intel_connector(conn_state->connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> - const struct drm_display_mode *adjusted_mode =
> - &crtc_state->hw.adjusted_mode;
> int slots = -EINVAL;
> int i, num_bpc;
> u8 dsc_bpc[3] = {};
> @@ -270,14 +334,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> return slots;
> }
>
> - intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
> - crtc_state->lane_count,
> - adjusted_mode->crtc_clock,
> - crtc_state->port_clock,
> - intel_dp_bw_fec_overhead(crtc_state->fec_enable),
> - &crtc_state->dp_m_n);
> - crtc_state->dp_m_n.tu = slots;
> -
> return 0;
> }
> static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
> @@ -980,6 +1036,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
> if (ret)
> return ret;
>
> + /* TODO: also check if compression would allow for the mode */
> if (mode_rate > max_rate || mode->clock > max_dotclk ||
> drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
> *status = MODE_CLOCK_HIGH;
> --
> 2.39.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v4 13/30] drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation
2023-11-06 20:39 ` Ville Syrjälä
@ 2023-11-06 21:02 ` Imre Deak
2023-11-06 21:15 ` Ville Syrjälä
0 siblings, 1 reply; 94+ messages in thread
From: Imre Deak @ 2023-11-06 21:02 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Nov 06, 2023 at 10:39:25PM +0200, Ville Syrjälä wrote:
> On Mon, Oct 30, 2023 at 05:58:26PM +0200, Imre Deak wrote:
> > Atm, the BW allocated for an MST stream doesn't take into account the
> > DSC control symbol (EOC) and data alignment overhead on the local (first
> > downstream) MST link (reflected by the data M/N/TU values) and - besides
> > the above overheads - the FEC symbol overhead on 8b/10b remote
> > (after a downstream branch device) MST links.
> >
> > In addition the FEC overhead used on the local link is a fixed amount,
> > which only applies to certain modes, but not enough for all modes; add a
> > code comment clarifying this.
> >
> > Fix the above by calculating the data M/N values with the total BW
> > overhead (not including the SSC overhead, since this isn't enabled by
> > the source device) and using this the PBN and TU values for the local
> > link and PBN for remote links (including SSC, since this is mandatory
> > for links after downstream branch devices).
> >
> > For now keep the current fixed FEC overhead as a minimum, since this is
> > what bspec requires for audio functionality.
> >
> > Calculate the effective link BW in a clearer way, applying the channel
> > coding efficiency based on the coding type. The calculation was correct
> > for 8b/10b, but not for 128b/132b links; this patch leaves the behavior
> > for this unchanged, leaving the fix for a follow-up.
> >
> > v2:
> > - Fix TU size programmed to the HW, making it match the payload size
> > programmed to the payload table.
> >
> > Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 107 +++++++++++++++-----
> > 1 file changed, 82 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index dcbc5d3aa7bc3..05b2d5d547c85 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -66,6 +66,63 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp
> > return 0;
> > }
> >
> > +static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
> > + const struct intel_connector *connector,
> > + bool ssc, bool dsc, int bpp)
> > +{
> > + const struct drm_display_mode *adjusted_mode =
> > + &crtc_state->hw.adjusted_mode;
> > + unsigned long flags = DRM_DP_BW_OVERHEAD_MST;
> > + int dsc_slice_count = 0;
> > + int overhead;
> > +
> > + flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0;
> > + flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
> > + flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
> > +
> > + if (dsc) {
> > + flags |= DRM_DP_BW_OVERHEAD_DSC;
> > + /* TODO: add support for bigjoiner */
> > + dsc_slice_count = intel_dp_dsc_get_slice_count(connector,
> > + adjusted_mode->clock,
> > + adjusted_mode->hdisplay,
> > + false);
> > + }
> > +
> > + overhead = drm_dp_bw_overhead(crtc_state->lane_count,
> > + adjusted_mode->hdisplay,
> > + dsc_slice_count,
> > + to_bpp_x16(bpp),
> > + flags);
> > +
> > + /*
> > + * TODO: clarify whether a minimum required by the fixed FEC overhead
> > + * in the bspec audio programming sequence is required here.
> > + */
> > + return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable));
> > +}
> > +
> > +static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
> > + const struct intel_connector *connector,
> > + bool ssc, bool dsc,
> > + int bpp,
> > + struct intel_link_m_n *m_n)
> > +{
> > + const struct drm_display_mode *adjusted_mode =
> > + &crtc_state->hw.adjusted_mode;
> > + int overhead = intel_dp_mst_bw_overhead(crtc_state,
> > + connector,
> > + ssc, dsc, bpp);
> > +
> > + intel_link_compute_m_n(bpp, crtc_state->lane_count,
> > + adjusted_mode->crtc_clock,
> > + crtc_state->port_clock,
> > + overhead,
> > + m_n);
> > +
> > + m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n);
> > +}
> > +
> > static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state,
> > int max_bpp,
> > @@ -106,14 +163,34 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> > crtc_state->lane_count);
> >
> > for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
> > + struct intel_link_m_n remote_m_n;
> > + int link_bpp;
> > +
> > drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
> >
> > ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, crtc_state, dsc);
> > if (ret)
> > continue;
> >
> > - crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
> > - bpp << 4);
> > + link_bpp = dsc ? bpp :
> > + intel_dp_output_bpp(crtc_state->output_format, bpp);
> > +
> > + intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc, link_bpp,
> > + &crtc_state->dp_m_n);
> > + intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc, link_bpp,
> > + &remote_m_n);
> > +
> > + /*
> > + * The TU size programmed to the HW determines which slots in
> > + * an MTP frame are used for this stream, which needs to match
> > + * the payload size programmed to the first downstream branch
> > + * device's payload table.
> > + */
> > + crtc_state->dp_m_n.tu = remote_m_n.tu;
>
> The fact we use the "remote" value here is because the mst manager code
> assumes the two numbers are the same, right? Should perhaps highlight
> that fact a bit better.
Yes, mst core assumes atm that the allocation on the MST link between
the source and the first downstream branch device - the payload size
programmed with direct AUX writes to this branch device's payload table
- and the corresponding allocation for farther links - the PBN contained
in the ALLOCATE_PAYLOAD side-band message - are the same (except for
units). The former allocation could be reduced for a source not
enabling SSC.
> Maybe we want a WARN_ON(remote_m_n.tu < dp_m_n.tu) here as well?
Ok, makes sense.
> > +
> > + crtc_state->pbn = DIV_ROUND_UP_ULL(mul_u32_u32(mst_state->pbn_div * 64,
> > + remote_m_n.data_m),
> > + remote_m_n.data_n);
The above can be actually simplified to
crtc_state->pbn = crtc_state->dp_m_n.tu * mst_state->pbn_div;
> >
> > slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
> > connector->port,
> > @@ -122,6 +199,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> > return slots;
> >
> > if (slots >= 0) {
> > + drm_WARN_ON(&i915->drm, slots != remote_m_n.tu);
> > +
> > ret = drm_dp_mst_atomic_check(state);
> > /*
> > * If we got slots >= 0 and we can fit those based on check
> > @@ -155,10 +234,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
> > struct drm_connector_state *conn_state,
> > struct link_config_limits *limits)
> > {
> > - const struct drm_display_mode *adjusted_mode =
> > - &crtc_state->hw.adjusted_mode;
> > int slots = -EINVAL;
> > - int link_bpp;
> >
> > /*
> > * FIXME: allocate the BW according to link_bpp, which in the case of
> > @@ -173,16 +249,6 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
> > if (slots < 0)
> > return slots;
> >
> > - link_bpp = intel_dp_output_bpp(crtc_state->output_format, crtc_state->pipe_bpp);
> > -
> > - intel_link_compute_m_n(link_bpp,
> > - crtc_state->lane_count,
> > - adjusted_mode->crtc_clock,
> > - crtc_state->port_clock,
> > - intel_dp_bw_fec_overhead(crtc_state->fec_enable),
> > - &crtc_state->dp_m_n);
> > - crtc_state->dp_m_n.tu = slots;
> > -
> > return 0;
> > }
> >
> > @@ -194,8 +260,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> > struct intel_connector *connector =
> > to_intel_connector(conn_state->connector);
> > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > - const struct drm_display_mode *adjusted_mode =
> > - &crtc_state->hw.adjusted_mode;
> > int slots = -EINVAL;
> > int i, num_bpc;
> > u8 dsc_bpc[3] = {};
> > @@ -270,14 +334,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> > return slots;
> > }
> >
> > - intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
> > - crtc_state->lane_count,
> > - adjusted_mode->crtc_clock,
> > - crtc_state->port_clock,
> > - intel_dp_bw_fec_overhead(crtc_state->fec_enable),
> > - &crtc_state->dp_m_n);
> > - crtc_state->dp_m_n.tu = slots;
> > -
> > return 0;
> > }
> > static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
> > @@ -980,6 +1036,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
> > if (ret)
> > return ret;
> >
> > + /* TODO: also check if compression would allow for the mode */
> > if (mode_rate > max_rate || mode->clock > max_dotclk ||
> > drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
> > *status = MODE_CLOCK_HIGH;
> > --
> > 2.39.2
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v4 13/30] drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation
2023-11-06 21:02 ` Imre Deak
@ 2023-11-06 21:15 ` Ville Syrjälä
2023-11-06 21:29 ` Imre Deak
0 siblings, 1 reply; 94+ messages in thread
From: Ville Syrjälä @ 2023-11-06 21:15 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Mon, Nov 06, 2023 at 11:02:32PM +0200, Imre Deak wrote:
> On Mon, Nov 06, 2023 at 10:39:25PM +0200, Ville Syrjälä wrote:
> > On Mon, Oct 30, 2023 at 05:58:26PM +0200, Imre Deak wrote:
> > > Atm, the BW allocated for an MST stream doesn't take into account the
> > > DSC control symbol (EOC) and data alignment overhead on the local (first
> > > downstream) MST link (reflected by the data M/N/TU values) and - besides
> > > the above overheads - the FEC symbol overhead on 8b/10b remote
> > > (after a downstream branch device) MST links.
> > >
> > > In addition the FEC overhead used on the local link is a fixed amount,
> > > which only applies to certain modes, but not enough for all modes; add a
> > > code comment clarifying this.
> > >
> > > Fix the above by calculating the data M/N values with the total BW
> > > overhead (not including the SSC overhead, since this isn't enabled by
> > > the source device) and using this the PBN and TU values for the local
> > > link and PBN for remote links (including SSC, since this is mandatory
> > > for links after downstream branch devices).
> > >
> > > For now keep the current fixed FEC overhead as a minimum, since this is
> > > what bspec requires for audio functionality.
> > >
> > > Calculate the effective link BW in a clearer way, applying the channel
> > > coding efficiency based on the coding type. The calculation was correct
> > > for 8b/10b, but not for 128b/132b links; this patch leaves the behavior
> > > for this unchanged, leaving the fix for a follow-up.
> > >
> > > v2:
> > > - Fix TU size programmed to the HW, making it match the payload size
> > > programmed to the payload table.
> > >
> > > Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 107 +++++++++++++++-----
> > > 1 file changed, 82 insertions(+), 25 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > index dcbc5d3aa7bc3..05b2d5d547c85 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > @@ -66,6 +66,63 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp
> > > return 0;
> > > }
> > >
> > > +static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
> > > + const struct intel_connector *connector,
> > > + bool ssc, bool dsc, int bpp)
> > > +{
> > > + const struct drm_display_mode *adjusted_mode =
> > > + &crtc_state->hw.adjusted_mode;
> > > + unsigned long flags = DRM_DP_BW_OVERHEAD_MST;
> > > + int dsc_slice_count = 0;
> > > + int overhead;
> > > +
> > > + flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0;
> > > + flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
> > > + flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
> > > +
> > > + if (dsc) {
> > > + flags |= DRM_DP_BW_OVERHEAD_DSC;
> > > + /* TODO: add support for bigjoiner */
> > > + dsc_slice_count = intel_dp_dsc_get_slice_count(connector,
> > > + adjusted_mode->clock,
> > > + adjusted_mode->hdisplay,
> > > + false);
> > > + }
> > > +
> > > + overhead = drm_dp_bw_overhead(crtc_state->lane_count,
> > > + adjusted_mode->hdisplay,
> > > + dsc_slice_count,
> > > + to_bpp_x16(bpp),
> > > + flags);
> > > +
> > > + /*
> > > + * TODO: clarify whether a minimum required by the fixed FEC overhead
> > > + * in the bspec audio programming sequence is required here.
> > > + */
> > > + return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable));
> > > +}
> > > +
> > > +static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
> > > + const struct intel_connector *connector,
> > > + bool ssc, bool dsc,
> > > + int bpp,
> > > + struct intel_link_m_n *m_n)
> > > +{
> > > + const struct drm_display_mode *adjusted_mode =
> > > + &crtc_state->hw.adjusted_mode;
> > > + int overhead = intel_dp_mst_bw_overhead(crtc_state,
> > > + connector,
> > > + ssc, dsc, bpp);
> > > +
> > > + intel_link_compute_m_n(bpp, crtc_state->lane_count,
> > > + adjusted_mode->crtc_clock,
> > > + crtc_state->port_clock,
> > > + overhead,
> > > + m_n);
> > > +
> > > + m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n);
> > > +}
> > > +
> > > static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> > > struct intel_crtc_state *crtc_state,
> > > int max_bpp,
> > > @@ -106,14 +163,34 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> > > crtc_state->lane_count);
> > >
> > > for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
> > > + struct intel_link_m_n remote_m_n;
> > > + int link_bpp;
> > > +
> > > drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
> > >
> > > ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, crtc_state, dsc);
> > > if (ret)
> > > continue;
> > >
> > > - crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
> > > - bpp << 4);
> > > + link_bpp = dsc ? bpp :
> > > + intel_dp_output_bpp(crtc_state->output_format, bpp);
> > > +
> > > + intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc, link_bpp,
> > > + &crtc_state->dp_m_n);
> > > + intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc, link_bpp,
> > > + &remote_m_n);
> > > +
> > > + /*
> > > + * The TU size programmed to the HW determines which slots in
> > > + * an MTP frame are used for this stream, which needs to match
> > > + * the payload size programmed to the first downstream branch
> > > + * device's payload table.
> > > + */
> > > + crtc_state->dp_m_n.tu = remote_m_n.tu;
> >
> > The fact we use the "remote" value here is because the mst manager code
> > assumes the two numbers are the same, right? Should perhaps highlight
> > that fact a bit better.
>
> Yes, mst core assumes atm that the allocation on the MST link between
> the source and the first downstream branch device - the payload size
> programmed with direct AUX writes to this branch device's payload table
> - and the corresponding allocation for farther links - the PBN contained
> in the ALLOCATE_PAYLOAD side-band message - are the same (except for
> units). The former allocation could be reduced for a source not
> enabling SSC.
>
> > Maybe we want a WARN_ON(remote_m_n.tu < dp_m_n.tu) here as well?
>
> Ok, makes sense.
>
> > > +
> > > + crtc_state->pbn = DIV_ROUND_UP_ULL(mul_u32_u32(mst_state->pbn_div * 64,
> > > + remote_m_n.data_m),
> > > + remote_m_n.data_n);
>
> The above can be actually simplified to
> crtc_state->pbn = crtc_state->dp_m_n.tu * mst_state->pbn_div;
I was wondering if it's safer to stick to remote_n_m here, in case
we manage to untangle the two values and then somehow forget to
change this. But I suppose we'd have to track both values anyway
somewhere, so maybe that's just nonsense.
>
> > >
> > > slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
> > > connector->port,
> > > @@ -122,6 +199,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> > > return slots;
> > >
> > > if (slots >= 0) {
> > > + drm_WARN_ON(&i915->drm, slots != remote_m_n.tu);
> > > +
> > > ret = drm_dp_mst_atomic_check(state);
> > > /*
> > > * If we got slots >= 0 and we can fit those based on check
> > > @@ -155,10 +234,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
> > > struct drm_connector_state *conn_state,
> > > struct link_config_limits *limits)
> > > {
> > > - const struct drm_display_mode *adjusted_mode =
> > > - &crtc_state->hw.adjusted_mode;
> > > int slots = -EINVAL;
> > > - int link_bpp;
> > >
> > > /*
> > > * FIXME: allocate the BW according to link_bpp, which in the case of
> > > @@ -173,16 +249,6 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
> > > if (slots < 0)
> > > return slots;
> > >
> > > - link_bpp = intel_dp_output_bpp(crtc_state->output_format, crtc_state->pipe_bpp);
> > > -
> > > - intel_link_compute_m_n(link_bpp,
> > > - crtc_state->lane_count,
> > > - adjusted_mode->crtc_clock,
> > > - crtc_state->port_clock,
> > > - intel_dp_bw_fec_overhead(crtc_state->fec_enable),
> > > - &crtc_state->dp_m_n);
> > > - crtc_state->dp_m_n.tu = slots;
> > > -
> > > return 0;
> > > }
> > >
> > > @@ -194,8 +260,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> > > struct intel_connector *connector =
> > > to_intel_connector(conn_state->connector);
> > > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > > - const struct drm_display_mode *adjusted_mode =
> > > - &crtc_state->hw.adjusted_mode;
> > > int slots = -EINVAL;
> > > int i, num_bpc;
> > > u8 dsc_bpc[3] = {};
> > > @@ -270,14 +334,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> > > return slots;
> > > }
> > >
> > > - intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
> > > - crtc_state->lane_count,
> > > - adjusted_mode->crtc_clock,
> > > - crtc_state->port_clock,
> > > - intel_dp_bw_fec_overhead(crtc_state->fec_enable),
> > > - &crtc_state->dp_m_n);
> > > - crtc_state->dp_m_n.tu = slots;
> > > -
> > > return 0;
> > > }
> > > static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
> > > @@ -980,6 +1036,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
> > > if (ret)
> > > return ret;
> > >
> > > + /* TODO: also check if compression would allow for the mode */
> > > if (mode_rate > max_rate || mode->clock > max_dotclk ||
> > > drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
> > > *status = MODE_CLOCK_HIGH;
> > > --
> > > 2.39.2
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v4 13/30] drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation
2023-11-06 21:15 ` Ville Syrjälä
@ 2023-11-06 21:29 ` Imre Deak
0 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-11-06 21:29 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Nov 06, 2023 at 11:15:54PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 06, 2023 at 11:02:32PM +0200, Imre Deak wrote:
> > On Mon, Nov 06, 2023 at 10:39:25PM +0200, Ville Syrjälä wrote:
> > > On Mon, Oct 30, 2023 at 05:58:26PM +0200, Imre Deak wrote:
> > > > Atm, the BW allocated for an MST stream doesn't take into account the
> > > > DSC control symbol (EOC) and data alignment overhead on the local (first
> > > > downstream) MST link (reflected by the data M/N/TU values) and - besides
> > > > the above overheads - the FEC symbol overhead on 8b/10b remote
> > > > (after a downstream branch device) MST links.
> > > >
> > > > In addition the FEC overhead used on the local link is a fixed amount,
> > > > which only applies to certain modes, but not enough for all modes; add a
> > > > code comment clarifying this.
> > > >
> > > > Fix the above by calculating the data M/N values with the total BW
> > > > overhead (not including the SSC overhead, since this isn't enabled by
> > > > the source device) and using this the PBN and TU values for the local
> > > > link and PBN for remote links (including SSC, since this is mandatory
> > > > for links after downstream branch devices).
> > > >
> > > > For now keep the current fixed FEC overhead as a minimum, since this is
> > > > what bspec requires for audio functionality.
> > > >
> > > > Calculate the effective link BW in a clearer way, applying the channel
> > > > coding efficiency based on the coding type. The calculation was correct
> > > > for 8b/10b, but not for 128b/132b links; this patch leaves the behavior
> > > > for this unchanged, leaving the fix for a follow-up.
> > > >
> > > > v2:
> > > > - Fix TU size programmed to the HW, making it match the payload size
> > > > programmed to the payload table.
> > > >
> > > > Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 107 +++++++++++++++-----
> > > > 1 file changed, 82 insertions(+), 25 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > > index dcbc5d3aa7bc3..05b2d5d547c85 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > > @@ -66,6 +66,63 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp
> > > > return 0;
> > > > }
> > > >
> > > > +static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
> > > > + const struct intel_connector *connector,
> > > > + bool ssc, bool dsc, int bpp)
> > > > +{
> > > > + const struct drm_display_mode *adjusted_mode =
> > > > + &crtc_state->hw.adjusted_mode;
> > > > + unsigned long flags = DRM_DP_BW_OVERHEAD_MST;
> > > > + int dsc_slice_count = 0;
> > > > + int overhead;
> > > > +
> > > > + flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0;
> > > > + flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
> > > > + flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
> > > > +
> > > > + if (dsc) {
> > > > + flags |= DRM_DP_BW_OVERHEAD_DSC;
> > > > + /* TODO: add support for bigjoiner */
> > > > + dsc_slice_count = intel_dp_dsc_get_slice_count(connector,
> > > > + adjusted_mode->clock,
> > > > + adjusted_mode->hdisplay,
> > > > + false);
> > > > + }
> > > > +
> > > > + overhead = drm_dp_bw_overhead(crtc_state->lane_count,
> > > > + adjusted_mode->hdisplay,
> > > > + dsc_slice_count,
> > > > + to_bpp_x16(bpp),
> > > > + flags);
> > > > +
> > > > + /*
> > > > + * TODO: clarify whether a minimum required by the fixed FEC overhead
> > > > + * in the bspec audio programming sequence is required here.
> > > > + */
> > > > + return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable));
> > > > +}
> > > > +
> > > > +static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
> > > > + const struct intel_connector *connector,
> > > > + bool ssc, bool dsc,
> > > > + int bpp,
> > > > + struct intel_link_m_n *m_n)
> > > > +{
> > > > + const struct drm_display_mode *adjusted_mode =
> > > > + &crtc_state->hw.adjusted_mode;
> > > > + int overhead = intel_dp_mst_bw_overhead(crtc_state,
> > > > + connector,
> > > > + ssc, dsc, bpp);
> > > > +
> > > > + intel_link_compute_m_n(bpp, crtc_state->lane_count,
> > > > + adjusted_mode->crtc_clock,
> > > > + crtc_state->port_clock,
> > > > + overhead,
> > > > + m_n);
> > > > +
> > > > + m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n);
> > > > +}
> > > > +
> > > > static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> > > > struct intel_crtc_state *crtc_state,
> > > > int max_bpp,
> > > > @@ -106,14 +163,34 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> > > > crtc_state->lane_count);
> > > >
> > > > for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
> > > > + struct intel_link_m_n remote_m_n;
> > > > + int link_bpp;
> > > > +
> > > > drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
> > > >
> > > > ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, crtc_state, dsc);
> > > > if (ret)
> > > > continue;
> > > >
> > > > - crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
> > > > - bpp << 4);
> > > > + link_bpp = dsc ? bpp :
> > > > + intel_dp_output_bpp(crtc_state->output_format, bpp);
> > > > +
> > > > + intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc, link_bpp,
> > > > + &crtc_state->dp_m_n);
> > > > + intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc, link_bpp,
> > > > + &remote_m_n);
> > > > +
> > > > + /*
> > > > + * The TU size programmed to the HW determines which slots in
> > > > + * an MTP frame are used for this stream, which needs to match
> > > > + * the payload size programmed to the first downstream branch
> > > > + * device's payload table.
> > > > + */
> > > > + crtc_state->dp_m_n.tu = remote_m_n.tu;
> > >
> > > The fact we use the "remote" value here is because the mst manager code
> > > assumes the two numbers are the same, right? Should perhaps highlight
> > > that fact a bit better.
> >
> > Yes, mst core assumes atm that the allocation on the MST link between
> > the source and the first downstream branch device - the payload size
> > programmed with direct AUX writes to this branch device's payload table
> > - and the corresponding allocation for farther links - the PBN contained
> > in the ALLOCATE_PAYLOAD side-band message - are the same (except for
> > units). The former allocation could be reduced for a source not
> > enabling SSC.
> >
> > > Maybe we want a WARN_ON(remote_m_n.tu < dp_m_n.tu) here as well?
> >
> > Ok, makes sense.
> >
> > > > +
> > > > + crtc_state->pbn = DIV_ROUND_UP_ULL(mul_u32_u32(mst_state->pbn_div * 64,
> > > > + remote_m_n.data_m),
> > > > + remote_m_n.data_n);
> >
> > The above can be actually simplified to
> > crtc_state->pbn = crtc_state->dp_m_n.tu * mst_state->pbn_div;
>
> I was wondering if it's safer to stick to remote_n_m here, in case
> we manage to untangle the two values and then somehow forget to
> change this. But I suppose we'd have to track both values anyway
> somewhere, so maybe that's just nonsense.
Yes, using remote_m_n.tu for this is clearer.
> > > > slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
> > > > connector->port,
> > > > @@ -122,6 +199,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> > > > return slots;
> > > >
> > > > if (slots >= 0) {
> > > > + drm_WARN_ON(&i915->drm, slots != remote_m_n.tu);
> > > > +
> > > > ret = drm_dp_mst_atomic_check(state);
> > > > /*
> > > > * If we got slots >= 0 and we can fit those based on check
> > > > @@ -155,10 +234,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
> > > > struct drm_connector_state *conn_state,
> > > > struct link_config_limits *limits)
> > > > {
> > > > - const struct drm_display_mode *adjusted_mode =
> > > > - &crtc_state->hw.adjusted_mode;
> > > > int slots = -EINVAL;
> > > > - int link_bpp;
> > > >
> > > > /*
> > > > * FIXME: allocate the BW according to link_bpp, which in the case of
> > > > @@ -173,16 +249,6 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
> > > > if (slots < 0)
> > > > return slots;
> > > >
> > > > - link_bpp = intel_dp_output_bpp(crtc_state->output_format, crtc_state->pipe_bpp);
> > > > -
> > > > - intel_link_compute_m_n(link_bpp,
> > > > - crtc_state->lane_count,
> > > > - adjusted_mode->crtc_clock,
> > > > - crtc_state->port_clock,
> > > > - intel_dp_bw_fec_overhead(crtc_state->fec_enable),
> > > > - &crtc_state->dp_m_n);
> > > > - crtc_state->dp_m_n.tu = slots;
> > > > -
> > > > return 0;
> > > > }
> > > >
> > > > @@ -194,8 +260,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> > > > struct intel_connector *connector =
> > > > to_intel_connector(conn_state->connector);
> > > > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > > > - const struct drm_display_mode *adjusted_mode =
> > > > - &crtc_state->hw.adjusted_mode;
> > > > int slots = -EINVAL;
> > > > int i, num_bpc;
> > > > u8 dsc_bpc[3] = {};
> > > > @@ -270,14 +334,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> > > > return slots;
> > > > }
> > > >
> > > > - intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
> > > > - crtc_state->lane_count,
> > > > - adjusted_mode->crtc_clock,
> > > > - crtc_state->port_clock,
> > > > - intel_dp_bw_fec_overhead(crtc_state->fec_enable),
> > > > - &crtc_state->dp_m_n);
> > > > - crtc_state->dp_m_n.tu = slots;
> > > > -
> > > > return 0;
> > > > }
> > > > static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
> > > > @@ -980,6 +1036,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
> > > > if (ret)
> > > > return ret;
> > > >
> > > > + /* TODO: also check if compression would allow for the mode */
> > > > if (mode_rate > max_rate || mode->clock > max_dotclk ||
> > > > drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
> > > > *status = MODE_CLOCK_HIGH;
> > > > --
> > > > 2.39.2
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [Intel-gfx] [PATCH v4 13/30] drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 13/30] drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation Imre Deak
2023-11-06 20:39 ` Ville Syrjälä
@ 2023-11-06 20:49 ` Ville Syrjälä
2023-11-06 21:54 ` Imre Deak
2023-11-07 0:14 ` [Intel-gfx] [PATCH v5 " Imre Deak
2 siblings, 1 reply; 94+ messages in thread
From: Ville Syrjälä @ 2023-11-06 20:49 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Mon, Oct 30, 2023 at 05:58:26PM +0200, Imre Deak wrote:
> Atm, the BW allocated for an MST stream doesn't take into account the
> DSC control symbol (EOC) and data alignment overhead on the local (first
> downstream) MST link (reflected by the data M/N/TU values) and - besides
> the above overheads - the FEC symbol overhead on 8b/10b remote
> (after a downstream branch device) MST links.
>
> In addition the FEC overhead used on the local link is a fixed amount,
> which only applies to certain modes, but not enough for all modes; add a
> code comment clarifying this.
>
> Fix the above by calculating the data M/N values with the total BW
> overhead (not including the SSC overhead, since this isn't enabled by
> the source device) and using this the PBN and TU values for the local
> link and PBN for remote links (including SSC, since this is mandatory
> for links after downstream branch devices).
>
> For now keep the current fixed FEC overhead as a minimum, since this is
> what bspec requires for audio functionality.
>
> Calculate the effective link BW in a clearer way, applying the channel
> coding efficiency based on the coding type. The calculation was correct
> for 8b/10b, but not for 128b/132b links; this patch leaves the behavior
> for this unchanged, leaving the fix for a follow-up.
>
> v2:
> - Fix TU size programmed to the HW, making it match the payload size
> programmed to the payload table.
>
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 107 +++++++++++++++-----
> 1 file changed, 82 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index dcbc5d3aa7bc3..05b2d5d547c85 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -66,6 +66,63 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp
> return 0;
> }
>
> +static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
> + const struct intel_connector *connector,
> + bool ssc, bool dsc, int bpp)
> +{
> + const struct drm_display_mode *adjusted_mode =
> + &crtc_state->hw.adjusted_mode;
> + unsigned long flags = DRM_DP_BW_OVERHEAD_MST;
> + int dsc_slice_count = 0;
> + int overhead;
> +
> + flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0;
> + flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
> + flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
> +
> + if (dsc) {
> + flags |= DRM_DP_BW_OVERHEAD_DSC;
> + /* TODO: add support for bigjoiner */
> + dsc_slice_count = intel_dp_dsc_get_slice_count(connector,
> + adjusted_mode->clock,
> + adjusted_mode->hdisplay,
> + false);
> + }
> +
> + overhead = drm_dp_bw_overhead(crtc_state->lane_count,
> + adjusted_mode->hdisplay,
> + dsc_slice_count,
> + to_bpp_x16(bpp),
> + flags);
> +
> + /*
> + * TODO: clarify whether a minimum required by the fixed FEC overhead
> + * in the bspec audio programming sequence is required here.
> + */
> + return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable));
> +}
> +
> +static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
> + const struct intel_connector *connector,
> + bool ssc, bool dsc,
> + int bpp,
> + struct intel_link_m_n *m_n)
> +{
> + const struct drm_display_mode *adjusted_mode =
> + &crtc_state->hw.adjusted_mode;
> + int overhead = intel_dp_mst_bw_overhead(crtc_state,
> + connector,
> + ssc, dsc, bpp);
> +
> + intel_link_compute_m_n(bpp, crtc_state->lane_count,
> + adjusted_mode->crtc_clock,
> + crtc_state->port_clock,
> + overhead,
> + m_n);
> +
> + m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n);
> +}
> +
> static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state,
> int max_bpp,
> @@ -106,14 +163,34 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> crtc_state->lane_count);
>
> for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
> + struct intel_link_m_n remote_m_n;
> + int link_bpp;
> +
> drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
>
> ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, crtc_state, dsc);
> if (ret)
> continue;
>
> - crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
> - bpp << 4);
> + link_bpp = dsc ? bpp :
> + intel_dp_output_bpp(crtc_state->output_format, bpp);
> +
> + intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc, link_bpp,
> + &crtc_state->dp_m_n);
> + intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc, link_bpp,
> + &remote_m_n);
> +
> + /*
> + * The TU size programmed to the HW determines which slots in
> + * an MTP frame are used for this stream, which needs to match
> + * the payload size programmed to the first downstream branch
> + * device's payload table.
> + */
> + crtc_state->dp_m_n.tu = remote_m_n.tu;
> +
> + crtc_state->pbn = DIV_ROUND_UP_ULL(mul_u32_u32(mst_state->pbn_div * 64,
> + remote_m_n.data_m),
> + remote_m_n.data_n);
>
> slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
> connector->port,
> @@ -122,6 +199,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> return slots;
>
> if (slots >= 0) {
> + drm_WARN_ON(&i915->drm, slots != remote_m_n.tu);
> +
> ret = drm_dp_mst_atomic_check(state);
> /*
> * If we got slots >= 0 and we can fit those based on check
> @@ -155,10 +234,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
> struct drm_connector_state *conn_state,
> struct link_config_limits *limits)
> {
> - const struct drm_display_mode *adjusted_mode =
> - &crtc_state->hw.adjusted_mode;
> int slots = -EINVAL;
> - int link_bpp;
>
> /*
> * FIXME: allocate the BW according to link_bpp, which in the case of
> @@ -173,16 +249,6 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
> if (slots < 0)
> return slots;
>
> - link_bpp = intel_dp_output_bpp(crtc_state->output_format, crtc_state->pipe_bpp);
> -
> - intel_link_compute_m_n(link_bpp,
> - crtc_state->lane_count,
> - adjusted_mode->crtc_clock,
> - crtc_state->port_clock,
> - intel_dp_bw_fec_overhead(crtc_state->fec_enable),
> - &crtc_state->dp_m_n);
> - crtc_state->dp_m_n.tu = slots;
> -
> return 0;
> }
>
> @@ -194,8 +260,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> struct intel_connector *connector =
> to_intel_connector(conn_state->connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> - const struct drm_display_mode *adjusted_mode =
> - &crtc_state->hw.adjusted_mode;
> int slots = -EINVAL;
> int i, num_bpc;
> u8 dsc_bpc[3] = {};
> @@ -270,14 +334,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> return slots;
> }
>
> - intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
> - crtc_state->lane_count,
> - adjusted_mode->crtc_clock,
> - crtc_state->port_clock,
> - intel_dp_bw_fec_overhead(crtc_state->fec_enable),
> - &crtc_state->dp_m_n);
> - crtc_state->dp_m_n.tu = slots;
> -
> return 0;
> }
> static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
> @@ -980,6 +1036,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
> if (ret)
> return ret;
>
> + /* TODO: also check if compression would allow for the mode */
We should also stop using drm_dp_calc_pbn_mode() since it makes some
wild assumptions, no?
> if (mode_rate > max_rate || mode->clock > max_dotclk ||
> drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
> *status = MODE_CLOCK_HIGH;
> --
> 2.39.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v4 13/30] drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation
2023-11-06 20:49 ` Ville Syrjälä
@ 2023-11-06 21:54 ` Imre Deak
0 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-11-06 21:54 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Nov 06, 2023 at 10:49:13PM +0200, Ville Syrjälä wrote:
> On Mon, Oct 30, 2023 at 05:58:26PM +0200, Imre Deak wrote:
> > Atm, the BW allocated for an MST stream doesn't take into account the
> > DSC control symbol (EOC) and data alignment overhead on the local (first
> > downstream) MST link (reflected by the data M/N/TU values) and - besides
> > the above overheads - the FEC symbol overhead on 8b/10b remote
> > (after a downstream branch device) MST links.
> >
> > In addition the FEC overhead used on the local link is a fixed amount,
> > which only applies to certain modes, but not enough for all modes; add a
> > code comment clarifying this.
> >
> > Fix the above by calculating the data M/N values with the total BW
> > overhead (not including the SSC overhead, since this isn't enabled by
> > the source device) and using this the PBN and TU values for the local
> > link and PBN for remote links (including SSC, since this is mandatory
> > for links after downstream branch devices).
> >
> > For now keep the current fixed FEC overhead as a minimum, since this is
> > what bspec requires for audio functionality.
> >
> > Calculate the effective link BW in a clearer way, applying the channel
> > coding efficiency based on the coding type. The calculation was correct
> > for 8b/10b, but not for 128b/132b links; this patch leaves the behavior
> > for this unchanged, leaving the fix for a follow-up.
> >
> > v2:
> > - Fix TU size programmed to the HW, making it match the payload size
> > programmed to the payload table.
> >
> > Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 107 +++++++++++++++-----
> > 1 file changed, 82 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index dcbc5d3aa7bc3..05b2d5d547c85 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -66,6 +66,63 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp
> > return 0;
> > }
> >
> > +static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
> > + const struct intel_connector *connector,
> > + bool ssc, bool dsc, int bpp)
> > +{
> > + const struct drm_display_mode *adjusted_mode =
> > + &crtc_state->hw.adjusted_mode;
> > + unsigned long flags = DRM_DP_BW_OVERHEAD_MST;
> > + int dsc_slice_count = 0;
> > + int overhead;
> > +
> > + flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0;
> > + flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
> > + flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
> > +
> > + if (dsc) {
> > + flags |= DRM_DP_BW_OVERHEAD_DSC;
> > + /* TODO: add support for bigjoiner */
> > + dsc_slice_count = intel_dp_dsc_get_slice_count(connector,
> > + adjusted_mode->clock,
> > + adjusted_mode->hdisplay,
> > + false);
> > + }
> > +
> > + overhead = drm_dp_bw_overhead(crtc_state->lane_count,
> > + adjusted_mode->hdisplay,
> > + dsc_slice_count,
> > + to_bpp_x16(bpp),
> > + flags);
> > +
> > + /*
> > + * TODO: clarify whether a minimum required by the fixed FEC overhead
> > + * in the bspec audio programming sequence is required here.
> > + */
> > + return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable));
> > +}
> > +
> > +static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
> > + const struct intel_connector *connector,
> > + bool ssc, bool dsc,
> > + int bpp,
> > + struct intel_link_m_n *m_n)
> > +{
> > + const struct drm_display_mode *adjusted_mode =
> > + &crtc_state->hw.adjusted_mode;
> > + int overhead = intel_dp_mst_bw_overhead(crtc_state,
> > + connector,
> > + ssc, dsc, bpp);
> > +
> > + intel_link_compute_m_n(bpp, crtc_state->lane_count,
> > + adjusted_mode->crtc_clock,
> > + crtc_state->port_clock,
> > + overhead,
> > + m_n);
> > +
> > + m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n);
> > +}
> > +
> > static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state,
> > int max_bpp,
> > @@ -106,14 +163,34 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> > crtc_state->lane_count);
> >
> > for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
> > + struct intel_link_m_n remote_m_n;
> > + int link_bpp;
> > +
> > drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
> >
> > ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, crtc_state, dsc);
> > if (ret)
> > continue;
> >
> > - crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
> > - bpp << 4);
> > + link_bpp = dsc ? bpp :
> > + intel_dp_output_bpp(crtc_state->output_format, bpp);
> > +
> > + intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc, link_bpp,
> > + &crtc_state->dp_m_n);
> > + intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc, link_bpp,
> > + &remote_m_n);
> > +
> > + /*
> > + * The TU size programmed to the HW determines which slots in
> > + * an MTP frame are used for this stream, which needs to match
> > + * the payload size programmed to the first downstream branch
> > + * device's payload table.
> > + */
> > + crtc_state->dp_m_n.tu = remote_m_n.tu;
> > +
> > + crtc_state->pbn = DIV_ROUND_UP_ULL(mul_u32_u32(mst_state->pbn_div * 64,
> > + remote_m_n.data_m),
> > + remote_m_n.data_n);
> >
> > slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
> > connector->port,
> > @@ -122,6 +199,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> > return slots;
> >
> > if (slots >= 0) {
> > + drm_WARN_ON(&i915->drm, slots != remote_m_n.tu);
> > +
> > ret = drm_dp_mst_atomic_check(state);
> > /*
> > * If we got slots >= 0 and we can fit those based on check
> > @@ -155,10 +234,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
> > struct drm_connector_state *conn_state,
> > struct link_config_limits *limits)
> > {
> > - const struct drm_display_mode *adjusted_mode =
> > - &crtc_state->hw.adjusted_mode;
> > int slots = -EINVAL;
> > - int link_bpp;
> >
> > /*
> > * FIXME: allocate the BW according to link_bpp, which in the case of
> > @@ -173,16 +249,6 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
> > if (slots < 0)
> > return slots;
> >
> > - link_bpp = intel_dp_output_bpp(crtc_state->output_format, crtc_state->pipe_bpp);
> > -
> > - intel_link_compute_m_n(link_bpp,
> > - crtc_state->lane_count,
> > - adjusted_mode->crtc_clock,
> > - crtc_state->port_clock,
> > - intel_dp_bw_fec_overhead(crtc_state->fec_enable),
> > - &crtc_state->dp_m_n);
> > - crtc_state->dp_m_n.tu = slots;
> > -
> > return 0;
> > }
> >
> > @@ -194,8 +260,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> > struct intel_connector *connector =
> > to_intel_connector(conn_state->connector);
> > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > - const struct drm_display_mode *adjusted_mode =
> > - &crtc_state->hw.adjusted_mode;
> > int slots = -EINVAL;
> > int i, num_bpc;
> > u8 dsc_bpc[3] = {};
> > @@ -270,14 +334,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> > return slots;
> > }
> >
> > - intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
> > - crtc_state->lane_count,
> > - adjusted_mode->crtc_clock,
> > - crtc_state->port_clock,
> > - intel_dp_bw_fec_overhead(crtc_state->fec_enable),
> > - &crtc_state->dp_m_n);
> > - crtc_state->dp_m_n.tu = slots;
> > -
> > return 0;
> > }
> > static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
> > @@ -980,6 +1036,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
> > if (ret)
> > return ret;
> >
> > + /* TODO: also check if compression would allow for the mode */
>
> We should also stop using drm_dp_calc_pbn_mode() since it makes some
> wild assumptions, no?
Yes, it doesn't account for some overhead now. It should be changed to
calculate the BW the same way as the compute config code does, can add
a note about it.
Another thing to check both here and during compute config is the BW
limit of the sink, in case the last branch device decompresses the
stream for it. Atm the BW checks are for the compressed stream only
(based on the ENUM_PATH_RESOURCES Full_Payload_Bandwidth_Number), for
the uncompressed one either DFP_Link_Available_Payload_Bandwidth_Number
should be checked or if that's not available, the sink's link params.
>
> > if (mode_rate > max_rate || mode->clock > max_dotclk ||
> > drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
> > *status = MODE_CLOCK_HIGH;
> > --
> > 2.39.2
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 94+ messages in thread
* [Intel-gfx] [PATCH v5 13/30] drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 13/30] drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation Imre Deak
2023-11-06 20:39 ` Ville Syrjälä
2023-11-06 20:49 ` Ville Syrjälä
@ 2023-11-07 0:14 ` Imre Deak
2 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-11-07 0:14 UTC (permalink / raw)
To: intel-gfx
Atm, the BW allocated for an MST stream doesn't take into account the
DSC control symbol (EOC) and data alignment overhead on the local (first
downstream) MST link (reflected by the data M/N/TU values) and - besides
the above overheads - the FEC symbol overhead on 8b/10b remote
(after a downstream branch device) MST links.
In addition the FEC overhead used on the local link is a fixed amount,
which only applies to certain modes, but not enough for all modes; add a
code comment clarifying this.
Fix the above by calculating the data M/N values with the total BW
overhead (not including the SSC overhead, since this isn't enabled by
the source device) and using this the PBN and TU values for the local
link and PBN for remote links (including SSC, since this is mandatory
for links after downstream branch devices).
For now keep the current fixed FEC overhead as a minimum, since this is
what bspec requires for audio functionality.
Calculate the effective link BW in a clearer way, applying the channel
coding efficiency based on the coding type. The calculation was correct
for 8b/10b, but not for 128b/132b links; this patch leaves the behavior
for this unchanged, leaving the fix for a follow-up.
v2:
- Fix TU size programmed to the HW, making it match the payload size
programmed to the payload table.
v3:
- Add code comment about the connection between the payload's size in
the payload table and the corresponding PBN value. (Ville)
- Add WARN_ON(remote_m_n.tu < dp_m_n.tu). (Ville)
- Add code comment about factors not accounted for by the BW
calculation in intel_dp_mst_mode_valid_ctx() (and compute config).
(Ville)
- Simplify calculation of PBN to remote_m_n.tu * mst_state->pbn_div.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 124 ++++++++++++++++----
1 file changed, 99 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 1f6fbab7d4ada..9d6b76d1a52a7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -67,6 +67,63 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp
return 0;
}
+static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
+ const struct intel_connector *connector,
+ bool ssc, bool dsc, int bpp)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+ unsigned long flags = DRM_DP_BW_OVERHEAD_MST;
+ int dsc_slice_count = 0;
+ int overhead;
+
+ flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0;
+ flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
+ flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
+
+ if (dsc) {
+ flags |= DRM_DP_BW_OVERHEAD_DSC;
+ /* TODO: add support for bigjoiner */
+ dsc_slice_count = intel_dp_dsc_get_slice_count(connector,
+ adjusted_mode->clock,
+ adjusted_mode->hdisplay,
+ false);
+ }
+
+ overhead = drm_dp_bw_overhead(crtc_state->lane_count,
+ adjusted_mode->hdisplay,
+ dsc_slice_count,
+ to_bpp_x16(bpp),
+ flags);
+
+ /*
+ * TODO: clarify whether a minimum required by the fixed FEC overhead
+ * in the bspec audio programming sequence is required here.
+ */
+ return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable));
+}
+
+static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
+ const struct intel_connector *connector,
+ bool ssc, bool dsc,
+ int bpp,
+ struct intel_link_m_n *m_n)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+ int overhead = intel_dp_mst_bw_overhead(crtc_state,
+ connector,
+ ssc, dsc, bpp);
+
+ intel_link_compute_m_n(bpp, crtc_state->lane_count,
+ adjusted_mode->crtc_clock,
+ crtc_state->port_clock,
+ overhead,
+ m_n);
+
+ m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n);
+}
+
static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
int max_bpp,
@@ -107,14 +164,40 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
crtc_state->lane_count);
for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
+ struct intel_link_m_n remote_m_n;
+ int link_bpp;
+
drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, crtc_state, dsc);
if (ret)
continue;
- crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
- bpp << 4);
+ link_bpp = dsc ? bpp :
+ intel_dp_output_bpp(crtc_state->output_format, bpp);
+
+ intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc, link_bpp,
+ &crtc_state->dp_m_n);
+ intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc, link_bpp,
+ &remote_m_n);
+
+ /*
+ * The TU size programmed to the HW determines which slots in
+ * an MTP frame are used for this stream, which needs to match
+ * the payload size programmed to the first downstream branch
+ * device's payload table.
+ *
+ * Note that atm the payload's PBN value DRM core sends via
+ * the ALLOCATE_PAYLOAD side-band message matches the payload
+ * size (which it calculates from the PBN value) it programs
+ * to the first branch device's payload table. The allocation
+ * in the payload table could be reduced though (to
+ * crtc_state->dp_m_n.tu), provided that the driver doesn't
+ * enable SSC on the corresponding link.
+ */
+ drm_WARN_ON(&i915->drm, remote_m_n.tu < crtc_state->dp_m_n.tu);
+ crtc_state->dp_m_n.tu = remote_m_n.tu;
+ crtc_state->pbn = remote_m_n.tu * mst_state->pbn_div;
slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
connector->port,
@@ -123,6 +206,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
return slots;
if (slots >= 0) {
+ drm_WARN_ON(&i915->drm, slots != remote_m_n.tu);
+
ret = drm_dp_mst_atomic_check(state);
/*
* If we got slots >= 0 and we can fit those based on check
@@ -156,10 +241,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
struct drm_connector_state *conn_state,
struct link_config_limits *limits)
{
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
int slots = -EINVAL;
- int link_bpp;
/*
* FIXME: allocate the BW according to link_bpp, which in the case of
@@ -174,16 +256,6 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
if (slots < 0)
return slots;
- link_bpp = intel_dp_output_bpp(crtc_state->output_format, crtc_state->pipe_bpp);
-
- intel_link_compute_m_n(link_bpp,
- crtc_state->lane_count,
- adjusted_mode->crtc_clock,
- crtc_state->port_clock,
- intel_dp_bw_fec_overhead(crtc_state->fec_enable),
- &crtc_state->dp_m_n);
- crtc_state->dp_m_n.tu = slots;
-
return 0;
}
@@ -195,8 +267,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
int slots = -EINVAL;
int i, num_bpc;
u8 dsc_bpc[3] = {};
@@ -271,14 +341,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
return slots;
}
- intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
- crtc_state->lane_count,
- adjusted_mode->crtc_clock,
- crtc_state->port_clock,
- intel_dp_bw_fec_overhead(crtc_state->fec_enable),
- &crtc_state->dp_m_n);
- crtc_state->dp_m_n.tu = slots;
-
return 0;
}
static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
@@ -987,6 +1049,18 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
if (ret)
return ret;
+ /*
+ * TODO:
+ * - Also check if compression would allow for the mode
+ * - Calculate the overhead using drm_dp_bw_overhead() /
+ * drm_dp_bw_channel_coding_efficiency(), similarly to the
+ * compute config code, as drm_dp_calc_pbn_mode() doesn't
+ * account with all the overheads.
+ * - Check here and during compute config the BW reported by
+ * DFP_Link_Available_Payload_Bandwidth_Number (or the
+ * corresponding link capabilities of the sink) in case the
+ * stream is uncompressed for it by the last branch device.
+ */
if (mode_rate > max_rate || mode->clock > max_dotclk ||
drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
*status = MODE_CLOCK_HIGH;
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread
* [Intel-gfx] [PATCH v4 14/30] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (12 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 13/30] drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 15/30] drm/i915/dp_mst: Program the DSC PPS SDP for each stream Imre Deak
` (25 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
If an MST stream is modeset, its state must be checked along all the
other streams on the same MST link, for instance to resolve a BW
overallocation of a non-sink MST port or to make sure that the FEC is
enabled/disabled the same way for all these streams.
To prepare for that this patch adds all the stream CRTCs to the atomic
state and marks them for modeset similarly to tgl+ platforms. (If the
state computation doesn't change the state the CRTC is switched back to
fastset mode.)
So far on tgl+ this was required because all streams in the topology
shared the master transcoder. For older platforms this didn't apply but
adding all the state is required now on all platforms based on the
above.
v2:
- Add code and commit log comment clarifying the requirements on old/new
platforms. (Stan)
- Rename the function based on the new semantic. (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 05b2d5d547c85..5e7aab2b23f2e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -541,19 +541,23 @@ static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder,
* that shares the same MST stream as mode changed,
* intel_modeset_pipe_config()+intel_crtc_check_fastset() will take care to do
* a fastset when possible.
+ *
+ * On TGL+ this is required since each stream go through a master transcoder,
+ * so if the master transcoder needs modeset, all other streams in the
+ * topology need a modeset. All platforms need to add the atomic state
+ * for all streams in the topology, since a modeset on one may require
+ * changing the MST link BW usage of the others, which in turn needs a
+ * recomputation of the corresponding CRTC states.
*/
static int
-intel_dp_mst_atomic_master_trans_check(struct intel_connector *connector,
- struct intel_atomic_state *state)
+intel_dp_mst_atomic_topology_check(struct intel_connector *connector,
+ struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct drm_connector_list_iter connector_list_iter;
struct intel_connector *connector_iter;
int ret = 0;
- if (DISPLAY_VER(dev_priv) < 12)
- return 0;
-
if (!intel_connector_needs_modeset(state, &connector->base))
return 0;
@@ -607,7 +611,7 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
if (ret)
return ret;
- ret = intel_dp_mst_atomic_master_trans_check(intel_connector, state);
+ ret = intel_dp_mst_atomic_topology_check(intel_connector, state);
if (ret)
return ret;
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [Intel-gfx] [PATCH v4 15/30] drm/i915/dp_mst: Program the DSC PPS SDP for each stream
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (13 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 14/30] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-11-07 0:15 ` [Intel-gfx] [PATCH v5 " Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 16/30] drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled Imre Deak
` (24 subsequent siblings)
39 siblings, 1 reply; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
Atm the DSC PPS SDP is programmed only if the first stream is compressed
and then it's programmed only for the first stream. This left all other
compressed streams blank. Program the SDP for all streams.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 12 +++++++-----
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index c4dc1f71da4bc..bc5e5d9ec8b53 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2505,7 +2505,8 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
/* 6.o Configure and enable FEC if needed */
intel_ddi_enable_fec(encoder, crtc_state);
- intel_dsc_dp_pps_write(encoder, crtc_state);
+ if (!is_mst)
+ intel_dsc_dp_pps_write(encoder, crtc_state);
}
static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -2643,7 +2644,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
/* 7.l Configure and enable FEC if needed */
intel_ddi_enable_fec(encoder, crtc_state);
- intel_dsc_dp_pps_write(encoder, crtc_state);
+ if (!is_mst)
+ intel_dsc_dp_pps_write(encoder, crtc_state);
}
static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -2705,10 +2707,10 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
intel_ddi_enable_fec(encoder, crtc_state);
- if (!is_mst)
+ if (!is_mst) {
intel_ddi_enable_transcoder_clock(encoder, crtc_state);
-
- intel_dsc_dp_pps_write(encoder, crtc_state);
+ intel_dsc_dp_pps_write(encoder, crtc_state);
+ }
}
static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 5e7aab2b23f2e..2d7ffbc9fe006 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -43,6 +43,7 @@
#include "intel_dpio_phy.h"
#include "intel_hdcp.h"
#include "intel_hotplug.h"
+#include "intel_vdsc.h"
#include "skl_scaler.h"
static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp,
@@ -842,6 +843,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
intel_ddi_enable_transcoder_clock(encoder, pipe_config);
+ intel_dsc_dp_pps_write(&dig_port->base, pipe_config);
intel_ddi_set_dp_msa(pipe_config, conn_state);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [Intel-gfx] [PATCH v5 15/30] drm/i915/dp_mst: Program the DSC PPS SDP for each stream
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 15/30] drm/i915/dp_mst: Program the DSC PPS SDP for each stream Imre Deak
@ 2023-11-07 0:15 ` Imre Deak
0 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-11-07 0:15 UTC (permalink / raw)
To: intel-gfx
Atm the DSC PPS SDP is programmed only if the first stream is compressed
and then it's programmed only for the first stream. This left all other
compressed streams blank. Program the SDP for all streams.
v2:
- Rebase on upstream include "intel_vdsc.h" change.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 12 +++++++-----
drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index c75fd00e360ac..87fa7f7369254 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2505,7 +2505,8 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
/* 6.o Configure and enable FEC if needed */
intel_ddi_enable_fec(encoder, crtc_state);
- intel_dsc_dp_pps_write(encoder, crtc_state);
+ if (!is_mst)
+ intel_dsc_dp_pps_write(encoder, crtc_state);
}
static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -2643,7 +2644,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
/* 7.l Configure and enable FEC if needed */
intel_ddi_enable_fec(encoder, crtc_state);
- intel_dsc_dp_pps_write(encoder, crtc_state);
+ if (!is_mst)
+ intel_dsc_dp_pps_write(encoder, crtc_state);
}
static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -2705,10 +2707,10 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
intel_ddi_enable_fec(encoder, crtc_state);
- if (!is_mst)
+ if (!is_mst) {
intel_ddi_enable_transcoder_clock(encoder, crtc_state);
-
- intel_dsc_dp_pps_write(encoder, crtc_state);
+ intel_dsc_dp_pps_write(encoder, crtc_state);
+ }
}
static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index c9faac174aa2c..5efc3cea73e52 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -860,6 +860,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
intel_ddi_enable_transcoder_clock(encoder, pipe_config);
+ intel_dsc_dp_pps_write(&dig_port->base, pipe_config);
intel_ddi_set_dp_msa(pipe_config, conn_state);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread
* [Intel-gfx] [PATCH v4 16/30] drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (14 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 15/30] drm/i915/dp_mst: Program the DSC PPS SDP for each stream Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 17/30] drm/i915/dp_mst: Add missing DSC compression disabling Imre Deak
` (23 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
Atm the DSC PPS SDP will stay enabled after enabling and disabling DSC.
This leaves an output blank after switching off DSC on it. Make sure the
SDP is disabled for an uncompressed output.
v2:
- Disable the SDP already during output disabling. (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 ++++-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++---
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 34da403fa512b..e4f674192f3b7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4069,7 +4069,10 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
- /* TODO: Add DSC case (DIP_ENABLE_PPS) */
+ /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
+ if (!enable && HAS_DSC(dev_priv))
+ val &= ~VDIP_ENABLE_PPS;
+
/* When PSR is enabled, this routine doesn't disable VSC DIP */
if (!crtc_state->has_psr)
val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 2d7ffbc9fe006..cfbe3430e5ace 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -729,9 +729,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
* BSpec 4287: disable DIP after the transcoder is disabled and before
* the transcoder clock select is set to none.
*/
- if (last_mst_stream)
- intel_dp_set_infoframes(&dig_port->base, false,
- old_crtc_state, NULL);
+ intel_dp_set_infoframes(&dig_port->base, false,
+ old_crtc_state, NULL);
/*
* From TGL spec: "If multi-stream slave transcoder: Configure
* Transcoder Clock Select to direct no clock to the transcoder"
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [Intel-gfx] [PATCH v4 17/30] drm/i915/dp_mst: Add missing DSC compression disabling
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (15 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 16/30] drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 18/30] drm/i915/dp: Rename intel_ddi_disable_fec_state() to intel_ddi_disable_fec() Imre Deak
` (22 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
Add the missing DSC compression disabling step for MST streams,
similarly to how this is done for SST outputs.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index cfbe3430e5ace..4ed6074125e05 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -713,6 +713,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
intel_ddi_disable_transcoder_func(old_crtc_state);
+ intel_dsc_disable(old_crtc_state);
+
if (DISPLAY_VER(dev_priv) >= 9)
skl_scaler_disable(old_crtc_state);
else
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [Intel-gfx] [PATCH v4 18/30] drm/i915/dp: Rename intel_ddi_disable_fec_state() to intel_ddi_disable_fec()
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (16 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 17/30] drm/i915/dp_mst: Add missing DSC compression disabling Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 19/30] drm/i915/dp: Wait for FEC detected status in the sink Imre Deak
` (21 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
Rename intel_ddi_disable_fec_state() to intel_ddi_disable_fec(), for
symmetry with intel_ddi_enable_fec().
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index bc5e5d9ec8b53..5683b94cbf0fe 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2234,8 +2234,8 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder,
0, DP_TP_CTL_FEC_ENABLE);
}
-static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+static void intel_ddi_disable_fec(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -2868,8 +2868,7 @@ static void disable_ddi_buf(struct intel_encoder *encoder,
intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
DP_TP_CTL_ENABLE, 0);
- /* Disable FEC in DP Sink */
- intel_ddi_disable_fec_state(encoder, crtc_state);
+ intel_ddi_disable_fec(encoder, crtc_state);
if (wait)
intel_wait_ddi_buf_idle(dev_priv, port);
@@ -2884,7 +2883,7 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
mtl_disable_ddi_buf(encoder, crtc_state);
/* 3.f Disable DP_TP_CTL FEC Enable if it is needed */
- intel_ddi_disable_fec_state(encoder, crtc_state);
+ intel_ddi_disable_fec(encoder, crtc_state);
} else {
disable_ddi_buf(encoder, crtc_state);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [Intel-gfx] [PATCH v4 19/30] drm/i915/dp: Wait for FEC detected status in the sink
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (17 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 18/30] drm/i915/dp: Rename intel_ddi_disable_fec_state() to intel_ddi_disable_fec() Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 20/30] drm/i915/dp: Disable FEC ready flag " Imre Deak
` (20 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
As required by the DP standard wait for the sink to detect the FEC
decode enabling symbol sent by the source.
There is a difference between SST and MST when the source enables
the FEC encoding: on SST this happens only after enabling the
transcoder, whereas on MST it happens already after enabling the
transcoder function (before enabling the transcoder). Wait for the
detected status at the earliest spot accordingly.
v2:
- Wait for the FEC detected status on SST after the transcoder is
enabled.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 73 +++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_ddi.h | 3 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++
3 files changed, 80 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 5683b94cbf0fe..818483d9a7fce 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -25,6 +25,7 @@
*
*/
+#include <linux/iopoll.h>
#include <linux/string_helpers.h>
#include <drm/display/drm_scdc_helper.h>
@@ -2220,6 +2221,74 @@ static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
drm_dbg_kms(&i915->drm,
"Failed to set FEC_READY in the sink\n");
+
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS,
+ DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0)
+ drm_dbg_kms(&i915->drm, "Failed to clear FEC detected flags\n");
+}
+
+static int read_fec_detected_status(struct drm_dp_aux *aux)
+{
+ int ret;
+ u8 status;
+
+ ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status);
+ if (ret < 0)
+ return ret;
+
+ return status;
+}
+
+static void wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled)
+{
+ struct drm_i915_private *i915 = to_i915(aux->drm_dev);
+ int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED;
+ int status;
+ int err;
+
+ err = readx_poll_timeout(read_fec_detected_status, aux, status,
+ status & mask || status < 0,
+ 10000, 200000);
+
+ if (!err && status >= 0)
+ return;
+
+ if (err == -ETIMEDOUT)
+ drm_err(&i915->drm, "Timeout waiting for FEC %s to get detected\n",
+ str_enabled_disabled(enabled));
+ else
+ drm_dbg_kms(&i915->drm, "FEC detected status read error: %d\n", status);
+}
+
+void intel_ddi_wait_for_fec_status(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ bool enabled)
+{
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ int ret;
+
+ if (!crtc_state->fec_enable)
+ return;
+
+ if (enabled)
+ ret = intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state),
+ DP_TP_STATUS_FEC_ENABLE_LIVE, 1);
+ else
+ ret = intel_de_wait_for_clear(i915, dp_tp_status_reg(encoder, crtc_state),
+ DP_TP_STATUS_FEC_ENABLE_LIVE, 1);
+
+ if (ret)
+ drm_err(&i915->drm,
+ "Timeout waiting for FEC live state to get %s\n",
+ str_enabled_disabled(enabled));
+
+ /*
+ * At least the Synoptics MST hub doesn't set the detected flag for
+ * FEC decoding disabling so skip waiting for that.
+ */
+ if (enabled)
+ wait_for_fec_detected(&intel_dp->aux, enabled);
}
static void intel_ddi_enable_fec(struct intel_encoder *encoder,
@@ -2887,6 +2956,8 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
} else {
disable_ddi_buf(encoder, crtc_state);
}
+
+ intel_ddi_wait_for_fec_status(encoder, crtc_state, false);
}
static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
@@ -3253,6 +3324,8 @@ static void intel_enable_ddi(struct intel_atomic_state *state,
intel_enable_transcoder(crtc_state);
+ intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
+
intel_crtc_vblank_on(crtc_state);
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index 4999c0ee229bd..e939b93fc81c2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -60,6 +60,9 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state);
+void intel_ddi_wait_for_fec_status(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ bool enabled);
void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 4ed6074125e05..191d45cddd498 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -861,6 +861,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
struct drm_dp_mst_topology_state *mst_state =
drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
enum transcoder trans = pipe_config->cpu_transcoder;
+ bool first_mst_stream = intel_dp->active_mst_links == 1;
drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
@@ -887,6 +888,9 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
wait_for_act_sent(encoder, pipe_config);
+ if (first_mst_stream)
+ intel_ddi_wait_for_fec_status(encoder, pipe_config, true);
+
drm_dp_add_payload_part2(&intel_dp->mst_mgr, &state->base,
drm_atomic_get_mst_payload_state(mst_state, connector->port));
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [Intel-gfx] [PATCH v4 20/30] drm/i915/dp: Disable FEC ready flag in the sink
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (18 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 19/30] drm/i915/dp: Wait for FEC detected status in the sink Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 21/30] drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk Imre Deak
` (19 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
Disable the FEC ready flag in the sink during a disabling modeset.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 818483d9a7fce..24b343465f6f6 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2211,18 +2211,21 @@ static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel
}
static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
+ const struct intel_crtc_state *crtc_state,
+ bool enable)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
if (!crtc_state->fec_enable)
return;
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
- drm_dbg_kms(&i915->drm,
- "Failed to set FEC_READY in the sink\n");
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION,
+ enable ? DP_FEC_READY : 0) <= 0)
+ drm_dbg_kms(&i915->drm, "Failed to set FEC_READY to %s in the sink\n",
+ enable ? "enabled" : "disabled");
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS,
+ if (enable &&
+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS,
DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0)
drm_dbg_kms(&i915->drm, "Failed to clear FEC detected flags\n");
}
@@ -2541,7 +2544,7 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
* in the FEC_CONFIGURATION register to 1 before initiating link
* training
*/
- intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
+ intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
intel_dp_check_frl_training(intel_dp);
intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
@@ -2692,7 +2695,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
* in the FEC_CONFIGURATION register to 1 before initiating link
* training
*/
- intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
+ intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
intel_dp_check_frl_training(intel_dp);
intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
@@ -2768,7 +2771,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
intel_dp_configure_protocol_converter(intel_dp, crtc_state);
intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
true);
- intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
+ intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
intel_dp_start_link_train(intel_dp, crtc_state);
if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
!is_trans_port_sync_mode(crtc_state))
@@ -2997,6 +3000,8 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
intel_disable_ddi_buf(encoder, old_crtc_state);
+ intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false);
+
/*
* From TGL spec: "If single stream or multi-stream master transcoder:
* Configure Transcoder Clock select to direct no clock to the
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [Intel-gfx] [PATCH v4 21/30] drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (19 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 20/30] drm/i915/dp: Disable FEC ready flag " Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-11-07 0:15 ` [Intel-gfx] [PATCH v5 " Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 22/30] drm/i915/dp_mst: Enable decompression in the sink from the MST encoder hooks Imre Deak
` (18 subsequent siblings)
39 siblings, 1 reply; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
The Synaptics MST hubs expose some sink EDID modes with a reduced HBLANK
period, presumedly to save BW, which the hub expands before forwarding
the stream to the sink. In particular a 4k mode with a standard CVT
HBLANK period is exposed with either a CVT reduced blank RBv1,v2 (80,
160 pixel) or a non-CVT 56 pixel HBLANK period. The DP standard
describes the above HBLANK expansion functionality, but it requires
enabling this explicitly, whereas these hubs apply the expansion
transparently.
Such modes will work okay until DSC decompression is enabled in the hub
for the given sink, but after this the same mode will not work reliably
in decompressed mode. As a workaround force enable DSC for such modes.
Apply the WA when the HBLANK period is 300ns or below, matching the
above tested modes with a 533.25MHz dotclock and maximum 160 HBLANK
pixels.
OTOH DSC for these modes will only work above a certain compressed bpp
threshold which depends on the link rate, so apply this limit as well
in the workaround.
Apply the workaround only for Synaptics hubs which support the HBLANK
expansion.
v2:
- Apply the WA whenever the HBLANK period is 300ns or below.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_types.h | 2 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 119 +++++++++++++++++-
2 files changed, 117 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 65ea37fe8cff3..409dbf8a2a1cd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -624,6 +624,8 @@ struct intel_connector {
struct drm_dp_aux *dsc_decompression_aux;
u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
u8 fec_capability;
+
+ u8 dsc_hblank_expansion_quirk:1;
} dp;
/* Work struct to schedule a uevent on link train failure */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 191d45cddd498..94627ab271c7d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -360,8 +360,77 @@ static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
return 0;
}
+static int mode_hblank_period_ns(const struct drm_display_mode *mode)
+{
+ return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(mode->htotal - mode->hdisplay,
+ NSEC_PER_SEC / 1000),
+ mode->crtc_clock);
+}
+
+static bool
+hblank_expansion_quirk_needs_dsc(const struct intel_connector *connector,
+ const struct intel_crtc_state *crtc_state)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+
+ if (!connector->dp.dsc_hblank_expansion_quirk)
+ return false;
+
+ if (mode_hblank_period_ns(adjusted_mode) > 300)
+ return false;
+
+ return true;
+}
+
+static bool
+adjust_limits_for_dsc_hblank_expansion_quirk(const struct intel_connector *connector,
+ const struct intel_crtc_state *crtc_state,
+ struct link_config_limits *limits,
+ bool dsc)
+{
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ int min_bpp_x16 = limits->link.min_bpp_x16;
+
+ if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state))
+ return true;
+
+ if (!dsc) {
+ drm_dbg_kms(&i915->drm,
+ "[CRTC:%d:%s][CONNECTOR:%d:%s] DSC required by hblank expansion quirk\n",
+ crtc->base.base.id, crtc->base.name,
+ connector->base.base.id, connector->base.name);
+ return false;
+ }
+
+ drm_WARN_ON(&i915->drm, limits->min_rate != limits->max_rate);
+
+ if (limits->max_rate < 540000)
+ min_bpp_x16 = to_bpp_x16(13);
+ else if (limits->max_rate < 810000)
+ min_bpp_x16 = to_bpp_x16(10);
+
+ if (limits->link.min_bpp_x16 >= min_bpp_x16)
+ return true;
+
+ drm_dbg_kms(&i915->drm,
+ "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to " BPP_X16_FMT " due to hblank expansion quirk\n",
+ crtc->base.base.id, crtc->base.name,
+ connector->base.base.id, connector->base.name,
+ BPP_X16_ARGS(min_bpp_x16));
+
+ if (limits->link.max_bpp_x16 < min_bpp_x16)
+ return false;
+
+ limits->link.min_bpp_x16 = min_bpp_x16;
+
+ return true;
+}
+
static bool
intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
+ const struct intel_connector *connector,
struct intel_crtc_state *crtc_state,
bool dsc,
struct link_config_limits *limits)
@@ -389,10 +458,16 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
- return intel_dp_compute_config_link_bpp_limits(intel_dp,
- crtc_state,
- dsc,
- limits);
+ if (!intel_dp_compute_config_link_bpp_limits(intel_dp,
+ crtc_state,
+ dsc,
+ limits))
+ return false;
+
+ return adjust_limits_for_dsc_hblank_expansion_quirk(connector,
+ crtc_state,
+ limits,
+ dsc);
}
static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
@@ -402,6 +477,8 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
struct intel_dp *intel_dp = &intel_mst->primary->dp;
+ const struct intel_connector *connector =
+ to_intel_connector(conn_state->connector);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
struct link_config_limits limits;
@@ -417,6 +494,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
dsc_needed = intel_dp->force_dsc_en ||
!intel_dp_mst_compute_config_limits(intel_dp,
+ connector,
pipe_config,
false,
&limits);
@@ -439,6 +517,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
str_yes_no(intel_dp->force_dsc_en));
if (!intel_dp_mst_compute_config_limits(intel_dp,
+ connector,
pipe_config,
true,
&limits))
@@ -1213,6 +1292,36 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], connector);
}
+static bool detect_dsc_hblank_expansion_quirk(const struct intel_connector *connector)
+{
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct drm_dp_desc desc;
+ u8 dpcd[DP_RECEIVER_CAP_SIZE];
+
+ if (!connector->dp.dsc_decompression_aux)
+ return false;
+
+ if (drm_dp_read_desc(connector->dp.dsc_decompression_aux,
+ &desc, true) < 0)
+ return false;
+
+ if (!drm_dp_has_quirk(&desc,
+ DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC))
+ return false;
+
+ if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd) < 0)
+ return false;
+
+ if (!(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE))
+ return false;
+
+ drm_dbg_kms(&i915->drm,
+ "[CONNECTOR:%d:%s] DSC HBLANK expansion quirk detected\n",
+ connector->base.base.id, connector->base.name);
+
+ return true;
+}
+
static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_port *port,
const char *pathprop)
@@ -1242,6 +1351,8 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
*/
intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);
+ intel_connector->dp.dsc_hblank_expansion_quirk =
+ detect_dsc_hblank_expansion_quirk(intel_connector);
connector = &intel_connector->base;
ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs,
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [Intel-gfx] [PATCH v5 21/30] drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 21/30] drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk Imre Deak
@ 2023-11-07 0:15 ` Imre Deak
0 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-11-07 0:15 UTC (permalink / raw)
To: intel-gfx
The Synaptics MST hubs expose some sink EDID modes with a reduced HBLANK
period, presumedly to save BW, which the hub expands before forwarding
the stream to the sink. In particular a 4k mode with a standard CVT
HBLANK period is exposed with either a CVT reduced blank RBv1,v2 (80,
160 pixel) or a non-CVT 56 pixel HBLANK period. The DP standard
describes the above HBLANK expansion functionality, but it requires
enabling this explicitly, whereas these hubs apply the expansion
transparently.
In some TBT docks with such a Synaptics hub (DELL WD22TB4) the above modes
will work okay until DSC decompression is enabled in the hub for the given
sink, but after this the same mode will not work reliably in decompressed
mode. In another TBT dock (Thinkpad 40B0) the above modes will not work
in uncompressed/18bpp mode (regardless of whether DSC decompression was
enabled before or not).
As a workaround force enable DSC for such modes. Apply the WA when the
HBLANK period is 300ns or below, matching the above tested modes with a
533.25MHz dotclock and maximum 160 HBLANK pixels.
OTOH DSC for these modes will only work above a certain compressed bpp
threshold which depends on the link rate, so apply this limit as well
in the workaround.
On platforms, pipe/port configurations where DSC is not supported, for
instance on ICL where DSC/MST is still work-in-progress, limit the
minimum link bpp to 24.
Apply the workaround only for Synaptics hubs which support the HBLANK
expansion.
v2:
- Apply the WA whenever the HBLANK period is 300ns or below.
v3:
- Clarify in the commit log the failure modes of the different docks.
- Handle platforms/pipe/port configurations without DSC support.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_types.h | 2 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 133 +++++++++++++++++-
2 files changed, 131 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 047fe3f8905ac..6c2f18ef543e4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -624,6 +624,8 @@ struct intel_connector {
struct drm_dp_aux *dsc_decompression_aux;
u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
u8 fec_capability;
+
+ u8 dsc_hblank_expansion_quirk:1;
} dp;
/* Work struct to schedule a uevent on link train failure */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 4d0827a3cd9b1..4f066a868b9a2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -378,8 +378,91 @@ intel_dp_mst_dsc_source_support(const struct intel_crtc_state *crtc_state)
return DISPLAY_VER(i915) >= 12 && intel_dsc_source_support(crtc_state);
}
+static int mode_hblank_period_ns(const struct drm_display_mode *mode)
+{
+ return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(mode->htotal - mode->hdisplay,
+ NSEC_PER_SEC / 1000),
+ mode->crtc_clock);
+}
+
+static bool
+hblank_expansion_quirk_needs_dsc(const struct intel_connector *connector,
+ const struct intel_crtc_state *crtc_state)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+
+ if (!connector->dp.dsc_hblank_expansion_quirk)
+ return false;
+
+ if (mode_hblank_period_ns(adjusted_mode) > 300)
+ return false;
+
+ return true;
+}
+
+static bool
+adjust_limits_for_dsc_hblank_expansion_quirk(const struct intel_connector *connector,
+ const struct intel_crtc_state *crtc_state,
+ struct link_config_limits *limits,
+ bool dsc)
+{
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ int min_bpp_x16 = limits->link.min_bpp_x16;
+
+ if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state))
+ return true;
+
+ if (!dsc) {
+ if (intel_dp_mst_dsc_source_support(crtc_state)) {
+ drm_dbg_kms(&i915->drm,
+ "[CRTC:%d:%s][CONNECTOR:%d:%s] DSC needed by hblank expansion quirk\n",
+ crtc->base.base.id, crtc->base.name,
+ connector->base.base.id, connector->base.name);
+ return false;
+ }
+
+ drm_dbg_kms(&i915->drm,
+ "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to 24 due to hblank expansion quirk\n",
+ crtc->base.base.id, crtc->base.name,
+ connector->base.base.id, connector->base.name);
+
+ if (limits->link.max_bpp_x16 < to_bpp_x16(24))
+ return false;
+
+ limits->link.min_bpp_x16 = to_bpp_x16(24);
+
+ return true;
+ }
+
+ drm_WARN_ON(&i915->drm, limits->min_rate != limits->max_rate);
+
+ if (limits->max_rate < 540000)
+ min_bpp_x16 = to_bpp_x16(13);
+ else if (limits->max_rate < 810000)
+ min_bpp_x16 = to_bpp_x16(10);
+
+ if (limits->link.min_bpp_x16 >= min_bpp_x16)
+ return true;
+
+ drm_dbg_kms(&i915->drm,
+ "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to " BPP_X16_FMT " in DSC mode due to hblank expansion quirk\n",
+ crtc->base.base.id, crtc->base.name,
+ connector->base.base.id, connector->base.name,
+ BPP_X16_ARGS(min_bpp_x16));
+
+ if (limits->link.max_bpp_x16 < min_bpp_x16)
+ return false;
+
+ limits->link.min_bpp_x16 = min_bpp_x16;
+
+ return true;
+}
+
static bool
intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
+ const struct intel_connector *connector,
struct intel_crtc_state *crtc_state,
bool dsc,
struct link_config_limits *limits)
@@ -407,10 +490,16 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
- return intel_dp_compute_config_link_bpp_limits(intel_dp,
- crtc_state,
- dsc,
- limits);
+ if (!intel_dp_compute_config_link_bpp_limits(intel_dp,
+ crtc_state,
+ dsc,
+ limits))
+ return false;
+
+ return adjust_limits_for_dsc_hblank_expansion_quirk(connector,
+ crtc_state,
+ limits,
+ dsc);
}
static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
@@ -420,6 +509,8 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
struct intel_dp *intel_dp = &intel_mst->primary->dp;
+ const struct intel_connector *connector =
+ to_intel_connector(conn_state->connector);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
struct link_config_limits limits;
@@ -435,6 +526,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
dsc_needed = intel_dp->force_dsc_en ||
!intel_dp_mst_compute_config_limits(intel_dp,
+ connector,
pipe_config,
false,
&limits);
@@ -460,6 +552,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
return -EINVAL;
if (!intel_dp_mst_compute_config_limits(intel_dp,
+ connector,
pipe_config,
true,
&limits))
@@ -1236,6 +1329,36 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], connector);
}
+static bool detect_dsc_hblank_expansion_quirk(const struct intel_connector *connector)
+{
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct drm_dp_desc desc;
+ u8 dpcd[DP_RECEIVER_CAP_SIZE];
+
+ if (!connector->dp.dsc_decompression_aux)
+ return false;
+
+ if (drm_dp_read_desc(connector->dp.dsc_decompression_aux,
+ &desc, true) < 0)
+ return false;
+
+ if (!drm_dp_has_quirk(&desc,
+ DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC))
+ return false;
+
+ if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd) < 0)
+ return false;
+
+ if (!(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE))
+ return false;
+
+ drm_dbg_kms(&i915->drm,
+ "[CONNECTOR:%d:%s] DSC HBLANK expansion quirk detected\n",
+ connector->base.base.id, connector->base.name);
+
+ return true;
+}
+
static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_port *port,
const char *pathprop)
@@ -1265,6 +1388,8 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
*/
intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);
+ intel_connector->dp.dsc_hblank_expansion_quirk =
+ detect_dsc_hblank_expansion_quirk(intel_connector);
connector = &intel_connector->base;
ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs,
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread
* [Intel-gfx] [PATCH v4 22/30] drm/i915/dp_mst: Enable decompression in the sink from the MST encoder hooks
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (20 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 21/30] drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-11-07 0:15 ` [Intel-gfx] [PATCH v5 " Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 23/30] drm/i915/dp: Enable DSC via the connector decompression AUX Imre Deak
` (17 subsequent siblings)
39 siblings, 1 reply; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
Enable/disable the DSC decompression in the sink/branch from the MST
encoder hooks. This prepares for an upcoming patch toggling DSC for each
stream as needed, but for now keeps the current behavior, as DSC is only
enabled for the first MST stream.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++++++++----
drivers/gpu/drm/i915/display/intel_dp_mst.c | 15 ++++++++++++++-
2 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 24b343465f6f6..0ec212ead9f02 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2538,7 +2538,9 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
intel_dp_configure_protocol_converter(intel_dp, crtc_state);
- intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
+ if (!is_mst)
+ intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
+
/*
* DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
* in the FEC_CONFIGURATION register to 1 before initiating link
@@ -2689,7 +2691,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
intel_dp_configure_protocol_converter(intel_dp, crtc_state);
- intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
+ if (!is_mst)
+ intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
/*
* DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
* in the FEC_CONFIGURATION register to 1 before initiating link
@@ -2769,8 +2772,9 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
if (!is_mst)
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
intel_dp_configure_protocol_converter(intel_dp, crtc_state);
- intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
- true);
+ if (!is_mst)
+ intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
+ true);
intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
intel_dp_start_link_train(intel_dp, crtc_state);
if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 94627ab271c7d..f970e25f57fec 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -747,6 +747,13 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state,
drm_dp_remove_payload_part1(&intel_dp->mst_mgr, new_mst_state, new_payload);
intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
+
+ if (intel_dp->active_mst_links == 1) /* last stream ? */
+ /*
+ * TODO: disable decompression for all streams/in any MST ports, not
+ * only in the first downstream branch device.
+ */
+ intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, false);
}
static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
@@ -901,9 +908,15 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
- if (first_mst_stream)
+ if (first_mst_stream) {
+ /*
+ * TODO: enable decompression for all streams/in any MST ports, not
+ * only in the first downstream branch device.
+ */
+ intel_dp_sink_set_decompression_state(intel_dp, pipe_config, true);
dig_port->base.pre_enable(state, &dig_port->base,
pipe_config, NULL);
+ }
intel_dp->active_mst_links++;
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [Intel-gfx] [PATCH v5 22/30] drm/i915/dp_mst: Enable decompression in the sink from the MST encoder hooks
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 22/30] drm/i915/dp_mst: Enable decompression in the sink from the MST encoder hooks Imre Deak
@ 2023-11-07 0:15 ` Imre Deak
0 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-11-07 0:15 UTC (permalink / raw)
To: intel-gfx
Enable/disable the DSC decompression in the sink/branch from the MST
encoder hooks. This prepares for an upcoming patch toggling DSC for each
stream as needed, but for now keeps the current behavior, as DSC is only
enabled for the first MST stream.
v2:
- Rebased on latest drm-tip.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++++++++----
drivers/gpu/drm/i915/display/intel_dp_mst.c | 15 ++++++++++++++-
2 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1abf74af6c5ce..cc2a38fc22d0d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2538,7 +2538,9 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
intel_dp_configure_protocol_converter(intel_dp, crtc_state);
- intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
+ if (!is_mst)
+ intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
+
/*
* DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
* in the FEC_CONFIGURATION register to 1 before initiating link
@@ -2689,7 +2691,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
intel_dp_configure_protocol_converter(intel_dp, crtc_state);
- intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
+ if (!is_mst)
+ intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
/*
* DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
* in the FEC_CONFIGURATION register to 1 before initiating link
@@ -2769,8 +2772,9 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
if (!is_mst)
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
intel_dp_configure_protocol_converter(intel_dp, crtc_state);
- intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
- true);
+ if (!is_mst)
+ intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
+ true);
intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
intel_dp_start_link_train(intel_dp, crtc_state);
if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 4f066a868b9a2..eab69f57655d9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -776,6 +776,13 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state,
intel_hdcp_disable(intel_mst->connector);
intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
+
+ if (intel_dp->active_mst_links == 1) /* last stream ? */
+ /*
+ * TODO: disable decompression for all streams/in any MST ports, not
+ * only in the first downstream branch device.
+ */
+ intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, false);
}
static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
@@ -932,9 +939,15 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
- if (first_mst_stream)
+ if (first_mst_stream) {
+ /*
+ * TODO: enable decompression for all streams/in any MST ports, not
+ * only in the first downstream branch device.
+ */
+ intel_dp_sink_set_decompression_state(intel_dp, pipe_config, true);
dig_port->base.pre_enable(state, &dig_port->base,
pipe_config, NULL);
+ }
intel_dp->active_mst_links++;
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread
* [Intel-gfx] [PATCH v4 23/30] drm/i915/dp: Enable DSC via the connector decompression AUX
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (21 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 22/30] drm/i915/dp_mst: Enable decompression in the sink from the MST encoder hooks Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 24/30] drm/i915/dp_mst: Enable DSC passthrough Imre Deak
` (16 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
Enable DSC using the DSC AUX device stored for this purpose in the
connector. For clarity add separate functions to enable/disable the
decompression, since these sequences will diverge more in follow-up
patches that also enable/disable DSC passthrough and on MST do the
actual enabling/disabling only for the first/last user of the given
AUX device. As a preparation for the latter refcounting change, also
pass the atomic state to the functions.
While at it set/clear only the DP_DECOMPRESSION_EN flag in the
DP_DSC_ENABLE DPCD register, preserving the reserved register bits.
Besides preserving the reserved register bits, the behavior stays as
before, as DSC is still only enabled for the first MST stream (which a
follow-up patch changes, enabling it for all streams).
v2:
- Add a helper function setting/clearing the decompression flag,
preserving the reserved register bits.
v3:
- Add separate functions to enable/disable decompression and pass the
atomic state to these.
- Add DocBook for both functions.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 19 +++--
drivers/gpu/drm/i915/display/intel_dp.c | 90 ++++++++++++++++++---
drivers/gpu/drm/i915/display/intel_dp.h | 9 ++-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +-
4 files changed, 101 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 0ec212ead9f02..972b8a5588ec2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2539,7 +2539,9 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
intel_dp_configure_protocol_converter(intel_dp, crtc_state);
if (!is_mst)
- intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
+ intel_dp_sink_enable_decompression(state,
+ to_intel_connector(conn_state->connector),
+ crtc_state);
/*
* DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
@@ -2692,7 +2694,9 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
intel_dp_configure_protocol_converter(intel_dp, crtc_state);
if (!is_mst)
- intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
+ intel_dp_sink_enable_decompression(state,
+ to_intel_connector(conn_state->connector),
+ crtc_state);
/*
* DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
* in the FEC_CONFIGURATION register to 1 before initiating link
@@ -2773,8 +2777,9 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
intel_dp_configure_protocol_converter(intel_dp, crtc_state);
if (!is_mst)
- intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
- true);
+ intel_dp_sink_enable_decompression(state,
+ to_intel_connector(conn_state->connector),
+ crtc_state);
intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
intel_dp_start_link_train(intel_dp, crtc_state);
if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
@@ -3354,6 +3359,8 @@ static void intel_disable_ddi_dp(struct intel_atomic_state *state,
const struct drm_connector_state *old_conn_state)
{
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct intel_connector *connector =
+ to_intel_connector(old_conn_state->connector);
intel_dp->link_trained = false;
@@ -3362,8 +3369,8 @@ static void intel_disable_ddi_dp(struct intel_atomic_state *state,
intel_psr_disable(intel_dp, old_crtc_state);
intel_edp_backlight_off(old_conn_state);
/* Disable the decompression in DP Sink */
- intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
- false);
+ intel_dp_sink_disable_decompression(state,
+ connector, old_crtc_state);
/* Disable Ignore_MSA bit in DP Sink */
intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
false);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e4f674192f3b7..0cdb4d176a8f9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2937,24 +2937,94 @@ static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
}
-void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- bool enable)
+static int
+write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set)
{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- int ret;
+ int err;
+ u8 val;
- if (!crtc_state->dsc.compression_enable)
- return;
+ err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val);
+ if (err < 0)
+ return err;
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
- enable ? DP_DECOMPRESSION_EN : 0);
- if (ret < 0)
+ if (set)
+ val |= flag;
+ else
+ val &= ~flag;
+
+ return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val);
+}
+
+static void
+intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,
+ bool enable)
+{
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+
+ if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux,
+ DP_DECOMPRESSION_EN, enable) < 0)
drm_dbg_kms(&i915->drm,
"Failed to %s sink decompression state\n",
str_enable_disable(enable));
}
+/**
+ * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
+ * @state: atomic state
+ * @connector: connector to enable the decompression for
+ * @new_crtc_state: new state for the CRTC driving @connector
+ *
+ * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
+ * register of the appropriate sink/branch device. On SST this is always the
+ * sink device, whereas on MST based on each device's DSC capabilities it's
+ * either the last branch device (enabling decompression in it) or both the
+ * last branch device (enabling passthrough in it) and the sink device
+ * (enabling decompression in it).
+ */
+void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
+ struct intel_connector *connector,
+ const struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+
+ if (!new_crtc_state->dsc.compression_enable)
+ return;
+
+ if (drm_WARN_ON(&i915->drm,
+ !connector->dp.dsc_decompression_aux))
+ return;
+
+ /* TODO: Enable passthrough in the MST last branch device if needed. */
+ intel_dp_sink_set_dsc_decompression(connector, true);
+}
+
+/**
+ * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device
+ * @state: atomic state
+ * @connector: connector to disable the decompression for
+ * @old_crtc_state: old state for the CRTC driving @connector
+ *
+ * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
+ * register of the appropriate sink/branch device, corresponding to the
+ * sequence in intel_dp_sink_enable_decompression().
+ */
+void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
+ struct intel_connector *connector,
+ const struct intel_crtc_state *old_crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+
+ if (!old_crtc_state->dsc.compression_enable)
+ return;
+
+ if (drm_WARN_ON(&i915->drm,
+ !connector->dp.dsc_decompression_aux))
+ return;
+
+ intel_dp_sink_set_dsc_decompression(connector, false);
+ /* TODO: Disable passthrough in the MST last branch device if needed. */
+}
+
static void
intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
{
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 2080575fef69a..7cc23d846dfbf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -57,9 +57,12 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode);
void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
-void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- bool enable);
+void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
+ struct intel_connector *connector,
+ const struct intel_crtc_state *new_crtc_state);
+void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
+ struct intel_connector *connector,
+ const struct intel_crtc_state *old_crtc_state);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder);
void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index f970e25f57fec..355a573c97930 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -753,7 +753,7 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state,
* TODO: disable decompression for all streams/in any MST ports, not
* only in the first downstream branch device.
*/
- intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, false);
+ intel_dp_sink_disable_decompression(state, connector, old_crtc_state);
}
static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
@@ -913,7 +913,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
* TODO: enable decompression for all streams/in any MST ports, not
* only in the first downstream branch device.
*/
- intel_dp_sink_set_decompression_state(intel_dp, pipe_config, true);
+ intel_dp_sink_enable_decompression(state, connector, pipe_config);
dig_port->base.pre_enable(state, &dig_port->base,
pipe_config, NULL);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [Intel-gfx] [PATCH v4 24/30] drm/i915/dp_mst: Enable DSC passthrough
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (22 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 23/30] drm/i915/dp: Enable DSC via the connector decompression AUX Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 25/30] drm/i915/dp_mst: Enable MST DSC decompression for all streams Imre Deak
` (15 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
Enable passing through DSC streams to the sink in last branch devices.
v2:
- Fix the DPCD register address while setting/clearing the passthrough
flag.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0cdb4d176a8f9..8bc4faa142a62 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2968,6 +2968,24 @@ intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,
str_enable_disable(enable));
}
+static void
+intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
+ bool enable)
+{
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct drm_dp_aux *aux = connector->port ?
+ connector->port->passthrough_aux : NULL;
+
+ if (!aux)
+ return;
+
+ if (write_dsc_decompression_flag(aux,
+ DP_DSC_PASSTHROUGH_EN, enable) < 0)
+ drm_dbg_kms(&i915->drm,
+ "Failed to %s sink compression passthrough state\n",
+ str_enable_disable(enable));
+}
+
/**
* intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
* @state: atomic state
@@ -2994,7 +3012,7 @@ void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
!connector->dp.dsc_decompression_aux))
return;
- /* TODO: Enable passthrough in the MST last branch device if needed. */
+ intel_dp_sink_set_dsc_passthrough(connector, true);
intel_dp_sink_set_dsc_decompression(connector, true);
}
@@ -3022,7 +3040,7 @@ void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
return;
intel_dp_sink_set_dsc_decompression(connector, false);
- /* TODO: Disable passthrough in the MST last branch device if needed. */
+ intel_dp_sink_set_dsc_passthrough(connector, false);
}
static void
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [Intel-gfx] [PATCH v4 25/30] drm/i915/dp_mst: Enable MST DSC decompression for all streams
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (23 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 24/30] drm/i915/dp_mst: Enable DSC passthrough Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-31 8:47 ` Lisovskiy, Stanislav
2023-11-07 0:15 ` [Intel-gfx] [PATCH v5 " Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 26/30] drm/i915: Factor out function to clear pipe update flags Imre Deak
` (14 subsequent siblings)
39 siblings, 2 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
Enable DSC decompression for all streams. In particular atm if a sink is
connected to a last branch device that is downstream of the first branch
device connected to the source, decompression is not enabled for it.
Similarly it's not enabled if the sink supports this with the last
branch device passing through the compressed stream to it.
Enable DSC in the above cases as well. Since last branch devices may
handle the decompression for multiple ports, toggling DSC needs to be
refcounted, add this using the DSC AUX device as a reference.
v2:
- Fix refcounting, setting/clearing
connector->dp.dsc_decompression_enabled always as needed. (Stan)
- Make the refcounting more uniform for the SST vs. MST case.
- Add state checks for connector->dp.dsc_decompression_enabled and
connector crtc.
- Sanitize connector DSC decompression state during HW setup.
- s/use_count/ref_count/
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 72 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 19 ++---
.../drm/i915/display/intel_modeset_setup.c | 6 ++
4 files changed, 82 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 409dbf8a2a1cd..b2744a9b4678c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -626,6 +626,7 @@ struct intel_connector {
u8 fec_capability;
u8 dsc_hblank_expansion_quirk:1;
+ u8 dsc_decompression_enabled:1;
} dp;
/* Work struct to schedule a uevent on link train failure */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8bc4faa142a62..6d2fd068b8359 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1403,6 +1403,7 @@ static bool intel_dp_supports_dsc(const struct intel_connector *connector,
return false;
return intel_dsc_source_support(crtc_state) &&
+ connector->dp.dsc_decompression_aux &&
drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd);
}
@@ -2986,6 +2987,65 @@ intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
str_enable_disable(enable));
}
+static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state,
+ const struct intel_connector *connector,
+ bool for_get_ref)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct drm_connector *_connector_iter;
+ struct drm_connector_state *old_conn_state;
+ struct drm_connector_state *new_conn_state;
+ int ref_count = 0;
+ int i;
+
+ /*
+ * On SST the decompression AUX device won't be shared, each connector
+ * uses for this its own AUX targeting the sink device.
+ */
+ if (!connector->mst_port)
+ return connector->dp.dsc_decompression_enabled ? 1 : 0;
+
+ for_each_oldnew_connector_in_state(&state->base, _connector_iter,
+ old_conn_state, new_conn_state, i) {
+ const struct intel_connector *
+ connector_iter = to_intel_connector(_connector_iter);
+
+ if (connector_iter->mst_port != connector->mst_port)
+ continue;
+
+ if (!connector_iter->dp.dsc_decompression_enabled)
+ continue;
+
+ drm_WARN_ON(&i915->drm,
+ (for_get_ref && !new_conn_state->crtc) ||
+ (!for_get_ref && !old_conn_state->crtc));
+
+ if (connector_iter->dp.dsc_decompression_aux ==
+ connector->dp.dsc_decompression_aux)
+ ref_count++;
+ }
+
+ return ref_count;
+}
+
+static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state,
+ struct intel_connector *connector)
+{
+ bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;
+
+ connector->dp.dsc_decompression_enabled = true;
+
+ return ret;
+}
+
+static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state,
+ struct intel_connector *connector)
+{
+ connector->dp.dsc_decompression_enabled = false;
+
+ return intel_dp_dsc_aux_ref_count(state, connector, false) == 0;
+}
+
/**
* intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
* @state: atomic state
@@ -3009,7 +3069,11 @@ void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
return;
if (drm_WARN_ON(&i915->drm,
- !connector->dp.dsc_decompression_aux))
+ !connector->dp.dsc_decompression_aux ||
+ connector->dp.dsc_decompression_enabled))
+ return;
+
+ if (!intel_dp_dsc_aux_get_ref(state, connector))
return;
intel_dp_sink_set_dsc_passthrough(connector, true);
@@ -3036,7 +3100,11 @@ void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
return;
if (drm_WARN_ON(&i915->drm,
- !connector->dp.dsc_decompression_aux))
+ !connector->dp.dsc_decompression_aux ||
+ !connector->dp.dsc_decompression_enabled))
+ return;
+
+ if (!intel_dp_dsc_aux_put_ref(state, connector))
return;
intel_dp_sink_set_dsc_decompression(connector, false);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 355a573c97930..9037e11ec6e0d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -748,12 +748,7 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state,
intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
- if (intel_dp->active_mst_links == 1) /* last stream ? */
- /*
- * TODO: disable decompression for all streams/in any MST ports, not
- * only in the first downstream branch device.
- */
- intel_dp_sink_disable_decompression(state, connector, old_crtc_state);
+ intel_dp_sink_disable_decompression(state, connector, old_crtc_state);
}
static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
@@ -908,15 +903,11 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
- if (first_mst_stream) {
- /*
- * TODO: enable decompression for all streams/in any MST ports, not
- * only in the first downstream branch device.
- */
- intel_dp_sink_enable_decompression(state, connector, pipe_config);
+ intel_dp_sink_enable_decompression(state, connector, pipe_config);
+
+ if (first_mst_stream)
dig_port->base.pre_enable(state, &dig_port->base,
pipe_config, NULL);
- }
intel_dp->active_mst_links++;
@@ -1362,7 +1353,7 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
* At the moment the driver only supports enabling this globally in the
* first downstream MST branch, via intel_dp's (root port) AUX.
*/
- intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
+ intel_connector->dp.dsc_decompression_aux = drm_dp_mst_dsc_aux_for_port(port);
intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);
intel_connector->dp.dsc_hblank_expansion_quirk =
detect_dsc_hblank_expansion_quirk(intel_connector);
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index b8f43efb0ab5a..94eece7f63be3 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -318,6 +318,12 @@ static void intel_modeset_update_connector_atomic_state(struct drm_i915_private
const struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
+ if (crtc_state->dsc.compression_enable) {
+ drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux);
+ connector->dp.dsc_decompression_enabled = true;
+ } else {
+ connector->dp.dsc_decompression_enabled = false;
+ }
conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v4 25/30] drm/i915/dp_mst: Enable MST DSC decompression for all streams
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 25/30] drm/i915/dp_mst: Enable MST DSC decompression for all streams Imre Deak
@ 2023-10-31 8:47 ` Lisovskiy, Stanislav
2023-11-07 0:15 ` [Intel-gfx] [PATCH v5 " Imre Deak
1 sibling, 0 replies; 94+ messages in thread
From: Lisovskiy, Stanislav @ 2023-10-31 8:47 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Mon, Oct 30, 2023 at 05:58:38PM +0200, Imre Deak wrote:
> Enable DSC decompression for all streams. In particular atm if a sink is
> connected to a last branch device that is downstream of the first branch
> device connected to the source, decompression is not enabled for it.
> Similarly it's not enabled if the sink supports this with the last
> branch device passing through the compressed stream to it.
>
> Enable DSC in the above cases as well. Since last branch devices may
> handle the decompression for multiple ports, toggling DSC needs to be
> refcounted, add this using the DSC AUX device as a reference.
>
> v2:
>
> - Fix refcounting, setting/clearing
> connector->dp.dsc_decompression_enabled always as needed. (Stan)
> - Make the refcounting more uniform for the SST vs. MST case.
> - Add state checks for connector->dp.dsc_decompression_enabled and
> connector crtc.
> - Sanitize connector DSC decompression state during HW setup.
> - s/use_count/ref_count/
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 72 ++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 19 ++---
> .../drm/i915/display/intel_modeset_setup.c | 6 ++
> 4 files changed, 82 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 409dbf8a2a1cd..b2744a9b4678c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -626,6 +626,7 @@ struct intel_connector {
> u8 fec_capability;
>
> u8 dsc_hblank_expansion_quirk:1;
> + u8 dsc_decompression_enabled:1;
> } dp;
>
> /* Work struct to schedule a uevent on link train failure */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8bc4faa142a62..6d2fd068b8359 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1403,6 +1403,7 @@ static bool intel_dp_supports_dsc(const struct intel_connector *connector,
> return false;
>
> return intel_dsc_source_support(crtc_state) &&
> + connector->dp.dsc_decompression_aux &&
> drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd);
> }
>
> @@ -2986,6 +2987,65 @@ intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
> str_enable_disable(enable));
> }
>
> +static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state,
> + const struct intel_connector *connector,
> + bool for_get_ref)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct drm_connector *_connector_iter;
> + struct drm_connector_state *old_conn_state;
> + struct drm_connector_state *new_conn_state;
> + int ref_count = 0;
> + int i;
> +
> + /*
> + * On SST the decompression AUX device won't be shared, each connector
> + * uses for this its own AUX targeting the sink device.
> + */
> + if (!connector->mst_port)
> + return connector->dp.dsc_decompression_enabled ? 1 : 0;
> +
> + for_each_oldnew_connector_in_state(&state->base, _connector_iter,
> + old_conn_state, new_conn_state, i) {
> + const struct intel_connector *
> + connector_iter = to_intel_connector(_connector_iter);
> +
> + if (connector_iter->mst_port != connector->mst_port)
> + continue;
> +
> + if (!connector_iter->dp.dsc_decompression_enabled)
> + continue;
> +
> + drm_WARN_ON(&i915->drm,
> + (for_get_ref && !new_conn_state->crtc) ||
> + (!for_get_ref && !old_conn_state->crtc));
> +
> + if (connector_iter->dp.dsc_decompression_aux ==
> + connector->dp.dsc_decompression_aux)
> + ref_count++;
> + }
> +
> + return ref_count;
> +}
> +
> +static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state,
> + struct intel_connector *connector)
> +{
> + bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;
> +
> + connector->dp.dsc_decompression_enabled = true;
> +
> + return ret;
> +}
> +
> +static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state,
> + struct intel_connector *connector)
> +{
> + connector->dp.dsc_decompression_enabled = false;
> +
> + return intel_dp_dsc_aux_ref_count(state, connector, false) == 0;
> +}
> +
> /**
> * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
> * @state: atomic state
> @@ -3009,7 +3069,11 @@ void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
> return;
>
> if (drm_WARN_ON(&i915->drm,
> - !connector->dp.dsc_decompression_aux))
> + !connector->dp.dsc_decompression_aux ||
> + connector->dp.dsc_decompression_enabled))
> + return;
> +
> + if (!intel_dp_dsc_aux_get_ref(state, connector))
> return;
>
> intel_dp_sink_set_dsc_passthrough(connector, true);
> @@ -3036,7 +3100,11 @@ void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
> return;
>
> if (drm_WARN_ON(&i915->drm,
> - !connector->dp.dsc_decompression_aux))
> + !connector->dp.dsc_decompression_aux ||
> + !connector->dp.dsc_decompression_enabled))
> + return;
> +
> + if (!intel_dp_dsc_aux_put_ref(state, connector))
> return;
>
> intel_dp_sink_set_dsc_decompression(connector, false);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 355a573c97930..9037e11ec6e0d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -748,12 +748,7 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state,
>
> intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
>
> - if (intel_dp->active_mst_links == 1) /* last stream ? */
> - /*
> - * TODO: disable decompression for all streams/in any MST ports, not
> - * only in the first downstream branch device.
> - */
> - intel_dp_sink_disable_decompression(state, connector, old_crtc_state);
> + intel_dp_sink_disable_decompression(state, connector, old_crtc_state);
> }
>
> static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
> @@ -908,15 +903,11 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
>
> drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
>
> - if (first_mst_stream) {
> - /*
> - * TODO: enable decompression for all streams/in any MST ports, not
> - * only in the first downstream branch device.
> - */
> - intel_dp_sink_enable_decompression(state, connector, pipe_config);
> + intel_dp_sink_enable_decompression(state, connector, pipe_config);
> +
> + if (first_mst_stream)
> dig_port->base.pre_enable(state, &dig_port->base,
> pipe_config, NULL);
> - }
>
> intel_dp->active_mst_links++;
>
> @@ -1362,7 +1353,7 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
> * At the moment the driver only supports enabling this globally in the
> * first downstream MST branch, via intel_dp's (root port) AUX.
> */
> - intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
> + intel_connector->dp.dsc_decompression_aux = drm_dp_mst_dsc_aux_for_port(port);
> intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);
> intel_connector->dp.dsc_hblank_expansion_quirk =
> detect_dsc_hblank_expansion_quirk(intel_connector);
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index b8f43efb0ab5a..94eece7f63be3 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -318,6 +318,12 @@ static void intel_modeset_update_connector_atomic_state(struct drm_i915_private
> const struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
>
> + if (crtc_state->dsc.compression_enable) {
> + drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux);
> + connector->dp.dsc_decompression_enabled = true;
> + } else {
> + connector->dp.dsc_decompression_enabled = false;
> + }
> conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
> }
> }
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 94+ messages in thread* [Intel-gfx] [PATCH v5 25/30] drm/i915/dp_mst: Enable MST DSC decompression for all streams
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 25/30] drm/i915/dp_mst: Enable MST DSC decompression for all streams Imre Deak
2023-10-31 8:47 ` Lisovskiy, Stanislav
@ 2023-11-07 0:15 ` Imre Deak
2023-11-08 8:09 ` Lisovskiy, Stanislav
2024-02-02 17:48 ` [v5, " Drew Davenport
1 sibling, 2 replies; 94+ messages in thread
From: Imre Deak @ 2023-11-07 0:15 UTC (permalink / raw)
To: intel-gfx
Enable DSC decompression for all streams. In particular atm if a sink is
connected to a last branch device that is downstream of the first branch
device connected to the source, decompression is not enabled for it.
Similarly it's not enabled if the sink supports this with the last
branch device passing through the compressed stream to it.
Enable DSC in the above cases as well. Since last branch devices may
handle the decompression for multiple ports, toggling DSC needs to be
refcounted, add this using the DSC AUX device as a reference.
v2:
- Fix refcounting, setting/clearing
connector->dp.dsc_decompression_enabled always as needed. (Stan)
- Make the refcounting more uniform for the SST vs. MST case.
- Add state checks for connector->dp.dsc_decompression_enabled and
connector crtc.
- Sanitize connector DSC decompression state during HW setup.
- s/use_count/ref_count/
v3:
- Remove stale TODO: comment to set the actual decompression_aux.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 72 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 24 ++-----
.../drm/i915/display/intel_modeset_setup.c | 6 ++
4 files changed, 82 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6c2f18ef543e4..0a5508c90e8bc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -626,6 +626,7 @@ struct intel_connector {
u8 fec_capability;
u8 dsc_hblank_expansion_quirk:1;
+ u8 dsc_decompression_enabled:1;
} dp;
/* Work struct to schedule a uevent on link train failure */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index bea0c03b94835..3fee371529f17 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1403,6 +1403,7 @@ static bool intel_dp_supports_dsc(const struct intel_connector *connector,
return false;
return intel_dsc_source_support(crtc_state) &&
+ connector->dp.dsc_decompression_aux &&
drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd);
}
@@ -2986,6 +2987,65 @@ intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
str_enable_disable(enable));
}
+static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state,
+ const struct intel_connector *connector,
+ bool for_get_ref)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct drm_connector *_connector_iter;
+ struct drm_connector_state *old_conn_state;
+ struct drm_connector_state *new_conn_state;
+ int ref_count = 0;
+ int i;
+
+ /*
+ * On SST the decompression AUX device won't be shared, each connector
+ * uses for this its own AUX targeting the sink device.
+ */
+ if (!connector->mst_port)
+ return connector->dp.dsc_decompression_enabled ? 1 : 0;
+
+ for_each_oldnew_connector_in_state(&state->base, _connector_iter,
+ old_conn_state, new_conn_state, i) {
+ const struct intel_connector *
+ connector_iter = to_intel_connector(_connector_iter);
+
+ if (connector_iter->mst_port != connector->mst_port)
+ continue;
+
+ if (!connector_iter->dp.dsc_decompression_enabled)
+ continue;
+
+ drm_WARN_ON(&i915->drm,
+ (for_get_ref && !new_conn_state->crtc) ||
+ (!for_get_ref && !old_conn_state->crtc));
+
+ if (connector_iter->dp.dsc_decompression_aux ==
+ connector->dp.dsc_decompression_aux)
+ ref_count++;
+ }
+
+ return ref_count;
+}
+
+static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state,
+ struct intel_connector *connector)
+{
+ bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;
+
+ connector->dp.dsc_decompression_enabled = true;
+
+ return ret;
+}
+
+static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state,
+ struct intel_connector *connector)
+{
+ connector->dp.dsc_decompression_enabled = false;
+
+ return intel_dp_dsc_aux_ref_count(state, connector, false) == 0;
+}
+
/**
* intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
* @state: atomic state
@@ -3009,7 +3069,11 @@ void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
return;
if (drm_WARN_ON(&i915->drm,
- !connector->dp.dsc_decompression_aux))
+ !connector->dp.dsc_decompression_aux ||
+ connector->dp.dsc_decompression_enabled))
+ return;
+
+ if (!intel_dp_dsc_aux_get_ref(state, connector))
return;
intel_dp_sink_set_dsc_passthrough(connector, true);
@@ -3036,7 +3100,11 @@ void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
return;
if (drm_WARN_ON(&i915->drm,
- !connector->dp.dsc_decompression_aux))
+ !connector->dp.dsc_decompression_aux ||
+ !connector->dp.dsc_decompression_enabled))
+ return;
+
+ if (!intel_dp_dsc_aux_put_ref(state, connector))
return;
intel_dp_sink_set_dsc_decompression(connector, false);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index bc992e77ffc7a..b3d952bbb3cf0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -777,12 +777,7 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state,
intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
- if (intel_dp->active_mst_links == 1) /* last stream ? */
- /*
- * TODO: disable decompression for all streams/in any MST ports, not
- * only in the first downstream branch device.
- */
- intel_dp_sink_disable_decompression(state, connector, old_crtc_state);
+ intel_dp_sink_disable_decompression(state, connector, old_crtc_state);
}
static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
@@ -939,15 +934,11 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
- if (first_mst_stream) {
- /*
- * TODO: enable decompression for all streams/in any MST ports, not
- * only in the first downstream branch device.
- */
- intel_dp_sink_enable_decompression(state, connector, pipe_config);
+ intel_dp_sink_enable_decompression(state, connector, pipe_config);
+
+ if (first_mst_stream)
dig_port->base.pre_enable(state, &dig_port->base,
pipe_config, NULL);
- }
intel_dp->active_mst_links++;
@@ -1394,12 +1385,7 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
intel_connector->port = port;
drm_dp_mst_get_port_malloc(port);
- /*
- * TODO: set the AUX for the actual MST port decompressing the stream.
- * At the moment the driver only supports enabling this globally in the
- * first downstream MST branch, via intel_dp's (root port) AUX.
- */
- intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
+ intel_connector->dp.dsc_decompression_aux = drm_dp_mst_dsc_aux_for_port(port);
intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);
intel_connector->dp.dsc_hblank_expansion_quirk =
detect_dsc_hblank_expansion_quirk(intel_connector);
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index b8f43efb0ab5a..94eece7f63be3 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -318,6 +318,12 @@ static void intel_modeset_update_connector_atomic_state(struct drm_i915_private
const struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
+ if (crtc_state->dsc.compression_enable) {
+ drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux);
+ connector->dp.dsc_decompression_enabled = true;
+ } else {
+ connector->dp.dsc_decompression_enabled = false;
+ }
conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v5 25/30] drm/i915/dp_mst: Enable MST DSC decompression for all streams
2023-11-07 0:15 ` [Intel-gfx] [PATCH v5 " Imre Deak
@ 2023-11-08 8:09 ` Lisovskiy, Stanislav
2024-02-02 17:48 ` [v5, " Drew Davenport
1 sibling, 0 replies; 94+ messages in thread
From: Lisovskiy, Stanislav @ 2023-11-08 8:09 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Tue, Nov 07, 2023 at 02:15:03AM +0200, Imre Deak wrote:
> Enable DSC decompression for all streams. In particular atm if a sink is
> connected to a last branch device that is downstream of the first branch
> device connected to the source, decompression is not enabled for it.
> Similarly it's not enabled if the sink supports this with the last
> branch device passing through the compressed stream to it.
>
> Enable DSC in the above cases as well. Since last branch devices may
> handle the decompression for multiple ports, toggling DSC needs to be
> refcounted, add this using the DSC AUX device as a reference.
>
> v2:
> - Fix refcounting, setting/clearing
> connector->dp.dsc_decompression_enabled always as needed. (Stan)
> - Make the refcounting more uniform for the SST vs. MST case.
> - Add state checks for connector->dp.dsc_decompression_enabled and
> connector crtc.
> - Sanitize connector DSC decompression state during HW setup.
> - s/use_count/ref_count/
> v3:
> - Remove stale TODO: comment to set the actual decompression_aux.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 72 ++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 24 ++-----
> .../drm/i915/display/intel_modeset_setup.c | 6 ++
> 4 files changed, 82 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 6c2f18ef543e4..0a5508c90e8bc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -626,6 +626,7 @@ struct intel_connector {
> u8 fec_capability;
>
> u8 dsc_hblank_expansion_quirk:1;
> + u8 dsc_decompression_enabled:1;
> } dp;
>
> /* Work struct to schedule a uevent on link train failure */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index bea0c03b94835..3fee371529f17 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1403,6 +1403,7 @@ static bool intel_dp_supports_dsc(const struct intel_connector *connector,
> return false;
>
> return intel_dsc_source_support(crtc_state) &&
> + connector->dp.dsc_decompression_aux &&
> drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd);
> }
>
> @@ -2986,6 +2987,65 @@ intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
> str_enable_disable(enable));
> }
>
> +static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state,
> + const struct intel_connector *connector,
> + bool for_get_ref)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct drm_connector *_connector_iter;
> + struct drm_connector_state *old_conn_state;
> + struct drm_connector_state *new_conn_state;
> + int ref_count = 0;
> + int i;
> +
> + /*
> + * On SST the decompression AUX device won't be shared, each connector
> + * uses for this its own AUX targeting the sink device.
> + */
> + if (!connector->mst_port)
> + return connector->dp.dsc_decompression_enabled ? 1 : 0;
> +
> + for_each_oldnew_connector_in_state(&state->base, _connector_iter,
> + old_conn_state, new_conn_state, i) {
> + const struct intel_connector *
> + connector_iter = to_intel_connector(_connector_iter);
> +
> + if (connector_iter->mst_port != connector->mst_port)
> + continue;
> +
> + if (!connector_iter->dp.dsc_decompression_enabled)
> + continue;
> +
> + drm_WARN_ON(&i915->drm,
> + (for_get_ref && !new_conn_state->crtc) ||
> + (!for_get_ref && !old_conn_state->crtc));
> +
> + if (connector_iter->dp.dsc_decompression_aux ==
> + connector->dp.dsc_decompression_aux)
> + ref_count++;
> + }
> +
> + return ref_count;
> +}
> +
> +static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state,
> + struct intel_connector *connector)
> +{
> + bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;
> +
> + connector->dp.dsc_decompression_enabled = true;
> +
> + return ret;
> +}
> +
> +static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state,
> + struct intel_connector *connector)
> +{
> + connector->dp.dsc_decompression_enabled = false;
> +
> + return intel_dp_dsc_aux_ref_count(state, connector, false) == 0;
> +}
> +
> /**
> * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
> * @state: atomic state
> @@ -3009,7 +3069,11 @@ void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
> return;
>
> if (drm_WARN_ON(&i915->drm,
> - !connector->dp.dsc_decompression_aux))
> + !connector->dp.dsc_decompression_aux ||
> + connector->dp.dsc_decompression_enabled))
> + return;
> +
> + if (!intel_dp_dsc_aux_get_ref(state, connector))
> return;
>
> intel_dp_sink_set_dsc_passthrough(connector, true);
> @@ -3036,7 +3100,11 @@ void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
> return;
>
> if (drm_WARN_ON(&i915->drm,
> - !connector->dp.dsc_decompression_aux))
> + !connector->dp.dsc_decompression_aux ||
> + !connector->dp.dsc_decompression_enabled))
> + return;
> +
> + if (!intel_dp_dsc_aux_put_ref(state, connector))
> return;
>
> intel_dp_sink_set_dsc_decompression(connector, false);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index bc992e77ffc7a..b3d952bbb3cf0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -777,12 +777,7 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state,
>
> intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
>
> - if (intel_dp->active_mst_links == 1) /* last stream ? */
> - /*
> - * TODO: disable decompression for all streams/in any MST ports, not
> - * only in the first downstream branch device.
> - */
> - intel_dp_sink_disable_decompression(state, connector, old_crtc_state);
> + intel_dp_sink_disable_decompression(state, connector, old_crtc_state);
> }
>
> static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
> @@ -939,15 +934,11 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
>
> drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
>
> - if (first_mst_stream) {
> - /*
> - * TODO: enable decompression for all streams/in any MST ports, not
> - * only in the first downstream branch device.
> - */
> - intel_dp_sink_enable_decompression(state, connector, pipe_config);
> + intel_dp_sink_enable_decompression(state, connector, pipe_config);
> +
> + if (first_mst_stream)
> dig_port->base.pre_enable(state, &dig_port->base,
> pipe_config, NULL);
> - }
>
> intel_dp->active_mst_links++;
>
> @@ -1394,12 +1385,7 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
> intel_connector->port = port;
> drm_dp_mst_get_port_malloc(port);
>
> - /*
> - * TODO: set the AUX for the actual MST port decompressing the stream.
> - * At the moment the driver only supports enabling this globally in the
> - * first downstream MST branch, via intel_dp's (root port) AUX.
> - */
> - intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
> + intel_connector->dp.dsc_decompression_aux = drm_dp_mst_dsc_aux_for_port(port);
> intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);
> intel_connector->dp.dsc_hblank_expansion_quirk =
> detect_dsc_hblank_expansion_quirk(intel_connector);
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index b8f43efb0ab5a..94eece7f63be3 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -318,6 +318,12 @@ static void intel_modeset_update_connector_atomic_state(struct drm_i915_private
> const struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
>
> + if (crtc_state->dsc.compression_enable) {
> + drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux);
> + connector->dp.dsc_decompression_enabled = true;
> + } else {
> + connector->dp.dsc_decompression_enabled = false;
> + }
> conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
> }
> }
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [v5, 25/30] drm/i915/dp_mst: Enable MST DSC decompression for all streams
2023-11-07 0:15 ` [Intel-gfx] [PATCH v5 " Imre Deak
2023-11-08 8:09 ` Lisovskiy, Stanislav
@ 2024-02-02 17:48 ` Drew Davenport
2024-02-05 13:38 ` Imre Deak
1 sibling, 1 reply; 94+ messages in thread
From: Drew Davenport @ 2024-02-02 17:48 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Tue, Nov 07, 2023 at 02:15:03AM +0200, Imre Deak wrote:
> Enable DSC decompression for all streams. In particular atm if a sink is
> connected to a last branch device that is downstream of the first branch
> device connected to the source, decompression is not enabled for it.
> Similarly it's not enabled if the sink supports this with the last
> branch device passing through the compressed stream to it.
>
> Enable DSC in the above cases as well. Since last branch devices may
> handle the decompression for multiple ports, toggling DSC needs to be
> refcounted, add this using the DSC AUX device as a reference.
>
> v2:
> - Fix refcounting, setting/clearing
> connector->dp.dsc_decompression_enabled always as needed. (Stan)
> - Make the refcounting more uniform for the SST vs. MST case.
> - Add state checks for connector->dp.dsc_decompression_enabled and
> connector crtc.
> - Sanitize connector DSC decompression state during HW setup.
> - s/use_count/ref_count/
> v3:
> - Remove stale TODO: comment to set the actual decompression_aux.
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 72 ++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 24 ++-----
> .../drm/i915/display/intel_modeset_setup.c | 6 ++
> 4 files changed, 82 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 6c2f18ef543e4..0a5508c90e8bc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -626,6 +626,7 @@ struct intel_connector {
> u8 fec_capability;
>
> u8 dsc_hblank_expansion_quirk:1;
> + u8 dsc_decompression_enabled:1;
> } dp;
>
> /* Work struct to schedule a uevent on link train failure */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index bea0c03b94835..3fee371529f17 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1403,6 +1403,7 @@ static bool intel_dp_supports_dsc(const struct intel_connector *connector,
> return false;
>
> return intel_dsc_source_support(crtc_state) &&
> + connector->dp.dsc_decompression_aux &&
> drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd);
> }
>
> @@ -2986,6 +2987,65 @@ intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
> str_enable_disable(enable));
> }
>
> +static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state,
> + const struct intel_connector *connector,
> + bool for_get_ref)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct drm_connector *_connector_iter;
> + struct drm_connector_state *old_conn_state;
> + struct drm_connector_state *new_conn_state;
> + int ref_count = 0;
> + int i;
> +
> + /*
> + * On SST the decompression AUX device won't be shared, each connector
> + * uses for this its own AUX targeting the sink device.
> + */
> + if (!connector->mst_port)
> + return connector->dp.dsc_decompression_enabled ? 1 : 0;
> +
> + for_each_oldnew_connector_in_state(&state->base, _connector_iter,
> + old_conn_state, new_conn_state, i) {
> + const struct intel_connector *
> + connector_iter = to_intel_connector(_connector_iter);
> +
> + if (connector_iter->mst_port != connector->mst_port)
> + continue;
> +
> + if (!connector_iter->dp.dsc_decompression_enabled)
> + continue;
> +
> + drm_WARN_ON(&i915->drm,
> + (for_get_ref && !new_conn_state->crtc) ||
> + (!for_get_ref && !old_conn_state->crtc));
> +
> + if (connector_iter->dp.dsc_decompression_aux ==
> + connector->dp.dsc_decompression_aux)
> + ref_count++;
> + }
> +
> + return ref_count;
> +}
> +
> +static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state,
> + struct intel_connector *connector)
> +{
> + bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;
> +
> + connector->dp.dsc_decompression_enabled = true;
> +
> + return ret;
> +}
> +
> +static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state,
> + struct intel_connector *connector)
> +{
> + connector->dp.dsc_decompression_enabled = false;
> +
> + return intel_dp_dsc_aux_ref_count(state, connector, false) == 0;
> +}
> +
> /**
> * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
> * @state: atomic state
> @@ -3009,7 +3069,11 @@ void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
> return;
>
> if (drm_WARN_ON(&i915->drm,
> - !connector->dp.dsc_decompression_aux))
> + !connector->dp.dsc_decompression_aux ||
> + connector->dp.dsc_decompression_enabled))
> + return;
> +
> + if (!intel_dp_dsc_aux_get_ref(state, connector))
> return;
>
> intel_dp_sink_set_dsc_passthrough(connector, true);
> @@ -3036,7 +3100,11 @@ void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
> return;
>
> if (drm_WARN_ON(&i915->drm,
> - !connector->dp.dsc_decompression_aux))
> + !connector->dp.dsc_decompression_aux ||
> + !connector->dp.dsc_decompression_enabled))
> + return;
> +
> + if (!intel_dp_dsc_aux_put_ref(state, connector))
> return;
>
> intel_dp_sink_set_dsc_decompression(connector, false);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index bc992e77ffc7a..b3d952bbb3cf0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -777,12 +777,7 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state,
>
> intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
>
> - if (intel_dp->active_mst_links == 1) /* last stream ? */
> - /*
> - * TODO: disable decompression for all streams/in any MST ports, not
> - * only in the first downstream branch device.
> - */
> - intel_dp_sink_disable_decompression(state, connector, old_crtc_state);
> + intel_dp_sink_disable_decompression(state, connector, old_crtc_state);
> }
>
> static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
> @@ -939,15 +934,11 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
>
> drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
>
> - if (first_mst_stream) {
> - /*
> - * TODO: enable decompression for all streams/in any MST ports, not
> - * only in the first downstream branch device.
> - */
> - intel_dp_sink_enable_decompression(state, connector, pipe_config);
> + intel_dp_sink_enable_decompression(state, connector, pipe_config);
> +
> + if (first_mst_stream)
> dig_port->base.pre_enable(state, &dig_port->base,
> pipe_config, NULL);
> - }
>
> intel_dp->active_mst_links++;
>
> @@ -1394,12 +1385,7 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
> intel_connector->port = port;
> drm_dp_mst_get_port_malloc(port);
>
> - /*
> - * TODO: set the AUX for the actual MST port decompressing the stream.
> - * At the moment the driver only supports enabling this globally in the
> - * first downstream MST branch, via intel_dp's (root port) AUX.
> - */
> - intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
> + intel_connector->dp.dsc_decompression_aux = drm_dp_mst_dsc_aux_for_port(port);
> intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);
> intel_connector->dp.dsc_hblank_expansion_quirk =
> detect_dsc_hblank_expansion_quirk(intel_connector);
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index b8f43efb0ab5a..94eece7f63be3 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -318,6 +318,12 @@ static void intel_modeset_update_connector_atomic_state(struct drm_i915_private
> const struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
>
> + if (crtc_state->dsc.compression_enable) {
> + drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux);
I'm running into this warning on a JSL device that uses a MIPI panel.
Looking at gen11_dsi_dsc_compute_config in icl_dsi.c, I don't see any
code paths where dsc_compression_aux would be set.
Should there be a check here for the encoder type to avoid setting
dsc_decompression_enabled for DSI encoders?
> + connector->dp.dsc_decompression_enabled = true;
> + } else {
> + connector->dp.dsc_decompression_enabled = false;
> + }
> conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
> }
> }
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [v5, 25/30] drm/i915/dp_mst: Enable MST DSC decompression for all streams
2024-02-02 17:48 ` [v5, " Drew Davenport
@ 2024-02-05 13:38 ` Imre Deak
0 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2024-02-05 13:38 UTC (permalink / raw)
To: Drew Davenport; +Cc: intel-gfx, I915-ci-infra
On Fri, Feb 02, 2024 at 10:48:32AM -0700, Drew Davenport wrote:
> [...]
> > diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > index b8f43efb0ab5a..94eece7f63be3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > @@ -318,6 +318,12 @@ static void intel_modeset_update_connector_atomic_state(struct drm_i915_private
> > const struct intel_crtc_state *crtc_state =
> > to_intel_crtc_state(crtc->base.state);
> >
> > + if (crtc_state->dsc.compression_enable) {
> > + drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux);
>
> I'm running into this warning on a JSL device that uses a MIPI panel.
>
> Looking at gen11_dsi_dsc_compute_config in icl_dsi.c, I don't see any
> code paths where dsc_compression_aux would be set.
>
> Should there be a check here for the encoder type to avoid setting
> dsc_decompression_enabled for DSI encoders?
Yes thanks for the report, this state should get updated only for DP
connectors, I missed this when adding the above. I think it's better to
do this in a connector specific hook as in:
https://lore.kernel.org/intel-gfx/20240205132631.1588577-1-imre.deak@intel.com
Also I wonder if we could add ICL/JSL platforms with DSI (DSC) output to
CI, CC'd the CI team.
> > + connector->dp.dsc_decompression_enabled = true;
> > + } else {
> > + connector->dp.dsc_decompression_enabled = false;
> > + }
> > conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
> > }
> > }
^ permalink raw reply [flat|nested] 94+ messages in thread
* [Intel-gfx] [PATCH v4 26/30] drm/i915: Factor out function to clear pipe update flags
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (24 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 25/30] drm/i915/dp_mst: Enable MST DSC decompression for all streams Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-11-01 10:17 ` Ville Syrjälä
2023-11-07 0:15 ` [Intel-gfx] [PATCH v5 " Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 27/30] drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires it Imre Deak
` (13 subsequent siblings)
39 siblings, 2 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
Factor out a helper to clear the pipe update flags, used by a follow-up
patch to modeset an MST topology.
v2:
- Move the intel_crtc_needs_modeset() check to the callers. (Ville)
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 52 ++++++++++----------
1 file changed, 27 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1133c2893bb38..d27afda0cfaa6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5551,6 +5551,14 @@ int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
return 0;
}
+static void
+clear_pipe_update_flags_on_modeset_crtc(struct intel_crtc_state *crtc_state)
+{
+ crtc_state->update_pipe = false;
+ crtc_state->update_m_n = false;
+ crtc_state->update_lrr = false;
+}
+
/**
* intel_modeset_all_pipes_late - force a full modeset on all pipes
* @state: intel atomic state
@@ -5584,9 +5592,8 @@ int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
if (ret)
return ret;
- crtc_state->update_pipe = false;
- crtc_state->update_m_n = false;
- crtc_state->update_lrr = false;
+ clear_pipe_update_flags_on_modeset_crtc(crtc_state);
+
crtc_state->update_planes |= crtc_state->active_planes;
crtc_state->async_flip_planes = 0;
crtc_state->do_async_flip = false;
@@ -5699,13 +5706,14 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
else
new_crtc_state->uapi.mode_changed = false;
- if (intel_crtc_needs_modeset(new_crtc_state) ||
- intel_compare_link_m_n(&old_crtc_state->dp_m_n,
+ if (intel_crtc_needs_modeset(new_crtc_state))
+ clear_pipe_update_flags_on_modeset_crtc(new_crtc_state);
+
+ if (intel_compare_link_m_n(&old_crtc_state->dp_m_n,
&new_crtc_state->dp_m_n))
new_crtc_state->update_m_n = false;
- if (intel_crtc_needs_modeset(new_crtc_state) ||
- (old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
+ if ((old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
new_crtc_state->update_lrr = false;
@@ -6484,12 +6492,9 @@ int intel_atomic_check(struct drm_device *dev,
if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
enum transcoder master = new_crtc_state->mst_master_transcoder;
- if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
- new_crtc_state->uapi.mode_changed = true;
- new_crtc_state->update_pipe = false;
- new_crtc_state->update_m_n = false;
- new_crtc_state->update_lrr = false;
- }
+ if (intel_cpu_transcoders_need_modeset(state, BIT(master)))
+ intel_modeset_pipes_in_mask_early(state, "MST master transcoder",
+ BIT(crtc->pipe));
}
if (is_trans_port_sync_mode(new_crtc_state)) {
@@ -6498,22 +6503,19 @@ int intel_atomic_check(struct drm_device *dev,
if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
trans |= BIT(new_crtc_state->master_transcoder);
- if (intel_cpu_transcoders_need_modeset(state, trans)) {
- new_crtc_state->uapi.mode_changed = true;
- new_crtc_state->update_pipe = false;
- new_crtc_state->update_m_n = false;
- new_crtc_state->update_lrr = false;
- }
+ if (intel_cpu_transcoders_need_modeset(state, trans))
+ intel_modeset_pipes_in_mask_early(state, "port sync",
+ BIT(crtc->pipe));
}
if (new_crtc_state->bigjoiner_pipes) {
- if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) {
- new_crtc_state->uapi.mode_changed = true;
- new_crtc_state->update_pipe = false;
- new_crtc_state->update_m_n = false;
- new_crtc_state->update_lrr = false;
- }
+ if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes))
+ intel_modeset_pipes_in_mask_early(state, "bigjoiner pipes",
+ BIT(crtc->pipe));
}
+
+ if (intel_crtc_needs_modeset(new_crtc_state))
+ clear_pipe_update_flags_on_modeset_crtc(new_crtc_state);
}
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v4 26/30] drm/i915: Factor out function to clear pipe update flags
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 26/30] drm/i915: Factor out function to clear pipe update flags Imre Deak
@ 2023-11-01 10:17 ` Ville Syrjälä
2023-11-01 11:38 ` Imre Deak
2023-11-07 0:15 ` [Intel-gfx] [PATCH v5 " Imre Deak
1 sibling, 1 reply; 94+ messages in thread
From: Ville Syrjälä @ 2023-11-01 10:17 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Mon, Oct 30, 2023 at 05:58:39PM +0200, Imre Deak wrote:
> Factor out a helper to clear the pipe update flags, used by a follow-up
> patch to modeset an MST topology.
>
> v2:
> - Move the intel_crtc_needs_modeset() check to the callers. (Ville)
>
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 52 ++++++++++----------
> 1 file changed, 27 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 1133c2893bb38..d27afda0cfaa6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5551,6 +5551,14 @@ int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
> return 0;
> }
>
> +static void
> +clear_pipe_update_flags_on_modeset_crtc(struct intel_crtc_state *crtc_state)
The 'on_modeset_crtc()' part doesn't make sense anymore.
Hmm. Another idea would be to move the mode_changed=true assignment
here and call this something like intel_crtc_flag_fmodeset(), which
might be a bit more descriptive.
> +{
> + crtc_state->update_pipe = false;
> + crtc_state->update_m_n = false;
> + crtc_state->update_lrr = false;
> +}
> +
> /**
> * intel_modeset_all_pipes_late - force a full modeset on all pipes
> * @state: intel atomic state
> @@ -5584,9 +5592,8 @@ int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
> if (ret)
> return ret;
>
> - crtc_state->update_pipe = false;
> - crtc_state->update_m_n = false;
> - crtc_state->update_lrr = false;
> + clear_pipe_update_flags_on_modeset_crtc(crtc_state);
> +
> crtc_state->update_planes |= crtc_state->active_planes;
> crtc_state->async_flip_planes = 0;
> crtc_state->do_async_flip = false;
> @@ -5699,13 +5706,14 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
> else
> new_crtc_state->uapi.mode_changed = false;
>
> - if (intel_crtc_needs_modeset(new_crtc_state) ||
> - intel_compare_link_m_n(&old_crtc_state->dp_m_n,
> + if (intel_crtc_needs_modeset(new_crtc_state))
> + clear_pipe_update_flags_on_modeset_crtc(new_crtc_state);
> +
> + if (intel_compare_link_m_n(&old_crtc_state->dp_m_n,
> &new_crtc_state->dp_m_n))
> new_crtc_state->update_m_n = false;
>
> - if (intel_crtc_needs_modeset(new_crtc_state) ||
> - (old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
> + if ((old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
> old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
> new_crtc_state->update_lrr = false;
>
> @@ -6484,12 +6492,9 @@ int intel_atomic_check(struct drm_device *dev,
> if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
> enum transcoder master = new_crtc_state->mst_master_transcoder;
>
> - if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
> - new_crtc_state->uapi.mode_changed = true;
> - new_crtc_state->update_pipe = false;
> - new_crtc_state->update_m_n = false;
> - new_crtc_state->update_lrr = false;
> - }
> + if (intel_cpu_transcoders_need_modeset(state, BIT(master)))
> + intel_modeset_pipes_in_mask_early(state, "MST master transcoder",
> + BIT(crtc->pipe));
These changes don't really belong in this refactoring patch.
> }
>
> if (is_trans_port_sync_mode(new_crtc_state)) {
> @@ -6498,22 +6503,19 @@ int intel_atomic_check(struct drm_device *dev,
> if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
> trans |= BIT(new_crtc_state->master_transcoder);
>
> - if (intel_cpu_transcoders_need_modeset(state, trans)) {
> - new_crtc_state->uapi.mode_changed = true;
> - new_crtc_state->update_pipe = false;
> - new_crtc_state->update_m_n = false;
> - new_crtc_state->update_lrr = false;
> - }
> + if (intel_cpu_transcoders_need_modeset(state, trans))
> + intel_modeset_pipes_in_mask_early(state, "port sync",
> + BIT(crtc->pipe));
> }
>
> if (new_crtc_state->bigjoiner_pipes) {
> - if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) {
> - new_crtc_state->uapi.mode_changed = true;
> - new_crtc_state->update_pipe = false;
> - new_crtc_state->update_m_n = false;
> - new_crtc_state->update_lrr = false;
> - }
> + if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes))
> + intel_modeset_pipes_in_mask_early(state, "bigjoiner pipes",
> + BIT(crtc->pipe));
> }
> +
> + if (intel_crtc_needs_modeset(new_crtc_state))
> + clear_pipe_update_flags_on_modeset_crtc(new_crtc_state);
> }
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> --
> 2.39.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v4 26/30] drm/i915: Factor out function to clear pipe update flags
2023-11-01 10:17 ` Ville Syrjälä
@ 2023-11-01 11:38 ` Imre Deak
0 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-11-01 11:38 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Nov 01, 2023 at 12:17:30PM +0200, Ville Syrjälä wrote:
> On Mon, Oct 30, 2023 at 05:58:39PM +0200, Imre Deak wrote:
> > Factor out a helper to clear the pipe update flags, used by a follow-up
> > patch to modeset an MST topology.
> >
> > v2:
> > - Move the intel_crtc_needs_modeset() check to the callers. (Ville)
> >
> > Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 52 ++++++++++----------
> > 1 file changed, 27 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 1133c2893bb38..d27afda0cfaa6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -5551,6 +5551,14 @@ int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
> > return 0;
> > }
> >
> > +static void
> > +clear_pipe_update_flags_on_modeset_crtc(struct intel_crtc_state *crtc_state)
>
> The 'on_modeset_crtc()' part doesn't make sense anymore.
>
> Hmm. Another idea would be to move the mode_changed=true assignment
> here and call this something like intel_crtc_flag_fmodeset(), which
> might be a bit more descriptive.
Ok makes sense, will do the above.
In intel_crtc_check_fastset() this will set mode_changed=true where it
wasn't before, but that looks ok.
> > +{
> > + crtc_state->update_pipe = false;
> > + crtc_state->update_m_n = false;
> > + crtc_state->update_lrr = false;
> > +}
> > +
> > /**
> > * intel_modeset_all_pipes_late - force a full modeset on all pipes
> > * @state: intel atomic state
> > @@ -5584,9 +5592,8 @@ int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
> > if (ret)
> > return ret;
> >
> > - crtc_state->update_pipe = false;
> > - crtc_state->update_m_n = false;
> > - crtc_state->update_lrr = false;
> > + clear_pipe_update_flags_on_modeset_crtc(crtc_state);
> > +
> > crtc_state->update_planes |= crtc_state->active_planes;
> > crtc_state->async_flip_planes = 0;
> > crtc_state->do_async_flip = false;
> > @@ -5699,13 +5706,14 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
> > else
> > new_crtc_state->uapi.mode_changed = false;
> >
> > - if (intel_crtc_needs_modeset(new_crtc_state) ||
> > - intel_compare_link_m_n(&old_crtc_state->dp_m_n,
> > + if (intel_crtc_needs_modeset(new_crtc_state))
> > + clear_pipe_update_flags_on_modeset_crtc(new_crtc_state);
> > +
> > + if (intel_compare_link_m_n(&old_crtc_state->dp_m_n,
> > &new_crtc_state->dp_m_n))
> > new_crtc_state->update_m_n = false;
> >
> > - if (intel_crtc_needs_modeset(new_crtc_state) ||
> > - (old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
> > + if ((old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
> > old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
> > new_crtc_state->update_lrr = false;
> >
> > @@ -6484,12 +6492,9 @@ int intel_atomic_check(struct drm_device *dev,
> > if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
> > enum transcoder master = new_crtc_state->mst_master_transcoder;
> >
> > - if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
> > - new_crtc_state->uapi.mode_changed = true;
> > - new_crtc_state->update_pipe = false;
> > - new_crtc_state->update_m_n = false;
> > - new_crtc_state->update_lrr = false;
> > - }
> > + if (intel_cpu_transcoders_need_modeset(state, BIT(master)))
> > + intel_modeset_pipes_in_mask_early(state, "MST master transcoder",
> > + BIT(crtc->pipe));
>
> These changes don't really belong in this refactoring patch.
This had the benefit to show the reason for the modeset, but yes,
should've been a separate change. I'll remove it.
> > }
> >
> > if (is_trans_port_sync_mode(new_crtc_state)) {
> > @@ -6498,22 +6503,19 @@ int intel_atomic_check(struct drm_device *dev,
> > if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
> > trans |= BIT(new_crtc_state->master_transcoder);
> >
> > - if (intel_cpu_transcoders_need_modeset(state, trans)) {
> > - new_crtc_state->uapi.mode_changed = true;
> > - new_crtc_state->update_pipe = false;
> > - new_crtc_state->update_m_n = false;
> > - new_crtc_state->update_lrr = false;
> > - }
> > + if (intel_cpu_transcoders_need_modeset(state, trans))
> > + intel_modeset_pipes_in_mask_early(state, "port sync",
> > + BIT(crtc->pipe));
> > }
> >
> > if (new_crtc_state->bigjoiner_pipes) {
> > - if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) {
> > - new_crtc_state->uapi.mode_changed = true;
> > - new_crtc_state->update_pipe = false;
> > - new_crtc_state->update_m_n = false;
> > - new_crtc_state->update_lrr = false;
> > - }
> > + if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes))
> > + intel_modeset_pipes_in_mask_early(state, "bigjoiner pipes",
> > + BIT(crtc->pipe));
> > }
> > +
> > + if (intel_crtc_needs_modeset(new_crtc_state))
> > + clear_pipe_update_flags_on_modeset_crtc(new_crtc_state);
> > }
> >
> > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> > --
> > 2.39.2
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 94+ messages in thread
* [Intel-gfx] [PATCH v5 26/30] drm/i915: Factor out function to clear pipe update flags
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 26/30] drm/i915: Factor out function to clear pipe update flags Imre Deak
2023-11-01 10:17 ` Ville Syrjälä
@ 2023-11-07 0:15 ` Imre Deak
1 sibling, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-11-07 0:15 UTC (permalink / raw)
To: intel-gfx
Factor out a helper to clear the pipe update flags, used by a follow-up
patch to modeset an MST topology.
v2:
- Move the intel_crtc_needs_modeset() check to the callers. (Ville)
v3 (Ville):
- Rename clear_pipe_update_flags_on_modeset_crtc() to
intel_crtc_flag_modeset().
- Also set crtc_state->uapi.mode_changed in the function.
- Leave out the unrelated change to use
intel_modeset_pipes_in_mask_early().
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 49 +++++++++-----------
1 file changed, 23 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3c7ef2cc3b8b1..afa5613fd847c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5542,6 +5542,16 @@ int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
return 0;
}
+static void
+intel_crtc_flag_modeset(struct intel_crtc_state *crtc_state)
+{
+ crtc_state->uapi.mode_changed = true;
+
+ crtc_state->update_pipe = false;
+ crtc_state->update_m_n = false;
+ crtc_state->update_lrr = false;
+}
+
/**
* intel_modeset_all_pipes_late - force a full modeset on all pipes
* @state: intel atomic state
@@ -5575,9 +5585,8 @@ int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
if (ret)
return ret;
- crtc_state->update_pipe = false;
- crtc_state->update_m_n = false;
- crtc_state->update_lrr = false;
+ intel_crtc_flag_modeset(crtc_state);
+
crtc_state->update_planes |= crtc_state->active_planes;
crtc_state->async_flip_planes = 0;
crtc_state->do_async_flip = false;
@@ -5690,17 +5699,17 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
else
new_crtc_state->uapi.mode_changed = false;
- if (intel_crtc_needs_modeset(new_crtc_state) ||
- intel_compare_link_m_n(&old_crtc_state->dp_m_n,
+ if (intel_compare_link_m_n(&old_crtc_state->dp_m_n,
&new_crtc_state->dp_m_n))
new_crtc_state->update_m_n = false;
- if (intel_crtc_needs_modeset(new_crtc_state) ||
- (old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
+ if ((old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
new_crtc_state->update_lrr = false;
- if (!intel_crtc_needs_modeset(new_crtc_state))
+ if (intel_crtc_needs_modeset(new_crtc_state))
+ intel_crtc_flag_modeset(new_crtc_state);
+ else
new_crtc_state->update_pipe = true;
}
@@ -6475,12 +6484,8 @@ int intel_atomic_check(struct drm_device *dev,
if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
enum transcoder master = new_crtc_state->mst_master_transcoder;
- if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
- new_crtc_state->uapi.mode_changed = true;
- new_crtc_state->update_pipe = false;
- new_crtc_state->update_m_n = false;
- new_crtc_state->update_lrr = false;
- }
+ if (intel_cpu_transcoders_need_modeset(state, BIT(master)))
+ intel_crtc_flag_modeset(new_crtc_state);
}
if (is_trans_port_sync_mode(new_crtc_state)) {
@@ -6489,21 +6494,13 @@ int intel_atomic_check(struct drm_device *dev,
if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
trans |= BIT(new_crtc_state->master_transcoder);
- if (intel_cpu_transcoders_need_modeset(state, trans)) {
- new_crtc_state->uapi.mode_changed = true;
- new_crtc_state->update_pipe = false;
- new_crtc_state->update_m_n = false;
- new_crtc_state->update_lrr = false;
- }
+ if (intel_cpu_transcoders_need_modeset(state, trans))
+ intel_crtc_flag_modeset(new_crtc_state);
}
if (new_crtc_state->bigjoiner_pipes) {
- if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) {
- new_crtc_state->uapi.mode_changed = true;
- new_crtc_state->update_pipe = false;
- new_crtc_state->update_m_n = false;
- new_crtc_state->update_lrr = false;
- }
+ if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes))
+ intel_crtc_flag_modeset(new_crtc_state);
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread
* [Intel-gfx] [PATCH v4 27/30] drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires it
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (25 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 26/30] drm/i915: Factor out function to clear pipe update flags Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-11-07 0:15 ` [Intel-gfx] [PATCH v5 " Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 28/30] drm/i915/dp_mst: Improve BW sharing between MST streams Imre Deak
` (12 subsequent siblings)
39 siblings, 1 reply; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
Enabling / disabling DSC decompression in the branch device downstream
of the source may reset the whole branch device. To avoid this while the
streams are still active, force a modeset on all CRTC/ports connected to
this branch device.
v2:
- Check the CRTC state for each connector in the topology, instead of
the CRTC being checked for a modeset requirement. (Ville)
- Add DocBook for the new function.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 88 ++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp_mst.h | 2 +
3 files changed, 94 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d27afda0cfaa6..2d614180b6bdc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6489,6 +6489,10 @@ int intel_atomic_check(struct drm_device *dev,
if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
continue;
+ if (intel_dp_mst_crtc_needs_modeset(state, crtc))
+ intel_modeset_pipes_in_mask_early(state, "MST topology",
+ BIT(crtc->pipe));
+
if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
enum transcoder master = new_crtc_state->mst_master_transcoder;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 9037e11ec6e0d..2313844456961 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1596,3 +1596,91 @@ int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state,
return 0;
}
+
+static struct intel_connector *
+get_connector_in_state_for_crtc(struct intel_atomic_state *state,
+ const struct intel_crtc *crtc)
+{
+ struct drm_connector_state *old_conn_state;
+ struct drm_connector_state *new_conn_state;
+ struct drm_connector *_connector;
+ int i;
+
+ for_each_oldnew_connector_in_state(&state->base, _connector,
+ old_conn_state, new_conn_state, i) {
+ struct intel_connector *connector =
+ to_intel_connector(_connector);
+
+ if (old_conn_state->crtc == &crtc->base ||
+ new_conn_state->crtc == &crtc->base)
+ return connector;
+ }
+
+ return NULL;
+}
+
+/**
+ * intel_dp_mst_crtc_needs_modeset - check if changes in topology need to modeset the given CRTC
+ * @state: atomic state
+ * @crtc: CRTC for which to check the modeset requirement
+ *
+ * Check if any change in a MST topology requires a forced modeset on @crtc in
+ * this topology. One such change is enabling/disabling the DSC decompression
+ * state in the first branch device's UFP DPCD as required by one CRTC, while
+ * the other @crtc in the same topology is still active, requiring a full modeset
+ * on @crtc.
+ */
+bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ const struct intel_connector *crtc_connector;
+ const struct drm_connector_state *conn_state;
+ const struct drm_connector *_connector;
+ int i;
+
+ if (!intel_crtc_has_type(intel_atomic_get_new_crtc_state(state, crtc),
+ INTEL_OUTPUT_DP_MST))
+ return false;
+
+ crtc_connector = get_connector_in_state_for_crtc(state, crtc);
+
+ if (!crtc_connector)
+ /* None of the connectors in the topology needs modeset */
+ return false;
+
+ for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {
+ const struct intel_connector *connector =
+ to_intel_connector(_connector);
+ const struct intel_crtc_state *new_crtc_state;
+ const struct intel_crtc_state *old_crtc_state;
+ struct intel_crtc *crtc_iter;
+
+ if (connector->mst_port != crtc_connector->mst_port ||
+ !conn_state->crtc)
+ continue;
+
+ crtc_iter = to_intel_crtc(conn_state->crtc);
+
+ new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc_iter);
+ old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc_iter);
+
+ if (!intel_crtc_needs_modeset(new_crtc_state))
+ continue;
+
+ if (old_crtc_state->dsc.compression_enable ==
+ new_crtc_state->dsc.compression_enable)
+ continue;
+ /*
+ * Toggling the decompression flag because of this stream in
+ * the first downstream branch device's UFP DPCD may reset the
+ * whole branch device. To avoid the reset while other streams
+ * are also active modeset the whole MST topology in this
+ * case.
+ */
+ if (connector->dp.dsc_decompression_aux ==
+ &connector->mst_port->aux)
+ return true;
+ }
+
+ return false;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h
index f1815bb722672..fc5e85776a858 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h
@@ -22,5 +22,7 @@ bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state);
bool intel_dp_mst_source_support(struct intel_dp *intel_dp);
int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state,
struct intel_crtc *crtc);
+bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
#endif /* __INTEL_DP_MST_H__ */
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [Intel-gfx] [PATCH v5 27/30] drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires it
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 27/30] drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires it Imre Deak
@ 2023-11-07 0:15 ` Imre Deak
0 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-11-07 0:15 UTC (permalink / raw)
To: intel-gfx
Enabling / disabling DSC decompression in the branch device downstream
of the source may reset the whole branch device. To avoid this while the
streams are still active, force a modeset on all CRTC/ports connected to
this branch device.
v2:
- Check the CRTC state for each connector in the topology, instead of
the CRTC being checked for a modeset requirement. (Ville)
- Add DocBook for the new function.
v3:
- Rebased on a change not to use
intel_modeset_pipes_in_mask_early().
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 88 ++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp_mst.h | 2 +
3 files changed, 93 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index afa5613fd847c..c4cb0e2273a00 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6481,6 +6481,9 @@ int intel_atomic_check(struct drm_device *dev,
if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
continue;
+ if (intel_dp_mst_crtc_needs_modeset(state, crtc))
+ intel_crtc_flag_modeset(new_crtc_state);
+
if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
enum transcoder master = new_crtc_state->mst_master_transcoder;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index b3d952bbb3cf0..079986b09f8bf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1628,3 +1628,91 @@ int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state,
return 0;
}
+
+static struct intel_connector *
+get_connector_in_state_for_crtc(struct intel_atomic_state *state,
+ const struct intel_crtc *crtc)
+{
+ struct drm_connector_state *old_conn_state;
+ struct drm_connector_state *new_conn_state;
+ struct drm_connector *_connector;
+ int i;
+
+ for_each_oldnew_connector_in_state(&state->base, _connector,
+ old_conn_state, new_conn_state, i) {
+ struct intel_connector *connector =
+ to_intel_connector(_connector);
+
+ if (old_conn_state->crtc == &crtc->base ||
+ new_conn_state->crtc == &crtc->base)
+ return connector;
+ }
+
+ return NULL;
+}
+
+/**
+ * intel_dp_mst_crtc_needs_modeset - check if changes in topology need to modeset the given CRTC
+ * @state: atomic state
+ * @crtc: CRTC for which to check the modeset requirement
+ *
+ * Check if any change in a MST topology requires a forced modeset on @crtc in
+ * this topology. One such change is enabling/disabling the DSC decompression
+ * state in the first branch device's UFP DPCD as required by one CRTC, while
+ * the other @crtc in the same topology is still active, requiring a full modeset
+ * on @crtc.
+ */
+bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ const struct intel_connector *crtc_connector;
+ const struct drm_connector_state *conn_state;
+ const struct drm_connector *_connector;
+ int i;
+
+ if (!intel_crtc_has_type(intel_atomic_get_new_crtc_state(state, crtc),
+ INTEL_OUTPUT_DP_MST))
+ return false;
+
+ crtc_connector = get_connector_in_state_for_crtc(state, crtc);
+
+ if (!crtc_connector)
+ /* None of the connectors in the topology needs modeset */
+ return false;
+
+ for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {
+ const struct intel_connector *connector =
+ to_intel_connector(_connector);
+ const struct intel_crtc_state *new_crtc_state;
+ const struct intel_crtc_state *old_crtc_state;
+ struct intel_crtc *crtc_iter;
+
+ if (connector->mst_port != crtc_connector->mst_port ||
+ !conn_state->crtc)
+ continue;
+
+ crtc_iter = to_intel_crtc(conn_state->crtc);
+
+ new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc_iter);
+ old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc_iter);
+
+ if (!intel_crtc_needs_modeset(new_crtc_state))
+ continue;
+
+ if (old_crtc_state->dsc.compression_enable ==
+ new_crtc_state->dsc.compression_enable)
+ continue;
+ /*
+ * Toggling the decompression flag because of this stream in
+ * the first downstream branch device's UFP DPCD may reset the
+ * whole branch device. To avoid the reset while other streams
+ * are also active modeset the whole MST topology in this
+ * case.
+ */
+ if (connector->dp.dsc_decompression_aux ==
+ &connector->mst_port->aux)
+ return true;
+ }
+
+ return false;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h
index f1815bb722672..fc5e85776a858 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h
@@ -22,5 +22,7 @@ bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state);
bool intel_dp_mst_source_support(struct intel_dp *intel_dp);
int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state,
struct intel_crtc *crtc);
+bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
#endif /* __INTEL_DP_MST_H__ */
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread
* [Intel-gfx] [PATCH v4 28/30] drm/i915/dp_mst: Improve BW sharing between MST streams
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (26 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 27/30] drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires it Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 29/30] drm/i915/dp_mst: Check BW limitations only after all streams are computed Imre Deak
` (11 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
At the moment modesetting a stream CRTC will fail if the stream's BW
along with the current BW of all the other streams on the same MST link
is above the total BW of the MST link. Make the BW sharing more dynamic
by trying to reduce the link bpp of one or more streams on the MST link
in this case.
When selecting a stream to reduce the BW for, take into account which
link segment in the MST topology ran out of BW and which streams go
through this link segment. For instance with A,B,C streams in the same
MST topology A and B may share the BW of a link segment downstream of a
branch device, stream C not downstream of the branch device, hence not
affecting this BW. If this link segment's BW runs out one or both of
stream A/B's BW will be reduced until their total BW is within limits.
While reducing the link bpp for a given stream DSC may need to be
enabled for it, which requires FEC on the whole MST link. Check for this
condition and recompute the state for all streams taking the FEC
overhead into account (on 8b/10b links).
v2:
- Rebase on s/min_bpp_pipes/min_bpp_reached_pipes/ change.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +-
drivers/gpu/drm/i915/display/intel_dp.c | 11 +-
drivers/gpu/drm/i915/display/intel_dp.h | 3 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 129 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp_mst.h | 3 +
drivers/gpu/drm/i915/display/intel_link_bw.c | 16 ++-
drivers/gpu/drm/i915/display/intel_link_bw.h | 1 +
7 files changed, 161 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2d614180b6bdc..8ec515d05a7f0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4707,6 +4707,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
if (ret)
return ret;
+ crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);
crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
if (crtc_state->pipe_bpp > to_bpp_int(crtc_state->max_link_bpp_x16)) {
@@ -6539,10 +6540,6 @@ int intel_atomic_check(struct drm_device *dev,
goto fail;
}
- ret = drm_dp_mst_atomic_check(&state->base);
- if (ret)
- goto fail;
-
ret = intel_atomic_check_planes(state);
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6d2fd068b8359..230a599ba4f40 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2138,8 +2138,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
&pipe_config->hw.adjusted_mode;
int ret;
- pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
- intel_dp_supports_fec(intel_dp, connector, pipe_config);
+ pipe_config->fec_enable = pipe_config->fec_enable ||
+ (!intel_dp_is_edp(intel_dp) &&
+ intel_dp_supports_fec(intel_dp, connector, pipe_config));
if (!intel_dp_supports_dsc(connector, pipe_config))
return -EINVAL;
@@ -2327,6 +2328,8 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ const struct intel_connector *connector =
+ to_intel_connector(conn_state->connector);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2335,6 +2338,10 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
bool dsc_needed;
int ret = 0;
+ if (pipe_config->fec_enable &&
+ !intel_dp_supports_fec(intel_dp, connector, pipe_config))
+ return -EINVAL;
+
if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
adjusted_mode->crtc_clock))
pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 7cc23d846dfbf..91051973be2d5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -140,6 +140,9 @@ static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
return ~((1 << lane_count) - 1) & 0xf;
}
+bool intel_dp_supports_fec(struct intel_dp *intel_dp,
+ const struct intel_connector *connector,
+ const struct intel_crtc_state *pipe_config);
u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
int intel_dp_bw_fec_overhead(bool fec_enabled);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 2313844456961..c9447df2ea7c3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -43,6 +43,7 @@
#include "intel_dpio_phy.h"
#include "intel_hdcp.h"
#include "intel_hotplug.h"
+#include "intel_link_bw.h"
#include "intel_vdsc.h"
#include "skl_scaler.h"
@@ -485,6 +486,10 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
bool dsc_needed;
int ret = 0;
+ if (pipe_config->fec_enable &&
+ !intel_dp_supports_fec(intel_dp, connector, pipe_config))
+ return -EINVAL;
+
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
@@ -601,6 +606,130 @@ intel_dp_mst_transcoder_mask(struct intel_atomic_state *state,
return transcoders;
}
+static u8 get_pipes_downstream_of_mst_port(struct intel_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mst_mgr,
+ struct drm_dp_mst_port *parent_port)
+{
+ const struct intel_digital_connector_state *conn_state;
+ struct intel_connector *connector;
+ u8 mask = 0;
+ int i;
+
+ for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
+ if (!conn_state->base.crtc)
+ continue;
+
+ if (&connector->mst_port->mst_mgr != mst_mgr)
+ continue;
+
+ if (connector->port != parent_port &&
+ !drm_dp_mst_port_downstream_of_parent(mst_mgr,
+ connector->port,
+ parent_port))
+ continue;
+
+ mask |= BIT(to_intel_crtc(conn_state->base.crtc)->pipe);
+ }
+
+ return mask;
+}
+
+static int intel_dp_mst_check_fec_change(struct intel_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mst_mgr,
+ struct intel_link_bw_limits *limits)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+ u8 mst_pipe_mask;
+ u8 fec_pipe_mask = 0;
+ int ret;
+
+ mst_pipe_mask = get_pipes_downstream_of_mst_port(state, mst_mgr, NULL);
+
+ for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mst_pipe_mask) {
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ /* Atomic connector check should've added all the MST CRTCs. */
+ if (drm_WARN_ON(&i915->drm, !crtc_state))
+ return -EINVAL;
+
+ if (crtc_state->fec_enable)
+ fec_pipe_mask |= BIT(crtc->pipe);
+ }
+
+ if (!fec_pipe_mask || mst_pipe_mask == fec_pipe_mask)
+ return 0;
+
+ limits->force_fec_pipes |= mst_pipe_mask;
+
+ ret = intel_modeset_pipes_in_mask_early(state, "MST FEC",
+ mst_pipe_mask);
+
+ return ret ? : -EAGAIN;
+}
+
+static int intel_dp_mst_check_bw(struct intel_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mst_mgr,
+ struct drm_dp_mst_topology_state *mst_state,
+ struct intel_link_bw_limits *limits)
+{
+ struct drm_dp_mst_port *mst_port;
+ u8 mst_port_pipes;
+ int ret;
+
+ ret = drm_dp_mst_atomic_check_mgr(&state->base, mst_mgr, mst_state, &mst_port);
+ if (ret != -ENOSPC)
+ return ret;
+
+ mst_port_pipes = get_pipes_downstream_of_mst_port(state, mst_mgr, mst_port);
+
+ ret = intel_link_bw_reduce_bpp(state, limits,
+ mst_port_pipes, "MST link BW");
+
+ return ret ? : -EAGAIN;
+}
+
+/**
+ * intel_dp_mst_atomic_check_link - check all modeset MST link configuration
+ * @state: intel atomic state
+ * @limits: link BW limits
+ *
+ * Check the link configuration for all modeset MST outputs. If the
+ * configuration is invalid @limits will be updated if possible to
+ * reduce the total BW, after which the configuration for all CRTCs in
+ * @state must be recomputed with the updated @limits.
+ *
+ * Returns:
+ * - 0 if the confugration is valid
+ * - %-EAGAIN, if the configuration is invalid and @limits got updated
+ * with fallback values with which the configuration of all CRTCs in
+ * @state must be recomputed
+ * - Other negative error, if the configuration is invalid without a
+ * fallback possibility, or the check failed for another reason
+ */
+int intel_dp_mst_atomic_check_link(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits)
+{
+ struct drm_dp_mst_topology_mgr *mgr;
+ struct drm_dp_mst_topology_state *mst_state;
+ int ret;
+ int i;
+
+ for_each_new_mst_mgr_in_state(&state->base, mgr, mst_state, i) {
+ ret = intel_dp_mst_check_fec_change(state, mgr, limits);
+ if (ret)
+ return ret;
+
+ ret = intel_dp_mst_check_bw(state, mgr, mst_state,
+ limits);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h
index fc5e85776a858..8ca1d599091c6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h
@@ -13,6 +13,7 @@ struct intel_crtc;
struct intel_crtc_state;
struct intel_digital_port;
struct intel_dp;
+struct intel_link_bw_limits;
int intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_id);
void intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port);
@@ -22,6 +23,8 @@ bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state);
bool intel_dp_mst_source_support(struct intel_dp *intel_dp);
int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state,
struct intel_crtc *crtc);
+int intel_dp_mst_atomic_check_link(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits);
bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
struct intel_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_link_bw.c b/drivers/gpu/drm/i915/display/intel_link_bw.c
index c5eb5f2425361..390db5c0c24a5 100644
--- a/drivers/gpu/drm/i915/display/intel_link_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_link_bw.c
@@ -7,6 +7,7 @@
#include "intel_atomic.h"
#include "intel_display_types.h"
+#include "intel_dp_mst.h"
#include "intel_fdi.h"
#include "intel_link_bw.h"
@@ -21,6 +22,7 @@ void intel_link_bw_init_limits(struct drm_i915_private *i915, struct intel_link_
{
enum pipe pipe;
+ limits->force_fec_pipes = 0;
limits->bpp_limit_reached_pipes = 0;
for_each_pipe(i915, pipe)
limits->max_bpp_x16[pipe] = INT_MAX;
@@ -143,6 +145,10 @@ static int check_all_link_config(struct intel_atomic_state *state,
/* TODO: Check additional shared display link configurations like MST */
int ret;
+ ret = intel_dp_mst_atomic_check_link(state, limits);
+ if (ret)
+ return ret;
+
ret = intel_fdi_atomic_check_link(state, limits);
if (ret)
return ret;
@@ -158,6 +164,12 @@ assert_link_limit_change_valid(struct drm_i915_private *i915,
bool bpps_changed = false;
enum pipe pipe;
+ /* FEC can't be forced off after it was forced on. */
+ if (drm_WARN_ON(&i915->drm,
+ (old_limits->force_fec_pipes & new_limits->force_fec_pipes) !=
+ old_limits->force_fec_pipes))
+ return false;
+
for_each_pipe(i915, pipe) {
/* The bpp limit can only decrease. */
if (drm_WARN_ON(&i915->drm,
@@ -172,7 +184,9 @@ assert_link_limit_change_valid(struct drm_i915_private *i915,
/* At least one limit must change. */
if (drm_WARN_ON(&i915->drm,
- !bpps_changed))
+ !bpps_changed &&
+ new_limits->force_fec_pipes ==
+ old_limits->force_fec_pipes))
return false;
return true;
diff --git a/drivers/gpu/drm/i915/display/intel_link_bw.h b/drivers/gpu/drm/i915/display/intel_link_bw.h
index e07df22a779a2..2cf57307cc249 100644
--- a/drivers/gpu/drm/i915/display/intel_link_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_link_bw.h
@@ -16,6 +16,7 @@ struct intel_atomic_state;
struct intel_crtc_state;
struct intel_link_bw_limits {
+ u8 force_fec_pipes;
u8 bpp_limit_reached_pipes;
/* in 1/16 bpp units */
int max_bpp_x16[I915_MAX_PIPES];
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [Intel-gfx] [PATCH v4 29/30] drm/i915/dp_mst: Check BW limitations only after all streams are computed
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (27 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 28/30] drm/i915/dp_mst: Improve BW sharing between MST streams Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 30/30] drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info Imre Deak
` (10 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
After the previous patch the BW limits on the whole MST topology will be
checked after computing the state for all the streams in the topology.
Accordingly remove the check during the stream's encoder compute config
step, to prevent failing an atomic commit due to a BW limit, if this can
be resolved only by reducing the BW of other streams on the same MST
link.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index c9447df2ea7c3..cf82832d6a951 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -203,13 +203,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
if (slots >= 0) {
drm_WARN_ON(&i915->drm, slots != remote_m_n.tu);
- ret = drm_dp_mst_atomic_check(state);
- /*
- * If we got slots >= 0 and we can fit those based on check
- * then we can exit the loop. Otherwise keep trying.
- */
- if (!ret)
- break;
+ break;
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [Intel-gfx] [PATCH v4 30/30] drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (28 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 29/30] drm/i915/dp_mst: Check BW limitations only after all streams are computed Imre Deak
@ 2023-10-30 15:58 ` Imre Deak
2023-10-30 23:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on MST links (rev8) Patchwork
` (9 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-30 15:58 UTC (permalink / raw)
To: intel-gfx
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Currently we seem to be using wrong DPCD register for reading
compressed bpps, reading min/max input bpc instead of compressed bpp.
Fix that, so that we now apply min/max compressed bpp limitations we
get from DP Spec Table 2-157 DP v2.0 and/or correspondent DPCD
register DP_DSC_MAX_BITS_PER_PIXEL_LOW/HIGH.
This might also allow us to get rid of an ugly compressed bpp
recalculation, which we had to add to make some MST hubs usable.
v2: - Fix operator precedence
v3: - Added debug info about compressed bpps
v4: - Don't try to intersect Sink input bpp and compressed bpps.
v5: - Decrease step while looking for suitable compressed bpp to
accommodate.
v6: - Use helper for getting min and max compressed_bpp (Ankit)
v7: - Fix checkpatch warning (Ankit)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 +++++---
drivers/gpu/drm/i915/display/intel_dp.h | 4 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 54 ++++++++++-----------
3 files changed, 41 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 230a599ba4f40..524390240eaf2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1811,7 +1811,7 @@ u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connec
return 0;
}
-static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
+int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
{
/* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
switch (pipe_config->output_format) {
@@ -1828,9 +1828,9 @@ static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
return 0;
}
-static int dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
- struct intel_crtc_state *pipe_config,
- int bpc)
+int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
+ struct intel_crtc_state *pipe_config,
+ int bpc)
{
return intel_dp_dsc_max_sink_compressed_bppx16(connector,
pipe_config, bpc) >> 4;
@@ -1944,12 +1944,14 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
int dsc_joiner_max_bpp;
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
- dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
+ dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
- dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(connector, pipe_config, pipe_bpp / 3);
+ dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
+ pipe_config,
+ pipe_bpp / 3);
dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
@@ -2104,12 +2106,14 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
pipe_config->lane_count = limits->max_lane_count;
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
- dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
+ dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
- dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(connector, pipe_config, pipe_bpp / 3);
+ dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
+ pipe_config,
+ pipe_bpp / 3);
dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 91051973be2d5..e80da67554196 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -129,6 +129,10 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
enum intel_output_format output_format,
u32 pipe_bpp,
u32 timeslots);
+int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config);
+int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
+ struct intel_crtc_state *pipe_config,
+ int bpc);
u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
int mode_clock, int mode_hdisplay,
bool bigjoiner);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index cf82832d6a951..cecd2fa365ed6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -164,6 +164,9 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
crtc_state->port_clock,
crtc_state->lane_count);
+ drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n",
+ min_bpp, max_bpp);
+
for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
struct intel_link_m_n remote_m_n;
int link_bpp;
@@ -261,8 +264,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
u8 dsc_bpc[3] = {};
int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
u8 dsc_max_bpc;
- bool need_timeslot_recalc = false;
- u32 last_compressed_bpp;
+ int min_compressed_bpp, max_compressed_bpp;
/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
if (DISPLAY_VER(i915) >= 12)
@@ -298,38 +300,32 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
if (max_bpp > sink_max_bpp)
max_bpp = sink_max_bpp;
- min_bpp = max(min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
- max_bpp = min(max_bpp, to_bpp_int(limits->link.max_bpp_x16));
+ max_compressed_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
+ crtc_state,
+ max_bpp / 3);
+ max_compressed_bpp = min(max_compressed_bpp,
+ to_bpp_int(limits->link.max_bpp_x16));
- slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_bpp,
- min_bpp, limits,
- conn_state, 2 * 3, true);
+ min_compressed_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
+ min_compressed_bpp = max(min_compressed_bpp,
+ to_bpp_int_roundup(limits->link.min_bpp_x16));
+
+ drm_dbg_kms(&i915->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n",
+ min_compressed_bpp, max_compressed_bpp);
+
+ /* Align compressed bpps according to our own constraints */
+ max_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, max_compressed_bpp,
+ crtc_state->pipe_bpp);
+ min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, min_compressed_bpp,
+ crtc_state->pipe_bpp);
+
+ slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_compressed_bpp,
+ min_compressed_bpp, limits,
+ conn_state, 1, true);
if (slots < 0)
return slots;
- last_compressed_bpp = crtc_state->dsc.compressed_bpp;
-
- crtc_state->dsc.compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915,
- last_compressed_bpp,
- crtc_state->pipe_bpp);
-
- if (crtc_state->dsc.compressed_bpp != last_compressed_bpp)
- need_timeslot_recalc = true;
-
- /*
- * Apparently some MST hubs dislike if vcpi slots are not matching precisely
- * the actual compressed bpp we use.
- */
- if (need_timeslot_recalc) {
- slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
- crtc_state->dsc.compressed_bpp,
- crtc_state->dsc.compressed_bpp,
- limits, conn_state, 2 * 3, true);
- if (slots < 0)
- return slots;
- }
-
return 0;
}
static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
--
2.39.2
^ permalink raw reply related [flat|nested] 94+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on MST links (rev8)
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (29 preceding siblings ...)
2023-10-30 15:58 ` [Intel-gfx] [PATCH v4 30/30] drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info Imre Deak
@ 2023-10-30 23:39 ` Patchwork
2023-10-30 23:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (8 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Patchwork @ 2023-10-30 23:39 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Improve BW management on MST links (rev8)
URL : https://patchwork.freedesktop.org/series/125490/
State : warning
== Summary ==
Error: dim checkpatch failed
5162d630ca8b drm/i915/dp_mst: Fix race between connector registration and setup
fec65fed5b98 drm/dp_mst: Fix fractional DSC bpp handling
fab68064b86f drm/dp_mst: Add helper to determine if an MST port is downstream of another port
815b40f2a09c drm/dp_mst: Factor out a helper to check the atomic state of a topology manager
e5585e2468a1 drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations
ee5f8dca9ffb drm/dp_mst: Allow DSC in any Synaptics last branch device
7608ff34f644 drm/dp: Add DP_HBLANK_EXPANSION_CAPABLE and DSC_PASSTHROUGH_EN DPCD flags
9e8726fe036e drm/dp_mst: Add HBLANK expansion quirk for Synaptics MST hubs
-:27: WARNING:LONG_LINE_COMMENT: line length of 103 exceeds 100 columns
#27: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2248:
+ /* Synaptics DP1.4 MST hubs require DSC for some modes on which it applies HBLANK expansion. */
-:28: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#28: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2249:
+ { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
total: 0 errors, 2 warnings, 0 checks, 21 lines checked
d6e18a7a3f0a drm/dp: Add helpers to calculate the link BW overhead
-:184: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#184: FILE: drivers/gpu/drm/display/drm_dp_helper.c:4026:
+ return 967100;
+ else
total: 0 errors, 1 warnings, 0 checks, 184 lines checked
8d7a379c0890 drm/i915/dp_mst: Enable FEC early once it's known DSC is needed
12c7ca063933 drm/i915/dp: Specify the FEC overhead as an increment vs. a remainder
5b584e6b6651 drm/i915/dp: Pass actual BW overhead to m_n calculation
64c6eb5c56cb drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation
3afe152692cd drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms
0eb5c7a549a5 drm/i915/dp_mst: Program the DSC PPS SDP for each stream
d73dd5aa9c3c drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled
dbfbb5d2a4b3 drm/i915/dp_mst: Add missing DSC compression disabling
e93b5ed2b93e drm/i915/dp: Rename intel_ddi_disable_fec_state() to intel_ddi_disable_fec()
e83a6029d965 drm/i915/dp: Wait for FEC detected status in the sink
640c280b24b8 drm/i915/dp: Disable FEC ready flag in the sink
3b8b6a81c56c drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk
c20152d0eb95 drm/i915/dp_mst: Enable decompression in the sink from the MST encoder hooks
6908e7f30ce8 drm/i915/dp: Enable DSC via the connector decompression AUX
ceb9e57fe346 drm/i915/dp_mst: Enable DSC passthrough
952792bd8519 drm/i915/dp_mst: Enable MST DSC decompression for all streams
b52079fd30d8 drm/i915: Factor out function to clear pipe update flags
-:61: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#61: FILE: drivers/gpu/drm/i915/display/intel_display.c:5716:
+ if ((old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
total: 0 errors, 1 warnings, 0 checks, 89 lines checked
560d3096cb5a drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires it
5410d6351d05 drm/i915/dp_mst: Improve BW sharing between MST streams
078a3f453b84 drm/i915/dp_mst: Check BW limitations only after all streams are computed
96967dd6a8e2 drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info
^ permalink raw reply [flat|nested] 94+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Improve BW management on MST links (rev8)
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (30 preceding siblings ...)
2023-10-30 23:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on MST links (rev8) Patchwork
@ 2023-10-30 23:39 ` Patchwork
2023-10-30 23:57 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (7 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Patchwork @ 2023-10-30 23:39 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Improve BW management on MST links (rev8)
URL : https://patchwork.freedesktop.org/series/125490/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 94+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Improve BW management on MST links (rev8)
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (31 preceding siblings ...)
2023-10-30 23:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-10-30 23:57 ` Patchwork
2023-10-31 14:16 ` Imre Deak
2023-11-01 4:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (6 subsequent siblings)
39 siblings, 1 reply; 94+ messages in thread
From: Patchwork @ 2023-10-30 23:57 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7796 bytes --]
== Series Details ==
Series: drm/i915: Improve BW management on MST links (rev8)
URL : https://patchwork.freedesktop.org/series/125490/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13814 -> Patchwork_125490v8
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_125490v8 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_125490v8, please notify your bug team (lgci.bug.filing@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/index.html
Participating hosts (35 -> 33)
------------------------------
Additional (2): bat-kbl-2 bat-jsl-3
Missing (4): fi-hsw-4770 bat-adlp-11 fi-snb-2520m bat-dg1-5
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_125490v8:
### IGT changes ###
#### Possible regressions ####
* igt@kms_force_connector_basic@force-connector-state:
- bat-rpls-1: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/bat-rpls-1/igt@kms_force_connector_basic@force-connector-state.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-rpls-1/igt@kms_force_connector_basic@force-connector-state.html
Known issues
------------
Here are the changes found in Patchwork_125490v8 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-jsl-3: NOTRUN -> [SKIP][3] ([i915#9318])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-jsl-3/igt@debugfs_test@basic-hwmon.html
* igt@fbdev@info:
- bat-kbl-2: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1849])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-kbl-2/igt@fbdev@info.html
* igt@gem_huc_copy@huc-copy:
- bat-jsl-3: NOTRUN -> [SKIP][5] ([i915#2190])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-jsl-3/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- bat-jsl-3: NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-jsl-3/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2: NOTRUN -> [SKIP][7] ([fdo#109271]) +39 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-kbl-2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][8] -> [DMESG-FAIL][9] ([i915#5334])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-jsl-3: NOTRUN -> [SKIP][10] ([i915#4103]) +1 other test skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-jsl-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-jsl-3: NOTRUN -> [SKIP][11] ([fdo#109285])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-jsl-3/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [PASS][12] -> [FAIL][13] ([IGT#3])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-jsl-3: NOTRUN -> [SKIP][14] ([i915#3555]) +1 other test skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-jsl-3/igt@kms_setmode@basic-clone-single-crtc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
Build changes
-------------
* Linux: CI_DRM_13814 -> Patchwork_125490v8
CI-20190529: 20190529
CI_DRM_13814: b560681c6bf623db41064ac486dd148d6c103e53 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7566: 7566
Patchwork_125490v8: b560681c6bf623db41064ac486dd148d6c103e53 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
1569a83c368b drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info
f752c221f7dc drm/i915/dp_mst: Check BW limitations only after all streams are computed
f6db4b851955 drm/i915/dp_mst: Improve BW sharing between MST streams
88174b0f14f5 drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires it
55bfd15b1f8a drm/i915: Factor out function to clear pipe update flags
7700735c22e9 drm/i915/dp_mst: Enable MST DSC decompression for all streams
2c703e559452 drm/i915/dp_mst: Enable DSC passthrough
6e3844f39232 drm/i915/dp: Enable DSC via the connector decompression AUX
1ac943431a78 drm/i915/dp_mst: Enable decompression in the sink from the MST encoder hooks
0c29eafc983f drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk
c2a5ca4ed9b5 drm/i915/dp: Disable FEC ready flag in the sink
8ddde9873129 drm/i915/dp: Wait for FEC detected status in the sink
50bde9c7a949 drm/i915/dp: Rename intel_ddi_disable_fec_state() to intel_ddi_disable_fec()
fbe41de11a43 drm/i915/dp_mst: Add missing DSC compression disabling
fca9f5c25986 drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled
d8e97f9f9957 drm/i915/dp_mst: Program the DSC PPS SDP for each stream
3569154af98e drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms
36246a635303 drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation
dc2f75e48632 drm/i915/dp: Pass actual BW overhead to m_n calculation
f5011a363aba drm/i915/dp: Specify the FEC overhead as an increment vs. a remainder
71ac021a3909 drm/i915/dp_mst: Enable FEC early once it's known DSC is needed
ae37af9911f5 drm/dp: Add helpers to calculate the link BW overhead
48155a9d962f drm/dp_mst: Add HBLANK expansion quirk for Synaptics MST hubs
b71fd60b8593 drm/dp: Add DP_HBLANK_EXPANSION_CAPABLE and DSC_PASSTHROUGH_EN DPCD flags
d1662e35c27c drm/dp_mst: Allow DSC in any Synaptics last branch device
cba9c81513dd drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations
64ffc1470787 drm/dp_mst: Factor out a helper to check the atomic state of a topology manager
0b631e694e25 drm/dp_mst: Add helper to determine if an MST port is downstream of another port
3f78b3a37478 drm/dp_mst: Fix fractional DSC bpp handling
9a1c5f7e42e3 drm/i915/dp_mst: Fix race between connector registration and setup
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/index.html
[-- Attachment #2: Type: text/html, Size: 8940 bytes --]
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Improve BW management on MST links (rev8)
2023-10-30 23:57 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2023-10-31 14:16 ` Imre Deak
0 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-10-31 14:16 UTC (permalink / raw)
To: intel-gfx, lgci.bug.filing
On Mon, Oct 30, 2023 at 11:57:27PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Improve BW management on MST links (rev8)
> URL : https://patchwork.freedesktop.org/series/125490/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_13814 -> Patchwork_125490v8
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_125490v8 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_125490v8, please notify your bug team (lgci.bug.filing@intel.com) to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/index.html
>
> Participating hosts (35 -> 33)
> ------------------------------
>
> Additional (2): bat-kbl-2 bat-jsl-3
> Missing (4): fi-hsw-4770 bat-adlp-11 fi-snb-2520m bat-dg1-5
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_125490v8:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@kms_force_connector_basic@force-connector-state:
> - bat-rpls-1: [PASS][1] -> [ABORT][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/bat-rpls-1/igt@kms_force_connector_basic@force-connector-state.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-rpls-1/igt@kms_force_connector_basic@force-connector-state.html
Looks like a corruption in the mode requested by the test or framebuffer
console:
<7> [72.565692] [drm:drm_client_modeset_probe] desired mode \xd8\xc0\x1c^\x81\x88\xff\xff set on crtc 80 (0,0)
<7> [72.565743] i915 0000:00:02.0: [drm:__drm_fb_helper_initial_config_and_unlock] test CRTC 0 primary plane
<7> [72.565749] i915 0000:00:02.0: [drm:__drm_fb_helper_initial_config_and_unlock] Fbdev over-allocation too large; clamping height to 16384
<7> [72.565754] i915 0000:00:02.0: [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
<3> [72.565837] __i915_gem_object_create_region:73 GEM_BUG_ON(!size)
Also happened recently in
Patchwork_125323v3/fi-kbl-guc
and even earlier in CI_DRM runs. I reopened the ticket which seemed to
have the same root cause:
https://gitlab.freedesktop.org/drm/intel/-/issues/9315
I don't see how it would be related to the changes, since there is
no display connected to the host and in this test an HDMI output is
force enabled (the changes affect only DP).
> Known issues
> ------------
>
> Here are the changes found in Patchwork_125490v8 that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@debugfs_test@basic-hwmon:
> - bat-jsl-3: NOTRUN -> [SKIP][3] ([i915#9318])
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-jsl-3/igt@debugfs_test@basic-hwmon.html
>
> * igt@fbdev@info:
> - bat-kbl-2: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1849])
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-kbl-2/igt@fbdev@info.html
>
> * igt@gem_huc_copy@huc-copy:
> - bat-jsl-3: NOTRUN -> [SKIP][5] ([i915#2190])
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-jsl-3/igt@gem_huc_copy@huc-copy.html
>
> * igt@gem_lmem_swapping@basic:
> - bat-jsl-3: NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-jsl-3/igt@gem_lmem_swapping@basic.html
>
> * igt@gem_lmem_swapping@parallel-random-engines:
> - bat-kbl-2: NOTRUN -> [SKIP][7] ([fdo#109271]) +39 other tests skip
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-kbl-2/igt@gem_lmem_swapping@parallel-random-engines.html
>
> * igt@i915_selftest@live@gt_heartbeat:
> - fi-apl-guc: [PASS][8] -> [DMESG-FAIL][9] ([i915#5334])
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
>
> * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
> - bat-jsl-3: NOTRUN -> [SKIP][10] ([i915#4103]) +1 other test skip
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-jsl-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
>
> * igt@kms_force_connector_basic@force-load-detect:
> - bat-jsl-3: NOTRUN -> [SKIP][11] ([fdo#109285])
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-jsl-3/igt@kms_force_connector_basic@force-load-detect.html
>
> * igt@kms_hdmi_inject@inject-audio:
> - fi-kbl-guc: [PASS][12] -> [FAIL][13] ([IGT#3])
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
>
> * igt@kms_setmode@basic-clone-single-crtc:
> - bat-jsl-3: NOTRUN -> [SKIP][14] ([i915#3555]) +1 other test skip
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-jsl-3/igt@kms_setmode@basic-clone-single-crtc.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
> [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
> [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
> [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
> [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
> [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
> [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
> [i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_13814 -> Patchwork_125490v8
>
> CI-20190529: 20190529
> CI_DRM_13814: b560681c6bf623db41064ac486dd148d6c103e53 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_7566: 7566
> Patchwork_125490v8: b560681c6bf623db41064ac486dd148d6c103e53 @ git://anongit.freedesktop.org/gfx-ci/linux
>
>
> ### Linux commits
>
> 1569a83c368b drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info
> f752c221f7dc drm/i915/dp_mst: Check BW limitations only after all streams are computed
> f6db4b851955 drm/i915/dp_mst: Improve BW sharing between MST streams
> 88174b0f14f5 drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires it
> 55bfd15b1f8a drm/i915: Factor out function to clear pipe update flags
> 7700735c22e9 drm/i915/dp_mst: Enable MST DSC decompression for all streams
> 2c703e559452 drm/i915/dp_mst: Enable DSC passthrough
> 6e3844f39232 drm/i915/dp: Enable DSC via the connector decompression AUX
> 1ac943431a78 drm/i915/dp_mst: Enable decompression in the sink from the MST encoder hooks
> 0c29eafc983f drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk
> c2a5ca4ed9b5 drm/i915/dp: Disable FEC ready flag in the sink
> 8ddde9873129 drm/i915/dp: Wait for FEC detected status in the sink
> 50bde9c7a949 drm/i915/dp: Rename intel_ddi_disable_fec_state() to intel_ddi_disable_fec()
> fbe41de11a43 drm/i915/dp_mst: Add missing DSC compression disabling
> fca9f5c25986 drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled
> d8e97f9f9957 drm/i915/dp_mst: Program the DSC PPS SDP for each stream
> 3569154af98e drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms
> 36246a635303 drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation
> dc2f75e48632 drm/i915/dp: Pass actual BW overhead to m_n calculation
> f5011a363aba drm/i915/dp: Specify the FEC overhead as an increment vs. a remainder
> 71ac021a3909 drm/i915/dp_mst: Enable FEC early once it's known DSC is needed
> ae37af9911f5 drm/dp: Add helpers to calculate the link BW overhead
> 48155a9d962f drm/dp_mst: Add HBLANK expansion quirk for Synaptics MST hubs
> b71fd60b8593 drm/dp: Add DP_HBLANK_EXPANSION_CAPABLE and DSC_PASSTHROUGH_EN DPCD flags
> d1662e35c27c drm/dp_mst: Allow DSC in any Synaptics last branch device
> cba9c81513dd drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations
> 64ffc1470787 drm/dp_mst: Factor out a helper to check the atomic state of a topology manager
> 0b631e694e25 drm/dp_mst: Add helper to determine if an MST port is downstream of another port
> 3f78b3a37478 drm/dp_mst: Fix fractional DSC bpp handling
> 9a1c5f7e42e3 drm/i915/dp_mst: Fix race between connector registration and setup
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/index.html
^ permalink raw reply [flat|nested] 94+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Improve BW management on MST links (rev8)
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (32 preceding siblings ...)
2023-10-30 23:57 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2023-11-01 4:32 ` Patchwork
2023-11-02 11:44 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (5 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Patchwork @ 2023-11-01 4:32 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7708 bytes --]
== Series Details ==
Series: drm/i915: Improve BW management on MST links (rev8)
URL : https://patchwork.freedesktop.org/series/125490/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13814 -> Patchwork_125490v8
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/index.html
Participating hosts (35 -> 34)
------------------------------
Additional (2): bat-kbl-2 bat-jsl-3
Missing (3): bat-adlp-11 fi-snb-2520m bat-dg1-5
Known issues
------------
Here are the changes found in Patchwork_125490v8 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-jsl-3: NOTRUN -> [SKIP][1] ([i915#9318])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-jsl-3/igt@debugfs_test@basic-hwmon.html
* igt@fbdev@info:
- bat-kbl-2: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1849])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-kbl-2/igt@fbdev@info.html
* igt@gem_huc_copy@huc-copy:
- bat-jsl-3: NOTRUN -> [SKIP][3] ([i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-jsl-3/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- bat-jsl-3: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-jsl-3/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2: NOTRUN -> [SKIP][5] ([fdo#109271]) +39 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-kbl-2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][6] -> [DMESG-FAIL][7] ([i915#5334])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-jsl-3: NOTRUN -> [SKIP][8] ([i915#4103]) +1 other test skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-jsl-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-connector-state:
- bat-rpls-1: [PASS][9] -> [ABORT][10] ([i915#9315])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/bat-rpls-1/igt@kms_force_connector_basic@force-connector-state.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-rpls-1/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-jsl-3: NOTRUN -> [SKIP][11] ([fdo#109285])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-jsl-3/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [PASS][12] -> [FAIL][13] ([IGT#3])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-vga-1:
- fi-hsw-4770: NOTRUN -> [DMESG-WARN][14] ([i915#8841]) +6 other tests dmesg-warn
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/fi-hsw-4770/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-vga-1.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-jsl-3: NOTRUN -> [SKIP][15] ([i915#3555]) +1 other test skip
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/bat-jsl-3/igt@kms_setmode@basic-clone-single-crtc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#9315]: https://gitlab.freedesktop.org/drm/intel/issues/9315
[i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
Build changes
-------------
* Linux: CI_DRM_13814 -> Patchwork_125490v8
CI-20190529: 20190529
CI_DRM_13814: b560681c6bf623db41064ac486dd148d6c103e53 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7566: 7566
Patchwork_125490v8: b560681c6bf623db41064ac486dd148d6c103e53 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
1569a83c368b drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info
f752c221f7dc drm/i915/dp_mst: Check BW limitations only after all streams are computed
f6db4b851955 drm/i915/dp_mst: Improve BW sharing between MST streams
88174b0f14f5 drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires it
55bfd15b1f8a drm/i915: Factor out function to clear pipe update flags
7700735c22e9 drm/i915/dp_mst: Enable MST DSC decompression for all streams
2c703e559452 drm/i915/dp_mst: Enable DSC passthrough
6e3844f39232 drm/i915/dp: Enable DSC via the connector decompression AUX
1ac943431a78 drm/i915/dp_mst: Enable decompression in the sink from the MST encoder hooks
0c29eafc983f drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk
c2a5ca4ed9b5 drm/i915/dp: Disable FEC ready flag in the sink
8ddde9873129 drm/i915/dp: Wait for FEC detected status in the sink
50bde9c7a949 drm/i915/dp: Rename intel_ddi_disable_fec_state() to intel_ddi_disable_fec()
fbe41de11a43 drm/i915/dp_mst: Add missing DSC compression disabling
fca9f5c25986 drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled
d8e97f9f9957 drm/i915/dp_mst: Program the DSC PPS SDP for each stream
3569154af98e drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms
36246a635303 drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation
dc2f75e48632 drm/i915/dp: Pass actual BW overhead to m_n calculation
f5011a363aba drm/i915/dp: Specify the FEC overhead as an increment vs. a remainder
71ac021a3909 drm/i915/dp_mst: Enable FEC early once it's known DSC is needed
ae37af9911f5 drm/dp: Add helpers to calculate the link BW overhead
48155a9d962f drm/dp_mst: Add HBLANK expansion quirk for Synaptics MST hubs
b71fd60b8593 drm/dp: Add DP_HBLANK_EXPANSION_CAPABLE and DSC_PASSTHROUGH_EN DPCD flags
d1662e35c27c drm/dp_mst: Allow DSC in any Synaptics last branch device
cba9c81513dd drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations
64ffc1470787 drm/dp_mst: Factor out a helper to check the atomic state of a topology manager
0b631e694e25 drm/dp_mst: Add helper to determine if an MST port is downstream of another port
3f78b3a37478 drm/dp_mst: Fix fractional DSC bpp handling
9a1c5f7e42e3 drm/i915/dp_mst: Fix race between connector registration and setup
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/index.html
[-- Attachment #2: Type: text/html, Size: 8866 bytes --]
^ permalink raw reply [flat|nested] 94+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Improve BW management on MST links (rev8)
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (33 preceding siblings ...)
2023-11-01 4:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-11-02 11:44 ` Patchwork
2023-11-03 22:43 ` [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Lyude Paul
` (4 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Patchwork @ 2023-11-02 11:44 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 100278 bytes --]
== Series Details ==
Series: drm/i915: Improve BW management on MST links (rev8)
URL : https://patchwork.freedesktop.org/series/125490/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13814_full -> Patchwork_125490v8_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_125490v8_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_125490v8_full, please notify your bug team (lgci.bug.filing@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (12 -> 13)
------------------------------
Additional (1): shard-tglu0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_125490v8_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_create@create-ext-cpu-access-big:
- shard-dg2: NOTRUN -> [ABORT][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@gem_create@create-ext-cpu-access-big.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff:
- shard-mtlp: [PASS][2] -> [INCOMPLETE][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff.html
Known issues
------------
Here are the changes found in Patchwork_125490v8_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-snb: ([PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28]) -> ([PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [FAIL][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53]) ([i915#8293])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb7/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb7/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb7/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb6/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb6/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb6/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb6/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb6/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb5/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb5/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb5/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb5/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb4/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb4/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb4/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb4/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb4/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb2/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb2/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb2/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb2/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb1/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb1/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb1/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb1/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb7/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb7/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb7/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb6/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb6/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb6/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb6/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb5/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb5/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb5/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb5/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb5/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb4/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb4/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb4/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb4/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb4/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb4/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb2/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb2/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb1/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb1/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb1/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb1/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb1/boot.html
- shard-apl: ([PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77]) -> ([FAIL][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102]) ([i915#8293])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl1/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl1/boot.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl1/boot.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl1/boot.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl1/boot.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl1/boot.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl2/boot.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl2/boot.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl2/boot.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl2/boot.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl2/boot.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl3/boot.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl4/boot.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl4/boot.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl4/boot.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl4/boot.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl6/boot.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl6/boot.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl6/boot.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl7/boot.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl7/boot.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl7/boot.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl7/boot.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl7/boot.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl4/boot.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl6/boot.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl6/boot.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl6/boot.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl6/boot.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl6/boot.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl6/boot.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl7/boot.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl7/boot.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl7/boot.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl7/boot.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl7/boot.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl7/boot.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl1/boot.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl1/boot.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl1/boot.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl1/boot.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl1/boot.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl1/boot.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl1/boot.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl2/boot.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl2/boot.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl2/boot.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl2/boot.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl4/boot.html
#### Possible fixes ####
* boot:
- shard-glk: ([PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [FAIL][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [FAIL][126], [PASS][127]) ([i915#8293]) -> ([PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134], [PASS][135], [PASS][136], [PASS][137], [PASS][138], [PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143], [PASS][144], [PASS][145], [PASS][146], [PASS][147], [PASS][148], [PASS][149], [PASS][150], [PASS][151], [PASS][152])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk9/boot.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk9/boot.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk9/boot.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk9/boot.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk8/boot.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk8/boot.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk8/boot.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk8/boot.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk6/boot.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk6/boot.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk6/boot.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk4/boot.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk4/boot.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk4/boot.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk4/boot.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk3/boot.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk3/boot.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk3/boot.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk3/boot.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk2/boot.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk2/boot.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk2/boot.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk2/boot.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk1/boot.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk1/boot.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk8/boot.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk9/boot.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk9/boot.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk9/boot.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk9/boot.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk8/boot.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk8/boot.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk8/boot.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk2/boot.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk2/boot.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk2/boot.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk2/boot.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk2/boot.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk3/boot.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk3/boot.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk3/boot.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk3/boot.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk4/boot.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk4/boot.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk4/boot.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk4/boot.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk6/boot.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk6/boot.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk6/boot.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk6/boot.html
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-keep-cache:
- shard-mtlp: NOTRUN -> [SKIP][153] ([i915#8411]) +1 other test skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-3/igt@api_intel_bb@blit-reloc-keep-cache.html
* igt@device_reset@cold-reset-bound:
- shard-dg2: NOTRUN -> [SKIP][154] ([i915#7701])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-6/igt@device_reset@cold-reset-bound.html
* igt@drm_fdinfo@busy-hang@bcs0:
- shard-dg2: NOTRUN -> [SKIP][155] ([i915#8414]) +20 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@drm_fdinfo@busy-hang@bcs0.html
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: NOTRUN -> [FAIL][156] ([i915#7742]) +1 other test fail
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- shard-rkl: [PASS][157] -> [FAIL][158] ([i915#7742])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
* igt@drm_fdinfo@virtual-busy-hang:
- shard-mtlp: NOTRUN -> [SKIP][159] ([i915#8414]) +1 other test skip
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@drm_fdinfo@virtual-busy-hang.html
* igt@fbdev@info:
- shard-rkl: NOTRUN -> [SKIP][160] ([i915#1849] / [i915#2582])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@fbdev@info.html
* igt@fbdev@unaligned-read:
- shard-rkl: [PASS][161] -> [SKIP][162] ([i915#2582])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-6/igt@fbdev@unaligned-read.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@fbdev@unaligned-read.html
* igt@gem_ccs@block-multicopy-inplace:
- shard-mtlp: NOTRUN -> [SKIP][163] ([i915#3555])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@gem_ccs@block-multicopy-inplace.html
* igt@gem_ccs@suspend-resume:
- shard-mtlp: NOTRUN -> [SKIP][164] ([i915#9323])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@gem_ccs@suspend-resume.html
* igt@gem_close_race@multigpu-basic-process:
- shard-mtlp: NOTRUN -> [SKIP][165] ([i915#7697])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_ctx_param@set-priority-not-supported:
- shard-mtlp: NOTRUN -> [SKIP][166] ([fdo#109314])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@gem_ctx_param@set-priority-not-supported.html
* igt@gem_ctx_persistence@engines-hostile@vcs0:
- shard-mtlp: NOTRUN -> [FAIL][167] ([i915#2410]) +2 other tests fail
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@gem_ctx_persistence@engines-hostile@vcs0.html
* igt@gem_ctx_persistence@heartbeat-hang:
- shard-mtlp: NOTRUN -> [SKIP][168] ([i915#8555])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@gem_ctx_persistence@heartbeat-hang.html
* igt@gem_ctx_sseu@engines:
- shard-dg2: NOTRUN -> [SKIP][169] ([i915#280])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-1/igt@gem_ctx_sseu@engines.html
* igt@gem_eio@hibernate:
- shard-dg2: [PASS][170] -> [ABORT][171] ([i915#7975] / [i915#8213])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-dg2-11/igt@gem_eio@hibernate.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-6/igt@gem_eio@hibernate.html
* igt@gem_exec_balancer@bonded-pair:
- shard-mtlp: NOTRUN -> [SKIP][172] ([i915#4771])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@gem_exec_balancer@bonded-pair.html
* igt@gem_exec_balancer@bonded-sync:
- shard-dg2: NOTRUN -> [SKIP][173] ([i915#4771])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@gem_exec_balancer@bonded-sync.html
* igt@gem_exec_balancer@noheartbeat:
- shard-dg2: NOTRUN -> [SKIP][174] ([i915#8555]) +2 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@gem_exec_balancer@noheartbeat.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-rkl: NOTRUN -> [SKIP][175] ([i915#4525])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_capture@capture-invisible@lmem0:
- shard-dg2: NOTRUN -> [SKIP][176] ([i915#6334]) +1 other test skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@gem_exec_capture@capture-invisible@lmem0.html
* igt@gem_exec_capture@capture-invisible@smem0:
- shard-glk: NOTRUN -> [SKIP][177] ([fdo#109271] / [i915#6334])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk3/igt@gem_exec_capture@capture-invisible@smem0.html
- shard-mtlp: NOTRUN -> [SKIP][178] ([i915#6334])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@gem_exec_capture@capture-invisible@smem0.html
* igt@gem_exec_capture@many-4k-zero:
- shard-dg2: NOTRUN -> [FAIL][179] ([i915#9606]) +1 other test fail
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@gem_exec_capture@many-4k-zero.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-rkl: NOTRUN -> [FAIL][180] ([i915#2842])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-vip:
- shard-mtlp: NOTRUN -> [SKIP][181] ([i915#4473] / [i915#4771]) +2 other tests skip
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@gem_exec_fair@basic-none-vip.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][182] -> [FAIL][183] ([i915#2842])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-throttle:
- shard-dg2: NOTRUN -> [SKIP][184] ([i915#3539])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-6/igt@gem_exec_fair@basic-throttle.html
* igt@gem_exec_fence@submit:
- shard-mtlp: NOTRUN -> [SKIP][185] ([i915#4812])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@gem_exec_fence@submit.html
* igt@gem_exec_fence@submit3:
- shard-dg2: NOTRUN -> [SKIP][186] ([i915#4812]) +2 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-1/igt@gem_exec_fence@submit3.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-rkl: NOTRUN -> [SKIP][187] ([fdo#109313])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_flush@basic-uc-ro-default:
- shard-dg2: NOTRUN -> [SKIP][188] ([i915#3539] / [i915#4852]) +2 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-1/igt@gem_exec_flush@basic-uc-ro-default.html
* igt@gem_exec_gttfill@multigpu-basic:
- shard-dg2: NOTRUN -> [SKIP][189] ([i915#7697])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@gem_exec_gttfill@multigpu-basic.html
* igt@gem_exec_params@rsvd2-dirt:
- shard-mtlp: NOTRUN -> [SKIP][190] ([i915#5107])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@gem_exec_params@rsvd2-dirt.html
* igt@gem_exec_params@secure-non-master:
- shard-dg2: NOTRUN -> [SKIP][191] ([fdo#112283])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@gem_exec_params@secure-non-master.html
- shard-mtlp: NOTRUN -> [SKIP][192] ([fdo#112283]) +1 other test skip
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@gem_exec_params@secure-non-master.html
* igt@gem_exec_reloc@basic-gtt-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][193] ([i915#3281]) +10 other tests skip
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@gem_exec_reloc@basic-gtt-noreloc.html
* igt@gem_exec_reloc@basic-scanout@bcs0:
- shard-rkl: NOTRUN -> [SKIP][194] ([i915#3639]) +3 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@gem_exec_reloc@basic-scanout@bcs0.html
* igt@gem_exec_reloc@basic-wc-active:
- shard-rkl: NOTRUN -> [SKIP][195] ([i915#3281])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@gem_exec_reloc@basic-wc-active.html
* igt@gem_exec_reloc@basic-wc-cpu:
- shard-dg2: NOTRUN -> [SKIP][196] ([i915#3281]) +11 other tests skip
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@gem_exec_reloc@basic-wc-cpu.html
* igt@gem_exec_reloc@basic-write-read:
- shard-rkl: [PASS][197] -> [SKIP][198] ([i915#3281]) +7 other tests skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@gem_exec_reloc@basic-write-read.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-7/igt@gem_exec_reloc@basic-write-read.html
* igt@gem_exec_schedule@preempt-queue:
- shard-mtlp: NOTRUN -> [SKIP][199] ([i915#4537] / [i915#4812])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@gem_exec_schedule@preempt-queue.html
* igt@gem_exec_schedule@semaphore-power:
- shard-dg2: NOTRUN -> [SKIP][200] ([i915#4537] / [i915#4812])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-6/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_exec_suspend@basic-s4-devices@lmem0:
- shard-dg2: NOTRUN -> [ABORT][201] ([i915#7975] / [i915#8213])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-1/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
* igt@gem_fenced_exec_thrash@too-many-fences:
- shard-mtlp: NOTRUN -> [SKIP][202] ([i915#4860]) +2 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@gem_fenced_exec_thrash@too-many-fences.html
* igt@gem_lmem_swapping@heavy-random:
- shard-glk: NOTRUN -> [SKIP][203] ([fdo#109271] / [i915#4613]) +2 other tests skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk2/igt@gem_lmem_swapping@heavy-random.html
* igt@gem_lmem_swapping@heavy-verify-multi:
- shard-apl: NOTRUN -> [SKIP][204] ([fdo#109271] / [i915#4613])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl7/igt@gem_lmem_swapping@heavy-verify-multi.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-rkl: NOTRUN -> [SKIP][205] ([i915#4613])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@random:
- shard-mtlp: NOTRUN -> [SKIP][206] ([i915#4613]) +2 other tests skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@gem_lmem_swapping@random.html
* igt@gem_madvise@dontneed-before-pwrite:
- shard-dg2: NOTRUN -> [SKIP][207] ([i915#3282]) +7 other tests skip
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@gem_madvise@dontneed-before-pwrite.html
* igt@gem_mmap@bad-size:
- shard-mtlp: NOTRUN -> [SKIP][208] ([i915#4083]) +6 other tests skip
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@gem_mmap@bad-size.html
* igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
- shard-mtlp: NOTRUN -> [SKIP][209] ([i915#4077]) +12 other tests skip
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
* igt@gem_mmap_gtt@cpuset-big-copy:
- shard-dg2: NOTRUN -> [SKIP][210] ([i915#4077]) +14 other tests skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@gem_mmap_gtt@cpuset-big-copy.html
* igt@gem_mmap_wc@copy:
- shard-dg2: NOTRUN -> [SKIP][211] ([i915#4083]) +9 other tests skip
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@gem_mmap_wc@copy.html
* igt@gem_partial_pwrite_pread@writes-after-reads-display:
- shard-mtlp: NOTRUN -> [SKIP][212] ([i915#3282]) +3 other tests skip
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-rkl: NOTRUN -> [SKIP][213] ([i915#3282]) +4 other tests skip
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gem_pxp@create-protected-buffer:
- shard-dg2: NOTRUN -> [SKIP][214] ([i915#4270]) +1 other test skip
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@gem_pxp@create-protected-buffer.html
* igt@gem_pxp@create-regular-buffer:
- shard-mtlp: NOTRUN -> [SKIP][215] ([i915#4270]) +3 other tests skip
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-3/igt@gem_pxp@create-regular-buffer.html
* igt@gem_pxp@reject-modify-context-protection-off-1:
- shard-rkl: NOTRUN -> [SKIP][216] ([i915#4270]) +1 other test skip
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@gem_pxp@reject-modify-context-protection-off-1.html
* igt@gem_render_copy@y-tiled:
- shard-mtlp: NOTRUN -> [SKIP][217] ([i915#8428]) +4 other tests skip
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-3/igt@gem_render_copy@y-tiled.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled:
- shard-rkl: NOTRUN -> [SKIP][218] ([i915#768]) +4 other tests skip
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html
* igt@gem_set_tiling_vs_blt@tiled-to-tiled:
- shard-dg2: NOTRUN -> [SKIP][219] ([i915#4079])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-1/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html
* igt@gem_set_tiling_vs_pwrite:
- shard-rkl: [PASS][220] -> [SKIP][221] ([i915#3282]) +3 other tests skip
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@gem_set_tiling_vs_pwrite.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-7/igt@gem_set_tiling_vs_pwrite.html
* igt@gem_softpin@evict-snoop:
- shard-mtlp: NOTRUN -> [SKIP][222] ([i915#4885])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@gem_softpin@evict-snoop.html
* igt@gem_unfence_active_buffers:
- shard-dg2: NOTRUN -> [SKIP][223] ([i915#4879])
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@gem_unfence_active_buffers.html
- shard-mtlp: NOTRUN -> [SKIP][224] ([i915#4879])
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@gem_unfence_active_buffers.html
* igt@gem_userptr_blits@access-control:
- shard-mtlp: NOTRUN -> [SKIP][225] ([i915#3297]) +2 other tests skip
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@gem_userptr_blits@access-control.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-dg2: NOTRUN -> [SKIP][226] ([i915#3297] / [i915#4880]) +1 other test skip
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-1/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-dg2: NOTRUN -> [SKIP][227] ([i915#3297]) +2 other tests skip
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@gem_userptr_blits@unsync-unmap-after-close.html
* igt@gem_userptr_blits@vma-merge:
- shard-dg2: NOTRUN -> [FAIL][228] ([i915#3318])
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-6/igt@gem_userptr_blits@vma-merge.html
* igt@gen3_render_linear_blits:
- shard-rkl: NOTRUN -> [SKIP][229] ([fdo#109289]) +2 other tests skip
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@gen3_render_linear_blits.html
* igt@gen3_render_tiledx_blits:
- shard-dg2: NOTRUN -> [SKIP][230] ([fdo#109289]) +6 other tests skip
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@gen3_render_tiledx_blits.html
* igt@gen9_exec_parse@allowed-all:
- shard-rkl: [PASS][231] -> [SKIP][232] ([i915#2527]) +2 other tests skip
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@gen9_exec_parse@allowed-all.html
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-1/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@cmd-crossing-page:
- shard-mtlp: NOTRUN -> [SKIP][233] ([i915#2856]) +1 other test skip
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@gen9_exec_parse@valid-registers:
- shard-dg2: NOTRUN -> [SKIP][234] ([i915#2856]) +3 other tests skip
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@gen9_exec_parse@valid-registers.html
* igt@i915_fb_tiling:
- shard-mtlp: NOTRUN -> [SKIP][235] ([i915#4881])
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@i915_fb_tiling.html
- shard-dg2: NOTRUN -> [SKIP][236] ([i915#4881])
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@i915_fb_tiling.html
* igt@i915_hangman@detector@vcs0:
- shard-mtlp: NOTRUN -> [FAIL][237] ([i915#8456]) +2 other tests fail
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@i915_hangman@detector@vcs0.html
* igt@i915_module_load@load:
- shard-dg2: NOTRUN -> [SKIP][238] ([i915#6227])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@i915_module_load@load.html
* igt@i915_pipe_stress@stress-xrgb8888-ytiled:
- shard-dg2: NOTRUN -> [SKIP][239] ([i915#7091])
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html
* igt@i915_pm_freq_mult@media-freq@gt1:
- shard-mtlp: NOTRUN -> [SKIP][240] ([i915#6590]) +1 other test skip
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@i915_pm_freq_mult@media-freq@gt1.html
* igt@i915_pm_rc6_residency@rc6-idle@vecs0:
- shard-dg1: [PASS][241] -> [FAIL][242] ([i915#3591]) +1 other test fail
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-rkl: NOTRUN -> [SKIP][243] ([fdo#109293] / [fdo#109506])
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_pm_rps@basic-api:
- shard-dg2: NOTRUN -> [SKIP][244] ([i915#6621])
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@i915_pm_rps@basic-api.html
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][245] -> [INCOMPLETE][246] ([i915#7790])
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-snb5/igt@i915_pm_rps@reset.html
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb4/igt@i915_pm_rps@reset.html
* igt@i915_pm_rps@thresholds-idle-park@gt0:
- shard-mtlp: NOTRUN -> [SKIP][247] ([i915#8925]) +1 other test skip
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@i915_pm_rps@thresholds-idle-park@gt0.html
* igt@i915_pm_rps@thresholds-idle-park@gt1:
- shard-mtlp: NOTRUN -> [SKIP][248] ([i915#3555] / [i915#8925]) +1 other test skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@i915_pm_rps@thresholds-idle-park@gt1.html
* igt@i915_pm_rps@thresholds@gt0:
- shard-dg2: NOTRUN -> [SKIP][249] ([i915#8925])
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-1/igt@i915_pm_rps@thresholds@gt0.html
* igt@i915_pm_sseu@full-enable:
- shard-rkl: [PASS][250] -> [SKIP][251] ([i915#4387])
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@i915_pm_sseu@full-enable.html
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-7/igt@i915_pm_sseu@full-enable.html
* igt@i915_query@query-topology-unsupported:
- shard-dg2: NOTRUN -> [SKIP][252] ([fdo#109302])
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@i915_query@query-topology-unsupported.html
* igt@i915_selftest@mock@memory_region:
- shard-mtlp: NOTRUN -> [DMESG-WARN][253] ([i915#9311])
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@i915_selftest@mock@memory_region.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- shard-dg2: NOTRUN -> [SKIP][254] ([i915#4215] / [i915#5190])
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@bo-too-small-due-to-tiling:
- shard-dg2: NOTRUN -> [SKIP][255] ([i915#4212])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- shard-mtlp: NOTRUN -> [SKIP][256] ([i915#4212]) +2 other tests skip
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_async_flips@crc@pipe-c-hdmi-a-1:
- shard-dg1: NOTRUN -> [FAIL][257] ([i915#8247]) +3 other tests fail
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg1-19/igt@kms_async_flips@crc@pipe-c-hdmi-a-1.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-mtlp: NOTRUN -> [SKIP][258] ([i915#1769] / [i915#3555]) +1 other test skip
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-glk: NOTRUN -> [SKIP][259] ([fdo#109271] / [i915#1769])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk3/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
- shard-dg2: NOTRUN -> [SKIP][260] ([i915#1769] / [i915#3555])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-0:
- shard-rkl: NOTRUN -> [SKIP][261] ([i915#4098]) +17 other tests skip
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-rkl: NOTRUN -> [SKIP][262] ([i915#5286])
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-mtlp: NOTRUN -> [FAIL][263] ([i915#5138])
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][264] ([fdo#111614]) +6 other tests skip
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-6/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-90:
- shard-mtlp: NOTRUN -> [SKIP][265] ([fdo#111614]) +1 other test skip
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-tglu: [PASS][266] -> [FAIL][267] ([i915#3743])
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-tglu-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-tglu-5/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][268] ([fdo#109271]) +77 other tests skip
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- shard-dg2: NOTRUN -> [SKIP][269] ([i915#5190]) +13 other tests skip
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-mtlp: NOTRUN -> [SKIP][270] ([fdo#111615]) +10 other tests skip
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][271] ([i915#4538] / [i915#5190]) +7 other tests skip
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-1/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-addfb:
- shard-mtlp: NOTRUN -> [SKIP][272] ([i915#6187])
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@kms_big_fb@yf-tiled-addfb.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
- shard-rkl: NOTRUN -> [SKIP][273] ([fdo#110723]) +2 other tests skip
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
* igt@kms_big_joiner@2x-modeset:
- shard-mtlp: NOTRUN -> [SKIP][274] ([i915#2705])
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-3/igt@kms_big_joiner@2x-modeset.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][275] ([i915#4087] / [i915#7213]) +4 other tests skip
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-6/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html
* igt@kms_cdclk@plane-scaling@pipe-c-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][276] ([i915#4087]) +3 other tests skip
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@kms_cdclk@plane-scaling@pipe-c-edp-1.html
* igt@kms_chamelium_audio@hdmi-audio-edid:
- shard-mtlp: NOTRUN -> [SKIP][277] ([i915#7828]) +7 other tests skip
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@kms_chamelium_audio@hdmi-audio-edid.html
* igt@kms_chamelium_color@degamma:
- shard-dg2: NOTRUN -> [SKIP][278] ([fdo#111827]) +3 other tests skip
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@kms_chamelium_color@degamma.html
- shard-mtlp: NOTRUN -> [SKIP][279] ([fdo#111827]) +1 other test skip
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@kms_chamelium_color@degamma.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- shard-dg2: NOTRUN -> [SKIP][280] ([i915#7828]) +12 other tests skip
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_frames@hdmi-crc-multiple:
- shard-rkl: NOTRUN -> [SKIP][281] ([i915#7828]) +3 other tests skip
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@kms_chamelium_frames@hdmi-crc-multiple.html
* igt@kms_color@deep-color:
- shard-dg2: NOTRUN -> [SKIP][282] ([i915#3555]) +6 other tests skip
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-1/igt@kms_color@deep-color.html
* igt@kms_color@gamma@pipe-a:
- shard-rkl: [PASS][283] -> [SKIP][284] ([i915#4098]) +2 other tests skip
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-6/igt@kms_color@gamma@pipe-a.html
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_color@gamma@pipe-a.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-dg2: NOTRUN -> [SKIP][285] ([i915#3299])
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-1/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-mtlp: NOTRUN -> [SKIP][286] ([i915#3299])
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@srm@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [TIMEOUT][287] ([i915#7173])
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@kms_content_protection@srm@pipe-a-dp-4.html
* igt@kms_content_protection@type1:
- shard-dg2: NOTRUN -> [SKIP][288] ([i915#7118]) +1 other test skip
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@kms_content_protection@type1.html
* igt@kms_content_protection@uevent:
- shard-mtlp: NOTRUN -> [SKIP][289] ([i915#6944]) +1 other test skip
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@kms_content_protection@uevent.html
* igt@kms_content_protection@uevent@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [FAIL][290] ([i915#1339])
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@kms_content_protection@uevent@pipe-a-dp-4.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-dg2: NOTRUN -> [SKIP][291] ([i915#3359]) +1 other test skip
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-mtlp: NOTRUN -> [SKIP][292] ([i915#3359])
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
- shard-mtlp: NOTRUN -> [SKIP][293] ([fdo#111767] / [i915#3546])
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-3/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
- shard-mtlp: NOTRUN -> [SKIP][294] ([i915#3546]) +2 other tests skip
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-3/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
- shard-rkl: NOTRUN -> [SKIP][295] ([i915#1845] / [i915#4098]) +16 other tests skip
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
- shard-dg2: NOTRUN -> [SKIP][296] ([fdo#109274] / [i915#5354]) +4 other tests skip
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-1/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-rkl: [PASS][297] -> [SKIP][298] ([i915#1845] / [i915#4098]) +12 other tests skip
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-dg2: NOTRUN -> [SKIP][299] ([i915#4103] / [i915#4213])
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
- shard-mtlp: NOTRUN -> [SKIP][300] ([i915#4213])
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_dirtyfb@dirtyfb-ioctl@drrs-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][301] ([i915#9226] / [i915#9261]) +1 other test skip
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-2/igt@kms_dirtyfb@dirtyfb-ioctl@drrs-hdmi-a-2.html
- shard-rkl: NOTRUN -> [SKIP][302] ([i915#9226] / [i915#9261]) +1 other test skip
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@kms_dirtyfb@dirtyfb-ioctl@drrs-hdmi-a-2.html
* igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-1:
- shard-dg1: NOTRUN -> [SKIP][303] ([i915#9227])
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg1-19/igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-1.html
* igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][304] ([i915#9227])
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-2/igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-2.html
- shard-rkl: NOTRUN -> [SKIP][305] ([i915#9227])
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-2.html
* igt@kms_dirtyfb@dirtyfb-ioctl@psr-hdmi-a-1:
- shard-dg1: NOTRUN -> [SKIP][306] ([i915#9226] / [i915#9261]) +1 other test skip
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg1-19/igt@kms_dirtyfb@dirtyfb-ioctl@psr-hdmi-a-1.html
* igt@kms_draw_crc@draw-method-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][307] ([i915#8812])
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@kms_draw_crc@draw-method-mmap-wc.html
* igt@kms_dsc@dsc-basic:
- shard-dg2: NOTRUN -> [SKIP][308] ([i915#3555] / [i915#3840]) +3 other tests skip
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-6/igt@kms_dsc@dsc-basic.html
* igt@kms_dsc@dsc-with-formats:
- shard-mtlp: NOTRUN -> [SKIP][309] ([i915#3555] / [i915#3840])
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@kms_dsc@dsc-with-formats.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-dg2: NOTRUN -> [SKIP][310] ([fdo#109274]) +10 other tests skip
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][311] ([i915#3637]) +6 other tests skip
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][312] ([fdo#111767] / [i915#3637])
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
- shard-dg2: NOTRUN -> [SKIP][313] ([fdo#109274] / [fdo#111767])
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-rmfb-interruptible:
- shard-rkl: NOTRUN -> [SKIP][314] ([fdo#111767] / [fdo#111825])
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
- shard-rkl: NOTRUN -> [SKIP][315] ([fdo#111825]) +5 other tests skip
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-snb: NOTRUN -> [SKIP][316] ([fdo#109271]) +10 other tests skip
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb7/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- shard-rkl: NOTRUN -> [SKIP][317] ([i915#3637] / [i915#4098]) +9 other tests skip
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_flip@basic-flip-vs-wf_vblank.html
* igt@kms_flip@flip-vs-fences:
- shard-mtlp: NOTRUN -> [SKIP][318] ([i915#8381])
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@kms_flip@flip-vs-fences.html
* igt@kms_flip@flip-vs-suspend@c-hdmi-a3:
- shard-dg2: [PASS][319] -> [FAIL][320] ([fdo#103375])
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-dg2-7/igt@kms_flip@flip-vs-suspend@c-hdmi-a3.html
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-1/igt@kms_flip@flip-vs-suspend@c-hdmi-a3.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][321] ([i915#2672]) +5 other tests skip
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][322] ([i915#2672]) +2 other tests skip
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][323] ([i915#2672]) +2 other tests skip
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][324] ([i915#2672] / [i915#3555])
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling:
- shard-rkl: NOTRUN -> [SKIP][325] ([i915#3555]) +6 other tests skip
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][326] ([i915#3555] / [i915#8810])
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite:
- shard-rkl: [PASS][327] -> [SKIP][328] ([i915#1849] / [i915#4098]) +5 other tests skip
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
- shard-dg2: [PASS][329] -> [FAIL][330] ([i915#6880])
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
- shard-mtlp: NOTRUN -> [SKIP][331] ([i915#1825]) +41 other tests skip
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][332] ([i915#3458]) +23 other tests skip
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move:
- shard-dg2: NOTRUN -> [SKIP][333] ([i915#5354]) +30 other tests skip
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
- shard-dg2: NOTRUN -> [SKIP][334] ([i915#5460]) +1 other test skip
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-1/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][335] ([i915#3023]) +5 other tests skip
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-rkl: NOTRUN -> [SKIP][336] ([i915#1849] / [i915#4098]) +17 other tests skip
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render:
- shard-rkl: NOTRUN -> [SKIP][337] ([fdo#111825] / [i915#1825]) +11 other tests skip
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][338] ([i915#8708]) +26 other tests skip
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][339] ([i915#8708]) +11 other tests skip
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html
* igt@kms_getfb@getfb-reject-ccs:
- shard-dg2: NOTRUN -> [SKIP][340] ([i915#6118])
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@kms_getfb@getfb-reject-ccs.html
* igt@kms_hdr@static-swap:
- shard-rkl: NOTRUN -> [SKIP][341] ([i915#3555] / [i915#8228])
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@kms_hdr@static-swap.html
* igt@kms_hdr@static-toggle-suspend:
- shard-mtlp: NOTRUN -> [SKIP][342] ([i915#3555] / [i915#8228]) +1 other test skip
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_invalid_mode@clock-too-high@pipe-c-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][343] ([i915#9457]) +2 other tests skip
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-3/igt@kms_invalid_mode@clock-too-high@pipe-c-edp-1.html
* igt@kms_invalid_mode@int-max-clock:
- shard-rkl: NOTRUN -> [SKIP][344] ([i915#3555] / [i915#4098])
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_invalid_mode@int-max-clock.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: NOTRUN -> [SKIP][345] ([i915#4816])
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_panel_fitting@atomic-fastset:
- shard-dg2: NOTRUN -> [SKIP][346] ([i915#6301])
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@kms_panel_fitting@atomic-fastset.html
* igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c:
- shard-mtlp: NOTRUN -> [SKIP][347] ([fdo#109289]) +2 other tests skip
[347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-3/igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-1:
- shard-apl: [PASS][348] -> [INCOMPLETE][349] ([i915#9392])
[348]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl2/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-1.html
[349]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl1/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-1.html
* igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-dp-1:
- shard-apl: NOTRUN -> [FAIL][350] ([i915#4573]) +1 other test fail
[350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl7/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-dp-1.html
* igt@kms_plane_lowres@tiling-yf:
- shard-mtlp: NOTRUN -> [SKIP][351] ([i915#3555] / [i915#8821])
[351]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_multiple@tiling-y:
- shard-mtlp: NOTRUN -> [SKIP][352] ([i915#3555] / [i915#8806])
[352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@kms_plane_multiple@tiling-y.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-dg2: NOTRUN -> [SKIP][353] ([i915#6953])
[353]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@kms_plane_scaling@intel-max-src-size.html
- shard-rkl: NOTRUN -> [SKIP][354] ([i915#6953] / [i915#8152])
[354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [FAIL][355] ([i915#8292])
[355]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg1-18/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][356] ([i915#5176] / [i915#9423]) +3 other tests skip
[356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg1-13/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][357] ([i915#5235]) +19 other tests skip
[357]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-hdmi-a-3.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][358] ([i915#5235]) +8 other tests skip
[358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-b-edp-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-20x20:
- shard-rkl: NOTRUN -> [SKIP][359] ([i915#8152]) +2 other tests skip
[359]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-20x20.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][360] ([i915#3555] / [i915#5235]) +2 other tests skip
[360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-3/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d-edp-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][361] ([i915#5235]) +19 other tests skip
[361]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg1-18/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-4.html
* igt@kms_prime@basic-crc-hybrid:
- shard-mtlp: NOTRUN -> [SKIP][362] ([i915#6524])
[362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_properties@crtc-properties-atomic:
- shard-rkl: [PASS][363] -> [SKIP][364] ([i915#1849])
[363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-4/igt@kms_properties@crtc-properties-atomic.html
[364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_properties@crtc-properties-atomic.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-glk: NOTRUN -> [SKIP][365] ([fdo#109271] / [i915#658]) +1 other test skip
[365]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk3/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-rkl: NOTRUN -> [SKIP][366] ([i915#658])
[366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-dg2: NOTRUN -> [SKIP][367] ([i915#658]) +3 other tests skip
[367]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@sprite_blt:
- shard-dg2: NOTRUN -> [SKIP][368] ([i915#1072]) +8 other tests skip
[368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@kms_psr@sprite_blt.html
* igt@kms_psr@sprite_plane_onoff:
- shard-rkl: NOTRUN -> [SKIP][369] ([i915#1072]) +4 other tests skip
[369]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_rotation_crc@exhaust-fences:
- shard-mtlp: NOTRUN -> [SKIP][370] ([i915#4235]) +1 other test skip
[370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@kms_rotation_crc@exhaust-fences.html
* igt@kms_rotation_crc@sprite-rotation-270:
- shard-rkl: NOTRUN -> [INCOMPLETE][371] ([i915#8875] / [i915#9569])
[371]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@kms_rotation_crc@sprite-rotation-270.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-dg2: NOTRUN -> [SKIP][372] ([i915#4235])
[372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@kms_setmode@basic-clone-single-crtc:
- shard-mtlp: NOTRUN -> [SKIP][373] ([i915#3555] / [i915#8809]) +1 other test skip
[373]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@kms_setmode@basic-clone-single-crtc.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-mtlp: NOTRUN -> [SKIP][374] ([i915#8623])
[374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_tv_load_detect@load-detect:
- shard-dg2: NOTRUN -> [SKIP][375] ([fdo#109309])
[375]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@kms_tv_load_detect@load-detect.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1:
- shard-tglu: [PASS][376] -> [FAIL][377] ([i915#9196])
[376]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-tglu-2/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1.html
[377]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-tglu-6/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1.html
* igt@kms_vblank@ts-continuation-suspend@pipe-b-hdmi-a-1:
- shard-snb: NOTRUN -> [DMESG-WARN][378] ([i915#8841]) +2 other tests dmesg-warn
[378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-snb1/igt@kms_vblank@ts-continuation-suspend@pipe-b-hdmi-a-1.html
* igt@kms_vrr@flip-suspend:
- shard-mtlp: NOTRUN -> [SKIP][379] ([i915#3555] / [i915#8808]) +1 other test skip
[379]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@kms_vrr@flip-suspend.html
* igt@kms_writeback@writeback-check-output:
- shard-rkl: NOTRUN -> [SKIP][380] ([i915#2437])
[380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id:
- shard-glk: NOTRUN -> [SKIP][381] ([fdo#109271] / [i915#2437])
[381]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk3/igt@kms_writeback@writeback-fb-id.html
- shard-dg2: NOTRUN -> [SKIP][382] ([i915#2437])
[382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@kms_writeback@writeback-fb-id.html
- shard-mtlp: NOTRUN -> [SKIP][383] ([i915#2437])
[383]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@kms_writeback@writeback-fb-id.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- shard-dg2: NOTRUN -> [SKIP][384] ([i915#2436])
[384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@perf@mi-rpc:
- shard-rkl: [PASS][385] -> [SKIP][386] ([i915#2434])
[385]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@perf@mi-rpc.html
[386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-7/igt@perf@mi-rpc.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [PASS][387] -> [FAIL][388] ([i915#7484])
[387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-dg2-5/igt@perf@non-zero-reason@0-rcs0.html
[388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@perf@non-zero-reason@0-rcs0.html
* igt@perf_pmu@busy-double-start@bcs0:
- shard-mtlp: [PASS][389] -> [FAIL][390] ([i915#4349])
[389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-mtlp-5/igt@perf_pmu@busy-double-start@bcs0.html
[390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-3/igt@perf_pmu@busy-double-start@bcs0.html
* igt@perf_pmu@event-wait@rcs0:
- shard-rkl: NOTRUN -> [SKIP][391] ([fdo#112283])
[391]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@perf_pmu@event-wait@rcs0.html
* igt@perf_pmu@frequency@gt0:
- shard-dg2: NOTRUN -> [FAIL][392] ([i915#6806])
[392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-6/igt@perf_pmu@frequency@gt0.html
* igt@perf_pmu@rc6-all-gts:
- shard-rkl: NOTRUN -> [SKIP][393] ([i915#8516])
[393]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@perf_pmu@rc6-all-gts.html
* igt@prime_udl:
- shard-dg2: NOTRUN -> [SKIP][394] ([fdo#109291])
[394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@prime_udl.html
* igt@prime_vgem@basic-fence-mmap:
- shard-dg2: NOTRUN -> [SKIP][395] ([i915#3708] / [i915#4077])
[395]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-6/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- shard-dg2: NOTRUN -> [SKIP][396] ([i915#3291] / [i915#3708])
[396]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@coherency-gtt:
- shard-rkl: NOTRUN -> [SKIP][397] ([fdo#109295] / [fdo#111656] / [i915#3708])
[397]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@prime_vgem@coherency-gtt.html
* igt@prime_vgem@fence-flip-hang:
- shard-mtlp: NOTRUN -> [SKIP][398] ([i915#3708])
[398]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@prime_vgem@fence-flip-hang.html
* igt@syncobj_timeline@invalid-multi-wait-all-available-unsubmitted-signaled:
- shard-mtlp: NOTRUN -> [FAIL][399] ([i915#9583]) +3 other tests fail
[399]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@syncobj_timeline@invalid-multi-wait-all-available-unsubmitted-signaled.html
* igt@syncobj_timeline@invalid-multi-wait-all-available-unsubmitted-submitted:
- shard-rkl: NOTRUN -> [FAIL][400] ([i915#9583])
[400]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@syncobj_timeline@invalid-multi-wait-all-available-unsubmitted-submitted.html
* igt@syncobj_timeline@invalid-multi-wait-available-unsubmitted:
- shard-dg2: NOTRUN -> [FAIL][401] ([i915#9583]) +1 other test fail
[401]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@syncobj_timeline@invalid-multi-wait-available-unsubmitted.html
* igt@syncobj_timeline@invalid-multi-wait-available-unsubmitted-submitted:
- shard-glk: NOTRUN -> [FAIL][402] ([i915#9583])
[402]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk3/igt@syncobj_timeline@invalid-multi-wait-available-unsubmitted-submitted.html
* igt@syncobj_timeline@invalid-single-wait-available-unsubmitted:
- shard-dg2: NOTRUN -> [FAIL][403] ([i915#9582]) +1 other test fail
[403]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@syncobj_timeline@invalid-single-wait-available-unsubmitted.html
* igt@v3d/v3d_create_bo@create-bo-zeroed:
- shard-rkl: NOTRUN -> [SKIP][404] ([fdo#109315]) +4 other tests skip
[404]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@v3d/v3d_create_bo@create-bo-zeroed.html
* igt@v3d/v3d_job_submission@array-job-submission:
- shard-dg2: NOTRUN -> [SKIP][405] ([i915#2575]) +16 other tests skip
[405]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-1/igt@v3d/v3d_job_submission@array-job-submission.html
* igt@v3d/v3d_submit_csd@bad-bo:
- shard-mtlp: NOTRUN -> [SKIP][406] ([i915#2575]) +14 other tests skip
[406]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@v3d/v3d_submit_csd@bad-bo.html
* igt@v3d/v3d_submit_csd@bad-pad:
- shard-glk: NOTRUN -> [SKIP][407] ([fdo#109271]) +72 other tests skip
[407]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk2/igt@v3d/v3d_submit_csd@bad-pad.html
* igt@vc4/vc4_dmabuf_poll@poll-read-waits-until-write-done:
- shard-rkl: NOTRUN -> [SKIP][408] ([i915#7711]) +5 other tests skip
[408]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@vc4/vc4_dmabuf_poll@poll-read-waits-until-write-done.html
* igt@vc4/vc4_mmap@mmap-bo:
- shard-dg2: NOTRUN -> [SKIP][409] ([i915#7711]) +10 other tests skip
[409]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-7/igt@vc4/vc4_mmap@mmap-bo.html
* igt@vc4/vc4_perfmon@get-values-invalid-pointer:
- shard-mtlp: NOTRUN -> [SKIP][410] ([i915#7711]) +7 other tests skip
[410]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-8/igt@vc4/vc4_perfmon@get-values-invalid-pointer.html
#### Possible fixes ####
* igt@api_intel_bb@object-reloc-keep-cache:
- shard-rkl: [SKIP][411] ([i915#8411]) -> [PASS][412]
[411]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-6/igt@api_intel_bb@object-reloc-keep-cache.html
[412]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@api_intel_bb@object-reloc-keep-cache.html
* igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0:
- shard-dg2: [INCOMPLETE][413] ([i915#7297]) -> [PASS][414]
[413]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-dg2-5/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
[414]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
* igt@gem_ctx_persistence@legacy-engines-hang@blt:
- shard-rkl: [SKIP][415] ([i915#6252]) -> [PASS][416]
[415]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@gem_ctx_persistence@legacy-engines-hang@blt.html
[416]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-1/igt@gem_ctx_persistence@legacy-engines-hang@blt.html
* igt@gem_eio@hibernate:
- shard-mtlp: [ABORT][417] ([i915#7975] / [i915#8213] / [i915#9262]) -> [PASS][418]
[417]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-mtlp-2/igt@gem_eio@hibernate.html
[418]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-5/igt@gem_eio@hibernate.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-rkl: [FAIL][419] ([i915#2842]) -> [PASS][420]
[419]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[420]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_reloc@basic-gtt-wc:
- shard-rkl: [SKIP][421] ([i915#3281]) -> [PASS][422] +6 other tests pass
[421]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-4/igt@gem_exec_reloc@basic-gtt-wc.html
[422]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@gem_exec_reloc@basic-gtt-wc.html
* igt@gem_exec_suspend@basic-s3@smem:
- shard-mtlp: [FAIL][423] ([fdo#103375]) -> [PASS][424] +4 other tests pass
[423]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-mtlp-5/igt@gem_exec_suspend@basic-s3@smem.html
[424]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-6/igt@gem_exec_suspend@basic-s3@smem.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg1: [DMESG-WARN][425] ([i915#4936] / [i915#5493]) -> [PASS][426]
[425]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html
[426]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg1-13/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_mmap_wc@set-cache-level:
- shard-rkl: [SKIP][427] ([i915#1850]) -> [PASS][428]
[427]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@gem_mmap_wc@set-cache-level.html
[428]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-7/igt@gem_mmap_wc@set-cache-level.html
* igt@gem_pread@self:
- shard-rkl: [SKIP][429] ([i915#3282]) -> [PASS][430]
[429]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-6/igt@gem_pread@self.html
[430]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@gem_pread@self.html
* igt@gen9_exec_parse@batch-zero-length:
- shard-rkl: [SKIP][431] ([i915#2527]) -> [PASS][432]
[431]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-4/igt@gen9_exec_parse@batch-zero-length.html
[432]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@gen9_exec_parse@batch-zero-length.html
* igt@i915_pm_rps@engine-order:
- shard-apl: [FAIL][433] ([i915#6537]) -> [PASS][434]
[433]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl1/igt@i915_pm_rps@engine-order.html
[434]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl1/igt@i915_pm_rps@engine-order.html
* igt@i915_power@sanity:
- shard-rkl: [SKIP][435] ([i915#7984]) -> [PASS][436]
[435]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-4/igt@i915_power@sanity.html
[436]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@i915_power@sanity.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-180:
- shard-mtlp: [FAIL][437] ([i915#5138]) -> [PASS][438]
[437]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-mtlp-6/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
[438]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-2/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-tglu: [FAIL][439] ([i915#3743]) -> [PASS][440] +1 other test pass
[439]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-tglu-7/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
[440]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-tglu-8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* {igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs}:
- shard-rkl: [SKIP][441] ([i915#4098]) -> [PASS][442] +11 other tests pass
[441]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs.html
[442]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-7/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y-tiled-gen12-rc-ccs.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [FAIL][443] ([i915#2346]) -> [PASS][444] +1 other test pass
[443]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[444]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@fbc:
- shard-rkl: [SKIP][445] ([i915#1849] / [i915#4098]) -> [PASS][446] +8 other tests pass
[445]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@kms_fbcon_fbt@fbc.html
[446]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-7/igt@kms_fbcon_fbt@fbc.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][447] ([i915#79]) -> [PASS][448]
[447]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
[448]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-edp1:
- shard-mtlp: [ABORT][449] ([i915#9414]) -> [PASS][450]
[449]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-mtlp-7/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
[450]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-3/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
* {igt@kms_pm_rpm@i2c}:
- shard-dg2: [FAIL][451] ([i915#8717]) -> [PASS][452]
[451]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-dg2-2/igt@kms_pm_rpm@i2c.html
[452]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-6/igt@kms_pm_rpm@i2c.html
- shard-rkl: [SKIP][453] ([fdo#109308]) -> [PASS][454]
[453]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@kms_pm_rpm@i2c.html
[454]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-1/igt@kms_pm_rpm@i2c.html
* {igt@kms_pm_rpm@modeset-lpsp-stress-no-wait}:
- shard-rkl: [SKIP][455] ([i915#9519]) -> [PASS][456]
[455]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-2/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
[456]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-7/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
* {igt@kms_pm_rpm@modeset-non-lpsp}:
- shard-dg2: [SKIP][457] ([i915#9519]) -> [PASS][458]
[457]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-dg2-10/igt@kms_pm_rpm@modeset-non-lpsp.html
[458]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-1/igt@kms_pm_rpm@modeset-non-lpsp.html
* {igt@kms_pm_rpm@system-suspend-modeset}:
- shard-dg2: [FAIL][459] ([fdo#103375]) -> [PASS][460]
[459]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-dg2-5/igt@kms_pm_rpm@system-suspend-modeset.html
[460]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-dg2-11/igt@kms_pm_rpm@system-suspend-modeset.html
* igt@kms_properties@plane-properties-legacy:
- shard-rkl: [SKIP][461] ([i915#1849]) -> [PASS][462] +1 other test pass
[461]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@kms_properties@plane-properties-legacy.html
[462]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-7/igt@kms_properties@plane-properties-legacy.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-rkl: [SKIP][463] ([i915#1845] / [i915#4098]) -> [PASS][464] +13 other tests pass
[463]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@kms_rotation_crc@primary-rotation-90.html
[464]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-1/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
- shard-rkl: [INCOMPLETE][465] ([i915#9475]) -> [PASS][466]
[465]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-4/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
[466]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-4/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1:
- shard-tglu: [FAIL][467] ([i915#9196]) -> [PASS][468]
[467]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-tglu-2/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
[468]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-tglu-6/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
* igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-dp-1:
- shard-apl: [INCOMPLETE][469] ([i915#4839]) -> [PASS][470]
[469]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-apl1/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-dp-1.html
[470]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-apl1/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-dp-1.html
* igt@perf_pmu@busy-double-start@ccs0:
- shard-mtlp: [FAIL][471] ([i915#4349]) -> [PASS][472]
[471]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-mtlp-5/igt@perf_pmu@busy-double-start@ccs0.html
[472]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-mtlp-3/igt@perf_pmu@busy-double-start@ccs0.html
#### Warnings ####
* igt@gem_ccs@block-multicopy-inplace:
- shard-rkl: [SKIP][473] ([i915#3555]) -> [SKIP][474] ([i915#7957])
[473]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-6/igt@gem_ccs@block-multicopy-inplace.html
[474]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@gem_ccs@block-multicopy-inplace.html
* igt@gem_exec_fair@basic-none@bcs0:
- shard-rkl: [FAIL][475] ([i915#2842]) -> [SKIP][476] ([i915#9591])
[475]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-6/igt@gem_exec_fair@basic-none@bcs0.html
[476]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@gem_exec_fair@basic-none@bcs0.html
* igt@gem_pread@exhaustion:
- shard-rkl: [SKIP][477] ([i915#3282]) -> [WARN][478] ([i915#2658])
[477]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-4/igt@gem_pread@exhaustion.html
[478]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@gem_pread@exhaustion.html
* igt@gem_pwrite@basic-exhaustion:
- shard-rkl: [WARN][479] ([i915#2658]) -> [SKIP][480] ([i915#3282])
[479]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@gem_pwrite@basic-exhaustion.html
[480]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-1/igt@gem_pwrite@basic-exhaustion.html
* igt@gen9_exec_parse@bb-oversize:
- shard-rkl: [SKIP][481] ([i915#2532]) -> [SKIP][482] ([i915#2527])
[481]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@gen9_exec_parse@bb-oversize.html
[482]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-7/igt@gen9_exec_parse@bb-oversize.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-rkl: [SKIP][483] ([i915#1845] / [i915#4098]) -> [SKIP][484] ([i915#1769] / [i915#3555])
[483]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
[484]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-7/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-90:
- shard-rkl: [SKIP][485] ([i915#5286]) -> [SKIP][486] ([i915#4098]) +2 other tests skip
[485]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-4/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
[486]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-rkl: [SKIP][487] ([i915#4098]) -> [SKIP][488] ([i915#5286]) +4 other tests skip
[487]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
[488]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@linear-8bpp-rotate-90:
- shard-rkl: [SKIP][489] ([fdo#111614] / [i915#3638]) -> [SKIP][490] ([i915#1845] / [i915#4098])
[489]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-4/igt@kms_big_fb@linear-8bpp-rotate-90.html
[490]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_big_fb@linear-8bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-90:
- shard-rkl: [SKIP][491] ([i915#1845] / [i915#4098]) -> [SKIP][492] ([fdo#111614] / [i915#3638]) +2 other tests skip
[491]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
[492]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-7/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
- shard-rkl: [SKIP][493] ([i915#1845] / [i915#4098]) -> [SKIP][494] ([fdo#110723]) +5 other tests skip
[493]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html
[494]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-7/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
- shard-rkl: [SKIP][495] ([fdo#110723]) -> [SKIP][496] ([i915#1845] / [i915#4098]) +1 other test skip
[495]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-6/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
[496]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-addfb:
- shard-rkl: [SKIP][497] ([i915#1845] / [i915#4098]) -> [SKIP][498] ([fdo#111615])
[497]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@kms_big_fb@yf-tiled-addfb.html
[498]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-7/igt@kms_big_fb@yf-tiled-addfb.html
* igt@kms_content_protection@atomic-dpms:
- shard-rkl: [SKIP][499] ([i915#7118]) -> [SKIP][500] ([i915#1845] / [i915#4098])
[499]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-4/igt@kms_content_protection@atomic-dpms.html
[500]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_content_protection@atomic-dpms.html
* igt@kms_cursor_crc@cursor-offscreen-512x170:
- shard-rkl: [SKIP][501] ([i915#4098]) -> [SKIP][502] ([fdo#109279] / [i915#3359])
[501]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@kms_cursor_crc@cursor-offscreen-512x170.html
[502]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-7/igt@kms_cursor_crc@cursor-offscreen-512x170.html
* igt@kms_cursor_crc@cursor-offscreen-max-size:
- shard-rkl: [SKIP][503] ([i915#4098]) -> [SKIP][504] ([i915#3555]) +1 other test skip
[503]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@kms_cursor_crc@cursor-offscreen-max-size.html
[504]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-1/igt@kms_cursor_crc@cursor-offscreen-max-size.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-rkl: [SKIP][505] ([i915#4098]) -> [SKIP][506] ([i915#3359]) +1 other test skip
[505]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@kms_cursor_crc@cursor-random-512x170.html
[506]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-7/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-rkl: [SKIP][507] ([i915#3359]) -> [SKIP][508] ([i915#4098])
[507]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-4/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
[508]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-rkl: [SKIP][509] ([i915#1845] / [i915#4098]) -> [SKIP][510] ([fdo#111825]) +3 other tests skip
[509]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
[510]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-1/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
- shard-rkl: [SKIP][511] ([fdo#111825]) -> [SKIP][512] ([i915#1845] / [i915#4098]) +1 other test skip
[511]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-4/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
[512]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-rkl: [SKIP][513] ([i915#1845] / [i915#4098]) -> [SKIP][514] ([i915#4103])
[513]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
[514]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-7/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_dsc@dsc-with-bpc:
- shard-rkl: [SKIP][515] ([i915#3555] / [i915#3840]) -> [SKIP][516] ([i915#4098])
[515]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-4/igt@kms_dsc@dsc-with-bpc.html
[516]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-5/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_fbcon_fbt@psr:
- shard-rkl: [SKIP][517] ([fdo#110189] / [i915#3955]) -> [SKIP][518] ([i915#3955])
[517]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13814/shard-rkl-5/igt@kms_fbcon_fbt@psr.html
[518]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/shard-rkl-7/igt@kms_fbcon_fbt@psr.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: [SKIP][519] ([i915#3955]) -> [SKIP][520] ([fdo#110189] / [i915#3955])
[519]: https://intel-gfx-ci.0
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v8/index.html
[-- Attachment #2: Type: text/html, Size: 110098 bytes --]
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (34 preceding siblings ...)
2023-11-02 11:44 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2023-11-03 22:43 ` Lyude Paul
2023-11-07 1:28 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on MST links (rev16) Patchwork
` (3 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Lyude Paul @ 2023-11-03 22:43 UTC (permalink / raw)
To: Imre Deak, intel-gfx
BTW - sorry it took me a little while to get back to this, I'm still getting
back into the swing of things but I should be able to review this next week :)
Thanks for all of the work you've done so far!
On Mon, 2023-10-30 at 17:58 +0200, Imre Deak wrote:
> This is v4 of [1] with the following changes:
>
> - Fix a race condition between connector setup and registration
> (added patch 1).
> - Rename DRM_DP_OVERHEAD_SSC to DRM_DP_OVERHEAD_SSC_REF_CLK
> (Ville, patch 9).
> - Fix setting crtc_state->fec_enable, once crtc_state->port_clock
> required for it is already set (patch 10).
> - Fix passing the correct fec_enable parameter to
> intel_dp_bw_fec_overhead() (patch 12).
> - Fix TU size, making it match the payload size in the payload table
> (Patch 13).
> - Apply the HBLANK expansion quirk whenever the HBLANK period is
> 300ns or less (Patch 21).
> - Fix refcounting of the DSC AUX decompression device
> (Stan, patch 25).
> - Fix HW readout/sanitize for the connector DSC decompression enabled
> state (patch 25).
> - Move intel_crtc_needs_modeset() check to callers of
> clear_pipe_update_flags_on_modeset_crtc() (Ville, patch 26).
> - Fix forcing modeset on CRTC due to a change in MST topology
> (Ville, patch 27).
> - Add missing DocBooks, fix typos.
>
> [1] https://lore.kernel.org/all/20231024010925.3949910-1-imre.deak@intel.com
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Cc: Arun R Murthy <arun.r.murthy@intel.com>
>
> Imre Deak (28):
> drm/i915/dp_mst: Fix race between connector registration and setup
> drm/dp_mst: Add helper to determine if an MST port is downstream of
> another port
> drm/dp_mst: Factor out a helper to check the atomic state of a
> topology manager
> drm/dp_mst: Swap the order of checking root vs. non-root port BW
> limitations
> drm/dp_mst: Allow DSC in any Synaptics last branch device
> drm/dp: Add DP_HBLANK_EXPANSION_CAPABLE and DSC_PASSTHROUGH_EN DPCD
> flags
> drm/dp_mst: Add HBLANK expansion quirk for Synaptics MST hubs
> drm/dp: Add helpers to calculate the link BW overhead
> drm/i915/dp_mst: Enable FEC early once it's known DSC is needed
> drm/i915/dp: Specify the FEC overhead as an increment vs. a remainder
> drm/i915/dp: Pass actual BW overhead to m_n calculation
> drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation
> drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms
> drm/i915/dp_mst: Program the DSC PPS SDP for each stream
> drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is
> disabled
> drm/i915/dp_mst: Add missing DSC compression disabling
> drm/i915/dp: Rename intel_ddi_disable_fec_state() to
> intel_ddi_disable_fec()
> drm/i915/dp: Wait for FEC detected status in the sink
> drm/i915/dp: Disable FEC ready flag in the sink
> drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk
> drm/i915/dp_mst: Enable decompression in the sink from the MST encoder
> hooks
> drm/i915/dp: Enable DSC via the connector decompression AUX
> drm/i915/dp_mst: Enable DSC passthrough
> drm/i915/dp_mst: Enable MST DSC decompression for all streams
> drm/i915: Factor out function to clear pipe update flags
> drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires it
> drm/i915/dp_mst: Improve BW sharing between MST streams
> drm/i915/dp_mst: Check BW limitations only after all streams are
> computed
>
> Stanislav Lisovskiy (1):
> drm/i915: Query compressed bpp properly using correct DPCD and DP Spec
> info
>
> Ville Syrjälä (1):
> drm/dp_mst: Fix fractional DSC bpp handling
>
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
> drivers/gpu/drm/display/drm_dp_helper.c | 134 +++++
> drivers/gpu/drm/display/drm_dp_mst_topology.c | 206 +++++--
> drivers/gpu/drm/i915/display/intel_ddi.c | 136 ++++-
> drivers/gpu/drm/i915/display/intel_ddi.h | 3 +
> drivers/gpu/drm/i915/display/intel_display.c | 101 ++--
> drivers/gpu/drm/i915/display/intel_display.h | 4 +-
> .../drm/i915/display/intel_display_types.h | 3 +
> drivers/gpu/drm/i915/display/intel_dp.c | 256 +++++++-
> drivers/gpu/drm/i915/display/intel_dp.h | 23 +-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 564 +++++++++++++++---
> drivers/gpu/drm/i915/display/intel_dp_mst.h | 5 +
> drivers/gpu/drm/i915/display/intel_fdi.c | 5 +-
> drivers/gpu/drm/i915/display/intel_link_bw.c | 16 +-
> drivers/gpu/drm/i915/display/intel_link_bw.h | 1 +
> .../drm/i915/display/intel_modeset_setup.c | 6 +
> drivers/gpu/drm/nouveau/dispnv50/disp.c | 3 +-
> .../gpu/drm/tests/drm_dp_mst_helper_test.c | 6 +-
> include/drm/display/drm_dp.h | 2 +
> include/drm/display/drm_dp_helper.h | 18 +
> include/drm/display/drm_dp_mst_helper.h | 9 +-
> 22 files changed, 1270 insertions(+), 235 deletions(-)
>
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
^ permalink raw reply [flat|nested] 94+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on MST links (rev16)
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (35 preceding siblings ...)
2023-11-03 22:43 ` [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Lyude Paul
@ 2023-11-07 1:28 ` Patchwork
2023-11-07 1:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
39 siblings, 0 replies; 94+ messages in thread
From: Patchwork @ 2023-11-07 1:28 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Improve BW management on MST links (rev16)
URL : https://patchwork.freedesktop.org/series/125490/
State : warning
== Summary ==
Error: dim checkpatch failed
7c2ff14192aa drm/i915/dp_mst: Fix race between connector registration and setup
3ddb8fb6b152 drm/dp_mst: Fix fractional DSC bpp handling
a880f8588c27 drm/dp_mst: Add helper to determine if an MST port is downstream of another port
3563665ec2b6 drm/dp_mst: Factor out a helper to check the atomic state of a topology manager
0455c3a13132 drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations
eb065c73226a drm/dp_mst: Allow DSC in any Synaptics last branch device
52dd2c737276 drm/dp: Add DP_HBLANK_EXPANSION_CAPABLE and DSC_PASSTHROUGH_EN DPCD flags
db6aa30cc4c4 drm/dp_mst: Add HBLANK expansion quirk for Synaptics MST hubs
-:27: WARNING:LONG_LINE_COMMENT: line length of 103 exceeds 100 columns
#27: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2248:
+ /* Synaptics DP1.4 MST hubs require DSC for some modes on which it applies HBLANK expansion. */
-:28: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#28: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2249:
+ { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
total: 0 errors, 2 warnings, 0 checks, 21 lines checked
d8070519d92f drm/dp: Add helpers to calculate the link BW overhead
-:189: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#189: FILE: drivers/gpu/drm/display/drm_dp_helper.c:4026:
+ return 967100;
+ else
total: 0 errors, 1 warnings, 0 checks, 184 lines checked
670895fde1b7 drm/i915/dp_mst: Enable FEC early once it's known DSC is needed
1c7d2a43854c drm/i915/dp: Specify the FEC overhead as an increment vs. a remainder
426af8244abb drm/i915/dp: Pass actual BW overhead to m_n calculation
595c839f30ca drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation
822b677dc0d1 drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms
1f34ef565508 drm/i915/dp_mst: Program the DSC PPS SDP for each stream
bb67bb6f6118 drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled
0a39af92185b drm/i915/dp_mst: Add missing DSC compression disabling
1bc3fc51e963 drm/i915/dp: Rename intel_ddi_disable_fec_state() to intel_ddi_disable_fec()
ac3f04fc6901 drm/i915/dp: Wait for FEC detected status in the sink
15cb069f5551 drm/i915/dp: Disable FEC ready flag in the sink
7ea3b4d6eccb drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk
0f92537096dd drm/i915/dp_mst: Enable decompression in the sink from the MST encoder hooks
95e452a8965e drm/i915/dp: Enable DSC via the connector decompression AUX
a4e5bd38ee12 drm/i915/dp_mst: Enable DSC passthrough
714cb24cac97 drm/i915/dp_mst: Enable MST DSC decompression for all streams
0e794cbc4123 drm/i915: Factor out function to clear pipe update flags
-:70: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#70: FILE: drivers/gpu/drm/i915/display/intel_display.c:5706:
+ if ((old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
total: 0 errors, 1 warnings, 0 checks, 88 lines checked
22d2ca44735c drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires it
39e97673b217 drm/i915/dp_mst: Improve BW sharing between MST streams
c873fa1d162e drm/i915/dp_mst: Check BW limitations only after all streams are computed
54df926b454a drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info
^ permalink raw reply [flat|nested] 94+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Improve BW management on MST links (rev16)
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (36 preceding siblings ...)
2023-11-07 1:28 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on MST links (rev16) Patchwork
@ 2023-11-07 1:28 ` Patchwork
2023-11-07 1:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-11-07 9:50 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
39 siblings, 0 replies; 94+ messages in thread
From: Patchwork @ 2023-11-07 1:28 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Improve BW management on MST links (rev16)
URL : https://patchwork.freedesktop.org/series/125490/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 94+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Improve BW management on MST links (rev16)
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (37 preceding siblings ...)
2023-11-07 1:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-11-07 1:41 ` Patchwork
2023-11-07 9:50 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
39 siblings, 0 replies; 94+ messages in thread
From: Patchwork @ 2023-11-07 1:41 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5518 bytes --]
== Series Details ==
Series: drm/i915: Improve BW management on MST links (rev16)
URL : https://patchwork.freedesktop.org/series/125490/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13844 -> Patchwork_125490v16
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/index.html
Participating hosts (33 -> 31)
------------------------------
Missing (2): bat-adlp-11 fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_125490v16 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][1] ([i915#7978] / [i915#9631])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/bat-rpls-1/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [PASS][2] -> [FAIL][3] ([IGT#3])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- fi-rkl-11600: [FAIL][4] ([fdo#103375]) -> [PASS][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/fi-rkl-11600/igt@gem_exec_suspend@basic-s0@smem.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/fi-rkl-11600/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][6] ([i915#5334]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@workarounds:
- bat-rpls-1: [INCOMPLETE][8] -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/bat-rpls-1/igt@i915_selftest@live@workarounds.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/bat-rpls-1/igt@i915_selftest@live@workarounds.html
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#9631]: https://gitlab.freedesktop.org/drm/intel/issues/9631
Build changes
-------------
* Linux: CI_DRM_13844 -> Patchwork_125490v16
CI-20190529: 20190529
CI_DRM_13844: 98a039fc048898d9ecec16153267968fd18a5a52 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7574: 0485a4bf66f69aaf7244a3e689402b522f636780 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_125490v16: 98a039fc048898d9ecec16153267968fd18a5a52 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
00ffe2cb401d drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info
07edaac2b3e8 drm/i915/dp_mst: Check BW limitations only after all streams are computed
ab0f11f7cbcb drm/i915/dp_mst: Improve BW sharing between MST streams
b2a102ea5143 drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires it
95d629cb30f3 drm/i915: Factor out function to clear pipe update flags
766324a18ac2 drm/i915/dp_mst: Enable MST DSC decompression for all streams
a65145fe4476 drm/i915/dp_mst: Enable DSC passthrough
97346f74dfaa drm/i915/dp: Enable DSC via the connector decompression AUX
4a453f366092 drm/i915/dp_mst: Enable decompression in the sink from the MST encoder hooks
2c62b16c173e drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk
62a34f5076ea drm/i915/dp: Disable FEC ready flag in the sink
4ed6a9950148 drm/i915/dp: Wait for FEC detected status in the sink
bca078d9b963 drm/i915/dp: Rename intel_ddi_disable_fec_state() to intel_ddi_disable_fec()
ff9aac6d8dd5 drm/i915/dp_mst: Add missing DSC compression disabling
f27a60c9027b drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled
644a564e38cc drm/i915/dp_mst: Program the DSC PPS SDP for each stream
dfa14b3b77f9 drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms
5b13209046aa drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation
f8ee10079f67 drm/i915/dp: Pass actual BW overhead to m_n calculation
acbf8cf8f789 drm/i915/dp: Specify the FEC overhead as an increment vs. a remainder
8ab47a012cd9 drm/i915/dp_mst: Enable FEC early once it's known DSC is needed
6a73b43d5a03 drm/dp: Add helpers to calculate the link BW overhead
3543c0ae6f14 drm/dp_mst: Add HBLANK expansion quirk for Synaptics MST hubs
2de99e537246 drm/dp: Add DP_HBLANK_EXPANSION_CAPABLE and DSC_PASSTHROUGH_EN DPCD flags
d174b202711f drm/dp_mst: Allow DSC in any Synaptics last branch device
9aaae5e4bdf9 drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations
e0d7271edaf6 drm/dp_mst: Factor out a helper to check the atomic state of a topology manager
7e37e6bedf15 drm/dp_mst: Add helper to determine if an MST port is downstream of another port
c5e975c5cb2b drm/dp_mst: Fix fractional DSC bpp handling
5d58750803d2 drm/i915/dp_mst: Fix race between connector registration and setup
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/index.html
[-- Attachment #2: Type: text/html, Size: 6421 bytes --]
^ permalink raw reply [flat|nested] 94+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Improve BW management on MST links (rev16)
2023-10-30 15:58 [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links Imre Deak
` (38 preceding siblings ...)
2023-11-07 1:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-11-07 9:50 ` Patchwork
2023-11-08 15:59 ` Imre Deak
39 siblings, 1 reply; 94+ messages in thread
From: Patchwork @ 2023-11-07 9:50 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 95260 bytes --]
== Series Details ==
Series: drm/i915: Improve BW management on MST links (rev16)
URL : https://patchwork.freedesktop.org/series/125490/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13844_full -> Patchwork_125490v16_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_125490v16_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_125490v16_full, please notify your bug team (lgci.bug.filing@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/index.html
Participating hosts (11 -> 10)
------------------------------
Missing (1): shard-mtlp0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_125490v16_full:
### IGT changes ###
#### Warnings ####
* igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- shard-snb: [SKIP][1] ([fdo#109271]) -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-snb2/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-snb6/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
Known issues
------------
Here are the changes found in Patchwork_125490v16_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-keep-cache:
- shard-rkl: [PASS][3] -> [SKIP][4] ([i915#8411]) +1 other test skip
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@api_intel_bb@blit-reloc-keep-cache.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-6/igt@api_intel_bb@blit-reloc-keep-cache.html
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-mtlp: NOTRUN -> [SKIP][5] ([i915#8411])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@api_intel_bb@blit-reloc-purge-cache.html
* igt@api_intel_bb@render-ccs:
- shard-dg2: NOTRUN -> [FAIL][6] ([i915#6122])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@api_intel_bb@render-ccs.html
* igt@drm_fdinfo@virtual-busy-hang:
- shard-mtlp: NOTRUN -> [SKIP][7] ([i915#8414])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@drm_fdinfo@virtual-busy-hang.html
* igt@fbdev@eof:
- shard-rkl: [PASS][8] -> [SKIP][9] ([i915#2582]) +1 other test skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@fbdev@eof.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@fbdev@eof.html
* igt@gem_ccs@block-multicopy-compressed:
- shard-rkl: NOTRUN -> [SKIP][10] ([i915#9323])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@gem_ccs@block-multicopy-compressed.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-rkl: NOTRUN -> [SKIP][11] ([i915#4098] / [i915#9323])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_close_race@multigpu-basic-process:
- shard-rkl: NOTRUN -> [SKIP][12] ([i915#7697])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_close_race@multigpu-basic-threads:
- shard-dg2: NOTRUN -> [SKIP][13] ([i915#7697])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gem_close_race@multigpu-basic-threads.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-mtlp: NOTRUN -> [SKIP][14] ([i915#6335])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_create@create-ext-set-pat:
- shard-rkl: NOTRUN -> [SKIP][15] ([i915#8562])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_isolation@preservation-s3@ccs2:
- shard-dg2: [PASS][16] -> [FAIL][17] ([fdo#103375]) +4 other tests fail
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-dg2-1/igt@gem_ctx_isolation@preservation-s3@ccs2.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-5/igt@gem_ctx_isolation@preservation-s3@ccs2.html
* igt@gem_ctx_persistence@heartbeat-hang:
- shard-dg2: NOTRUN -> [SKIP][18] ([i915#8555])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@gem_ctx_persistence@heartbeat-hang.html
* igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0:
- shard-dg2: NOTRUN -> [SKIP][19] ([i915#5882]) +9 other tests skip
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0.html
* igt@gem_ctx_sseu@invalid-args:
- shard-dg2: NOTRUN -> [SKIP][20] ([i915#280])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@gem_ctx_sseu@invalid-args.html
- shard-rkl: NOTRUN -> [SKIP][21] ([i915#280])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@gem_ctx_sseu@invalid-args.html
* igt@gem_eio@hibernate:
- shard-mtlp: [PASS][22] -> [ABORT][23] ([i915#7975] / [i915#8213] / [i915#9414])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-mtlp-1/igt@gem_eio@hibernate.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@gem_eio@hibernate.html
* igt@gem_exec_balancer@bonded-dual:
- shard-mtlp: NOTRUN -> [SKIP][24] ([i915#4771])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@gem_exec_balancer@bonded-dual.html
* igt@gem_exec_balancer@bonded-false-hang:
- shard-dg2: NOTRUN -> [SKIP][25] ([i915#4812]) +1 other test skip
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gem_exec_balancer@bonded-false-hang.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-rkl: NOTRUN -> [SKIP][26] ([i915#4525]) +2 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_endless@dispatch@bcs0:
- shard-rkl: [PASS][27] -> [SKIP][28] ([i915#9591])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@gem_exec_endless@dispatch@bcs0.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@gem_exec_endless@dispatch@bcs0.html
* igt@gem_exec_fair@basic-none-solo:
- shard-mtlp: NOTRUN -> [SKIP][29] ([i915#4473])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@gem_exec_fair@basic-none-solo.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-rkl: NOTRUN -> [FAIL][30] ([i915#2842])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-tglu: [PASS][31] -> [FAIL][32] ([i915#2842])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-tglu-9/igt@gem_exec_fair@basic-pace-share@rcs0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-tglu-3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-rkl: [PASS][33] -> [FAIL][34] ([i915#2842]) +2 other tests fail
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@gem_exec_fair@basic-pace@vecs0.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-6/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_flush@basic-uc-pro-default:
- shard-dg2: NOTRUN -> [SKIP][35] ([i915#3539] / [i915#4852]) +5 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gem_exec_flush@basic-uc-pro-default.html
* igt@gem_exec_params@secure-non-master:
- shard-dg2: NOTRUN -> [SKIP][36] ([fdo#112283])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gem_exec_params@secure-non-master.html
* igt@gem_exec_params@secure-non-root:
- shard-mtlp: NOTRUN -> [SKIP][37] ([fdo#112283])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@gem_exec_params@secure-non-root.html
* igt@gem_exec_reloc@basic-gtt-read:
- shard-dg2: NOTRUN -> [SKIP][38] ([i915#3281]) +14 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@gem_exec_reloc@basic-gtt-read.html
* igt@gem_exec_reloc@basic-softpin:
- shard-mtlp: NOTRUN -> [SKIP][39] ([i915#3281])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@gem_exec_reloc@basic-softpin.html
* igt@gem_exec_reloc@basic-write-read:
- shard-rkl: NOTRUN -> [SKIP][40] ([i915#3281]) +12 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@gem_exec_reloc@basic-write-read.html
* igt@gem_exec_reloc@basic-write-wc-noreloc:
- shard-rkl: [PASS][41] -> [SKIP][42] ([i915#3281]) +10 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@gem_exec_reloc@basic-write-wc-noreloc.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-2/igt@gem_exec_reloc@basic-write-wc-noreloc.html
* igt@gem_exec_suspend@basic-s4-devices@smem:
- shard-rkl: NOTRUN -> [ABORT][43] ([i915#7975] / [i915#8213])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@gem_exec_suspend@basic-s4-devices@smem.html
* igt@gem_fence_thrash@bo-write-verify-x:
- shard-dg2: NOTRUN -> [SKIP][44] ([i915#4860]) +1 other test skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@gem_fence_thrash@bo-write-verify-x.html
* igt@gem_lmem_swapping@heavy-verify-multi:
- shard-glk: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#4613]) +1 other test skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-glk5/igt@gem_lmem_swapping@heavy-verify-multi.html
* igt@gem_lmem_swapping@smem-oom:
- shard-mtlp: NOTRUN -> [SKIP][46] ([i915#4613]) +2 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [PASS][47] -> [TIMEOUT][48] ([i915#5493])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-dg2-7/igt@gem_lmem_swapping@smem-oom@lmem0.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-5/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_lmem_swapping@verify:
- shard-apl: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#4613]) +2 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-apl4/igt@gem_lmem_swapping@verify.html
* igt@gem_lmem_swapping@verify-random:
- shard-rkl: NOTRUN -> [SKIP][50] ([i915#4613]) +1 other test skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@big-bo:
- shard-dg2: NOTRUN -> [SKIP][51] ([i915#4083]) +6 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gem_mmap@big-bo.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-dg2: NOTRUN -> [SKIP][52] ([i915#4077]) +17 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@gem_mmap_gtt@isolation:
- shard-mtlp: NOTRUN -> [SKIP][53] ([i915#4077])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@gem_mmap_gtt@isolation.html
* igt@gem_mmap_wc@write-read-distinct:
- shard-mtlp: NOTRUN -> [SKIP][54] ([i915#4083]) +1 other test skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@gem_mmap_wc@write-read-distinct.html
* igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
- shard-dg2: NOTRUN -> [SKIP][55] ([i915#3282]) +5 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-rkl: NOTRUN -> [SKIP][56] ([i915#3282]) +5 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gem_pwrite@basic-random:
- shard-rkl: [PASS][57] -> [SKIP][58] ([i915#3282]) +10 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@gem_pwrite@basic-random.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-2/igt@gem_pwrite@basic-random.html
* igt@gem_pxp@create-regular-context-2:
- shard-dg2: NOTRUN -> [SKIP][59] ([i915#4270]) +3 other tests skip
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@gem_pxp@create-regular-context-2.html
- shard-rkl: NOTRUN -> [SKIP][60] ([i915#4270]) +1 other test skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@gem_pxp@create-regular-context-2.html
* igt@gem_readwrite@write-bad-handle:
- shard-mtlp: NOTRUN -> [SKIP][61] ([i915#3282]) +1 other test skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@gem_readwrite@write-bad-handle.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs:
- shard-rkl: NOTRUN -> [SKIP][62] ([i915#768]) +3 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs.html
* igt@gem_render_copy@y-tiled-to-vebox-y-tiled:
- shard-mtlp: NOTRUN -> [SKIP][63] ([i915#8428]) +3 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@gem_render_copy@y-tiled-to-vebox-y-tiled.html
* igt@gem_set_tiling_vs_blt@tiled-to-tiled:
- shard-rkl: NOTRUN -> [SKIP][64] ([i915#8411])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-mtlp: NOTRUN -> [SKIP][65] ([i915#4079])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gem_softpin@evict-snoop:
- shard-dg2: NOTRUN -> [SKIP][66] ([i915#4885])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@gem_softpin@evict-snoop.html
* igt@gem_spin_batch@spin-all-new:
- shard-dg2: NOTRUN -> [FAIL][67] ([i915#5889])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gem_spin_batch@spin-all-new.html
* igt@gem_tiled_pread_pwrite:
- shard-dg2: NOTRUN -> [SKIP][68] ([i915#4079]) +1 other test skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gem_tiled_pread_pwrite.html
* igt@gem_unfence_active_buffers:
- shard-dg2: NOTRUN -> [SKIP][69] ([i915#4879])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@gem_unfence_active_buffers.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-rkl: NOTRUN -> [SKIP][70] ([i915#3323])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-mtlp: NOTRUN -> [SKIP][71] ([i915#3297])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@invalid-mmap-offset-unsync:
- shard-dg2: NOTRUN -> [SKIP][72] ([i915#3297]) +3 other tests skip
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
- shard-rkl: NOTRUN -> [SKIP][73] ([i915#3297]) +1 other test skip
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-dg2: NOTRUN -> [SKIP][74] ([i915#3297] / [i915#4880]) +1 other test skip
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@vma-merge:
- shard-dg2: NOTRUN -> [FAIL][75] ([i915#3318])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@gem_userptr_blits@vma-merge.html
- shard-rkl: NOTRUN -> [FAIL][76] ([i915#3318])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@allowed-all:
- shard-dg2: NOTRUN -> [SKIP][77] ([i915#2856]) +5 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@allowed-single:
- shard-mtlp: NOTRUN -> [SKIP][78] ([i915#2856])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@secure-batches:
- shard-rkl: [PASS][79] -> [SKIP][80] ([i915#2527]) +5 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@gen9_exec_parse@secure-batches.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@gen9_exec_parse@secure-batches.html
* igt@gen9_exec_parse@valid-registers:
- shard-rkl: NOTRUN -> [SKIP][81] ([i915#2527]) +2 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@gen9_exec_parse@valid-registers.html
* igt@i915_module_load@resize-bar:
- shard-rkl: NOTRUN -> [SKIP][82] ([i915#6412])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@i915_module_load@resize-bar.html
* igt@i915_pm_freq_api@freq-suspend:
- shard-rkl: NOTRUN -> [SKIP][83] ([i915#8399]) +1 other test skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@i915_pm_freq_api@freq-suspend.html
* igt@i915_pm_rps@thresholds@gt0:
- shard-dg2: NOTRUN -> [SKIP][84] ([i915#8925])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@i915_pm_rps@thresholds@gt0.html
* igt@i915_power@sanity:
- shard-rkl: [PASS][85] -> [SKIP][86] ([i915#7984])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@i915_power@sanity.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@i915_power@sanity.html
* igt@i915_query@query-topology-unsupported:
- shard-rkl: NOTRUN -> [SKIP][87] ([fdo#109302])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@i915_query@query-topology-unsupported.html
* igt@i915_query@test-query-geometry-subslices:
- shard-rkl: NOTRUN -> [SKIP][88] ([i915#5723])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@i915_query@test-query-geometry-subslices.html
* igt@i915_selftest@mock@memory_region:
- shard-dg2: NOTRUN -> [DMESG-WARN][89] ([i915#9311])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@i915_selftest@mock@memory_region.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- shard-mtlp: NOTRUN -> [SKIP][90] ([i915#4212]) +1 other test skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- shard-dg2: NOTRUN -> [SKIP][91] ([i915#4212])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- shard-dg2: NOTRUN -> [SKIP][92] ([i915#4215] / [i915#5190])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_async_flips@crc:
- shard-rkl: NOTRUN -> [SKIP][93] ([i915#1845] / [i915#4098]) +10 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_async_flips@crc.html
* igt@kms_async_flips@crc@pipe-c-hdmi-a-1:
- shard-dg1: NOTRUN -> [FAIL][94] ([i915#8247]) +3 other tests fail
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg1-19/igt@kms_async_flips@crc@pipe-c-hdmi-a-1.html
* igt@kms_async_flips@crc@pipe-d-dp-4:
- shard-dg2: NOTRUN -> [FAIL][95] ([i915#8247]) +3 other tests fail
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_async_flips@crc@pipe-d-dp-4.html
* igt@kms_async_flips@invalid-async-flip:
- shard-dg2: NOTRUN -> [SKIP][96] ([i915#6228])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_async_flips@invalid-async-flip.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-dg2: NOTRUN -> [SKIP][97] ([i915#1769] / [i915#3555])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-0:
- shard-rkl: NOTRUN -> [SKIP][98] ([i915#5286]) +3 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-180:
- shard-mtlp: [PASS][99] -> [FAIL][100] ([i915#5138])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-mtlp-1/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-7/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][101] ([fdo#111614]) +5 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-90:
- shard-mtlp: NOTRUN -> [SKIP][102] ([fdo#111614]) +2 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-0:
- shard-dg2: NOTRUN -> [SKIP][103] ([i915#5190]) +17 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][104] ([fdo#111614] / [i915#3638]) +5 other tests skip
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
- shard-mtlp: NOTRUN -> [SKIP][105] ([fdo#111615]) +3 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
- shard-dg2: NOTRUN -> [SKIP][106] ([i915#4538] / [i915#5190]) +4 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][107] ([fdo#110723]) +3 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html
* igt@kms_big_joiner@invalid-modeset:
- shard-mtlp: NOTRUN -> [SKIP][108] ([i915#2705])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-dg2: NOTRUN -> [SKIP][109] ([i915#4087] / [i915#7213])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_cdclk@mode-transition@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][110] ([i915#7213] / [i915#9010]) +3 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_cdclk@mode-transition@pipe-b-edp-1.html
* igt@kms_chamelium_color@ctm-negative:
- shard-dg2: NOTRUN -> [SKIP][111] ([fdo#111827]) +2 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_chamelium_color@ctm-negative.html
- shard-rkl: NOTRUN -> [SKIP][112] ([fdo#111827])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@kms_chamelium_color@ctm-negative.html
* igt@kms_chamelium_edid@hdmi-edid-read:
- shard-rkl: NOTRUN -> [SKIP][113] ([i915#7828]) +4 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_chamelium_edid@hdmi-edid-read.html
* igt@kms_chamelium_frames@dp-frame-dump:
- shard-dg2: NOTRUN -> [SKIP][114] ([i915#7828]) +9 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_chamelium_frames@dp-frame-dump.html
* igt@kms_chamelium_hpd@vga-hpd:
- shard-mtlp: NOTRUN -> [SKIP][115] ([i915#7828]) +5 other tests skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_chamelium_hpd@vga-hpd.html
* igt@kms_color@ctm-green-to-red@pipe-b:
- shard-rkl: [PASS][116] -> [SKIP][117] ([i915#4098]) +3 other tests skip
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_color@ctm-green-to-red@pipe-b.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_color@ctm-green-to-red@pipe-b.html
* igt@kms_content_protection@atomic:
- shard-mtlp: NOTRUN -> [SKIP][118] ([i915#6944])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-dg2: NOTRUN -> [SKIP][119] ([i915#3299]) +1 other test skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-rkl: NOTRUN -> [SKIP][120] ([i915#3116])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@lic@pipe-a-dp-1:
- shard-apl: NOTRUN -> [TIMEOUT][121] ([i915#7173]) +1 other test timeout
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-apl3/igt@kms_content_protection@lic@pipe-a-dp-1.html
* igt@kms_content_protection@srm:
- shard-rkl: NOTRUN -> [SKIP][122] ([i915#7118]) +1 other test skip
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-dg2: NOTRUN -> [SKIP][123] ([i915#3359]) +2 other tests skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x10:
- shard-mtlp: NOTRUN -> [SKIP][124] ([i915#3555] / [i915#8814])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x32:
- shard-dg2: NOTRUN -> [SKIP][125] ([i915#3555]) +7 other tests skip
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-rkl: NOTRUN -> [SKIP][126] ([i915#3359])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-dg2: NOTRUN -> [SKIP][127] ([fdo#109274] / [i915#5354]) +2 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
- shard-dg2: NOTRUN -> [SKIP][128] ([fdo#109274] / [fdo#111767] / [i915#5354]) +1 other test skip
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
- shard-rkl: NOTRUN -> [SKIP][129] ([fdo#111767] / [fdo#111825])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-rkl: NOTRUN -> [SKIP][130] ([i915#4103]) +2 other tests skip
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
- shard-mtlp: NOTRUN -> [SKIP][131] ([i915#3546]) +2 other tests skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-dg2: NOTRUN -> [SKIP][132] ([i915#4103] / [i915#4213])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][133] ([i915#3804])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html
* igt@kms_dp_aux_dev:
- shard-rkl: NOTRUN -> [SKIP][134] ([i915#1257])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@kms_dp_aux_dev.html
* igt@kms_draw_crc@draw-method-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][135] ([i915#8812])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_draw_crc@draw-method-mmap-gtt.html
* igt@kms_dsc@dsc-basic:
- shard-rkl: NOTRUN -> [SKIP][136] ([i915#3555] / [i915#3840])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_dsc@dsc-basic.html
* igt@kms_dsc@dsc-with-bpc:
- shard-dg2: NOTRUN -> [SKIP][137] ([i915#3555] / [i915#3840])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-mtlp: NOTRUN -> [SKIP][138] ([i915#3555] / [i915#3840])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_flip@2x-blocking-wf_vblank:
- shard-dg2: NOTRUN -> [SKIP][139] ([fdo#109274]) +4 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_flip@2x-blocking-wf_vblank.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-dg2: NOTRUN -> [SKIP][140] ([fdo#109274] / [fdo#111767])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-dg2: NOTRUN -> [SKIP][141] ([i915#8381]) +1 other test skip
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@2x-flip-vs-panning-vs-hang:
- shard-rkl: NOTRUN -> [SKIP][142] ([fdo#111825]) +4 other tests skip
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
* igt@kms_flip@2x-flip-vs-rmfb:
- shard-mtlp: NOTRUN -> [SKIP][143] ([i915#3637]) +1 other test skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_flip@2x-flip-vs-rmfb.html
* igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-vga1-hdmi-a1:
- shard-snb: NOTRUN -> [DMESG-WARN][144] ([i915#8841])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-snb1/igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-vga1-hdmi-a1.html
* igt@kms_flip@bo-too-big-interruptible:
- shard-rkl: NOTRUN -> [SKIP][145] ([i915#3637] / [i915#4098]) +10 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_flip@bo-too-big-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][146] ([i915#2672]) +5 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][147] ([i915#3555] / [i915#8810])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][148] ([i915#2672] / [i915#3555])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][149] ([i915#2672])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
- shard-rkl: NOTRUN -> [SKIP][150] ([i915#3555]) +11 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][151] ([i915#2672]) +6 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-mtlp: NOTRUN -> [SKIP][152] ([fdo#109285])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt:
- shard-dg2: [PASS][153] -> [FAIL][154] ([i915#6880])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
- shard-rkl: [PASS][155] -> [SKIP][156] ([i915#1849] / [i915#4098]) +17 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][157] ([i915#8708]) +12 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][158] ([i915#8708]) +1 other test skip
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
- shard-rkl: NOTRUN -> [SKIP][159] ([i915#3023]) +18 other tests skip
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
- shard-mtlp: NOTRUN -> [SKIP][160] ([i915#1825]) +13 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff:
- shard-rkl: NOTRUN -> [SKIP][161] ([fdo#111825] / [i915#1825]) +25 other tests skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
- shard-apl: NOTRUN -> [SKIP][162] ([fdo#109271]) +131 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-apl3/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
- shard-dg2: NOTRUN -> [SKIP][163] ([i915#5460])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
- shard-dg2: NOTRUN -> [SKIP][164] ([i915#3458]) +22 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt:
- shard-dg2: NOTRUN -> [SKIP][165] ([i915#5354]) +36 other tests skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_getfb@getfb-reject-ccs:
- shard-dg2: NOTRUN -> [SKIP][166] ([i915#6118])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_getfb@getfb-reject-ccs.html
* igt@kms_hdr@static-swap:
- shard-dg2: NOTRUN -> [SKIP][167] ([i915#3555] / [i915#8228])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_hdr@static-swap.html
* igt@kms_invalid_mode@bad-htotal:
- shard-rkl: NOTRUN -> [SKIP][168] ([i915#3555] / [i915#4098])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_invalid_mode@bad-htotal.html
* igt@kms_panel_fitting@legacy:
- shard-dg2: NOTRUN -> [SKIP][169] ([i915#6301])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_panel_fitting@legacy.html
* igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
- shard-dg2: NOTRUN -> [SKIP][170] ([fdo#109289]) +2 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html
* igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c:
- shard-mtlp: NOTRUN -> [SKIP][171] ([fdo#109289]) +2 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c.html
* igt@kms_pipe_crc_basic@bad-source:
- shard-rkl: [PASS][172] -> [SKIP][173] ([i915#1845] / [i915#4098]) +22 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_pipe_crc_basic@bad-source.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_pipe_crc_basic@bad-source.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][174] ([fdo#109271]) +28 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-snb1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-hdmi-a-1.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-1:
- shard-apl: [PASS][175] -> [ABORT][176] ([i915#180])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-apl1/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-1.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-apl7/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-1.html
* igt@kms_plane@plane-position-hole-dpms:
- shard-rkl: NOTRUN -> [SKIP][177] ([i915#4098] / [i915#8825])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_plane@plane-position-hole-dpms.html
* igt@kms_plane_alpha_blend@constant-alpha-max@pipe-c-hdmi-a-1:
- shard-glk: NOTRUN -> [FAIL][178] ([i915#4573]) +1 other test fail
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-glk5/igt@kms_plane_alpha_blend@constant-alpha-max@pipe-c-hdmi-a-1.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [FAIL][179] ([i915#8292])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [FAIL][180] ([i915#8292])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg1-16/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation:
- shard-rkl: NOTRUN -> [SKIP][181] ([i915#3555] / [i915#4098] / [i915#8152])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-1:
- shard-dg1: NOTRUN -> [SKIP][182] ([i915#5235]) +7 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg1-19/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][183] ([i915#5235]) +3 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling:
- shard-rkl: NOTRUN -> [SKIP][184] ([i915#8152]) +1 other test skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling.html
* igt@kms_plane_scaling@planes-upscale-20x20:
- shard-rkl: NOTRUN -> [SKIP][185] ([i915#4098] / [i915#6953] / [i915#8152])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_plane_scaling@planes-upscale-20x20.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-c-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][186] ([i915#5235]) +2 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-c-edp-1.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][187] ([i915#3555] / [i915#5235])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-d-edp-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25:
- shard-rkl: NOTRUN -> [SKIP][188] ([i915#3555] / [i915#4098] / [i915#6953] / [i915#8152])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_plane_scaling@planes-upscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][189] ([i915#5235]) +5 other tests skip
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2.html
* igt@kms_prime@basic-crc-hybrid:
- shard-dg2: NOTRUN -> [SKIP][190] ([i915#6524] / [i915#6805]) +1 other test skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_properties@plane-properties-legacy:
- shard-rkl: [PASS][191] -> [SKIP][192] ([i915#1849]) +1 other test skip
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_properties@plane-properties-legacy.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_properties@plane-properties-legacy.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf:
- shard-rkl: NOTRUN -> [SKIP][193] ([i915#658])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf:
- shard-glk: NOTRUN -> [SKIP][194] ([fdo#109271] / [i915#658])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-glk5/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-apl: NOTRUN -> [SKIP][195] ([fdo#109271] / [i915#658]) +2 other tests skip
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-apl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-dg2: NOTRUN -> [SKIP][196] ([i915#658]) +3 other tests skip
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-p010:
- shard-rkl: NOTRUN -> [SKIP][197] ([fdo#111068] / [i915#658]) +1 other test skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@primary_page_flip:
- shard-rkl: NOTRUN -> [SKIP][198] ([i915#1072]) +4 other tests skip
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_psr@primary_page_flip.html
* igt@kms_psr@psr2_cursor_mmap_gtt:
- shard-glk: NOTRUN -> [SKIP][199] ([fdo#109271]) +36 other tests skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-glk5/igt@kms_psr@psr2_cursor_mmap_gtt.html
* igt@kms_psr@psr2_sprite_blt:
- shard-dg2: NOTRUN -> [SKIP][200] ([i915#1072]) +7 other tests skip
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-rkl: NOTRUN -> [SKIP][201] ([i915#5461] / [i915#658])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
- shard-rkl: NOTRUN -> [SKIP][202] ([i915#5289])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
* igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
- shard-mtlp: NOTRUN -> [SKIP][203] ([i915#4235]) +1 other test skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-mtlp: NOTRUN -> [SKIP][204] ([i915#3555] / [i915#8809])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_tv_load_detect@load-detect:
- shard-dg2: NOTRUN -> [SKIP][205] ([fdo#109309])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_tv_load_detect@load-detect.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1:
- shard-mtlp: [PASS][206] -> [FAIL][207] ([i915#9196])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-mtlp-3/igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1.html
* igt@kms_vblank@wait-forked-busy-hang:
- shard-rkl: NOTRUN -> [SKIP][208] ([i915#4098]) +21 other tests skip
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_vblank@wait-forked-busy-hang.html
* igt@kms_vrr@flip-dpms:
- shard-mtlp: NOTRUN -> [SKIP][209] ([i915#3555] / [i915#8808])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_vrr@flip-dpms.html
* igt@kms_writeback@writeback-check-output:
- shard-mtlp: NOTRUN -> [SKIP][210] ([i915#2437])
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id:
- shard-rkl: NOTRUN -> [SKIP][211] ([i915#2437])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_writeback@writeback-fb-id.html
* igt@perf@enable-disable@0-rcs0:
- shard-dg2: NOTRUN -> [FAIL][212] ([i915#8724])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@perf@enable-disable@0-rcs0.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- shard-rkl: [PASS][213] -> [SKIP][214] ([i915#2436])
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@perf@gen8-unprivileged-single-ctx-counters.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-6/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@perf@global-sseu-config:
- shard-dg2: NOTRUN -> [SKIP][215] ([i915#7387])
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@perf@global-sseu-config.html
* igt@perf_pmu@cpu-hotplug:
- shard-rkl: NOTRUN -> [SKIP][216] ([i915#8850])
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@perf_pmu@cpu-hotplug.html
* igt@perf_pmu@frequency@gt0:
- shard-dg2: NOTRUN -> [FAIL][217] ([i915#6806])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@perf_pmu@frequency@gt0.html
* igt@perf_pmu@module-unload:
- shard-dg2: NOTRUN -> [FAIL][218] ([i915#5793])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@perf_pmu@module-unload.html
* igt@perf_pmu@rc6@other-idle-gt0:
- shard-dg2: NOTRUN -> [SKIP][219] ([i915#8516])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@perf_pmu@rc6@other-idle-gt0.html
* igt@prime_udl:
- shard-dg2: NOTRUN -> [SKIP][220] ([fdo#109291])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@prime_udl.html
* igt@prime_vgem@basic-fence-mmap:
- shard-mtlp: NOTRUN -> [SKIP][221] ([i915#3708] / [i915#4077])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-write:
- shard-dg2: NOTRUN -> [SKIP][222] ([i915#3291] / [i915#3708])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@prime_vgem@basic-write.html
* igt@prime_vgem@fence-read-hang:
- shard-rkl: NOTRUN -> [SKIP][223] ([fdo#109295] / [i915#3708])
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@prime_vgem@fence-read-hang.html
* igt@syncobj_timeline@invalid-multi-wait-all-available-unsubmitted-submitted:
- shard-rkl: NOTRUN -> [FAIL][224] ([i915#9583]) +1 other test fail
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@syncobj_timeline@invalid-multi-wait-all-available-unsubmitted-submitted.html
* igt@syncobj_timeline@invalid-multi-wait-available-unsubmitted:
- shard-dg2: NOTRUN -> [FAIL][225] ([i915#9583])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@syncobj_timeline@invalid-multi-wait-available-unsubmitted.html
* igt@syncobj_timeline@invalid-multi-wait-available-unsubmitted-submitted:
- shard-snb: NOTRUN -> [FAIL][226] ([i915#9583])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-snb7/igt@syncobj_timeline@invalid-multi-wait-available-unsubmitted-submitted.html
* igt@v3d/v3d_submit_cl@bad-multisync-in-sync:
- shard-rkl: NOTRUN -> [SKIP][227] ([fdo#109315]) +7 other tests skip
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@v3d/v3d_submit_cl@bad-multisync-in-sync.html
* igt@v3d/v3d_submit_cl@simple-flush-cache:
- shard-mtlp: NOTRUN -> [SKIP][228] ([i915#2575]) +4 other tests skip
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@v3d/v3d_submit_cl@simple-flush-cache.html
* igt@v3d/v3d_submit_csd@bad-flag:
- shard-dg2: NOTRUN -> [SKIP][229] ([i915#2575]) +13 other tests skip
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@v3d/v3d_submit_csd@bad-flag.html
* igt@vc4/vc4_create_bo@create-bo-4096:
- shard-dg2: NOTRUN -> [SKIP][230] ([i915#7711]) +9 other tests skip
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@vc4/vc4_create_bo@create-bo-4096.html
- shard-rkl: NOTRUN -> [SKIP][231] ([i915#7711]) +6 other tests skip
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@vc4/vc4_create_bo@create-bo-4096.html
* igt@vc4/vc4_tiling@get-bad-modifier:
- shard-mtlp: NOTRUN -> [SKIP][232] ([i915#7711]) +3 other tests skip
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@vc4/vc4_tiling@get-bad-modifier.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- shard-rkl: [FAIL][233] ([i915#7742]) -> [PASS][234]
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
* igt@fbdev@nullptr:
- shard-rkl: [SKIP][235] ([i915#2582]) -> [PASS][236] +1 other test pass
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@fbdev@nullptr.html
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@fbdev@nullptr.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl: [FAIL][237] ([i915#6268]) -> [PASS][238]
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@gem_ctx_exec@basic-nohangcheck.html
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@gem_ctx_exec@basic-nohangcheck.html
- shard-tglu: [FAIL][239] ([i915#6268]) -> [PASS][240]
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-tglu-3/igt@gem_ctx_exec@basic-nohangcheck.html
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-tglu-2/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_persistence@engines-hang@bcs0:
- shard-rkl: [SKIP][241] ([i915#6252]) -> [PASS][242] +1 other test pass
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@gem_ctx_persistence@engines-hang@bcs0.html
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@gem_ctx_persistence@engines-hang@bcs0.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-mtlp: [ABORT][243] ([i915#9414]) -> [PASS][244]
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-mtlp-5/igt@gem_eio@in-flight-contexts-10ms.html
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_exec_balancer@fairslice:
- shard-rkl: [SKIP][245] ([Intel XE#874]) -> [PASS][246]
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@gem_exec_balancer@fairslice.html
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@gem_exec_balancer@fairslice.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][247] ([i915#2842]) -> [PASS][248]
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-rkl: [FAIL][249] ([i915#2842]) -> [PASS][250]
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-rkl: [SKIP][251] ([fdo#109313]) -> [PASS][252]
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_reloc@basic-write-read-noreloc:
- shard-rkl: [SKIP][253] ([i915#3281]) -> [PASS][254] +13 other tests pass
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@gem_exec_reloc@basic-write-read-noreloc.html
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@gem_exec_reloc@basic-write-read-noreloc.html
* igt@gem_exec_schedule@semaphore-power:
- shard-rkl: [SKIP][255] ([i915#7276]) -> [PASS][256]
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@gem_exec_schedule@semaphore-power.html
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_mmap_gtt@coherency:
- shard-rkl: [SKIP][257] ([fdo#111656]) -> [PASS][258]
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@gem_mmap_gtt@coherency.html
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@gem_mmap_gtt@coherency.html
* igt@gem_pread@snoop:
- shard-rkl: [SKIP][259] ([i915#3282]) -> [PASS][260] +3 other tests pass
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@gem_pread@snoop.html
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@gem_pread@snoop.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-rkl: [SKIP][261] ([i915#8411]) -> [PASS][262]
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gen9_exec_parse@allowed-all:
- shard-rkl: [SKIP][263] ([i915#2527]) -> [PASS][264] +3 other tests pass
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@gen9_exec_parse@allowed-all.html
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@gen9_exec_parse@allowed-all.html
* igt@i915_hangman@engine-engine-error@bcs0:
- shard-rkl: [SKIP][265] ([i915#9588]) -> [PASS][266]
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@i915_hangman@engine-engine-error@bcs0.html
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@i915_hangman@engine-engine-error@bcs0.html
* igt@i915_pm_rc6_residency@rc6-idle@bcs0:
- shard-dg1: [FAIL][267] ([i915#3591]) -> [PASS][268]
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html
* igt@i915_pm_rps@reset:
- shard-snb: [INCOMPLETE][269] ([i915#7790]) -> [PASS][270]
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-snb7/igt@i915_pm_rps@reset.html
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-snb7/igt@i915_pm_rps@reset.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-0:
- shard-rkl: [SKIP][271] ([i915#1845] / [i915#4098]) -> [PASS][272] +33 other tests pass
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-2/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
* {igt@kms_ccs@pipe-b-bad-pixel-format-y-tiled-gen12-rc-ccs}:
- shard-rkl: [SKIP][273] ([i915#4098]) -> [PASS][274] +18 other tests pass
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_ccs@pipe-b-bad-pixel-format-y-tiled-gen12-rc-ccs.html
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-2/igt@kms_ccs@pipe-b-bad-pixel-format-y-tiled-gen12-rc-ccs.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-rkl: [SKIP][275] ([i915#1849] / [i915#4098]) -> [PASS][276] +12 other tests pass
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html
* {igt@kms_pm_rpm@dpms-mode-unset-non-lpsp}:
- shard-rkl: [SKIP][277] ([i915#9519]) -> [PASS][278]
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_properties@plane-properties-atomic:
- shard-rkl: [SKIP][279] ([i915#1849]) -> [PASS][280]
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_properties@plane-properties-atomic.html
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-6/igt@kms_properties@plane-properties-atomic.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-rkl: [INCOMPLETE][281] ([i915#8875] / [i915#9569]) -> [PASS][282]
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@kms_rotation_crc@bad-pixel-format.html
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_rotation_crc@bad-pixel-format.html
* {igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-3}:
- shard-dg1: [FAIL][283] ([i915#9196]) -> [PASS][284]
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-dg1-13/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-3.html
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg1-13/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-3.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1:
- shard-tglu: [FAIL][285] ([i915#9196]) -> [PASS][286]
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-tglu-7/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-tglu-9/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [FAIL][287] ([i915#7484]) -> [PASS][288]
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-dg2-7/igt@perf@non-zero-reason@0-rcs0.html
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-5/igt@perf@non-zero-reason@0-rcs0.html
#### Warnings ####
* igt@gem_ccs@block-multicopy-inplace:
- shard-rkl: [SKIP][289] ([i915#7957]) -> [SKIP][290] ([i915#3555])
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@gem_ccs@block-multicopy-inplace.html
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@gem_ccs@block-multicopy-inplace.html
* igt@gem_ccs@suspend-resume:
- shard-rkl: [SKIP][291] ([i915#7957]) -> [SKIP][292] ([i915#9323])
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@gem_ccs@suspend-resume.html
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@gem_ccs@suspend-resume.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-rkl: [SKIP][293] ([i915#9591]) -> [FAIL][294] ([i915#2842])
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@gem_exec_fair@basic-pace@bcs0.html
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-6/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gen9_exec_parse@bb-secure:
- shard-dg1: [SKIP][295] ([i915#2527] / [i915#4423]) -> [SKIP][296] ([i915#2527])
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-dg1-16/igt@gen9_exec_parse@bb-secure.html
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg1-17/igt@gen9_exec_parse@bb-secure.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-rkl: [SKIP][297] ([i915#1769] / [i915#3555]) -> [SKIP][298] ([i915#1845] / [i915#4098]) +1 other test skip
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-180:
- shard-rkl: [SKIP][299] ([i915#4098]) -> [SKIP][300] ([i915#5286]) +6 other tests skip
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_big_fb@4-tiled-32bpp-rotate-180.html
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-2/igt@kms_big_fb@4-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-rkl: [SKIP][301] ([i915#5286]) -> [SKIP][302] ([i915#4098]) +6 other tests skip
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@linear-64bpp-rotate-90:
- shard-rkl: [SKIP][303] ([i915#1845] / [i915#4098]) -> [SKIP][304] ([fdo#111614] / [i915#3638]) +4 other tests skip
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_big_fb@linear-64bpp-rotate-90.html
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@kms_big_fb@linear-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-rkl: [SKIP][305] ([fdo#111614] / [i915#3638]) -> [SKIP][306] ([i915#1845] / [i915#4098]) +5 other tests skip
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
- shard-rkl: [SKIP][307] ([fdo#110723]) -> [SKIP][308] ([i915#1845] / [i915#4098]) +5 other tests skip
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-addfb-size-overflow:
- shard-rkl: [SKIP][309] ([fdo#111615]) -> [SKIP][310] ([i915#1845] / [i915#4098])
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
- shard-rkl: [SKIP][311] ([i915#1845] / [i915#4098]) -> [SKIP][312] ([fdo#110723]) +7 other tests skip
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-rkl: [SKIP][313] ([i915#1845] / [i915#4098]) -> [SKIP][314] ([i915#3116]) +1 other test skip
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_content_protection@dp-mst-lic-type-1.html
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@lic:
- shard-rkl: [SKIP][315] ([i915#7118]) -> [SKIP][316] ([i915#1845] / [i915#4098])
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_content_protection@lic.html
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_content_protection@lic.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-rkl: [SKIP][317] ([i915#3359]) -> [SKIP][318] ([i915#4098]) +1 other test skip
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_cursor_crc@cursor-random-512x512.html
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_crc@cursor-sliding-max-size:
- shard-rkl: [SKIP][319] ([i915#3555]) -> [SKIP][320] ([i915#4098]) +4 other tests skip
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@kms_cursor_crc@cursor-sliding-max-size.html
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_cursor_crc@cursor-sliding-max-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
- shard-rkl: [SKIP][321] ([fdo#111825]) -> [SKIP][322] ([i915#1845] / [i915#4098]) +7 other tests skip
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-rkl: [SKIP][323] ([i915#1845] / [i915#4098]) -> [SKIP][324] ([fdo#111767] / [fdo#111825]) +1 other test skip
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-6/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-rkl: [SKIP][325] ([i915#1845] / [i915#4098]) -> [SKIP][326] ([fdo#111825]) +5 other tests skip
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-2/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-rkl: [SKIP][327] ([i915#4103]) -> [SKIP][328] ([i915#1845] / [i915#4098])
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
- shard-rkl: [SKIP][329] ([i915#1845] / [i915#4098]) -> [SKIP][330] ([i915#4103])
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-rkl: [SKIP][331] ([i915#3555] / [i915#3840]) -> [SKIP][332] ([i915#4098]) +1 other test skip
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_dsc@dsc-with-output-formats.html
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_fbcon_fbt@psr:
- shard-rkl: [SKIP][333] ([i915#3955]) -> [SKIP][334] ([fdo#110189] / [i915#3955])
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-6/igt@kms_fbcon_fbt@psr.html
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@kms_fbcon_fbt@psr.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-rkl: [SKIP][335] ([fdo#109285]) -> [SKIP][336] ([fdo#109285] / [i915#4098])
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_force_connector_basic@force-load-detect.html
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt:
- shard-rkl: [SKIP][337] ([i915#1849] / [i915#4098]) -> [SKIP][338] ([fdo#111825])
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt.html
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-rkl: [SKIP][339] ([i915#1849] / [i915#4098]) -> [SKIP][340] ([i915#5439])
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt:
- shard-rkl: [SKIP][341] ([i915#1849] / [i915#4098]) -> [SKIP][342] ([i915#3023]) +33 other tests skip
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt:
- shard-rkl: [SKIP][343] ([i915#3023]) -> [SKIP][344] ([i915#1849] / [i915#4098]) +29 other tests skip
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-rkl: [SKIP][345] ([fdo#111825] / [i915#1825]) -> [SKIP][346] ([i915#1849] / [i915#4098]) +37 other tests skip
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
- shard-rkl: [SKIP][347] ([i915#1849] / [i915#4098]) -> [SKIP][348] ([fdo#111825] / [i915#1825]) +52 other tests skip
[347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html
[348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html
* igt@kms_hdr@invalid-hdr:
- shard-rkl: [SKIP][349] ([i915#3555] / [i915#8228]) -> [SKIP][350] ([i915#4098])
[349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_hdr@invalid-hdr.html
[350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_hdr@invalid-hdr.html
* igt@kms_hdr@static-swap:
- shard-rkl: [SKIP][351] ([i915#1845] / [i915#4098]) -> [SKIP][352] ([i915#3555] / [i915#8228]) +1 other test skip
[351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_hdr@static-swap.html
[352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_hdr@static-swap.html
* igt@kms_panel_fitting@atomic-fastset:
- shard-rkl: [SKIP][353] ([i915#1845] / [i915#4098]) -> [SKIP][354] ([i915#6301]) +1 other test skip
[353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_panel_fitting@atomic-fastset.html
[354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@kms_panel_fitting@atomic-fastset.html
* igt@kms_plane_multiple@tiling-yf:
- shard-rkl: [SKIP][355] ([i915#4098]) -> [SKIP][356] ([i915#3555]) +7 other tests skip
[355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_plane_multiple@tiling-yf.html
[356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-6/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-rkl: [SKIP][357] ([i915#1845] / [i915#4098]) -> [SKIP][358] ([fdo#111615] / [i915#5289])
[357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
[358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_vrr@flip-dpms:
- shard-rkl: [SKIP][359] ([i915#3555]) -> [SKIP][360] ([i915#1845] / [i915#4098]) +1 other test skip
[359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_vrr@flip-dpms.html
[360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_vrr@flip-dpms.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/874
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5460]: https://gitlab.freedesktop.org/drm/intel/issues/5460
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5793]: https://gitlab.freedesktop.org/drm/intel/issues/5793
[i915#5882]: https://gitlab.freedesktop.org/drm/intel/issues/5882
[i915#5889]: https://gitlab.freedesktop.org/drm/intel/issues/5889
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6118]: https://gitlab.freedesktop.org/drm/intel/issues/6118
[i915#6122]: https://gitlab.freedesktop.org/drm/intel/issues/6122
[i915#6228]: https://gitlab.freedesktop.org/drm/intel/issues/6228
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
[i915#6806]: https://gitlab.freedesktop.org/drm/intel/issues/6806
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
[i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
[i915#7276]: https://gitlab.freedesktop.org/drm/intel/issues/7276
[i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
[i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484
[i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#7984]: https://gitlab.freedesktop.org/drm/intel/issues/7984
[i915#8152]: https://gitlab.freedesktop.org/drm/intel/issues/8152
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
[i915#8399]: https://gitlab.freedesktop.org/drm/intel/issues/8399
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8430]: https://gitlab.freedesktop.org/drm/intel/issues/8430
[i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8562]: https://gitlab.freedesktop.org/drm/intel/issues/8562
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8724]: https://gitlab.freedesktop.org/drm/intel/issues/8724
[i915#8808]: https://gitlab.freedesktop.org/drm/intel/issues/8808
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
[i915#8812]: https://gitlab.freedesktop.org/drm/intel/issues/8812
[i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
[i915#8825]: https://gitlab.freedesktop.org/drm/intel/issues/8825
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#8850]: https://gitlab.freedesktop.org/drm/intel/issues/8850
[i915#8875]: https://gitlab.freedesktop.org/drm/intel/issues/8875
[i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
[i915#9010]: https://gitlab.freedesktop.org/drm/intel/issues/9010
[i915#9053]: https://gitlab.freedesktop.org/drm/intel/issues/9053
[i915#9067]: https://gitlab.freedesktop.org/drm/intel/issues/9067
[i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
[i915#9293]: https://gitlab.freedesktop.org/drm/intel/issues/9293
[i915#9310]: https://gitlab.freedesktop.org/drm/intel/issues/9310
[i915#9311]: https://gitlab.freedesktop.org/drm/intel/issues/9311
[i915#9323]: https://gitlab.freedesktop.org/drm/intel/issues/9323
[i915#9414]: https://gitlab.freedesktop.org/drm/intel/issues/9414
[i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/intel/issues/9424
[i915#9519]: https://gitlab.freedesktop.org/drm/intel/issues/9519
[i915#9569]: https://gitlab.freedesktop.org/drm/intel/issues/9569
[i915#9583]: https://gitlab.freedesktop.org/drm/intel/issues/9583
[i915#9588]: https://gitlab.freedesktop.org/drm/intel/issues/9588
[i915#9591]: https://gitlab.freedesktop.org/drm/intel/issues/9591
Build changes
-------------
* Linux: CI_DRM_13844 -> Patchwork_125490v16
CI-20190529: 20190529
CI_DRM_13844: 98a039fc048898d9ecec16153267968fd18a5a52 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7574: 0485a4bf66f69aaf7244a3e689402b522f636780 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_125490v16: 98a039fc048898d9ecec16153267968fd18a5a52 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/index.html
[-- Attachment #2: Type: text/html, Size: 117197 bytes --]
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Improve BW management on MST links (rev16)
2023-11-07 9:50 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2023-11-08 15:59 ` Imre Deak
0 siblings, 0 replies; 94+ messages in thread
From: Imre Deak @ 2023-11-08 15:59 UTC (permalink / raw)
To: Stanislav Lisovskiy, Lyude Paul, Ville Syrjälä,
Ankit K Nautiyal, Arun R Murthy, Jani Nikula, Maxime Ripard,
Harry Wentland
Cc: intel-gfx
On Tue, Nov 07, 2023 at 09:50:23AM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Improve BW management on MST links (rev16)
> URL : https://patchwork.freedesktop.org/series/125490/
> State : success
Patchset pushed to drm-intel-next, thanks for the reviews, acks.
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_13844_full -> Patchwork_125490v16_full
> ====================================================
>
> Summary
> -------
>
> **WARNING**
>
> Minor unknown changes coming with Patchwork_125490v16_full need to be verified
> manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_125490v16_full, please notify your bug team (lgci.bug.filing@intel.com) to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/index.html
>
> Participating hosts (11 -> 10)
> ------------------------------
>
> Missing (1): shard-mtlp0
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_125490v16_full:
>
> ### IGT changes ###
>
> #### Warnings ####
>
> * igt@gem_lmem_swapping@heavy-verify-multi-ccs:
> - shard-snb: [SKIP][1] ([fdo#109271]) -> [INCOMPLETE][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-snb2/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-snb6/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_125490v16_full that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@api_intel_bb@blit-reloc-keep-cache:
> - shard-rkl: [PASS][3] -> [SKIP][4] ([i915#8411]) +1 other test skip
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@api_intel_bb@blit-reloc-keep-cache.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-6/igt@api_intel_bb@blit-reloc-keep-cache.html
>
> * igt@api_intel_bb@blit-reloc-purge-cache:
> - shard-mtlp: NOTRUN -> [SKIP][5] ([i915#8411])
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@api_intel_bb@blit-reloc-purge-cache.html
>
> * igt@api_intel_bb@render-ccs:
> - shard-dg2: NOTRUN -> [FAIL][6] ([i915#6122])
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@api_intel_bb@render-ccs.html
>
> * igt@drm_fdinfo@virtual-busy-hang:
> - shard-mtlp: NOTRUN -> [SKIP][7] ([i915#8414])
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@drm_fdinfo@virtual-busy-hang.html
>
> * igt@fbdev@eof:
> - shard-rkl: [PASS][8] -> [SKIP][9] ([i915#2582]) +1 other test skip
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@fbdev@eof.html
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@fbdev@eof.html
>
> * igt@gem_ccs@block-multicopy-compressed:
> - shard-rkl: NOTRUN -> [SKIP][10] ([i915#9323])
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@gem_ccs@block-multicopy-compressed.html
>
> * igt@gem_ccs@ctrl-surf-copy-new-ctx:
> - shard-rkl: NOTRUN -> [SKIP][11] ([i915#4098] / [i915#9323])
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
>
> * igt@gem_close_race@multigpu-basic-process:
> - shard-rkl: NOTRUN -> [SKIP][12] ([i915#7697])
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@gem_close_race@multigpu-basic-process.html
>
> * igt@gem_close_race@multigpu-basic-threads:
> - shard-dg2: NOTRUN -> [SKIP][13] ([i915#7697])
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gem_close_race@multigpu-basic-threads.html
>
> * igt@gem_create@create-ext-cpu-access-big:
> - shard-mtlp: NOTRUN -> [SKIP][14] ([i915#6335])
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@gem_create@create-ext-cpu-access-big.html
>
> * igt@gem_create@create-ext-set-pat:
> - shard-rkl: NOTRUN -> [SKIP][15] ([i915#8562])
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@gem_create@create-ext-set-pat.html
>
> * igt@gem_ctx_isolation@preservation-s3@ccs2:
> - shard-dg2: [PASS][16] -> [FAIL][17] ([fdo#103375]) +4 other tests fail
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-dg2-1/igt@gem_ctx_isolation@preservation-s3@ccs2.html
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-5/igt@gem_ctx_isolation@preservation-s3@ccs2.html
>
> * igt@gem_ctx_persistence@heartbeat-hang:
> - shard-dg2: NOTRUN -> [SKIP][18] ([i915#8555])
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@gem_ctx_persistence@heartbeat-hang.html
>
> * igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0:
> - shard-dg2: NOTRUN -> [SKIP][19] ([i915#5882]) +9 other tests skip
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0.html
>
> * igt@gem_ctx_sseu@invalid-args:
> - shard-dg2: NOTRUN -> [SKIP][20] ([i915#280])
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@gem_ctx_sseu@invalid-args.html
> - shard-rkl: NOTRUN -> [SKIP][21] ([i915#280])
> [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@gem_ctx_sseu@invalid-args.html
>
> * igt@gem_eio@hibernate:
> - shard-mtlp: [PASS][22] -> [ABORT][23] ([i915#7975] / [i915#8213] / [i915#9414])
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-mtlp-1/igt@gem_eio@hibernate.html
> [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@gem_eio@hibernate.html
>
> * igt@gem_exec_balancer@bonded-dual:
> - shard-mtlp: NOTRUN -> [SKIP][24] ([i915#4771])
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@gem_exec_balancer@bonded-dual.html
>
> * igt@gem_exec_balancer@bonded-false-hang:
> - shard-dg2: NOTRUN -> [SKIP][25] ([i915#4812]) +1 other test skip
> [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gem_exec_balancer@bonded-false-hang.html
>
> * igt@gem_exec_balancer@parallel-balancer:
> - shard-rkl: NOTRUN -> [SKIP][26] ([i915#4525]) +2 other tests skip
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@gem_exec_balancer@parallel-balancer.html
>
> * igt@gem_exec_endless@dispatch@bcs0:
> - shard-rkl: [PASS][27] -> [SKIP][28] ([i915#9591])
> [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@gem_exec_endless@dispatch@bcs0.html
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@gem_exec_endless@dispatch@bcs0.html
>
> * igt@gem_exec_fair@basic-none-solo:
> - shard-mtlp: NOTRUN -> [SKIP][29] ([i915#4473])
> [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@gem_exec_fair@basic-none-solo.html
>
> * igt@gem_exec_fair@basic-pace-share@rcs0:
> - shard-rkl: NOTRUN -> [FAIL][30] ([i915#2842])
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@gem_exec_fair@basic-pace-share@rcs0.html
> - shard-tglu: [PASS][31] -> [FAIL][32] ([i915#2842])
> [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-tglu-9/igt@gem_exec_fair@basic-pace-share@rcs0.html
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-tglu-3/igt@gem_exec_fair@basic-pace-share@rcs0.html
>
> * igt@gem_exec_fair@basic-pace@vecs0:
> - shard-rkl: [PASS][33] -> [FAIL][34] ([i915#2842]) +2 other tests fail
> [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@gem_exec_fair@basic-pace@vecs0.html
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-6/igt@gem_exec_fair@basic-pace@vecs0.html
>
> * igt@gem_exec_flush@basic-uc-pro-default:
> - shard-dg2: NOTRUN -> [SKIP][35] ([i915#3539] / [i915#4852]) +5 other tests skip
> [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gem_exec_flush@basic-uc-pro-default.html
>
> * igt@gem_exec_params@secure-non-master:
> - shard-dg2: NOTRUN -> [SKIP][36] ([fdo#112283])
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gem_exec_params@secure-non-master.html
>
> * igt@gem_exec_params@secure-non-root:
> - shard-mtlp: NOTRUN -> [SKIP][37] ([fdo#112283])
> [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@gem_exec_params@secure-non-root.html
>
> * igt@gem_exec_reloc@basic-gtt-read:
> - shard-dg2: NOTRUN -> [SKIP][38] ([i915#3281]) +14 other tests skip
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@gem_exec_reloc@basic-gtt-read.html
>
> * igt@gem_exec_reloc@basic-softpin:
> - shard-mtlp: NOTRUN -> [SKIP][39] ([i915#3281])
> [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@gem_exec_reloc@basic-softpin.html
>
> * igt@gem_exec_reloc@basic-write-read:
> - shard-rkl: NOTRUN -> [SKIP][40] ([i915#3281]) +12 other tests skip
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@gem_exec_reloc@basic-write-read.html
>
> * igt@gem_exec_reloc@basic-write-wc-noreloc:
> - shard-rkl: [PASS][41] -> [SKIP][42] ([i915#3281]) +10 other tests skip
> [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@gem_exec_reloc@basic-write-wc-noreloc.html
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-2/igt@gem_exec_reloc@basic-write-wc-noreloc.html
>
> * igt@gem_exec_suspend@basic-s4-devices@smem:
> - shard-rkl: NOTRUN -> [ABORT][43] ([i915#7975] / [i915#8213])
> [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@gem_exec_suspend@basic-s4-devices@smem.html
>
> * igt@gem_fence_thrash@bo-write-verify-x:
> - shard-dg2: NOTRUN -> [SKIP][44] ([i915#4860]) +1 other test skip
> [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@gem_fence_thrash@bo-write-verify-x.html
>
> * igt@gem_lmem_swapping@heavy-verify-multi:
> - shard-glk: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#4613]) +1 other test skip
> [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-glk5/igt@gem_lmem_swapping@heavy-verify-multi.html
>
> * igt@gem_lmem_swapping@smem-oom:
> - shard-mtlp: NOTRUN -> [SKIP][46] ([i915#4613]) +2 other tests skip
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@gem_lmem_swapping@smem-oom.html
>
> * igt@gem_lmem_swapping@smem-oom@lmem0:
> - shard-dg2: [PASS][47] -> [TIMEOUT][48] ([i915#5493])
> [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-dg2-7/igt@gem_lmem_swapping@smem-oom@lmem0.html
> [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-5/igt@gem_lmem_swapping@smem-oom@lmem0.html
>
> * igt@gem_lmem_swapping@verify:
> - shard-apl: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#4613]) +2 other tests skip
> [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-apl4/igt@gem_lmem_swapping@verify.html
>
> * igt@gem_lmem_swapping@verify-random:
> - shard-rkl: NOTRUN -> [SKIP][50] ([i915#4613]) +1 other test skip
> [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@gem_lmem_swapping@verify-random.html
>
> * igt@gem_mmap@big-bo:
> - shard-dg2: NOTRUN -> [SKIP][51] ([i915#4083]) +6 other tests skip
> [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gem_mmap@big-bo.html
>
> * igt@gem_mmap_gtt@cpuset-big-copy-odd:
> - shard-dg2: NOTRUN -> [SKIP][52] ([i915#4077]) +17 other tests skip
> [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
>
> * igt@gem_mmap_gtt@isolation:
> - shard-mtlp: NOTRUN -> [SKIP][53] ([i915#4077])
> [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@gem_mmap_gtt@isolation.html
>
> * igt@gem_mmap_wc@write-read-distinct:
> - shard-mtlp: NOTRUN -> [SKIP][54] ([i915#4083]) +1 other test skip
> [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@gem_mmap_wc@write-read-distinct.html
>
> * igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
> - shard-dg2: NOTRUN -> [SKIP][55] ([i915#3282]) +5 other tests skip
> [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
>
> * igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
> - shard-rkl: NOTRUN -> [SKIP][56] ([i915#3282]) +5 other tests skip
> [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
>
> * igt@gem_pwrite@basic-random:
> - shard-rkl: [PASS][57] -> [SKIP][58] ([i915#3282]) +10 other tests skip
> [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@gem_pwrite@basic-random.html
> [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-2/igt@gem_pwrite@basic-random.html
>
> * igt@gem_pxp@create-regular-context-2:
> - shard-dg2: NOTRUN -> [SKIP][59] ([i915#4270]) +3 other tests skip
> [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@gem_pxp@create-regular-context-2.html
> - shard-rkl: NOTRUN -> [SKIP][60] ([i915#4270]) +1 other test skip
> [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@gem_pxp@create-regular-context-2.html
>
> * igt@gem_readwrite@write-bad-handle:
> - shard-mtlp: NOTRUN -> [SKIP][61] ([i915#3282]) +1 other test skip
> [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@gem_readwrite@write-bad-handle.html
>
> * igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs:
> - shard-rkl: NOTRUN -> [SKIP][62] ([i915#768]) +3 other tests skip
> [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs.html
>
> * igt@gem_render_copy@y-tiled-to-vebox-y-tiled:
> - shard-mtlp: NOTRUN -> [SKIP][63] ([i915#8428]) +3 other tests skip
> [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@gem_render_copy@y-tiled-to-vebox-y-tiled.html
>
> * igt@gem_set_tiling_vs_blt@tiled-to-tiled:
> - shard-rkl: NOTRUN -> [SKIP][64] ([i915#8411])
> [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html
>
> * igt@gem_set_tiling_vs_blt@tiled-to-untiled:
> - shard-mtlp: NOTRUN -> [SKIP][65] ([i915#4079])
> [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
>
> * igt@gem_softpin@evict-snoop:
> - shard-dg2: NOTRUN -> [SKIP][66] ([i915#4885])
> [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@gem_softpin@evict-snoop.html
>
> * igt@gem_spin_batch@spin-all-new:
> - shard-dg2: NOTRUN -> [FAIL][67] ([i915#5889])
> [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gem_spin_batch@spin-all-new.html
>
> * igt@gem_tiled_pread_pwrite:
> - shard-dg2: NOTRUN -> [SKIP][68] ([i915#4079]) +1 other test skip
> [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gem_tiled_pread_pwrite.html
>
> * igt@gem_unfence_active_buffers:
> - shard-dg2: NOTRUN -> [SKIP][69] ([i915#4879])
> [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@gem_unfence_active_buffers.html
>
> * igt@gem_userptr_blits@dmabuf-sync:
> - shard-rkl: NOTRUN -> [SKIP][70] ([i915#3323])
> [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@gem_userptr_blits@dmabuf-sync.html
>
> * igt@gem_userptr_blits@dmabuf-unsync:
> - shard-mtlp: NOTRUN -> [SKIP][71] ([i915#3297])
> [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@gem_userptr_blits@dmabuf-unsync.html
>
> * igt@gem_userptr_blits@invalid-mmap-offset-unsync:
> - shard-dg2: NOTRUN -> [SKIP][72] ([i915#3297]) +3 other tests skip
> [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
> - shard-rkl: NOTRUN -> [SKIP][73] ([i915#3297]) +1 other test skip
> [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
>
> * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
> - shard-dg2: NOTRUN -> [SKIP][74] ([i915#3297] / [i915#4880]) +1 other test skip
> [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
>
> * igt@gem_userptr_blits@vma-merge:
> - shard-dg2: NOTRUN -> [FAIL][75] ([i915#3318])
> [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@gem_userptr_blits@vma-merge.html
> - shard-rkl: NOTRUN -> [FAIL][76] ([i915#3318])
> [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@gem_userptr_blits@vma-merge.html
>
> * igt@gen9_exec_parse@allowed-all:
> - shard-dg2: NOTRUN -> [SKIP][77] ([i915#2856]) +5 other tests skip
> [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@gen9_exec_parse@allowed-all.html
>
> * igt@gen9_exec_parse@allowed-single:
> - shard-mtlp: NOTRUN -> [SKIP][78] ([i915#2856])
> [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@gen9_exec_parse@allowed-single.html
>
> * igt@gen9_exec_parse@secure-batches:
> - shard-rkl: [PASS][79] -> [SKIP][80] ([i915#2527]) +5 other tests skip
> [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@gen9_exec_parse@secure-batches.html
> [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@gen9_exec_parse@secure-batches.html
>
> * igt@gen9_exec_parse@valid-registers:
> - shard-rkl: NOTRUN -> [SKIP][81] ([i915#2527]) +2 other tests skip
> [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@gen9_exec_parse@valid-registers.html
>
> * igt@i915_module_load@resize-bar:
> - shard-rkl: NOTRUN -> [SKIP][82] ([i915#6412])
> [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@i915_module_load@resize-bar.html
>
> * igt@i915_pm_freq_api@freq-suspend:
> - shard-rkl: NOTRUN -> [SKIP][83] ([i915#8399]) +1 other test skip
> [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@i915_pm_freq_api@freq-suspend.html
>
> * igt@i915_pm_rps@thresholds@gt0:
> - shard-dg2: NOTRUN -> [SKIP][84] ([i915#8925])
> [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@i915_pm_rps@thresholds@gt0.html
>
> * igt@i915_power@sanity:
> - shard-rkl: [PASS][85] -> [SKIP][86] ([i915#7984])
> [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@i915_power@sanity.html
> [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@i915_power@sanity.html
>
> * igt@i915_query@query-topology-unsupported:
> - shard-rkl: NOTRUN -> [SKIP][87] ([fdo#109302])
> [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@i915_query@query-topology-unsupported.html
>
> * igt@i915_query@test-query-geometry-subslices:
> - shard-rkl: NOTRUN -> [SKIP][88] ([i915#5723])
> [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@i915_query@test-query-geometry-subslices.html
>
> * igt@i915_selftest@mock@memory_region:
> - shard-dg2: NOTRUN -> [DMESG-WARN][89] ([i915#9311])
> [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@i915_selftest@mock@memory_region.html
>
> * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
> - shard-mtlp: NOTRUN -> [SKIP][90] ([i915#4212]) +1 other test skip
> [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
>
> * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
> - shard-dg2: NOTRUN -> [SKIP][91] ([i915#4212])
> [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
>
> * igt@kms_addfb_basic@basic-y-tiled-legacy:
> - shard-dg2: NOTRUN -> [SKIP][92] ([i915#4215] / [i915#5190])
> [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_addfb_basic@basic-y-tiled-legacy.html
>
> * igt@kms_async_flips@crc:
> - shard-rkl: NOTRUN -> [SKIP][93] ([i915#1845] / [i915#4098]) +10 other tests skip
> [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_async_flips@crc.html
>
> * igt@kms_async_flips@crc@pipe-c-hdmi-a-1:
> - shard-dg1: NOTRUN -> [FAIL][94] ([i915#8247]) +3 other tests fail
> [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg1-19/igt@kms_async_flips@crc@pipe-c-hdmi-a-1.html
>
> * igt@kms_async_flips@crc@pipe-d-dp-4:
> - shard-dg2: NOTRUN -> [FAIL][95] ([i915#8247]) +3 other tests fail
> [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_async_flips@crc@pipe-d-dp-4.html
>
> * igt@kms_async_flips@invalid-async-flip:
> - shard-dg2: NOTRUN -> [SKIP][96] ([i915#6228])
> [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_async_flips@invalid-async-flip.html
>
> * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
> - shard-dg2: NOTRUN -> [SKIP][97] ([i915#1769] / [i915#3555])
> [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
>
> * igt@kms_big_fb@4-tiled-16bpp-rotate-0:
> - shard-rkl: NOTRUN -> [SKIP][98] ([i915#5286]) +3 other tests skip
> [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html
>
> * igt@kms_big_fb@4-tiled-64bpp-rotate-180:
> - shard-mtlp: [PASS][99] -> [FAIL][100] ([i915#5138])
> [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-mtlp-1/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
> [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-7/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
>
> * igt@kms_big_fb@x-tiled-32bpp-rotate-270:
> - shard-dg2: NOTRUN -> [SKIP][101] ([fdo#111614]) +5 other tests skip
> [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
>
> * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
> - shard-mtlp: NOTRUN -> [SKIP][102] ([fdo#111614]) +2 other tests skip
> [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
>
> * igt@kms_big_fb@y-tiled-64bpp-rotate-0:
> - shard-dg2: NOTRUN -> [SKIP][103] ([i915#5190]) +17 other tests skip
> [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
>
> * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
> - shard-rkl: NOTRUN -> [SKIP][104] ([fdo#111614] / [i915#3638]) +5 other tests skip
> [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
>
> * igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
> - shard-mtlp: NOTRUN -> [SKIP][105] ([fdo#111615]) +3 other tests skip
> [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
>
> * igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
> - shard-dg2: NOTRUN -> [SKIP][106] ([i915#4538] / [i915#5190]) +4 other tests skip
> [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html
>
> * igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
> - shard-rkl: NOTRUN -> [SKIP][107] ([fdo#110723]) +3 other tests skip
> [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html
>
> * igt@kms_big_joiner@invalid-modeset:
> - shard-mtlp: NOTRUN -> [SKIP][108] ([i915#2705])
> [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_big_joiner@invalid-modeset.html
>
> * igt@kms_cdclk@mode-transition-all-outputs:
> - shard-dg2: NOTRUN -> [SKIP][109] ([i915#4087] / [i915#7213])
> [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_cdclk@mode-transition-all-outputs.html
>
> * igt@kms_cdclk@mode-transition@pipe-b-edp-1:
> - shard-mtlp: NOTRUN -> [SKIP][110] ([i915#7213] / [i915#9010]) +3 other tests skip
> [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_cdclk@mode-transition@pipe-b-edp-1.html
>
> * igt@kms_chamelium_color@ctm-negative:
> - shard-dg2: NOTRUN -> [SKIP][111] ([fdo#111827]) +2 other tests skip
> [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_chamelium_color@ctm-negative.html
> - shard-rkl: NOTRUN -> [SKIP][112] ([fdo#111827])
> [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@kms_chamelium_color@ctm-negative.html
>
> * igt@kms_chamelium_edid@hdmi-edid-read:
> - shard-rkl: NOTRUN -> [SKIP][113] ([i915#7828]) +4 other tests skip
> [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_chamelium_edid@hdmi-edid-read.html
>
> * igt@kms_chamelium_frames@dp-frame-dump:
> - shard-dg2: NOTRUN -> [SKIP][114] ([i915#7828]) +9 other tests skip
> [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_chamelium_frames@dp-frame-dump.html
>
> * igt@kms_chamelium_hpd@vga-hpd:
> - shard-mtlp: NOTRUN -> [SKIP][115] ([i915#7828]) +5 other tests skip
> [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_chamelium_hpd@vga-hpd.html
>
> * igt@kms_color@ctm-green-to-red@pipe-b:
> - shard-rkl: [PASS][116] -> [SKIP][117] ([i915#4098]) +3 other tests skip
> [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_color@ctm-green-to-red@pipe-b.html
> [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_color@ctm-green-to-red@pipe-b.html
>
> * igt@kms_content_protection@atomic:
> - shard-mtlp: NOTRUN -> [SKIP][118] ([i915#6944])
> [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_content_protection@atomic.html
>
> * igt@kms_content_protection@dp-mst-lic-type-1:
> - shard-dg2: NOTRUN -> [SKIP][119] ([i915#3299]) +1 other test skip
> [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_content_protection@dp-mst-lic-type-1.html
>
> * igt@kms_content_protection@dp-mst-type-1:
> - shard-rkl: NOTRUN -> [SKIP][120] ([i915#3116])
> [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@kms_content_protection@dp-mst-type-1.html
>
> * igt@kms_content_protection@lic@pipe-a-dp-1:
> - shard-apl: NOTRUN -> [TIMEOUT][121] ([i915#7173]) +1 other test timeout
> [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-apl3/igt@kms_content_protection@lic@pipe-a-dp-1.html
>
> * igt@kms_content_protection@srm:
> - shard-rkl: NOTRUN -> [SKIP][122] ([i915#7118]) +1 other test skip
> [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_content_protection@srm.html
>
> * igt@kms_cursor_crc@cursor-random-512x170:
> - shard-dg2: NOTRUN -> [SKIP][123] ([i915#3359]) +2 other tests skip
> [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_cursor_crc@cursor-random-512x170.html
>
> * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
> - shard-mtlp: NOTRUN -> [SKIP][124] ([i915#3555] / [i915#8814])
> [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
>
> * igt@kms_cursor_crc@cursor-rapid-movement-32x32:
> - shard-dg2: NOTRUN -> [SKIP][125] ([i915#3555]) +7 other tests skip
> [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html
>
> * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
> - shard-rkl: NOTRUN -> [SKIP][126] ([i915#3359])
> [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
>
> * igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
> - shard-dg2: NOTRUN -> [SKIP][127] ([fdo#109274] / [i915#5354]) +2 other tests skip
> [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
>
> * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
> - shard-dg2: NOTRUN -> [SKIP][128] ([fdo#109274] / [fdo#111767] / [i915#5354]) +1 other test skip
> [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
> - shard-rkl: NOTRUN -> [SKIP][129] ([fdo#111767] / [fdo#111825])
> [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
>
> * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
> - shard-rkl: NOTRUN -> [SKIP][130] ([i915#4103]) +2 other tests skip
> [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
>
> * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
> - shard-mtlp: NOTRUN -> [SKIP][131] ([i915#3546]) +2 other tests skip
> [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
>
> * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
> - shard-dg2: NOTRUN -> [SKIP][132] ([i915#4103] / [i915#4213])
> [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
>
> * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
> - shard-rkl: NOTRUN -> [SKIP][133] ([i915#3804])
> [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html
>
> * igt@kms_dp_aux_dev:
> - shard-rkl: NOTRUN -> [SKIP][134] ([i915#1257])
> [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@kms_dp_aux_dev.html
>
> * igt@kms_draw_crc@draw-method-mmap-gtt:
> - shard-dg2: NOTRUN -> [SKIP][135] ([i915#8812])
> [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_draw_crc@draw-method-mmap-gtt.html
>
> * igt@kms_dsc@dsc-basic:
> - shard-rkl: NOTRUN -> [SKIP][136] ([i915#3555] / [i915#3840])
> [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_dsc@dsc-basic.html
>
> * igt@kms_dsc@dsc-with-bpc:
> - shard-dg2: NOTRUN -> [SKIP][137] ([i915#3555] / [i915#3840])
> [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_dsc@dsc-with-bpc.html
>
> * igt@kms_dsc@dsc-with-bpc-formats:
> - shard-mtlp: NOTRUN -> [SKIP][138] ([i915#3555] / [i915#3840])
> [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_dsc@dsc-with-bpc-formats.html
>
> * igt@kms_flip@2x-blocking-wf_vblank:
> - shard-dg2: NOTRUN -> [SKIP][139] ([fdo#109274]) +4 other tests skip
> [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_flip@2x-blocking-wf_vblank.html
>
> * igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
> - shard-dg2: NOTRUN -> [SKIP][140] ([fdo#109274] / [fdo#111767])
> [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
>
> * igt@kms_flip@2x-flip-vs-fences:
> - shard-dg2: NOTRUN -> [SKIP][141] ([i915#8381]) +1 other test skip
> [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_flip@2x-flip-vs-fences.html
>
> * igt@kms_flip@2x-flip-vs-panning-vs-hang:
> - shard-rkl: NOTRUN -> [SKIP][142] ([fdo#111825]) +4 other tests skip
> [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
>
> * igt@kms_flip@2x-flip-vs-rmfb:
> - shard-mtlp: NOTRUN -> [SKIP][143] ([i915#3637]) +1 other test skip
> [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_flip@2x-flip-vs-rmfb.html
>
> * igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-vga1-hdmi-a1:
> - shard-snb: NOTRUN -> [DMESG-WARN][144] ([i915#8841])
> [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-snb1/igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-vga1-hdmi-a1.html
>
> * igt@kms_flip@bo-too-big-interruptible:
> - shard-rkl: NOTRUN -> [SKIP][145] ([i915#3637] / [i915#4098]) +10 other tests skip
> [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_flip@bo-too-big-interruptible.html
>
> * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
> - shard-rkl: NOTRUN -> [SKIP][146] ([i915#2672]) +5 other tests skip
> [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
>
> * igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling@pipe-a-default-mode:
> - shard-mtlp: NOTRUN -> [SKIP][147] ([i915#3555] / [i915#8810])
> [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling@pipe-a-default-mode.html
>
> * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode:
> - shard-mtlp: NOTRUN -> [SKIP][148] ([i915#2672] / [i915#3555])
> [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
>
> * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode:
> - shard-mtlp: NOTRUN -> [SKIP][149] ([i915#2672])
> [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode.html
>
> * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
> - shard-rkl: NOTRUN -> [SKIP][150] ([i915#3555]) +11 other tests skip
> [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
>
> * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode:
> - shard-dg2: NOTRUN -> [SKIP][151] ([i915#2672]) +6 other tests skip
> [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode.html
>
> * igt@kms_force_connector_basic@force-load-detect:
> - shard-mtlp: NOTRUN -> [SKIP][152] ([fdo#109285])
> [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_force_connector_basic@force-load-detect.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt:
> - shard-dg2: [PASS][153] -> [FAIL][154] ([i915#6880])
> [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html
> [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
> - shard-rkl: [PASS][155] -> [SKIP][156] ([i915#1849] / [i915#4098]) +17 other tests skip
> [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite.html
> [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
> - shard-dg2: NOTRUN -> [SKIP][157] ([i915#8708]) +12 other tests skip
> [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html
>
> * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt:
> - shard-mtlp: NOTRUN -> [SKIP][158] ([i915#8708]) +1 other test skip
> [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
> - shard-rkl: NOTRUN -> [SKIP][159] ([i915#3023]) +18 other tests skip
> [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
> - shard-mtlp: NOTRUN -> [SKIP][160] ([i915#1825]) +13 other tests skip
> [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff:
> - shard-rkl: NOTRUN -> [SKIP][161] ([fdo#111825] / [i915#1825]) +25 other tests skip
> [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
> - shard-apl: NOTRUN -> [SKIP][162] ([fdo#109271]) +131 other tests skip
> [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-apl3/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
> - shard-dg2: NOTRUN -> [SKIP][163] ([i915#5460])
> [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
> - shard-dg2: NOTRUN -> [SKIP][164] ([i915#3458]) +22 other tests skip
> [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
>
> * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt:
> - shard-dg2: NOTRUN -> [SKIP][165] ([i915#5354]) +36 other tests skip
> [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt.html
>
> * igt@kms_getfb@getfb-reject-ccs:
> - shard-dg2: NOTRUN -> [SKIP][166] ([i915#6118])
> [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_getfb@getfb-reject-ccs.html
>
> * igt@kms_hdr@static-swap:
> - shard-dg2: NOTRUN -> [SKIP][167] ([i915#3555] / [i915#8228])
> [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_hdr@static-swap.html
>
> * igt@kms_invalid_mode@bad-htotal:
> - shard-rkl: NOTRUN -> [SKIP][168] ([i915#3555] / [i915#4098])
> [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_invalid_mode@bad-htotal.html
>
> * igt@kms_panel_fitting@legacy:
> - shard-dg2: NOTRUN -> [SKIP][169] ([i915#6301])
> [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_panel_fitting@legacy.html
>
> * igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
> - shard-dg2: NOTRUN -> [SKIP][170] ([fdo#109289]) +2 other tests skip
> [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html
>
> * igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c:
> - shard-mtlp: NOTRUN -> [SKIP][171] ([fdo#109289]) +2 other tests skip
> [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c.html
>
> * igt@kms_pipe_crc_basic@bad-source:
> - shard-rkl: [PASS][172] -> [SKIP][173] ([i915#1845] / [i915#4098]) +22 other tests skip
> [172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_pipe_crc_basic@bad-source.html
> [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_pipe_crc_basic@bad-source.html
>
> * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-hdmi-a-1:
> - shard-snb: NOTRUN -> [SKIP][174] ([fdo#109271]) +28 other tests skip
> [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-snb1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-hdmi-a-1.html
>
> * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-1:
> - shard-apl: [PASS][175] -> [ABORT][176] ([i915#180])
> [175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-apl1/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-1.html
> [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-apl7/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-1.html
>
> * igt@kms_plane@plane-position-hole-dpms:
> - shard-rkl: NOTRUN -> [SKIP][177] ([i915#4098] / [i915#8825])
> [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_plane@plane-position-hole-dpms.html
>
> * igt@kms_plane_alpha_blend@constant-alpha-max@pipe-c-hdmi-a-1:
> - shard-glk: NOTRUN -> [FAIL][178] ([i915#4573]) +1 other test fail
> [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-glk5/igt@kms_plane_alpha_blend@constant-alpha-max@pipe-c-hdmi-a-1.html
>
> * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
> - shard-rkl: NOTRUN -> [FAIL][179] ([i915#8292])
> [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
>
> * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4:
> - shard-dg1: NOTRUN -> [FAIL][180] ([i915#8292])
> [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg1-16/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4.html
>
> * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation:
> - shard-rkl: NOTRUN -> [SKIP][181] ([i915#3555] / [i915#4098] / [i915#8152])
> [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation.html
>
> * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-1:
> - shard-dg1: NOTRUN -> [SKIP][182] ([i915#5235]) +7 other tests skip
> [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg1-19/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-1.html
>
> * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-2:
> - shard-dg2: NOTRUN -> [SKIP][183] ([i915#5235]) +3 other tests skip
> [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-2.html
>
> * igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling:
> - shard-rkl: NOTRUN -> [SKIP][184] ([i915#8152]) +1 other test skip
> [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling.html
>
> * igt@kms_plane_scaling@planes-upscale-20x20:
> - shard-rkl: NOTRUN -> [SKIP][185] ([i915#4098] / [i915#6953] / [i915#8152])
> [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_plane_scaling@planes-upscale-20x20.html
>
> * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-c-edp-1:
> - shard-mtlp: NOTRUN -> [SKIP][186] ([i915#5235]) +2 other tests skip
> [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-c-edp-1.html
>
> * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-d-edp-1:
> - shard-mtlp: NOTRUN -> [SKIP][187] ([i915#3555] / [i915#5235])
> [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-d-edp-1.html
>
> * igt@kms_plane_scaling@planes-upscale-factor-0-25:
> - shard-rkl: NOTRUN -> [SKIP][188] ([i915#3555] / [i915#4098] / [i915#6953] / [i915#8152])
> [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_plane_scaling@planes-upscale-factor-0-25.html
>
> * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2:
> - shard-rkl: NOTRUN -> [SKIP][189] ([i915#5235]) +5 other tests skip
> [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2.html
>
> * igt@kms_prime@basic-crc-hybrid:
> - shard-dg2: NOTRUN -> [SKIP][190] ([i915#6524] / [i915#6805]) +1 other test skip
> [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_prime@basic-crc-hybrid.html
>
> * igt@kms_properties@plane-properties-legacy:
> - shard-rkl: [PASS][191] -> [SKIP][192] ([i915#1849]) +1 other test skip
> [191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_properties@plane-properties-legacy.html
> [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_properties@plane-properties-legacy.html
>
> * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf:
> - shard-rkl: NOTRUN -> [SKIP][193] ([i915#658])
> [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
>
> * igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf:
> - shard-glk: NOTRUN -> [SKIP][194] ([fdo#109271] / [i915#658])
> [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-glk5/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
>
> * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
> - shard-apl: NOTRUN -> [SKIP][195] ([fdo#109271] / [i915#658]) +2 other tests skip
> [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-apl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
>
> * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
> - shard-dg2: NOTRUN -> [SKIP][196] ([i915#658]) +3 other tests skip
> [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
>
> * igt@kms_psr2_su@page_flip-p010:
> - shard-rkl: NOTRUN -> [SKIP][197] ([fdo#111068] / [i915#658]) +1 other test skip
> [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@kms_psr2_su@page_flip-p010.html
>
> * igt@kms_psr@primary_page_flip:
> - shard-rkl: NOTRUN -> [SKIP][198] ([i915#1072]) +4 other tests skip
> [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_psr@primary_page_flip.html
>
> * igt@kms_psr@psr2_cursor_mmap_gtt:
> - shard-glk: NOTRUN -> [SKIP][199] ([fdo#109271]) +36 other tests skip
> [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-glk5/igt@kms_psr@psr2_cursor_mmap_gtt.html
>
> * igt@kms_psr@psr2_sprite_blt:
> - shard-dg2: NOTRUN -> [SKIP][200] ([i915#1072]) +7 other tests skip
> [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@kms_psr@psr2_sprite_blt.html
>
> * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
> - shard-rkl: NOTRUN -> [SKIP][201] ([i915#5461] / [i915#658])
> [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
>
> * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
> - shard-rkl: NOTRUN -> [SKIP][202] ([i915#5289])
> [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
>
> * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
> - shard-mtlp: NOTRUN -> [SKIP][203] ([i915#4235]) +1 other test skip
> [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
>
> * igt@kms_setmode@clone-exclusive-crtc:
> - shard-mtlp: NOTRUN -> [SKIP][204] ([i915#3555] / [i915#8809])
> [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_setmode@clone-exclusive-crtc.html
>
> * igt@kms_tv_load_detect@load-detect:
> - shard-dg2: NOTRUN -> [SKIP][205] ([fdo#109309])
> [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@kms_tv_load_detect@load-detect.html
>
> * igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1:
> - shard-mtlp: [PASS][206] -> [FAIL][207] ([i915#9196])
> [206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-mtlp-3/igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1.html
> [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1.html
>
> * igt@kms_vblank@wait-forked-busy-hang:
> - shard-rkl: NOTRUN -> [SKIP][208] ([i915#4098]) +21 other tests skip
> [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_vblank@wait-forked-busy-hang.html
>
> * igt@kms_vrr@flip-dpms:
> - shard-mtlp: NOTRUN -> [SKIP][209] ([i915#3555] / [i915#8808])
> [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-8/igt@kms_vrr@flip-dpms.html
>
> * igt@kms_writeback@writeback-check-output:
> - shard-mtlp: NOTRUN -> [SKIP][210] ([i915#2437])
> [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@kms_writeback@writeback-check-output.html
>
> * igt@kms_writeback@writeback-fb-id:
> - shard-rkl: NOTRUN -> [SKIP][211] ([i915#2437])
> [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_writeback@writeback-fb-id.html
>
> * igt@perf@enable-disable@0-rcs0:
> - shard-dg2: NOTRUN -> [FAIL][212] ([i915#8724])
> [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@perf@enable-disable@0-rcs0.html
>
> * igt@perf@gen8-unprivileged-single-ctx-counters:
> - shard-rkl: [PASS][213] -> [SKIP][214] ([i915#2436])
> [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@perf@gen8-unprivileged-single-ctx-counters.html
> [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-6/igt@perf@gen8-unprivileged-single-ctx-counters.html
>
> * igt@perf@global-sseu-config:
> - shard-dg2: NOTRUN -> [SKIP][215] ([i915#7387])
> [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@perf@global-sseu-config.html
>
> * igt@perf_pmu@cpu-hotplug:
> - shard-rkl: NOTRUN -> [SKIP][216] ([i915#8850])
> [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@perf_pmu@cpu-hotplug.html
>
> * igt@perf_pmu@frequency@gt0:
> - shard-dg2: NOTRUN -> [FAIL][217] ([i915#6806])
> [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@perf_pmu@frequency@gt0.html
>
> * igt@perf_pmu@module-unload:
> - shard-dg2: NOTRUN -> [FAIL][218] ([i915#5793])
> [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@perf_pmu@module-unload.html
>
> * igt@perf_pmu@rc6@other-idle-gt0:
> - shard-dg2: NOTRUN -> [SKIP][219] ([i915#8516])
> [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@perf_pmu@rc6@other-idle-gt0.html
>
> * igt@prime_udl:
> - shard-dg2: NOTRUN -> [SKIP][220] ([fdo#109291])
> [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@prime_udl.html
>
> * igt@prime_vgem@basic-fence-mmap:
> - shard-mtlp: NOTRUN -> [SKIP][221] ([i915#3708] / [i915#4077])
> [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@prime_vgem@basic-fence-mmap.html
>
> * igt@prime_vgem@basic-write:
> - shard-dg2: NOTRUN -> [SKIP][222] ([i915#3291] / [i915#3708])
> [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@prime_vgem@basic-write.html
>
> * igt@prime_vgem@fence-read-hang:
> - shard-rkl: NOTRUN -> [SKIP][223] ([fdo#109295] / [i915#3708])
> [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@prime_vgem@fence-read-hang.html
>
> * igt@syncobj_timeline@invalid-multi-wait-all-available-unsubmitted-submitted:
> - shard-rkl: NOTRUN -> [FAIL][224] ([i915#9583]) +1 other test fail
> [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@syncobj_timeline@invalid-multi-wait-all-available-unsubmitted-submitted.html
>
> * igt@syncobj_timeline@invalid-multi-wait-available-unsubmitted:
> - shard-dg2: NOTRUN -> [FAIL][225] ([i915#9583])
> [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@syncobj_timeline@invalid-multi-wait-available-unsubmitted.html
>
> * igt@syncobj_timeline@invalid-multi-wait-available-unsubmitted-submitted:
> - shard-snb: NOTRUN -> [FAIL][226] ([i915#9583])
> [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-snb7/igt@syncobj_timeline@invalid-multi-wait-available-unsubmitted-submitted.html
>
> * igt@v3d/v3d_submit_cl@bad-multisync-in-sync:
> - shard-rkl: NOTRUN -> [SKIP][227] ([fdo#109315]) +7 other tests skip
> [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@v3d/v3d_submit_cl@bad-multisync-in-sync.html
>
> * igt@v3d/v3d_submit_cl@simple-flush-cache:
> - shard-mtlp: NOTRUN -> [SKIP][228] ([i915#2575]) +4 other tests skip
> [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@v3d/v3d_submit_cl@simple-flush-cache.html
>
> * igt@v3d/v3d_submit_csd@bad-flag:
> - shard-dg2: NOTRUN -> [SKIP][229] ([i915#2575]) +13 other tests skip
> [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-11/igt@v3d/v3d_submit_csd@bad-flag.html
>
> * igt@vc4/vc4_create_bo@create-bo-4096:
> - shard-dg2: NOTRUN -> [SKIP][230] ([i915#7711]) +9 other tests skip
> [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-2/igt@vc4/vc4_create_bo@create-bo-4096.html
> - shard-rkl: NOTRUN -> [SKIP][231] ([i915#7711]) +6 other tests skip
> [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@vc4/vc4_create_bo@create-bo-4096.html
>
> * igt@vc4/vc4_tiling@get-bad-modifier:
> - shard-mtlp: NOTRUN -> [SKIP][232] ([i915#7711]) +3 other tests skip
> [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@vc4/vc4_tiling@get-bad-modifier.html
>
>
> #### Possible fixes ####
>
> * igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
> - shard-rkl: [FAIL][233] ([i915#7742]) -> [PASS][234]
> [233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
> [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
>
> * igt@fbdev@nullptr:
> - shard-rkl: [SKIP][235] ([i915#2582]) -> [PASS][236] +1 other test pass
> [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@fbdev@nullptr.html
> [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@fbdev@nullptr.html
>
> * igt@gem_ctx_exec@basic-nohangcheck:
> - shard-rkl: [FAIL][237] ([i915#6268]) -> [PASS][238]
> [237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@gem_ctx_exec@basic-nohangcheck.html
> [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@gem_ctx_exec@basic-nohangcheck.html
> - shard-tglu: [FAIL][239] ([i915#6268]) -> [PASS][240]
> [239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-tglu-3/igt@gem_ctx_exec@basic-nohangcheck.html
> [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-tglu-2/igt@gem_ctx_exec@basic-nohangcheck.html
>
> * igt@gem_ctx_persistence@engines-hang@bcs0:
> - shard-rkl: [SKIP][241] ([i915#6252]) -> [PASS][242] +1 other test pass
> [241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@gem_ctx_persistence@engines-hang@bcs0.html
> [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@gem_ctx_persistence@engines-hang@bcs0.html
>
> * igt@gem_eio@in-flight-contexts-10ms:
> - shard-mtlp: [ABORT][243] ([i915#9414]) -> [PASS][244]
> [243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-mtlp-5/igt@gem_eio@in-flight-contexts-10ms.html
> [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-mtlp-5/igt@gem_eio@in-flight-contexts-10ms.html
>
> * igt@gem_exec_balancer@fairslice:
> - shard-rkl: [SKIP][245] ([Intel XE#874]) -> [PASS][246]
> [245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@gem_exec_balancer@fairslice.html
> [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@gem_exec_balancer@fairslice.html
>
> * igt@gem_exec_fair@basic-pace-share@rcs0:
> - shard-glk: [FAIL][247] ([i915#2842]) -> [PASS][248]
> [247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
> [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
>
> * igt@gem_exec_fair@basic-pace-solo@rcs0:
> - shard-rkl: [FAIL][249] ([i915#2842]) -> [PASS][250]
> [249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
> [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
>
> * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
> - shard-rkl: [SKIP][251] ([fdo#109313]) -> [PASS][252]
> [251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
> [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
>
> * igt@gem_exec_reloc@basic-write-read-noreloc:
> - shard-rkl: [SKIP][253] ([i915#3281]) -> [PASS][254] +13 other tests pass
> [253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@gem_exec_reloc@basic-write-read-noreloc.html
> [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@gem_exec_reloc@basic-write-read-noreloc.html
>
> * igt@gem_exec_schedule@semaphore-power:
> - shard-rkl: [SKIP][255] ([i915#7276]) -> [PASS][256]
> [255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@gem_exec_schedule@semaphore-power.html
> [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@gem_exec_schedule@semaphore-power.html
>
> * igt@gem_mmap_gtt@coherency:
> - shard-rkl: [SKIP][257] ([fdo#111656]) -> [PASS][258]
> [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@gem_mmap_gtt@coherency.html
> [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@gem_mmap_gtt@coherency.html
>
> * igt@gem_pread@snoop:
> - shard-rkl: [SKIP][259] ([i915#3282]) -> [PASS][260] +3 other tests pass
> [259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@gem_pread@snoop.html
> [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@gem_pread@snoop.html
>
> * igt@gem_set_tiling_vs_blt@tiled-to-untiled:
> - shard-rkl: [SKIP][261] ([i915#8411]) -> [PASS][262]
> [261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
> [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
>
> * igt@gen9_exec_parse@allowed-all:
> - shard-rkl: [SKIP][263] ([i915#2527]) -> [PASS][264] +3 other tests pass
> [263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@gen9_exec_parse@allowed-all.html
> [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@gen9_exec_parse@allowed-all.html
>
> * igt@i915_hangman@engine-engine-error@bcs0:
> - shard-rkl: [SKIP][265] ([i915#9588]) -> [PASS][266]
> [265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@i915_hangman@engine-engine-error@bcs0.html
> [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@i915_hangman@engine-engine-error@bcs0.html
>
> * igt@i915_pm_rc6_residency@rc6-idle@bcs0:
> - shard-dg1: [FAIL][267] ([i915#3591]) -> [PASS][268]
> [267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html
> [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html
>
> * igt@i915_pm_rps@reset:
> - shard-snb: [INCOMPLETE][269] ([i915#7790]) -> [PASS][270]
> [269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-snb7/igt@i915_pm_rps@reset.html
> [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-snb7/igt@i915_pm_rps@reset.html
>
> * igt@kms_big_fb@x-tiled-32bpp-rotate-0:
> - shard-rkl: [SKIP][271] ([i915#1845] / [i915#4098]) -> [PASS][272] +33 other tests pass
> [271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
> [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-2/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
>
> * {igt@kms_ccs@pipe-b-bad-pixel-format-y-tiled-gen12-rc-ccs}:
> - shard-rkl: [SKIP][273] ([i915#4098]) -> [PASS][274] +18 other tests pass
> [273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_ccs@pipe-b-bad-pixel-format-y-tiled-gen12-rc-ccs.html
> [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-2/igt@kms_ccs@pipe-b-bad-pixel-format-y-tiled-gen12-rc-ccs.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
> - shard-rkl: [SKIP][275] ([i915#1849] / [i915#4098]) -> [PASS][276] +12 other tests pass
> [275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html
> [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html
>
> * {igt@kms_pm_rpm@dpms-mode-unset-non-lpsp}:
> - shard-rkl: [SKIP][277] ([i915#9519]) -> [PASS][278]
> [277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
> [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
>
> * igt@kms_properties@plane-properties-atomic:
> - shard-rkl: [SKIP][279] ([i915#1849]) -> [PASS][280]
> [279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_properties@plane-properties-atomic.html
> [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-6/igt@kms_properties@plane-properties-atomic.html
>
> * igt@kms_rotation_crc@bad-pixel-format:
> - shard-rkl: [INCOMPLETE][281] ([i915#8875] / [i915#9569]) -> [PASS][282]
> [281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@kms_rotation_crc@bad-pixel-format.html
> [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_rotation_crc@bad-pixel-format.html
>
> * {igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-3}:
> - shard-dg1: [FAIL][283] ([i915#9196]) -> [PASS][284]
> [283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-dg1-13/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-3.html
> [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg1-13/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-3.html
>
> * igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1:
> - shard-tglu: [FAIL][285] ([i915#9196]) -> [PASS][286]
> [285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-tglu-7/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
> [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-tglu-9/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
>
> * igt@perf@non-zero-reason@0-rcs0:
> - shard-dg2: [FAIL][287] ([i915#7484]) -> [PASS][288]
> [287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-dg2-7/igt@perf@non-zero-reason@0-rcs0.html
> [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg2-5/igt@perf@non-zero-reason@0-rcs0.html
>
>
> #### Warnings ####
>
> * igt@gem_ccs@block-multicopy-inplace:
> - shard-rkl: [SKIP][289] ([i915#7957]) -> [SKIP][290] ([i915#3555])
> [289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@gem_ccs@block-multicopy-inplace.html
> [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@gem_ccs@block-multicopy-inplace.html
>
> * igt@gem_ccs@suspend-resume:
> - shard-rkl: [SKIP][291] ([i915#7957]) -> [SKIP][292] ([i915#9323])
> [291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@gem_ccs@suspend-resume.html
> [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@gem_ccs@suspend-resume.html
>
> * igt@gem_exec_fair@basic-pace@bcs0:
> - shard-rkl: [SKIP][293] ([i915#9591]) -> [FAIL][294] ([i915#2842])
> [293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@gem_exec_fair@basic-pace@bcs0.html
> [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-6/igt@gem_exec_fair@basic-pace@bcs0.html
>
> * igt@gen9_exec_parse@bb-secure:
> - shard-dg1: [SKIP][295] ([i915#2527] / [i915#4423]) -> [SKIP][296] ([i915#2527])
> [295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-dg1-16/igt@gen9_exec_parse@bb-secure.html
> [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-dg1-17/igt@gen9_exec_parse@bb-secure.html
>
> * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
> - shard-rkl: [SKIP][297] ([i915#1769] / [i915#3555]) -> [SKIP][298] ([i915#1845] / [i915#4098]) +1 other test skip
> [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
> [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
>
> * igt@kms_big_fb@4-tiled-32bpp-rotate-180:
> - shard-rkl: [SKIP][299] ([i915#4098]) -> [SKIP][300] ([i915#5286]) +6 other tests skip
> [299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_big_fb@4-tiled-32bpp-rotate-180.html
> [300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-2/igt@kms_big_fb@4-tiled-32bpp-rotate-180.html
>
> * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
> - shard-rkl: [SKIP][301] ([i915#5286]) -> [SKIP][302] ([i915#4098]) +6 other tests skip
> [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
> [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
>
> * igt@kms_big_fb@linear-64bpp-rotate-90:
> - shard-rkl: [SKIP][303] ([i915#1845] / [i915#4098]) -> [SKIP][304] ([fdo#111614] / [i915#3638]) +4 other tests skip
> [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_big_fb@linear-64bpp-rotate-90.html
> [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@kms_big_fb@linear-64bpp-rotate-90.html
>
> * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
> - shard-rkl: [SKIP][305] ([fdo#111614] / [i915#3638]) -> [SKIP][306] ([i915#1845] / [i915#4098]) +5 other tests skip
> [305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
> [306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
>
> * igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
> - shard-rkl: [SKIP][307] ([fdo#110723]) -> [SKIP][308] ([i915#1845] / [i915#4098]) +5 other tests skip
> [307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
> [308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
>
> * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
> - shard-rkl: [SKIP][309] ([fdo#111615]) -> [SKIP][310] ([i915#1845] / [i915#4098])
> [309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
> [310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
>
> * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
> - shard-rkl: [SKIP][311] ([i915#1845] / [i915#4098]) -> [SKIP][312] ([fdo#110723]) +7 other tests skip
> [311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
> [312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
>
> * igt@kms_content_protection@dp-mst-lic-type-1:
> - shard-rkl: [SKIP][313] ([i915#1845] / [i915#4098]) -> [SKIP][314] ([i915#3116]) +1 other test skip
> [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_content_protection@dp-mst-lic-type-1.html
> [314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_content_protection@dp-mst-lic-type-1.html
>
> * igt@kms_content_protection@lic:
> - shard-rkl: [SKIP][315] ([i915#7118]) -> [SKIP][316] ([i915#1845] / [i915#4098])
> [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_content_protection@lic.html
> [316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_content_protection@lic.html
>
> * igt@kms_cursor_crc@cursor-random-512x512:
> - shard-rkl: [SKIP][317] ([i915#3359]) -> [SKIP][318] ([i915#4098]) +1 other test skip
> [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_cursor_crc@cursor-random-512x512.html
> [318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_cursor_crc@cursor-random-512x512.html
>
> * igt@kms_cursor_crc@cursor-sliding-max-size:
> - shard-rkl: [SKIP][319] ([i915#3555]) -> [SKIP][320] ([i915#4098]) +4 other tests skip
> [319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@kms_cursor_crc@cursor-sliding-max-size.html
> [320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_cursor_crc@cursor-sliding-max-size.html
>
> * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
> - shard-rkl: [SKIP][321] ([fdo#111825]) -> [SKIP][322] ([i915#1845] / [i915#4098]) +7 other tests skip
> [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
> [322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
>
> * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
> - shard-rkl: [SKIP][323] ([i915#1845] / [i915#4098]) -> [SKIP][324] ([fdo#111767] / [fdo#111825]) +1 other test skip
> [323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
> [324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-6/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
>
> * igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
> - shard-rkl: [SKIP][325] ([i915#1845] / [i915#4098]) -> [SKIP][326] ([fdo#111825]) +5 other tests skip
> [325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
> [326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-2/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
>
> * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
> - shard-rkl: [SKIP][327] ([i915#4103]) -> [SKIP][328] ([i915#1845] / [i915#4098])
> [327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
> [328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
>
> * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
> - shard-rkl: [SKIP][329] ([i915#1845] / [i915#4098]) -> [SKIP][330] ([i915#4103])
> [329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
> [330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
>
> * igt@kms_dsc@dsc-with-output-formats:
> - shard-rkl: [SKIP][331] ([i915#3555] / [i915#3840]) -> [SKIP][332] ([i915#4098]) +1 other test skip
> [331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_dsc@dsc-with-output-formats.html
> [332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_dsc@dsc-with-output-formats.html
>
> * igt@kms_fbcon_fbt@psr:
> - shard-rkl: [SKIP][333] ([i915#3955]) -> [SKIP][334] ([fdo#110189] / [i915#3955])
> [333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-6/igt@kms_fbcon_fbt@psr.html
> [334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-1/igt@kms_fbcon_fbt@psr.html
>
> * igt@kms_force_connector_basic@force-load-detect:
> - shard-rkl: [SKIP][335] ([fdo#109285]) -> [SKIP][336] ([fdo#109285] / [i915#4098])
> [335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_force_connector_basic@force-load-detect.html
> [336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_force_connector_basic@force-load-detect.html
>
> * igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt:
> - shard-rkl: [SKIP][337] ([i915#1849] / [i915#4098]) -> [SKIP][338] ([fdo#111825])
> [337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt.html
> [338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt.html
>
> * igt@kms_frontbuffer_tracking@fbc-tiling-4:
> - shard-rkl: [SKIP][339] ([i915#1849] / [i915#4098]) -> [SKIP][340] ([i915#5439])
> [339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
> [340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt:
> - shard-rkl: [SKIP][341] ([i915#1849] / [i915#4098]) -> [SKIP][342] ([i915#3023]) +33 other tests skip
> [341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html
> [342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt:
> - shard-rkl: [SKIP][343] ([i915#3023]) -> [SKIP][344] ([i915#1849] / [i915#4098]) +29 other tests skip
> [343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
> [344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
>
> * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc:
> - shard-rkl: [SKIP][345] ([fdo#111825] / [i915#1825]) -> [SKIP][346] ([i915#1849] / [i915#4098]) +37 other tests skip
> [345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html
> [346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html
>
> * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
> - shard-rkl: [SKIP][347] ([i915#1849] / [i915#4098]) -> [SKIP][348] ([fdo#111825] / [i915#1825]) +52 other tests skip
> [347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html
> [348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html
>
> * igt@kms_hdr@invalid-hdr:
> - shard-rkl: [SKIP][349] ([i915#3555] / [i915#8228]) -> [SKIP][350] ([i915#4098])
> [349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_hdr@invalid-hdr.html
> [350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_hdr@invalid-hdr.html
>
> * igt@kms_hdr@static-swap:
> - shard-rkl: [SKIP][351] ([i915#1845] / [i915#4098]) -> [SKIP][352] ([i915#3555] / [i915#8228]) +1 other test skip
> [351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_hdr@static-swap.html
> [352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_hdr@static-swap.html
>
> * igt@kms_panel_fitting@atomic-fastset:
> - shard-rkl: [SKIP][353] ([i915#1845] / [i915#4098]) -> [SKIP][354] ([i915#6301]) +1 other test skip
> [353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_panel_fitting@atomic-fastset.html
> [354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-4/igt@kms_panel_fitting@atomic-fastset.html
>
> * igt@kms_plane_multiple@tiling-yf:
> - shard-rkl: [SKIP][355] ([i915#4098]) -> [SKIP][356] ([i915#3555]) +7 other tests skip
> [355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_plane_multiple@tiling-yf.html
> [356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-6/igt@kms_plane_multiple@tiling-yf.html
>
> * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
> - shard-rkl: [SKIP][357] ([i915#1845] / [i915#4098]) -> [SKIP][358] ([fdo#111615] / [i915#5289])
> [357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
> [358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
>
> * igt@kms_vrr@flip-dpms:
> - shard-rkl: [SKIP][359] ([i915#3555]) -> [SKIP][360] ([i915#1845] / [i915#4098]) +1 other test skip
> [359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13844/shard-rkl-7/igt@kms_vrr@flip-dpms.html
> [360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/shard-rkl-5/igt@kms_vrr@flip-dpms.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [Intel XE#874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/874
> [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
> [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
> [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
> [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
> [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
> [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
> [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
> [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
> [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
> [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
> [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
> [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
> [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
> [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
> [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
> [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
> [fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
> [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
> [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
> [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
> [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
> [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
> [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
> [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
> [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
> [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
> [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
> [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
> [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
> [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
> [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
> [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
> [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
> [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
> [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
> [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
> [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
> [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
> [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
> [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
> [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
> [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
> [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
> [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
> [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
> [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
> [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
> [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
> [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
> [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
> [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
> [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
> [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
> [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
> [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
> [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
> [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
> [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
> [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
> [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
> [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
> [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
> [i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
> [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
> [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
> [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
> [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
> [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
> [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
> [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
> [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
> [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
> [i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
> [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
> [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
> [i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
> [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
> [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
> [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
> [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
> [i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
> [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
> [i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
> [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
> [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
> [i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
> [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
> [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
> [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
> [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
> [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
> [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
> [i915#5460]: https://gitlab.freedesktop.org/drm/intel/issues/5460
> [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
> [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
> [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
> [i915#5793]: https://gitlab.freedesktop.org/drm/intel/issues/5793
> [i915#5882]: https://gitlab.freedesktop.org/drm/intel/issues/5882
> [i915#5889]: https://gitlab.freedesktop.org/drm/intel/issues/5889
> [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
> [i915#6118]: https://gitlab.freedesktop.org/drm/intel/issues/6118
> [i915#6122]: https://gitlab.freedesktop.org/drm/intel/issues/6122
> [i915#6228]: https://gitlab.freedesktop.org/drm/intel/issues/6228
> [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
> [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
> [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
> [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
> [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
> [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> [i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
> [i915#6806]: https://gitlab.freedesktop.org/drm/intel/issues/6806
> [i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
> [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
> [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
> [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
> [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
> [i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
> [i915#7276]: https://gitlab.freedesktop.org/drm/intel/issues/7276
> [i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
> [i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484
> [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
> [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
> [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
> [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
> [i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790
> [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
> [i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
> [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
> [i915#7984]: https://gitlab.freedesktop.org/drm/intel/issues/7984
> [i915#8152]: https://gitlab.freedesktop.org/drm/intel/issues/8152
> [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
> [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
> [i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
> [i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
> [i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
> [i915#8399]: https://gitlab.freedesktop.org/drm/intel/issues/8399
> [i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
> [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
> [i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
> [i915#8430]: https://gitlab.freedesktop.org/drm/intel/issues/8430
> [i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516
> [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
> [i915#8562]: https://gitlab.freedesktop.org/drm/intel/issues/8562
> [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
> [i915#8724]: https://gitlab.freedesktop.org/drm/intel/issues/8724
> [i915#8808]: https://gitlab.freedesktop.org/drm/intel/issues/8808
> [i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
> [i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
> [i915#8812]: https://gitlab.freedesktop.org/drm/intel/issues/8812
> [i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
> [i915#8825]: https://gitlab.freedesktop.org/drm/intel/issues/8825
> [i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
> [i915#8850]: https://gitlab.freedesktop.org/drm/intel/issues/8850
> [i915#8875]: https://gitlab.freedesktop.org/drm/intel/issues/8875
> [i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
> [i915#9010]: https://gitlab.freedesktop.org/drm/intel/issues/9010
> [i915#9053]: https://gitlab.freedesktop.org/drm/intel/issues/9053
> [i915#9067]: https://gitlab.freedesktop.org/drm/intel/issues/9067
> [i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
> [i915#9293]: https://gitlab.freedesktop.org/drm/intel/issues/9293
> [i915#9310]: https://gitlab.freedesktop.org/drm/intel/issues/9310
> [i915#9311]: https://gitlab.freedesktop.org/drm/intel/issues/9311
> [i915#9323]: https://gitlab.freedesktop.org/drm/intel/issues/9323
> [i915#9414]: https://gitlab.freedesktop.org/drm/intel/issues/9414
> [i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423
> [i915#9424]: https://gitlab.freedesktop.org/drm/intel/issues/9424
> [i915#9519]: https://gitlab.freedesktop.org/drm/intel/issues/9519
> [i915#9569]: https://gitlab.freedesktop.org/drm/intel/issues/9569
> [i915#9583]: https://gitlab.freedesktop.org/drm/intel/issues/9583
> [i915#9588]: https://gitlab.freedesktop.org/drm/intel/issues/9588
> [i915#9591]: https://gitlab.freedesktop.org/drm/intel/issues/9591
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_13844 -> Patchwork_125490v16
>
> CI-20190529: 20190529
> CI_DRM_13844: 98a039fc048898d9ecec16153267968fd18a5a52 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_7574: 0485a4bf66f69aaf7244a3e689402b522f636780 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_125490v16: 98a039fc048898d9ecec16153267968fd18a5a52 @ git://anongit.freedesktop.org/gfx-ci/linux
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125490v16/index.html
^ permalink raw reply [flat|nested] 94+ messages in thread