From: Jani Nikula <jani.nikula@linux.intel.com>
To: Anusha Srivatsa <anusha.srivatsa@intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 2/5] drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines
Date: Mon, 05 Jun 2023 18:16:57 +0300 [thread overview]
Message-ID: <87legyaqhi.fsf@intel.com> (raw)
In-Reply-To: <20230530185529.3378520-3-anusha.srivatsa@intel.com>
On Tue, 30 May 2023, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
> Follow consistent naming convention. Replace ADLP with
> ALDERLAKE_P.
Here too the consistent naming convention for all macros using
IS_SUBPLATFORM() is to use the acronym. The IS_METEORLAKE_M() and
IS_METEORLAKE_P() macros are the outliers.
Again, do you suggest we rename all of them, or just ADL-P? The former
is a lot of churn, and the latter is not consistent.
BR,
Jani.
>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_step.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1a50b8b2f00d..43414cdc137c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -581,7 +581,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
> #define IS_ADLP_N(i915) \
> IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
> -#define IS_ADLP_RPLP(i915) \
> +#define IS_ALDERLAKE_P_RPLP(i915) \
> IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
> #define IS_ADLP_RPLU(i915) \
> IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
> diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
> index 8a9ff6227e53..10d86c525beb 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -195,7 +195,7 @@ void intel_step_init(struct drm_i915_private *i915)
> } else if (IS_ADLP_N(i915)) {
> revids = adlp_n_revids;
> size = ARRAY_SIZE(adlp_n_revids);
> - } else if (IS_ADLP_RPLP(i915)) {
> + } else if (IS_ALDERLAKE_P_RPLP(i915)) {
> revids = adlp_rplp_revids;
> size = ARRAY_SIZE(adlp_rplp_revids);
> } else if (IS_ALDERLAKE_P(i915)) {
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2023-06-05 15:17 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-30 18:55 [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE Anusha Srivatsa
2023-05-30 18:55 ` [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step Anusha Srivatsa
2023-06-05 15:13 ` Jani Nikula
2023-06-05 18:20 ` Srivatsa, Anusha
2023-06-05 18:29 ` Jani Nikula
2023-06-05 20:40 ` Srivatsa, Anusha
2023-05-30 18:55 ` [Intel-gfx] [PATCH 2/5] drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines Anusha Srivatsa
2023-06-05 15:16 ` Jani Nikula [this message]
2023-05-30 18:55 ` [Intel-gfx] [PATCH 3/5] drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines Anusha Srivatsa
2023-05-30 18:55 ` [Intel-gfx] [PATCH 4/5] drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines Anusha Srivatsa
2023-05-30 18:55 ` [Intel-gfx] [PATCH 5/5] drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines Anusha Srivatsa
2023-05-31 16:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for s/ADL/ALDERLAKE Patchwork
2023-05-31 16:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-05-31 16:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-06-02 4:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-06-05 15:19 ` [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE Jani Nikula
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