* [Intel-gfx] [CI 0/3] drm/i915 / LPSS / mfd: Select correct PWM controller to use based on VBT
@ 2019-12-16 20:29 ` Hans de Goede
0 siblings, 0 replies; 21+ messages in thread
From: Hans de Goede @ 2019-12-16 20:29 UTC (permalink / raw)
To: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä, intel-gfx, Rafael J . Wysocki, Lee Jones
Cc: linux-kernel, dri-devel, linux-acpi
Hi All,
Somehow the CI system did not pick up this series the first time, there
are no test results recorded for it:
https://patchwork.freedesktop.org/series/69685
So this is a resend for CI to do its thing. As soon as CI is happy with
this I will push this to drm-intel-next-queued.
Regards,
Hans
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
* [CI 0/3] drm/i915 / LPSS / mfd: Select correct PWM controller to use based on VBT
@ 2019-12-16 20:29 ` Hans de Goede
0 siblings, 0 replies; 21+ messages in thread
From: Hans de Goede @ 2019-12-16 20:29 UTC (permalink / raw)
To: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä, intel-gfx, Rafael J . Wysocki, Lee Jones
Cc: Hans de Goede, linux-kernel, dri-devel, linux-acpi
Hi All,
Somehow the CI system did not pick up this series the first time, there
are no test results recorded for it:
https://patchwork.freedesktop.org/series/69685
So this is a resend for CI to do its thing. As soon as CI is happy with
this I will push this to drm-intel-next-queued.
Regards,
Hans
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 21+ messages in thread
* [CI 1/3] ACPI / LPSS: Rename pwm_backlight pwm-lookup to pwm_soc_backlight
2019-12-16 20:29 ` Hans de Goede
(?)
@ 2019-12-16 20:29 ` Hans de Goede
-1 siblings, 0 replies; 21+ messages in thread
From: Hans de Goede @ 2019-12-16 20:29 UTC (permalink / raw)
To: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä, intel-gfx, Rafael J . Wysocki, Lee Jones
Cc: Hans de Goede, dri-devel, linux-acpi, linux-kernel, Jani Nikula,
Andy Shevchenko, Rafael J . Wysocki
At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
different PWM controllers for controlling the LCD's backlight brightness.
Either the one integrated into the PMIC or the one integrated into the
SoC (the 1st LPSS PWM controller).
So far in the LPSS code on BYT we have skipped registering the LPSS PWM
controller "pwm_backlight" lookup entry when a Crystal Cove PMIC is
present, assuming that in this case the PMIC PWM controller will be used.
On CHT we have been relying on only 1 of the 2 PWM controllers being
enabled in the DSDT at the same time; and always registered the lookup.
So far this has been working, but the correct way to determine which PWM
controller needs to be used is by checking a bit in the VBT table and
recently I've learned about 2 different BYT devices:
Point of View MOBII TAB-P800W
Acer Switch 10 SW5-012
Which use a Crystal Cove PMIC, yet the LCD is connected to the SoC/LPSS
PWM controller (and the VBT correctly indicates this), so here our old
heuristics fail.
Since only the i915 driver has access to the VBT, this commit renames
the "pwm_backlight" lookup entries for the 1st BYT/CHT LPSS PWM controller
to "pwm_soc_backlight" so that the i915 driver can do a pwm_get() for
the right controller depending on the VBT bit, instead of the i915 driver
relying on a "pwm_backlight" lookup getting registered which magically
points to the right controller.
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/acpi/acpi_lpss.c | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c
index 70f740b09684..db18df6cb330 100644
--- a/drivers/acpi/acpi_lpss.c
+++ b/drivers/acpi/acpi_lpss.c
@@ -69,10 +69,6 @@ ACPI_MODULE_NAME("acpi_lpss");
#define LPSS_SAVE_CTX BIT(4)
#define LPSS_NO_D3_DELAY BIT(5)
-/* Crystal Cove PMIC shares same ACPI ID between different platforms */
-#define BYT_CRC_HRV 2
-#define CHT_CRC_HRV 3
-
struct lpss_private_data;
struct lpss_device_desc {
@@ -158,7 +154,7 @@ static void lpss_deassert_reset(struct lpss_private_data *pdata)
*/
static struct pwm_lookup byt_pwm_lookup[] = {
PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0",
- "pwm_backlight", 0, PWM_POLARITY_NORMAL,
+ "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
"pwm-lpss-platform"),
};
@@ -170,8 +166,7 @@ static void byt_pwm_setup(struct lpss_private_data *pdata)
if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
return;
- if (!acpi_dev_present("INT33FD", NULL, BYT_CRC_HRV))
- pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
+ pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
}
#define LPSS_I2C_ENABLE 0x6c
@@ -204,7 +199,7 @@ static void byt_i2c_setup(struct lpss_private_data *pdata)
/* BSW PWM used for backlight control by the i915 driver */
static struct pwm_lookup bsw_pwm_lookup[] = {
PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
- "pwm_backlight", 0, PWM_POLARITY_NORMAL,
+ "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
"pwm-lpss-platform"),
};
--
2.23.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Intel-gfx] [CI 1/3] ACPI / LPSS: Rename pwm_backlight pwm-lookup to pwm_soc_backlight
@ 2019-12-16 20:29 ` Hans de Goede
0 siblings, 0 replies; 21+ messages in thread
From: Hans de Goede @ 2019-12-16 20:29 UTC (permalink / raw)
To: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä, intel-gfx, Rafael J . Wysocki, Lee Jones
Cc: linux-acpi, Jani Nikula, Rafael J . Wysocki, linux-kernel,
dri-devel, Andy Shevchenko
At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
different PWM controllers for controlling the LCD's backlight brightness.
Either the one integrated into the PMIC or the one integrated into the
SoC (the 1st LPSS PWM controller).
So far in the LPSS code on BYT we have skipped registering the LPSS PWM
controller "pwm_backlight" lookup entry when a Crystal Cove PMIC is
present, assuming that in this case the PMIC PWM controller will be used.
On CHT we have been relying on only 1 of the 2 PWM controllers being
enabled in the DSDT at the same time; and always registered the lookup.
So far this has been working, but the correct way to determine which PWM
controller needs to be used is by checking a bit in the VBT table and
recently I've learned about 2 different BYT devices:
Point of View MOBII TAB-P800W
Acer Switch 10 SW5-012
Which use a Crystal Cove PMIC, yet the LCD is connected to the SoC/LPSS
PWM controller (and the VBT correctly indicates this), so here our old
heuristics fail.
Since only the i915 driver has access to the VBT, this commit renames
the "pwm_backlight" lookup entries for the 1st BYT/CHT LPSS PWM controller
to "pwm_soc_backlight" so that the i915 driver can do a pwm_get() for
the right controller depending on the VBT bit, instead of the i915 driver
relying on a "pwm_backlight" lookup getting registered which magically
points to the right controller.
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/acpi/acpi_lpss.c | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c
index 70f740b09684..db18df6cb330 100644
--- a/drivers/acpi/acpi_lpss.c
+++ b/drivers/acpi/acpi_lpss.c
@@ -69,10 +69,6 @@ ACPI_MODULE_NAME("acpi_lpss");
#define LPSS_SAVE_CTX BIT(4)
#define LPSS_NO_D3_DELAY BIT(5)
-/* Crystal Cove PMIC shares same ACPI ID between different platforms */
-#define BYT_CRC_HRV 2
-#define CHT_CRC_HRV 3
-
struct lpss_private_data;
struct lpss_device_desc {
@@ -158,7 +154,7 @@ static void lpss_deassert_reset(struct lpss_private_data *pdata)
*/
static struct pwm_lookup byt_pwm_lookup[] = {
PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0",
- "pwm_backlight", 0, PWM_POLARITY_NORMAL,
+ "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
"pwm-lpss-platform"),
};
@@ -170,8 +166,7 @@ static void byt_pwm_setup(struct lpss_private_data *pdata)
if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
return;
- if (!acpi_dev_present("INT33FD", NULL, BYT_CRC_HRV))
- pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
+ pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
}
#define LPSS_I2C_ENABLE 0x6c
@@ -204,7 +199,7 @@ static void byt_i2c_setup(struct lpss_private_data *pdata)
/* BSW PWM used for backlight control by the i915 driver */
static struct pwm_lookup bsw_pwm_lookup[] = {
PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
- "pwm_backlight", 0, PWM_POLARITY_NORMAL,
+ "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
"pwm-lpss-platform"),
};
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread* [CI 1/3] ACPI / LPSS: Rename pwm_backlight pwm-lookup to pwm_soc_backlight
@ 2019-12-16 20:29 ` Hans de Goede
0 siblings, 0 replies; 21+ messages in thread
From: Hans de Goede @ 2019-12-16 20:29 UTC (permalink / raw)
To: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä, intel-gfx, Rafael J . Wysocki, Lee Jones
Cc: linux-acpi, Jani Nikula, Rafael J . Wysocki, linux-kernel,
dri-devel, Hans de Goede, Andy Shevchenko
At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
different PWM controllers for controlling the LCD's backlight brightness.
Either the one integrated into the PMIC or the one integrated into the
SoC (the 1st LPSS PWM controller).
So far in the LPSS code on BYT we have skipped registering the LPSS PWM
controller "pwm_backlight" lookup entry when a Crystal Cove PMIC is
present, assuming that in this case the PMIC PWM controller will be used.
On CHT we have been relying on only 1 of the 2 PWM controllers being
enabled in the DSDT at the same time; and always registered the lookup.
So far this has been working, but the correct way to determine which PWM
controller needs to be used is by checking a bit in the VBT table and
recently I've learned about 2 different BYT devices:
Point of View MOBII TAB-P800W
Acer Switch 10 SW5-012
Which use a Crystal Cove PMIC, yet the LCD is connected to the SoC/LPSS
PWM controller (and the VBT correctly indicates this), so here our old
heuristics fail.
Since only the i915 driver has access to the VBT, this commit renames
the "pwm_backlight" lookup entries for the 1st BYT/CHT LPSS PWM controller
to "pwm_soc_backlight" so that the i915 driver can do a pwm_get() for
the right controller depending on the VBT bit, instead of the i915 driver
relying on a "pwm_backlight" lookup getting registered which magically
points to the right controller.
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/acpi/acpi_lpss.c | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c
index 70f740b09684..db18df6cb330 100644
--- a/drivers/acpi/acpi_lpss.c
+++ b/drivers/acpi/acpi_lpss.c
@@ -69,10 +69,6 @@ ACPI_MODULE_NAME("acpi_lpss");
#define LPSS_SAVE_CTX BIT(4)
#define LPSS_NO_D3_DELAY BIT(5)
-/* Crystal Cove PMIC shares same ACPI ID between different platforms */
-#define BYT_CRC_HRV 2
-#define CHT_CRC_HRV 3
-
struct lpss_private_data;
struct lpss_device_desc {
@@ -158,7 +154,7 @@ static void lpss_deassert_reset(struct lpss_private_data *pdata)
*/
static struct pwm_lookup byt_pwm_lookup[] = {
PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0",
- "pwm_backlight", 0, PWM_POLARITY_NORMAL,
+ "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
"pwm-lpss-platform"),
};
@@ -170,8 +166,7 @@ static void byt_pwm_setup(struct lpss_private_data *pdata)
if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
return;
- if (!acpi_dev_present("INT33FD", NULL, BYT_CRC_HRV))
- pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
+ pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
}
#define LPSS_I2C_ENABLE 0x6c
@@ -204,7 +199,7 @@ static void byt_i2c_setup(struct lpss_private_data *pdata)
/* BSW PWM used for backlight control by the i915 driver */
static struct pwm_lookup bsw_pwm_lookup[] = {
PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
- "pwm_backlight", 0, PWM_POLARITY_NORMAL,
+ "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
"pwm-lpss-platform"),
};
--
2.23.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [CI 2/3] mfd: intel_soc_pmic: Rename pwm_backlight pwm-lookup to pwm_pmic_backlight
2019-12-16 20:29 ` Hans de Goede
(?)
@ 2019-12-16 20:29 ` Hans de Goede
-1 siblings, 0 replies; 21+ messages in thread
From: Hans de Goede @ 2019-12-16 20:29 UTC (permalink / raw)
To: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä, intel-gfx, Rafael J . Wysocki, Lee Jones
Cc: Hans de Goede, dri-devel, linux-acpi, linux-kernel, Jani Nikula,
Andy Shevchenko
At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
different PWM controllers for controlling the LCD's backlight brightness.
Either the one integrated into the PMIC or the one integrated into the
SoC (the 1st LPSS PWM controller).
So far in the LPSS code on BYT we have skipped registering the LPSS PWM
controller "pwm_backlight" lookup entry when a Crystal Cove PMIC is
present, assuming that in this case the PMIC PWM controller will be used.
On CHT we have been relying on only 1 of the 2 PWM controllers being
enabled in the DSDT at the same time; and always registered the lookup.
So far this has been working, but the correct way to determine which PWM
controller needs to be used is by checking a bit in the VBT table and
recently I've learned about 2 different BYT devices:
Point of View MOBII TAB-P800W
Acer Switch 10 SW5-012
Which use a Crystal Cove PMIC, yet the LCD is connected to the SoC/LPSS
PWM controller (and the VBT correctly indicates this), so here our old
heuristics fail.
Since only the i915 driver has access to the VBT, this commit renames
the "pwm_backlight" lookup entries for the Crystal Cove PMIC's PWM
controller to "pwm_pmic_backlight" so that the i915 driver can do a
pwm_get() for the right controller depending on the VBT bit, instead of
the i915 driver relying on a "pwm_backlight" lookup getting registered
which magically points to the right controller.
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/mfd/intel_soc_pmic_core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mfd/intel_soc_pmic_core.c b/drivers/mfd/intel_soc_pmic_core.c
index c9f35378d391..47188df3080d 100644
--- a/drivers/mfd/intel_soc_pmic_core.c
+++ b/drivers/mfd/intel_soc_pmic_core.c
@@ -38,7 +38,7 @@ static struct gpiod_lookup_table panel_gpio_table = {
/* PWM consumed by the Intel GFX */
static struct pwm_lookup crc_pwm_lookup[] = {
- PWM_LOOKUP("crystal_cove_pwm", 0, "0000:00:02.0", "pwm_backlight", 0, PWM_POLARITY_NORMAL),
+ PWM_LOOKUP("crystal_cove_pwm", 0, "0000:00:02.0", "pwm_pmic_backlight", 0, PWM_POLARITY_NORMAL),
};
static int intel_soc_pmic_i2c_probe(struct i2c_client *i2c,
--
2.23.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Intel-gfx] [CI 2/3] mfd: intel_soc_pmic: Rename pwm_backlight pwm-lookup to pwm_pmic_backlight
@ 2019-12-16 20:29 ` Hans de Goede
0 siblings, 0 replies; 21+ messages in thread
From: Hans de Goede @ 2019-12-16 20:29 UTC (permalink / raw)
To: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä, intel-gfx, Rafael J . Wysocki, Lee Jones
Cc: linux-acpi, Jani Nikula, linux-kernel, dri-devel, Andy Shevchenko
At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
different PWM controllers for controlling the LCD's backlight brightness.
Either the one integrated into the PMIC or the one integrated into the
SoC (the 1st LPSS PWM controller).
So far in the LPSS code on BYT we have skipped registering the LPSS PWM
controller "pwm_backlight" lookup entry when a Crystal Cove PMIC is
present, assuming that in this case the PMIC PWM controller will be used.
On CHT we have been relying on only 1 of the 2 PWM controllers being
enabled in the DSDT at the same time; and always registered the lookup.
So far this has been working, but the correct way to determine which PWM
controller needs to be used is by checking a bit in the VBT table and
recently I've learned about 2 different BYT devices:
Point of View MOBII TAB-P800W
Acer Switch 10 SW5-012
Which use a Crystal Cove PMIC, yet the LCD is connected to the SoC/LPSS
PWM controller (and the VBT correctly indicates this), so here our old
heuristics fail.
Since only the i915 driver has access to the VBT, this commit renames
the "pwm_backlight" lookup entries for the Crystal Cove PMIC's PWM
controller to "pwm_pmic_backlight" so that the i915 driver can do a
pwm_get() for the right controller depending on the VBT bit, instead of
the i915 driver relying on a "pwm_backlight" lookup getting registered
which magically points to the right controller.
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/mfd/intel_soc_pmic_core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mfd/intel_soc_pmic_core.c b/drivers/mfd/intel_soc_pmic_core.c
index c9f35378d391..47188df3080d 100644
--- a/drivers/mfd/intel_soc_pmic_core.c
+++ b/drivers/mfd/intel_soc_pmic_core.c
@@ -38,7 +38,7 @@ static struct gpiod_lookup_table panel_gpio_table = {
/* PWM consumed by the Intel GFX */
static struct pwm_lookup crc_pwm_lookup[] = {
- PWM_LOOKUP("crystal_cove_pwm", 0, "0000:00:02.0", "pwm_backlight", 0, PWM_POLARITY_NORMAL),
+ PWM_LOOKUP("crystal_cove_pwm", 0, "0000:00:02.0", "pwm_pmic_backlight", 0, PWM_POLARITY_NORMAL),
};
static int intel_soc_pmic_i2c_probe(struct i2c_client *i2c,
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread* [CI 2/3] mfd: intel_soc_pmic: Rename pwm_backlight pwm-lookup to pwm_pmic_backlight
@ 2019-12-16 20:29 ` Hans de Goede
0 siblings, 0 replies; 21+ messages in thread
From: Hans de Goede @ 2019-12-16 20:29 UTC (permalink / raw)
To: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä, intel-gfx, Rafael J . Wysocki, Lee Jones
Cc: linux-acpi, Jani Nikula, linux-kernel, dri-devel, Hans de Goede,
Andy Shevchenko
At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
different PWM controllers for controlling the LCD's backlight brightness.
Either the one integrated into the PMIC or the one integrated into the
SoC (the 1st LPSS PWM controller).
So far in the LPSS code on BYT we have skipped registering the LPSS PWM
controller "pwm_backlight" lookup entry when a Crystal Cove PMIC is
present, assuming that in this case the PMIC PWM controller will be used.
On CHT we have been relying on only 1 of the 2 PWM controllers being
enabled in the DSDT at the same time; and always registered the lookup.
So far this has been working, but the correct way to determine which PWM
controller needs to be used is by checking a bit in the VBT table and
recently I've learned about 2 different BYT devices:
Point of View MOBII TAB-P800W
Acer Switch 10 SW5-012
Which use a Crystal Cove PMIC, yet the LCD is connected to the SoC/LPSS
PWM controller (and the VBT correctly indicates this), so here our old
heuristics fail.
Since only the i915 driver has access to the VBT, this commit renames
the "pwm_backlight" lookup entries for the Crystal Cove PMIC's PWM
controller to "pwm_pmic_backlight" so that the i915 driver can do a
pwm_get() for the right controller depending on the VBT bit, instead of
the i915 driver relying on a "pwm_backlight" lookup getting registered
which magically points to the right controller.
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/mfd/intel_soc_pmic_core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mfd/intel_soc_pmic_core.c b/drivers/mfd/intel_soc_pmic_core.c
index c9f35378d391..47188df3080d 100644
--- a/drivers/mfd/intel_soc_pmic_core.c
+++ b/drivers/mfd/intel_soc_pmic_core.c
@@ -38,7 +38,7 @@ static struct gpiod_lookup_table panel_gpio_table = {
/* PWM consumed by the Intel GFX */
static struct pwm_lookup crc_pwm_lookup[] = {
- PWM_LOOKUP("crystal_cove_pwm", 0, "0000:00:02.0", "pwm_backlight", 0, PWM_POLARITY_NORMAL),
+ PWM_LOOKUP("crystal_cove_pwm", 0, "0000:00:02.0", "pwm_pmic_backlight", 0, PWM_POLARITY_NORMAL),
};
static int intel_soc_pmic_i2c_probe(struct i2c_client *i2c,
--
2.23.0
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [CI 2/3] mfd: intel_soc_pmic: Rename pwm_backlight pwm-lookup to pwm_pmic_backlight
2019-12-16 20:29 ` Hans de Goede
(?)
@ 2019-12-17 8:04 ` Lee Jones
-1 siblings, 0 replies; 21+ messages in thread
From: Lee Jones @ 2019-12-17 8:04 UTC (permalink / raw)
To: Hans de Goede
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä, intel-gfx, Rafael J . Wysocki, dri-devel,
linux-acpi, linux-kernel, Jani Nikula, Andy Shevchenko
On Mon, 16 Dec 2019, Hans de Goede wrote:
> At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
> different PWM controllers for controlling the LCD's backlight brightness.
>
> Either the one integrated into the PMIC or the one integrated into the
> SoC (the 1st LPSS PWM controller).
>
> So far in the LPSS code on BYT we have skipped registering the LPSS PWM
> controller "pwm_backlight" lookup entry when a Crystal Cove PMIC is
> present, assuming that in this case the PMIC PWM controller will be used.
>
> On CHT we have been relying on only 1 of the 2 PWM controllers being
> enabled in the DSDT at the same time; and always registered the lookup.
>
> So far this has been working, but the correct way to determine which PWM
> controller needs to be used is by checking a bit in the VBT table and
> recently I've learned about 2 different BYT devices:
> Point of View MOBII TAB-P800W
> Acer Switch 10 SW5-012
>
> Which use a Crystal Cove PMIC, yet the LCD is connected to the SoC/LPSS
> PWM controller (and the VBT correctly indicates this), so here our old
> heuristics fail.
>
> Since only the i915 driver has access to the VBT, this commit renames
> the "pwm_backlight" lookup entries for the Crystal Cove PMIC's PWM
> controller to "pwm_pmic_backlight" so that the i915 driver can do a
> pwm_get() for the right controller depending on the VBT bit, instead of
> the i915 driver relying on a "pwm_backlight" lookup getting registered
> which magically points to the right controller.
>
> Acked-by: Jani Nikula <jani.nikula@intel.com>
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> drivers/mfd/intel_soc_pmic_core.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Lee Jones <lee.jones@linaro.org>
--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [CI 2/3] mfd: intel_soc_pmic: Rename pwm_backlight pwm-lookup to pwm_pmic_backlight
@ 2019-12-17 8:04 ` Lee Jones
0 siblings, 0 replies; 21+ messages in thread
From: Lee Jones @ 2019-12-17 8:04 UTC (permalink / raw)
To: Hans de Goede
Cc: Jani Nikula, intel-gfx, Rafael J . Wysocki, linux-kernel,
linux-acpi, dri-devel, Andy Shevchenko
On Mon, 16 Dec 2019, Hans de Goede wrote:
> At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
> different PWM controllers for controlling the LCD's backlight brightness.
>
> Either the one integrated into the PMIC or the one integrated into the
> SoC (the 1st LPSS PWM controller).
>
> So far in the LPSS code on BYT we have skipped registering the LPSS PWM
> controller "pwm_backlight" lookup entry when a Crystal Cove PMIC is
> present, assuming that in this case the PMIC PWM controller will be used.
>
> On CHT we have been relying on only 1 of the 2 PWM controllers being
> enabled in the DSDT at the same time; and always registered the lookup.
>
> So far this has been working, but the correct way to determine which PWM
> controller needs to be used is by checking a bit in the VBT table and
> recently I've learned about 2 different BYT devices:
> Point of View MOBII TAB-P800W
> Acer Switch 10 SW5-012
>
> Which use a Crystal Cove PMIC, yet the LCD is connected to the SoC/LPSS
> PWM controller (and the VBT correctly indicates this), so here our old
> heuristics fail.
>
> Since only the i915 driver has access to the VBT, this commit renames
> the "pwm_backlight" lookup entries for the Crystal Cove PMIC's PWM
> controller to "pwm_pmic_backlight" so that the i915 driver can do a
> pwm_get() for the right controller depending on the VBT bit, instead of
> the i915 driver relying on a "pwm_backlight" lookup getting registered
> which magically points to the right controller.
>
> Acked-by: Jani Nikula <jani.nikula@intel.com>
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> drivers/mfd/intel_soc_pmic_core.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Lee Jones <lee.jones@linaro.org>
--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [CI 2/3] mfd: intel_soc_pmic: Rename pwm_backlight pwm-lookup to pwm_pmic_backlight
@ 2019-12-17 8:04 ` Lee Jones
0 siblings, 0 replies; 21+ messages in thread
From: Lee Jones @ 2019-12-17 8:04 UTC (permalink / raw)
To: Hans de Goede
Cc: Jani Nikula, intel-gfx, Rafael J . Wysocki, linux-kernel,
linux-acpi, dri-devel, Rodrigo Vivi, Andy Shevchenko
On Mon, 16 Dec 2019, Hans de Goede wrote:
> At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
> different PWM controllers for controlling the LCD's backlight brightness.
>
> Either the one integrated into the PMIC or the one integrated into the
> SoC (the 1st LPSS PWM controller).
>
> So far in the LPSS code on BYT we have skipped registering the LPSS PWM
> controller "pwm_backlight" lookup entry when a Crystal Cove PMIC is
> present, assuming that in this case the PMIC PWM controller will be used.
>
> On CHT we have been relying on only 1 of the 2 PWM controllers being
> enabled in the DSDT at the same time; and always registered the lookup.
>
> So far this has been working, but the correct way to determine which PWM
> controller needs to be used is by checking a bit in the VBT table and
> recently I've learned about 2 different BYT devices:
> Point of View MOBII TAB-P800W
> Acer Switch 10 SW5-012
>
> Which use a Crystal Cove PMIC, yet the LCD is connected to the SoC/LPSS
> PWM controller (and the VBT correctly indicates this), so here our old
> heuristics fail.
>
> Since only the i915 driver has access to the VBT, this commit renames
> the "pwm_backlight" lookup entries for the Crystal Cove PMIC's PWM
> controller to "pwm_pmic_backlight" so that the i915 driver can do a
> pwm_get() for the right controller depending on the VBT bit, instead of
> the i915 driver relying on a "pwm_backlight" lookup getting registered
> which magically points to the right controller.
>
> Acked-by: Jani Nikula <jani.nikula@intel.com>
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> drivers/mfd/intel_soc_pmic_core.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Lee Jones <lee.jones@linaro.org>
--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 21+ messages in thread
* [CI 3/3] drm/i915: DSI: select correct PWM controller to use based on the VBT
2019-12-16 20:29 ` Hans de Goede
(?)
@ 2019-12-16 20:29 ` Hans de Goede
-1 siblings, 0 replies; 21+ messages in thread
From: Hans de Goede @ 2019-12-16 20:29 UTC (permalink / raw)
To: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä, intel-gfx, Rafael J . Wysocki, Lee Jones
Cc: Hans de Goede, dri-devel, linux-acpi, linux-kernel, Jani Nikula,
Andy Shevchenko
At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
different PWM controllers for controlling the LCD's backlight brightness.
Either the one integrated into the PMIC or the one integrated into the
SoC (the 1st LPSS PWM controller).
So far in the LPSS code on BYT we have skipped registering the LPSS PWM
controller "pwm_backlight" lookup entry when a Crystal Cove PMIC is
present, assuming that in this case the PMIC PWM controller will be used.
On CHT we have been relying on only 1 of the 2 PWM controllers being
enabled in the DSDT at the same time; and always registered the lookup.
So far this has been working, but the correct way to determine which PWM
controller needs to be used is by checking a bit in the VBT table and
recently I've learned about 2 different BYT devices:
Point of View MOBII TAB-P800W
Acer Switch 10 SW5-012
Which use a Crystal Cove PMIC, yet the LCD is connected to the SoC/LPSS
PWM controller (and the VBT correctly indicates this), so here our old
heuristics fail.
This commit fixes using the wrong PWM controller on these devices by
calling pwm_get() for the right PWM controller based on the
VBT dsi.config.pwm_blc bit.
Note this is part of a series which contains 2 other patches which renames
the PWM lookup for the 1st SoC/LPSS PWM from "pwm_backlight" to
"pwm_pmic_backlight" and the PWM lookup for the Crystal Cove PMIC PWM
from "pwm_backlight" to "pwm_pmic_backlight".
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/gpu/drm/i915/display/intel_panel.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index bc14e9c0285a..ddcf311d1114 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -1840,13 +1840,22 @@ static int pwm_setup_backlight(struct intel_connector *connector,
enum pipe pipe)
{
struct drm_device *dev = connector->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_panel *panel = &connector->panel;
+ const char *desc;
int retval;
- /* Get the PWM chip for backlight control */
- panel->backlight.pwm = pwm_get(dev->dev, "pwm_backlight");
+ /* Get the right PWM chip for DSI backlight according to VBT */
+ if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {
+ panel->backlight.pwm = pwm_get(dev->dev, "pwm_pmic_backlight");
+ desc = "PMIC";
+ } else {
+ panel->backlight.pwm = pwm_get(dev->dev, "pwm_soc_backlight");
+ desc = "SoC";
+ }
+
if (IS_ERR(panel->backlight.pwm)) {
- DRM_ERROR("Failed to own the pwm chip\n");
+ DRM_ERROR("Failed to get the %s PWM chip\n", desc);
panel->backlight.pwm = NULL;
return -ENODEV;
}
@@ -1873,6 +1882,7 @@ static int pwm_setup_backlight(struct intel_connector *connector,
CRC_PMIC_PWM_PERIOD_NS);
panel->backlight.enabled = panel->backlight.level != 0;
+ DRM_INFO("Using %s PWM for LCD backlight control\n", desc);
return 0;
}
--
2.23.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Intel-gfx] [CI 3/3] drm/i915: DSI: select correct PWM controller to use based on the VBT
@ 2019-12-16 20:29 ` Hans de Goede
0 siblings, 0 replies; 21+ messages in thread
From: Hans de Goede @ 2019-12-16 20:29 UTC (permalink / raw)
To: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä, intel-gfx, Rafael J . Wysocki, Lee Jones
Cc: linux-acpi, Jani Nikula, linux-kernel, dri-devel, Andy Shevchenko
At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
different PWM controllers for controlling the LCD's backlight brightness.
Either the one integrated into the PMIC or the one integrated into the
SoC (the 1st LPSS PWM controller).
So far in the LPSS code on BYT we have skipped registering the LPSS PWM
controller "pwm_backlight" lookup entry when a Crystal Cove PMIC is
present, assuming that in this case the PMIC PWM controller will be used.
On CHT we have been relying on only 1 of the 2 PWM controllers being
enabled in the DSDT at the same time; and always registered the lookup.
So far this has been working, but the correct way to determine which PWM
controller needs to be used is by checking a bit in the VBT table and
recently I've learned about 2 different BYT devices:
Point of View MOBII TAB-P800W
Acer Switch 10 SW5-012
Which use a Crystal Cove PMIC, yet the LCD is connected to the SoC/LPSS
PWM controller (and the VBT correctly indicates this), so here our old
heuristics fail.
This commit fixes using the wrong PWM controller on these devices by
calling pwm_get() for the right PWM controller based on the
VBT dsi.config.pwm_blc bit.
Note this is part of a series which contains 2 other patches which renames
the PWM lookup for the 1st SoC/LPSS PWM from "pwm_backlight" to
"pwm_pmic_backlight" and the PWM lookup for the Crystal Cove PMIC PWM
from "pwm_backlight" to "pwm_pmic_backlight".
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/gpu/drm/i915/display/intel_panel.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index bc14e9c0285a..ddcf311d1114 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -1840,13 +1840,22 @@ static int pwm_setup_backlight(struct intel_connector *connector,
enum pipe pipe)
{
struct drm_device *dev = connector->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_panel *panel = &connector->panel;
+ const char *desc;
int retval;
- /* Get the PWM chip for backlight control */
- panel->backlight.pwm = pwm_get(dev->dev, "pwm_backlight");
+ /* Get the right PWM chip for DSI backlight according to VBT */
+ if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {
+ panel->backlight.pwm = pwm_get(dev->dev, "pwm_pmic_backlight");
+ desc = "PMIC";
+ } else {
+ panel->backlight.pwm = pwm_get(dev->dev, "pwm_soc_backlight");
+ desc = "SoC";
+ }
+
if (IS_ERR(panel->backlight.pwm)) {
- DRM_ERROR("Failed to own the pwm chip\n");
+ DRM_ERROR("Failed to get the %s PWM chip\n", desc);
panel->backlight.pwm = NULL;
return -ENODEV;
}
@@ -1873,6 +1882,7 @@ static int pwm_setup_backlight(struct intel_connector *connector,
CRC_PMIC_PWM_PERIOD_NS);
panel->backlight.enabled = panel->backlight.level != 0;
+ DRM_INFO("Using %s PWM for LCD backlight control\n", desc);
return 0;
}
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread* [CI 3/3] drm/i915: DSI: select correct PWM controller to use based on the VBT
@ 2019-12-16 20:29 ` Hans de Goede
0 siblings, 0 replies; 21+ messages in thread
From: Hans de Goede @ 2019-12-16 20:29 UTC (permalink / raw)
To: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä, intel-gfx, Rafael J . Wysocki, Lee Jones
Cc: linux-acpi, Jani Nikula, linux-kernel, dri-devel, Hans de Goede,
Andy Shevchenko
At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
different PWM controllers for controlling the LCD's backlight brightness.
Either the one integrated into the PMIC or the one integrated into the
SoC (the 1st LPSS PWM controller).
So far in the LPSS code on BYT we have skipped registering the LPSS PWM
controller "pwm_backlight" lookup entry when a Crystal Cove PMIC is
present, assuming that in this case the PMIC PWM controller will be used.
On CHT we have been relying on only 1 of the 2 PWM controllers being
enabled in the DSDT at the same time; and always registered the lookup.
So far this has been working, but the correct way to determine which PWM
controller needs to be used is by checking a bit in the VBT table and
recently I've learned about 2 different BYT devices:
Point of View MOBII TAB-P800W
Acer Switch 10 SW5-012
Which use a Crystal Cove PMIC, yet the LCD is connected to the SoC/LPSS
PWM controller (and the VBT correctly indicates this), so here our old
heuristics fail.
This commit fixes using the wrong PWM controller on these devices by
calling pwm_get() for the right PWM controller based on the
VBT dsi.config.pwm_blc bit.
Note this is part of a series which contains 2 other patches which renames
the PWM lookup for the 1st SoC/LPSS PWM from "pwm_backlight" to
"pwm_pmic_backlight" and the PWM lookup for the Crystal Cove PMIC PWM
from "pwm_backlight" to "pwm_pmic_backlight".
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/gpu/drm/i915/display/intel_panel.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index bc14e9c0285a..ddcf311d1114 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -1840,13 +1840,22 @@ static int pwm_setup_backlight(struct intel_connector *connector,
enum pipe pipe)
{
struct drm_device *dev = connector->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_panel *panel = &connector->panel;
+ const char *desc;
int retval;
- /* Get the PWM chip for backlight control */
- panel->backlight.pwm = pwm_get(dev->dev, "pwm_backlight");
+ /* Get the right PWM chip for DSI backlight according to VBT */
+ if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {
+ panel->backlight.pwm = pwm_get(dev->dev, "pwm_pmic_backlight");
+ desc = "PMIC";
+ } else {
+ panel->backlight.pwm = pwm_get(dev->dev, "pwm_soc_backlight");
+ desc = "SoC";
+ }
+
if (IS_ERR(panel->backlight.pwm)) {
- DRM_ERROR("Failed to own the pwm chip\n");
+ DRM_ERROR("Failed to get the %s PWM chip\n", desc);
panel->backlight.pwm = NULL;
return -ENODEV;
}
@@ -1873,6 +1882,7 @@ static int pwm_setup_backlight(struct intel_connector *connector,
CRC_PMIC_PWM_PERIOD_NS);
panel->backlight.enabled = panel->backlight.level != 0;
+ DRM_INFO("Using %s PWM for LCD backlight control\n", desc);
return 0;
}
--
2.23.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915 / LPSS / mfd: Select correct PWM controller to use based on VBT (rev3)
2019-12-16 20:29 ` Hans de Goede
` (4 preceding siblings ...)
(?)
@ 2019-12-17 3:13 ` Patchwork
-1 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2019-12-17 3:13 UTC (permalink / raw)
To: Hans de Goede; +Cc: intel-gfx
== Series Details ==
Series: drm/i915 / LPSS / mfd: Select correct PWM controller to use based on VBT (rev3)
URL : https://patchwork.freedesktop.org/series/69686/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9a0b084effd9 ACPI / LPSS: Rename pwm_backlight pwm-lookup to pwm_soc_backlight
7f06eeff5a09 mfd: intel_soc_pmic: Rename pwm_backlight pwm-lookup to pwm_pmic_backlight
-:50: WARNING:LONG_LINE: line over 100 characters
#50: FILE: drivers/mfd/intel_soc_pmic_core.c:41:
+ PWM_LOOKUP("crystal_cove_pwm", 0, "0000:00:02.0", "pwm_pmic_backlight", 0, PWM_POLARITY_NORMAL),
total: 0 errors, 1 warnings, 0 checks, 8 lines checked
b075d00cadea drm/i915: DSI: select correct PWM controller to use based on the VBT
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915 / LPSS / mfd: Select correct PWM controller to use based on VBT (rev3)
2019-12-16 20:29 ` Hans de Goede
` (5 preceding siblings ...)
(?)
@ 2019-12-17 3:54 ` Patchwork
-1 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2019-12-17 3:54 UTC (permalink / raw)
To: Hans de Goede; +Cc: intel-gfx
== Series Details ==
Series: drm/i915 / LPSS / mfd: Select correct PWM controller to use based on VBT (rev3)
URL : https://patchwork.freedesktop.org/series/69686/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7578 -> Patchwork_15800
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/index.html
Known issues
------------
Here are the changes found in Patchwork_15800 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_sync@basic-all:
- fi-tgl-y: [PASS][1] -> [INCOMPLETE][2] ([i915#470] / [i915#472])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-tgl-y/igt@gem_sync@basic-all.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/fi-tgl-y/igt@gem_sync@basic-all.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-lmem: [PASS][3] -> [DMESG-WARN][4] ([i915#592])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_blt:
- fi-hsw-4770r: [PASS][5] -> [DMESG-FAIL][6] ([i915#770])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-hsw-4770r/igt@i915_selftest@live_blt.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/fi-hsw-4770r/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-byt-j1900: [PASS][7] -> [INCOMPLETE][8] ([i915#45])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
- fi-hsw-peppy: [PASS][9] -> [INCOMPLETE][10] ([i915#694])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
* igt@kms_frontbuffer_tracking@basic:
- fi-kbl-r: [PASS][11] -> [INCOMPLETE][12] ([i915#667])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-kbl-r/igt@kms_frontbuffer_tracking@basic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/fi-kbl-r/igt@kms_frontbuffer_tracking@basic.html
- fi-hsw-peppy: [PASS][13] -> [DMESG-WARN][14] ([i915#44])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@gem_exec_parallel@basic:
- {fi-tgl-u}: [INCOMPLETE][15] ([i915#476]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-tgl-u/igt@gem_exec_parallel@basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/fi-tgl-u/igt@gem_exec_parallel@basic.html
* igt@gem_exec_suspend@basic-s3:
- fi-icl-u2: [FAIL][17] ([fdo#103375]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-icl-u2/igt@gem_exec_suspend@basic-s3.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/fi-icl-u2/igt@gem_exec_suspend@basic-s3.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u2: [FAIL][19] ([fdo#111550]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-icl-u2/igt@gem_exec_suspend@basic-s4-devices.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/fi-icl-u2/igt@gem_exec_suspend@basic-s4-devices.html
* igt@i915_selftest@live_blt:
- fi-ivb-3770: [DMESG-FAIL][21] ([i915#725]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-ivb-3770/igt@i915_selftest@live_blt.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/fi-ivb-3770/igt@i915_selftest@live_blt.html
- fi-hsw-4770: [DMESG-FAIL][23] ([i915#553] / [i915#725]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-hsw-4770/igt@i915_selftest@live_blt.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/fi-hsw-4770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-byt-n2820: [DMESG-FAIL][25] ([i915#722]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
- fi-cfl-guc: [DMESG-FAIL][27] ([i915#730]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
* igt@kms_busy@basic-flip-pipe-a:
- fi-icl-u2: [INCOMPLETE][29] ([i915#140]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-icl-u2/igt@kms_busy@basic-flip-pipe-a.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/fi-icl-u2/igt@kms_busy@basic-flip-pipe-a.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][31] ([fdo#109635] / [i915#217]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][33] ([fdo#111096] / [i915#323]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][35] ([i915#62] / [i915#92]) -> [DMESG-WARN][36] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
* igt@kms_flip@basic-flip-vs-modeset:
- fi-kbl-x1275: [DMESG-WARN][37] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][38] ([i915#62] / [i915#92]) +8 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111550]: https://bugs.freedesktop.org/show_bug.cgi?id=111550
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
[i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
[i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#44]: https://gitlab.freedesktop.org/drm/intel/issues/44
[i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
[i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
[i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
[i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#592]: https://gitlab.freedesktop.org/drm/intel/issues/592
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#667]: https://gitlab.freedesktop.org/drm/intel/issues/667
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#730]: https://gitlab.freedesktop.org/drm/intel/issues/730
[i915#770]: https://gitlab.freedesktop.org/drm/intel/issues/770
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (51 -> 44)
------------------------------
Additional (1): fi-kbl-soraka
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-whl-u fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7578 -> Patchwork_15800
CI-20190529: 20190529
CI_DRM_7578: cc329d389f5609d2969d0797bc96f754adb26d62 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5349: 048f58513d8b8ec6bb307a939f0ac959bc0f0e10 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15800: b075d00cadea3e5ffb29bf64c0a18c3aab85caba @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b075d00cadea drm/i915: DSI: select correct PWM controller to use based on the VBT
7f06eeff5a09 mfd: intel_soc_pmic: Rename pwm_backlight pwm-lookup to pwm_pmic_backlight
9a0b084effd9 ACPI / LPSS: Rename pwm_backlight pwm-lookup to pwm_soc_backlight
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915 / LPSS / mfd: Select correct PWM controller to use based on VBT (rev3)
2019-12-16 20:29 ` Hans de Goede
` (6 preceding siblings ...)
(?)
@ 2019-12-17 9:43 ` Patchwork
-1 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2019-12-17 9:43 UTC (permalink / raw)
To: Hans de Goede; +Cc: intel-gfx
== Series Details ==
Series: drm/i915 / LPSS / mfd: Select correct PWM controller to use based on VBT (rev3)
URL : https://patchwork.freedesktop.org/series/69686/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7578_full -> Patchwork_15800_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_15800_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@vcs0-s3:
- shard-skl: [PASS][1] -> [INCOMPLETE][2] ([i915#69])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl9/igt@gem_ctx_isolation@vcs0-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-skl7/igt@gem_ctx_isolation@vcs0-s3.html
* igt@gem_ctx_persistence@vcs1-cleanup:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb4/igt@gem_ctx_persistence@vcs1-cleanup.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-iclb5/igt@gem_ctx_persistence@vcs1-cleanup.html
* igt@gem_exec_basic@readonly-vcs1:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112080]) +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb4/igt@gem_exec_basic@readonly-vcs1.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-iclb5/igt@gem_exec_basic@readonly-vcs1.html
* igt@gem_exec_create@basic:
- shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([fdo#111736])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb4/igt@gem_exec_create@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-tglb6/igt@gem_exec_create@basic.html
* igt@gem_exec_gttfill@basic:
- shard-tglb: [PASS][9] -> [INCOMPLETE][10] ([fdo#111593])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb5/igt@gem_exec_gttfill@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-tglb5/igt@gem_exec_gttfill@basic.html
* igt@gem_exec_nop@basic-series:
- shard-tglb: [PASS][11] -> [INCOMPLETE][12] ([i915#435])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb5/igt@gem_exec_nop@basic-series.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-tglb6/igt@gem_exec_nop@basic-series.html
* igt@gem_exec_schedule@fifo-bsd1:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109276]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb4/igt@gem_exec_schedule@fifo-bsd1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-iclb5/igt@gem_exec_schedule@fifo-bsd1.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#112146]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb6/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [PASS][17] -> [FAIL][18] ([i915#644])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-glk7/igt@gem_ppgtt@flink-and-close-vma-leak.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-glk5/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][19] -> [FAIL][20] ([i915#454])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb2/igt@i915_pm_dc@dc6-dpms.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_selftest@live_gem_contexts:
- shard-tglb: [PASS][21] -> [INCOMPLETE][22] ([i915#455])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb2/igt@i915_selftest@live_gem_contexts.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-tglb6/igt@i915_selftest@live_gem_contexts.html
* igt@kms_color@pipe-b-ctm-0-5:
- shard-skl: [PASS][23] -> [DMESG-WARN][24] ([i915#109])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl10/igt@kms_color@pipe-b-ctm-0-5.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-skl9/igt@kms_color@pipe-b-ctm-0-5.html
* igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding:
- shard-skl: [PASS][25] -> [FAIL][26] ([i915#54]) +2 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-skl5/igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding.html
* igt@kms_flip@plain-flip-ts-check-interruptible:
- shard-skl: [PASS][27] -> [FAIL][28] ([i915#34])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl7/igt@kms_flip@plain-flip-ts-check-interruptible.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-skl10/igt@kms_flip@plain-flip-ts-check-interruptible.html
* igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
- shard-skl: [PASS][29] -> [INCOMPLETE][30] ([i915#123] / [i915#667])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl8/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-skl7/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html
* igt@kms_plane@pixel-format-pipe-b-planes:
- shard-kbl: [PASS][31] -> [INCOMPLETE][32] ([fdo#103665] / [i915#648] / [i915#667])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-kbl6/igt@kms_plane@pixel-format-pipe-b-planes.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-kbl7/igt@kms_plane@pixel-format-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][33] -> [FAIL][34] ([fdo#108145] / [i915#265])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109441]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-iclb3/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@kms_psr@psr2_suspend:
- shard-tglb: [PASS][37] -> [INCOMPLETE][38] ([i915#456] / [i915#460])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb9/igt@kms_psr@psr2_suspend.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-tglb4/igt@kms_psr@psr2_suspend.html
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- shard-tglb: [PASS][39] -> [INCOMPLETE][40] ([i915#460])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb8/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-tglb5/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][41] -> [DMESG-WARN][42] ([i915#180]) +7 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
#### Possible fixes ####
* igt@gem_busy@close-race:
- shard-tglb: [INCOMPLETE][43] ([i915#435]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb6/igt@gem_busy@close-race.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-tglb8/igt@gem_busy@close-race.html
* igt@gem_ctx_persistence@vcs1-mixed-process:
- shard-iclb: [SKIP][45] ([fdo#109276] / [fdo#112080]) -> [PASS][46] +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb8/igt@gem_ctx_persistence@vcs1-mixed-process.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-iclb1/igt@gem_ctx_persistence@vcs1-mixed-process.html
* igt@gem_eio@banned:
- shard-tglb: [INCOMPLETE][47] ([i915#476]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb6/igt@gem_eio@banned.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-tglb7/igt@gem_eio@banned.html
* igt@gem_eio@suspend:
- shard-tglb: [INCOMPLETE][49] ([i915#460]) -> [PASS][50] +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb2/igt@gem_eio@suspend.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-tglb9/igt@gem_eio@suspend.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [SKIP][51] ([fdo#110854]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb6/igt@gem_exec_balancer@smoke.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-iclb2/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_reloc@basic-wc-active:
- shard-skl: [DMESG-WARN][53] ([i915#109]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl8/igt@gem_exec_reloc@basic-wc-active.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-skl6/igt@gem_exec_reloc@basic-wc-active.html
* {igt@gem_exec_schedule@pi-common-bsd1}:
- shard-iclb: [SKIP][55] ([fdo#109276]) -> [PASS][56] +8 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb3/igt@gem_exec_schedule@pi-common-bsd1.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-iclb2/igt@gem_exec_schedule@pi-common-bsd1.html
* {igt@gen9_exec_parse@allowed-single}:
- shard-glk: [DMESG-WARN][57] ([i915#716]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-glk9/igt@gen9_exec_parse@allowed-single.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-glk4/igt@gen9_exec_parse@allowed-single.html
- shard-skl: [DMESG-WARN][59] ([i915#716]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl6/igt@gen9_exec_parse@allowed-single.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-skl9/igt@gen9_exec_parse@allowed-single.html
* igt@kms_cursor_crc@pipe-a-cursor-128x128-sliding:
- shard-skl: [FAIL][61] ([i915#54]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl10/igt@kms_cursor_crc@pipe-a-cursor-128x128-sliding.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-skl9/igt@kms_cursor_crc@pipe-a-cursor-128x128-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-tglb: [INCOMPLETE][63] ([i915#456] / [i915#460]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb5/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-tglb4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: [FAIL][65] ([i915#79]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-apl: [FAIL][67] ([i915#79]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-apl8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-apl3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [INCOMPLETE][69] ([i915#221]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl4/igt@kms_flip@flip-vs-suspend.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-skl3/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render:
- shard-tglb: [FAIL][71] ([i915#49]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
- shard-iclb: [INCOMPLETE][73] ([i915#123] / [i915#140]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-tglb: [INCOMPLETE][75] ([i915#456] / [i915#460] / [i915#474]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: [SKIP][77] ([fdo#109441]) -> [PASS][78] +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb6/igt@kms_psr@psr2_dpms.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-iclb2/igt@kms_psr@psr2_dpms.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][79] ([i915#180]) -> [PASS][80] +2 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-apl1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-apl2/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@perf_pmu@busy-accuracy-98-vcs1:
- shard-iclb: [SKIP][81] ([fdo#112080]) -> [PASS][82] +2 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb6/igt@perf_pmu@busy-accuracy-98-vcs1.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-iclb2/igt@perf_pmu@busy-accuracy-98-vcs1.html
#### Warnings ####
* igt@kms_atomic_transition@6x-modeset-transitions:
- shard-tglb: [SKIP][83] ([fdo#112021]) -> [SKIP][84] ([fdo#112016] / [fdo#112021])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb9/igt@kms_atomic_transition@6x-modeset-transitions.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-tglb4/igt@kms_atomic_transition@6x-modeset-transitions.html
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-skl: [INCOMPLETE][85] ([i915#648]) -> [INCOMPLETE][86] ([i915#648] / [i915#667])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl5/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-skl10/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-skl: [INCOMPLETE][87] ([fdo#112347] / [i915#648] / [i915#667]) -> [INCOMPLETE][88] ([fdo#112347] / [fdo#112391] / [i915#648] / [i915#667])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl7/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/shard-skl4/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
[fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
[fdo#112016]: https://bugs.freedesktop.org/show_bug.cgi?id=112016
[fdo#112021]: https://bugs.freedesktop.org/show_bug.cgi?id=112021
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[fdo#112347]: https://bugs.freedesktop.org/show_bug.cgi?id=112347
[fdo#112391]: https://bugs.freedesktop.org/show_bug.cgi?id=112391
[i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
[i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123
[i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#455]: https://gitlab.freedesktop.org/drm/intel/issues/455
[i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
[i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460
[i915#474]: https://gitlab.freedesktop.org/drm/intel/issues/474
[i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648
[i915#667]: https://gitlab.freedesktop.org/drm/intel/issues/667
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7578 -> Patchwork_15800
CI-20190529: 20190529
CI_DRM_7578: cc329d389f5609d2969d0797bc96f754adb26d62 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5349: 048f58513d8b8ec6bb307a939f0ac959bc0f0e10 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15800: b075d00cadea3e5ffb29bf64c0a18c3aab85caba @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15800/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [CI 0/3] drm/i915 / LPSS / mfd: Select correct PWM controller to use based on VBT
2019-12-16 20:29 ` Hans de Goede
(?)
@ 2019-12-17 11:36 ` Jani Nikula
-1 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2019-12-17 11:36 UTC (permalink / raw)
To: Hans de Goede, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä, intel-gfx, Rafael J . Wysocki, Lee Jones
Cc: Hans de Goede, dri-devel, linux-acpi, linux-kernel
On Mon, 16 Dec 2019, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi All,
>
> Somehow the CI system did not pick up this series the first time, there
> are no test results recorded for it:
> https://patchwork.freedesktop.org/series/69685
>
> So this is a resend for CI to do its thing. As soon as CI is happy with
> this I will push this to drm-intel-next-queued.
Thanks, please go ahead.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [CI 0/3] drm/i915 / LPSS / mfd: Select correct PWM controller to use based on VBT
@ 2019-12-17 11:36 ` Jani Nikula
0 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2019-12-17 11:36 UTC (permalink / raw)
To: Hans de Goede, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä, intel-gfx, Rafael J . Wysocki, Lee Jones
Cc: linux-kernel, dri-devel, linux-acpi
On Mon, 16 Dec 2019, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi All,
>
> Somehow the CI system did not pick up this series the first time, there
> are no test results recorded for it:
> https://patchwork.freedesktop.org/series/69685
>
> So this is a resend for CI to do its thing. As soon as CI is happy with
> this I will push this to drm-intel-next-queued.
Thanks, please go ahead.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [CI 0/3] drm/i915 / LPSS / mfd: Select correct PWM controller to use based on VBT
@ 2019-12-17 11:36 ` Jani Nikula
0 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2019-12-17 11:36 UTC (permalink / raw)
To: Hans de Goede, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä, intel-gfx, Rafael J . Wysocki, Lee Jones
Cc: Hans de Goede, linux-kernel, dri-devel, linux-acpi
On Mon, 16 Dec 2019, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi All,
>
> Somehow the CI system did not pick up this series the first time, there
> are no test results recorded for it:
> https://patchwork.freedesktop.org/series/69685
>
> So this is a resend for CI to do its thing. As soon as CI is happy with
> this I will push this to drm-intel-next-queued.
Thanks, please go ahead.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 21+ messages in thread