* [PATCH v3] drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection
@ 2018-03-20 18:37 Oscar Mateo
2018-03-20 18:55 ` Lionel Landwerlin
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Oscar Mateo @ 2018-03-20 18:37 UTC (permalink / raw)
To: intel-gfx
From: Kelvin Gardiner <kelvin.gardiner@intel.com>
This patch adds support to detect ICL, slice, subslice and EU fuse
settings.
Add addresses for ICL 11 slice, subslice and EU fuses registers.
These register addresses are the same as previous platforms but the
format and / or the meaning of the information is different. Therefore
Gen11 defines for these registers are added.
Bspec: 9731
Bspec: 20643
Bspec: 20673
v2: Update fusing information storage after introducing the new query
uAPI (Lionel)
v3 (Oscar):
- The maximum number of slices in ICL 11 is 1
- The subslice disable fuse can potentially store information in
all bits
- GEN_MAX_SUBSLICES has to be increased to 8
- Don't trust the slice enabled fuse outside the max number of
expected slices
- Indentation fix and some reordering and renaming of local
variables
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Kelvin Gardiner <kelvin.gardiner@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++
drivers/gpu/drm/i915/intel_device_info.c | 43 +++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_device_info.h | 2 +-
3 files changed, 51 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dc41961..1f47806 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2554,6 +2554,14 @@ enum i915_power_well_id {
#define GEN11_GT_VEBOX_DISABLE_SHIFT 16
#define GEN11_GT_VEBOX_DISABLE_MASK (0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
+#define GEN11_EU_DISABLE _MMIO(0x9134)
+#define GEN11_EU_DIS_MASK 0xFF
+
+#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
+#define GEN11_GT_S_ENA_MASK 0xFF
+
+#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
+
#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 4babfc6..a504281 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -158,6 +158,45 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu)
return total;
}
+static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+ struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+ u8 s_en;
+ u32 ss_en, ss_en_mask;
+ u8 eu_en;
+ int s;
+
+ sseu->max_slices = 1;
+ sseu->max_subslices = 8;
+ sseu->max_eus_per_subslice = 8;
+
+ s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
+ ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
+ ss_en_mask = BIT(sseu->max_subslices) - 1;
+ eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ if (s_en & BIT(s)) {
+ int ss_idx = sseu->max_subslices * s;
+ int ss;
+
+ sseu->slice_mask |= BIT(s);
+ sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask;
+ for (ss = 0; ss < sseu->max_subslices; ss++) {
+ if (sseu->subslice_mask[s] & BIT(ss))
+ sseu_set_eus(sseu, s, ss, eu_en);
+ }
+ }
+ }
+ sseu->eu_per_subslice = hweight8(eu_en);
+ sseu->eu_total = compute_eu_total(sseu);
+
+ /* ICL has no power gating restrictions. */
+ sseu->has_slice_pg = 1;
+ sseu->has_subslice_pg = 1;
+ sseu->has_eu_pg = 1;
+}
+
static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
@@ -768,8 +807,10 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
broadwell_sseu_info_init(dev_priv);
else if (INTEL_GEN(dev_priv) == 9)
gen9_sseu_info_init(dev_priv);
- else if (INTEL_GEN(dev_priv) >= 10)
+ else if (INTEL_GEN(dev_priv) == 10)
gen10_sseu_info_init(dev_priv);
+ else if (INTEL_INFO(dev_priv)->gen >= 11)
+ gen11_sseu_info_init(dev_priv);
/* Initialize command stream timestamp frequency */
info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 0cbb922..933e316 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -114,7 +114,7 @@ enum intel_platform {
func(has_ipc);
#define GEN_MAX_SLICES (6) /* CNL upper bound */
-#define GEN_MAX_SUBSLICES (7)
+#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
struct sseu_dev_info {
u8 slice_mask;
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v3] drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection
2018-03-20 18:37 [PATCH v3] drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection Oscar Mateo
@ 2018-03-20 18:55 ` Lionel Landwerlin
2018-03-20 19:45 ` [PATCH v4] " Oscar Mateo
2018-03-20 19:08 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Lionel Landwerlin @ 2018-03-20 18:55 UTC (permalink / raw)
To: Oscar Mateo, intel-gfx
On 20/03/18 18:37, Oscar Mateo wrote:
> From: Kelvin Gardiner <kelvin.gardiner@intel.com>
>
> This patch adds support to detect ICL, slice, subslice and EU fuse
> settings.
>
> Add addresses for ICL 11 slice, subslice and EU fuses registers.
> These register addresses are the same as previous platforms but the
> format and / or the meaning of the information is different. Therefore
> Gen11 defines for these registers are added.
>
> Bspec: 9731
> Bspec: 20643
> Bspec: 20673
>
> v2: Update fusing information storage after introducing the new query
> uAPI (Lionel)
>
> v3 (Oscar):
> - The maximum number of slices in ICL 11 is 1
> - The subslice disable fuse can potentially store information in
> all bits
> - GEN_MAX_SUBSLICES has to be increased to 8
> - Don't trust the slice enabled fuse outside the max number of
> expected slices
> - Indentation fix and some reordering and renaming of local
> variables
>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Kelvin Gardiner <kelvin.gardiner@intel.com>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++
> drivers/gpu/drm/i915/intel_device_info.c | 43 +++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_device_info.h | 2 +-
> 3 files changed, 51 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dc41961..1f47806 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2554,6 +2554,14 @@ enum i915_power_well_id {
> #define GEN11_GT_VEBOX_DISABLE_SHIFT 16
> #define GEN11_GT_VEBOX_DISABLE_MASK (0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
>
> +#define GEN11_EU_DISABLE _MMIO(0x9134)
> +#define GEN11_EU_DIS_MASK 0xFF
> +
> +#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
> +#define GEN11_GT_S_ENA_MASK 0xFF
> +
> +#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
> +
> #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
> #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
> #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 4babfc6..a504281 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -158,6 +158,45 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu)
> return total;
> }
>
> +static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
> +{
> + struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
> + u8 s_en;
> + u32 ss_en, ss_en_mask;
> + u8 eu_en;
> + int s;
> +
> + sseu->max_slices = 1;
> + sseu->max_subslices = 8;
> + sseu->max_eus_per_subslice = 8;
> +
> + s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
> + ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
> + ss_en_mask = BIT(sseu->max_subslices) - 1;
> + eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + if (s_en & BIT(s)) {
> + int ss_idx = sseu->max_subslices * s;
> + int ss;
> +
> + sseu->slice_mask |= BIT(s);
> + sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask;
> + for (ss = 0; ss < sseu->max_subslices; ss++) {
> + if (sseu->subslice_mask[s] & BIT(ss))
> + sseu_set_eus(sseu, s, ss, eu_en);
> + }
> + }
> + }
> + sseu->eu_per_subslice = hweight8(eu_en);
> + sseu->eu_total = compute_eu_total(sseu);
> +
> + /* ICL has no power gating restrictions. */
> + sseu->has_slice_pg = 1;
> + sseu->has_subslice_pg = 1;
> + sseu->has_eu_pg = 1;
> +}
> +
> static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
> {
> struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
> @@ -768,8 +807,10 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
> broadwell_sseu_info_init(dev_priv);
> else if (INTEL_GEN(dev_priv) == 9)
> gen9_sseu_info_init(dev_priv);
> - else if (INTEL_GEN(dev_priv) >= 10)
> + else if (INTEL_GEN(dev_priv) == 10)
> gen10_sseu_info_init(dev_priv);
> + else if (INTEL_INFO(dev_priv)->gen >= 11)
> + gen11_sseu_info_init(dev_priv);
>
> /* Initialize command stream timestamp frequency */
> info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 0cbb922..933e316 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -114,7 +114,7 @@ enum intel_platform {
> func(has_ipc);
>
> #define GEN_MAX_SLICES (6) /* CNL upper bound */
> -#define GEN_MAX_SUBSLICES (7)
> +#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
>
> struct sseu_dev_info {
> u8 slice_mask;
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v4] drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection
2018-03-20 18:55 ` Lionel Landwerlin
@ 2018-03-20 19:45 ` Oscar Mateo
2018-03-21 10:03 ` Tvrtko Ursulin
0 siblings, 1 reply; 9+ messages in thread
From: Oscar Mateo @ 2018-03-20 19:45 UTC (permalink / raw)
To: intel-gfx
From: Kelvin Gardiner <kelvin.gardiner@intel.com>
This patch adds support to detect ICL, slice, subslice and EU fuse
settings.
Add addresses for ICL 11 slice, subslice and EU fuses registers.
These register addresses are the same as previous platforms but the
format and / or the meaning of the information is different. Therefore
Gen11 defines for these registers are added.
Bspec: 9731
Bspec: 20643
Bspec: 20673
v2: Update fusing information storage after introducing the new query
uAPI (Lionel)
v3 (Oscar):
- The maximum number of slices in ICL 11 is 1
- The subslice disable fuse can potentially store information in
all bits
- GEN_MAX_SUBSLICES has to be increased to 8
- Don't trust the slice enabled fuse outside the max number of
expected slices
- Indentation fix and some reordering and renaming of local
variables
v4: Use single space after Cc tag
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Kelvin Gardiner <kelvin.gardiner@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++
drivers/gpu/drm/i915/intel_device_info.c | 43 +++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_device_info.h | 2 +-
3 files changed, 51 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dc41961..1f47806 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2554,6 +2554,14 @@ enum i915_power_well_id {
#define GEN11_GT_VEBOX_DISABLE_SHIFT 16
#define GEN11_GT_VEBOX_DISABLE_MASK (0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
+#define GEN11_EU_DISABLE _MMIO(0x9134)
+#define GEN11_EU_DIS_MASK 0xFF
+
+#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
+#define GEN11_GT_S_ENA_MASK 0xFF
+
+#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
+
#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 4babfc6..a504281 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -158,6 +158,45 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu)
return total;
}
+static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+ struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+ u8 s_en;
+ u32 ss_en, ss_en_mask;
+ u8 eu_en;
+ int s;
+
+ sseu->max_slices = 1;
+ sseu->max_subslices = 8;
+ sseu->max_eus_per_subslice = 8;
+
+ s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
+ ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
+ ss_en_mask = BIT(sseu->max_subslices) - 1;
+ eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ if (s_en & BIT(s)) {
+ int ss_idx = sseu->max_subslices * s;
+ int ss;
+
+ sseu->slice_mask |= BIT(s);
+ sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask;
+ for (ss = 0; ss < sseu->max_subslices; ss++) {
+ if (sseu->subslice_mask[s] & BIT(ss))
+ sseu_set_eus(sseu, s, ss, eu_en);
+ }
+ }
+ }
+ sseu->eu_per_subslice = hweight8(eu_en);
+ sseu->eu_total = compute_eu_total(sseu);
+
+ /* ICL has no power gating restrictions. */
+ sseu->has_slice_pg = 1;
+ sseu->has_subslice_pg = 1;
+ sseu->has_eu_pg = 1;
+}
+
static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
@@ -768,8 +807,10 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
broadwell_sseu_info_init(dev_priv);
else if (INTEL_GEN(dev_priv) == 9)
gen9_sseu_info_init(dev_priv);
- else if (INTEL_GEN(dev_priv) >= 10)
+ else if (INTEL_GEN(dev_priv) == 10)
gen10_sseu_info_init(dev_priv);
+ else if (INTEL_INFO(dev_priv)->gen >= 11)
+ gen11_sseu_info_init(dev_priv);
/* Initialize command stream timestamp frequency */
info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 0cbb922..933e316 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -114,7 +114,7 @@ enum intel_platform {
func(has_ipc);
#define GEN_MAX_SLICES (6) /* CNL upper bound */
-#define GEN_MAX_SUBSLICES (7)
+#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
struct sseu_dev_info {
u8 slice_mask;
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v4] drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection
2018-03-20 19:45 ` [PATCH v4] " Oscar Mateo
@ 2018-03-21 10:03 ` Tvrtko Ursulin
2018-03-21 12:08 ` Mika Kuoppala
0 siblings, 1 reply; 9+ messages in thread
From: Tvrtko Ursulin @ 2018-03-21 10:03 UTC (permalink / raw)
To: Oscar Mateo, intel-gfx
On 20/03/2018 19:45, Oscar Mateo wrote:
> From: Kelvin Gardiner <kelvin.gardiner@intel.com>
>
> This patch adds support to detect ICL, slice, subslice and EU fuse
> settings.
>
> Add addresses for ICL 11 slice, subslice and EU fuses registers.
> These register addresses are the same as previous platforms but the
> format and / or the meaning of the information is different. Therefore
> Gen11 defines for these registers are added.
>
> Bspec: 9731
> Bspec: 20643
> Bspec: 20673
>
> v2: Update fusing information storage after introducing the new query
> uAPI (Lionel)
>
> v3 (Oscar):
> - The maximum number of slices in ICL 11 is 1
> - The subslice disable fuse can potentially store information in
> all bits
> - GEN_MAX_SUBSLICES has to be increased to 8
> - Don't trust the slice enabled fuse outside the max number of
> expected slices
> - Indentation fix and some reordering and renaming of local
> variables
>
> v4: Use single space after Cc tag
>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Kelvin Gardiner <kelvin.gardiner@intel.com>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++
> drivers/gpu/drm/i915/intel_device_info.c | 43 +++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_device_info.h | 2 +-
> 3 files changed, 51 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dc41961..1f47806 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2554,6 +2554,14 @@ enum i915_power_well_id {
> #define GEN11_GT_VEBOX_DISABLE_SHIFT 16
> #define GEN11_GT_VEBOX_DISABLE_MASK (0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
>
> +#define GEN11_EU_DISABLE _MMIO(0x9134)
> +#define GEN11_EU_DIS_MASK 0xFF
> +
> +#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
> +#define GEN11_GT_S_ENA_MASK 0xFF
> +
> +#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
> +
> #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
> #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
> #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 4babfc6..a504281 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -158,6 +158,45 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu)
> return total;
> }
>
> +static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
> +{
> + struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
> + u8 s_en;
> + u32 ss_en, ss_en_mask;
> + u8 eu_en;
> + int s;
> +
> + sseu->max_slices = 1;
> + sseu->max_subslices = 8;
> + sseu->max_eus_per_subslice = 8;
> +
> + s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
> + ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
> + ss_en_mask = BIT(sseu->max_subslices) - 1;
> + eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + if (s_en & BIT(s)) {
> + int ss_idx = sseu->max_subslices * s;
> + int ss;
> +
> + sseu->slice_mask |= BIT(s);
> + sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask;
> + for (ss = 0; ss < sseu->max_subslices; ss++) {
> + if (sseu->subslice_mask[s] & BIT(ss))
> + sseu_set_eus(sseu, s, ss, eu_en);
> + }
> + }
> + }
> + sseu->eu_per_subslice = hweight8(eu_en);
> + sseu->eu_total = compute_eu_total(sseu);
> +
> + /* ICL has no power gating restrictions. */
> + sseu->has_slice_pg = 1;
> + sseu->has_subslice_pg = 1;
> + sseu->has_eu_pg = 1;
> +}
> +
> static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
> {
> struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
> @@ -768,8 +807,10 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
> broadwell_sseu_info_init(dev_priv);
> else if (INTEL_GEN(dev_priv) == 9)
> gen9_sseu_info_init(dev_priv);
> - else if (INTEL_GEN(dev_priv) >= 10)
> + else if (INTEL_GEN(dev_priv) == 10)
> gen10_sseu_info_init(dev_priv);
> + else if (INTEL_INFO(dev_priv)->gen >= 11)
INTEL_GEN(dev_priv) >= 11
Regards,
Tvrtko
> + gen11_sseu_info_init(dev_priv);
>
> /* Initialize command stream timestamp frequency */
> info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 0cbb922..933e316 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -114,7 +114,7 @@ enum intel_platform {
> func(has_ipc);
>
> #define GEN_MAX_SLICES (6) /* CNL upper bound */
> -#define GEN_MAX_SUBSLICES (7)
> +#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
>
> struct sseu_dev_info {
> u8 slice_mask;
>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v4] drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection
2018-03-21 10:03 ` Tvrtko Ursulin
@ 2018-03-21 12:08 ` Mika Kuoppala
0 siblings, 0 replies; 9+ messages in thread
From: Mika Kuoppala @ 2018-03-21 12:08 UTC (permalink / raw)
To: Tvrtko Ursulin, Oscar Mateo, intel-gfx
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> writes:
> On 20/03/2018 19:45, Oscar Mateo wrote:
>> From: Kelvin Gardiner <kelvin.gardiner@intel.com>
>>
>> This patch adds support to detect ICL, slice, subslice and EU fuse
>> settings.
>>
>> Add addresses for ICL 11 slice, subslice and EU fuses registers.
>> These register addresses are the same as previous platforms but the
>> format and / or the meaning of the information is different. Therefore
>> Gen11 defines for these registers are added.
>>
>> Bspec: 9731
>> Bspec: 20643
>> Bspec: 20673
>>
>> v2: Update fusing information storage after introducing the new query
>> uAPI (Lionel)
>>
>> v3 (Oscar):
>> - The maximum number of slices in ICL 11 is 1
>> - The subslice disable fuse can potentially store information in
>> all bits
>> - GEN_MAX_SUBSLICES has to be increased to 8
>> - Don't trust the slice enabled fuse outside the max number of
>> expected slices
>> - Indentation fix and some reordering and renaming of local
>> variables
>>
>> v4: Use single space after Cc tag
>>
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Signed-off-by: Kelvin Gardiner <kelvin.gardiner@intel.com>
>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++
>> drivers/gpu/drm/i915/intel_device_info.c | 43 +++++++++++++++++++++++++++++++-
>> drivers/gpu/drm/i915/intel_device_info.h | 2 +-
>> 3 files changed, 51 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index dc41961..1f47806 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2554,6 +2554,14 @@ enum i915_power_well_id {
>> #define GEN11_GT_VEBOX_DISABLE_SHIFT 16
>> #define GEN11_GT_VEBOX_DISABLE_MASK (0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
>>
>> +#define GEN11_EU_DISABLE _MMIO(0x9134)
>> +#define GEN11_EU_DIS_MASK 0xFF
>> +
>> +#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
>> +#define GEN11_GT_S_ENA_MASK 0xFF
>> +
>> +#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
>> +
>> #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
>> #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
>> #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index 4babfc6..a504281 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -158,6 +158,45 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu)
>> return total;
>> }
>>
>> +static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
>> +{
>> + struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
>> + u8 s_en;
>> + u32 ss_en, ss_en_mask;
>> + u8 eu_en;
>> + int s;
>> +
>> + sseu->max_slices = 1;
>> + sseu->max_subslices = 8;
>> + sseu->max_eus_per_subslice = 8;
>> +
>> + s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
>> + ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
>> + ss_en_mask = BIT(sseu->max_subslices) - 1;
>> + eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
>> +
>> + for (s = 0; s < sseu->max_slices; s++) {
>> + if (s_en & BIT(s)) {
>> + int ss_idx = sseu->max_subslices * s;
>> + int ss;
>> +
>> + sseu->slice_mask |= BIT(s);
>> + sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask;
>> + for (ss = 0; ss < sseu->max_subslices; ss++) {
>> + if (sseu->subslice_mask[s] & BIT(ss))
>> + sseu_set_eus(sseu, s, ss, eu_en);
>> + }
>> + }
>> + }
>> + sseu->eu_per_subslice = hweight8(eu_en);
>> + sseu->eu_total = compute_eu_total(sseu);
>> +
>> + /* ICL has no power gating restrictions. */
>> + sseu->has_slice_pg = 1;
>> + sseu->has_subslice_pg = 1;
>> + sseu->has_eu_pg = 1;
>> +}
>> +
>> static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
>> {
>> struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
>> @@ -768,8 +807,10 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>> broadwell_sseu_info_init(dev_priv);
>> else if (INTEL_GEN(dev_priv) == 9)
>> gen9_sseu_info_init(dev_priv);
>> - else if (INTEL_GEN(dev_priv) >= 10)
>> + else if (INTEL_GEN(dev_priv) == 10)
>> gen10_sseu_info_init(dev_priv);
>> + else if (INTEL_INFO(dev_priv)->gen >= 11)
>
> INTEL_GEN(dev_priv) >= 11
I was too quick with this patch. Already pushed :O
Thanks for patch and review.
-Mika
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection
2018-03-20 18:37 [PATCH v3] drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection Oscar Mateo
2018-03-20 18:55 ` Lionel Landwerlin
@ 2018-03-20 19:08 ` Patchwork
2018-03-20 19:25 ` ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-03-20 19:08 UTC (permalink / raw)
To: Oscar Mateo; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection
URL : https://patchwork.freedesktop.org/series/40315/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f61c5df8f12d drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection
-:32: WARNING:BAD_SIGN_OFF: Use a single space after Cc:
#32:
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
total: 0 errors, 1 warnings, 0 checks, 78 lines checked
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection
2018-03-20 18:37 [PATCH v3] drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection Oscar Mateo
2018-03-20 18:55 ` Lionel Landwerlin
2018-03-20 19:08 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2018-03-20 19:25 ` Patchwork
2018-03-20 20:22 ` ✓ Fi.CI.BAT: success for drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection (rev2) Patchwork
2018-03-21 2:32 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-03-20 19:25 UTC (permalink / raw)
To: Oscar Mateo; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection
URL : https://patchwork.freedesktop.org/series/40315/
State : success
== Summary ==
Series 40315v1 drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection
https://patchwork.freedesktop.org/api/1.0/series/40315/revisions/1/mbox/
---- Possible new issues:
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS (fi-cfl-s2)
---- Known issues:
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass -> FAIL (fi-gdg-551) fdo#102575
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fi-bdw-5557u total:285 pass:264 dwarn:0 dfail:0 fail:0 skip:21 time:430s
fi-bdw-gvtdvm total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:441s
fi-blb-e6850 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:381s
fi-bsw-n3050 total:285 pass:239 dwarn:0 dfail:0 fail:0 skip:46 time:542s
fi-bwr-2160 total:285 pass:180 dwarn:0 dfail:0 fail:0 skip:105 time:296s
fi-bxt-dsi total:285 pass:255 dwarn:0 dfail:0 fail:0 skip:30 time:512s
fi-bxt-j4205 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:513s
fi-byt-j1900 total:285 pass:250 dwarn:0 dfail:0 fail:0 skip:35 time:518s
fi-byt-n2820 total:285 pass:246 dwarn:0 dfail:0 fail:0 skip:39 time:499s
fi-cfl-8700k total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:410s
fi-cfl-s2 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:581s
fi-cfl-u total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:509s
fi-cnl-drrs total:285 pass:254 dwarn:3 dfail:0 fail:0 skip:28 time:522s
fi-elk-e7500 total:285 pass:225 dwarn:1 dfail:0 fail:0 skip:59 time:426s
fi-gdg-551 total:285 pass:176 dwarn:0 dfail:0 fail:1 skip:108 time:319s
fi-glk-1 total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:538s
fi-hsw-4770 total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:404s
fi-ilk-650 total:285 pass:225 dwarn:0 dfail:0 fail:0 skip:60 time:421s
fi-ivb-3520m total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:470s
fi-ivb-3770 total:285 pass:252 dwarn:0 dfail:0 fail:0 skip:33 time:428s
fi-kbl-7500u total:285 pass:260 dwarn:1 dfail:0 fail:0 skip:24 time:474s
fi-kbl-7567u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:470s
fi-kbl-r total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:512s
fi-pnv-d510 total:285 pass:219 dwarn:1 dfail:0 fail:0 skip:65 time:661s
fi-skl-6260u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:441s
fi-skl-6600u total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:535s
fi-skl-6700hq total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:541s
fi-skl-6700k2 total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:507s
fi-skl-6770hq total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:508s
fi-skl-guc total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:429s
fi-snb-2520m total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:581s
fi-snb-2600 total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:401s
9d737cebc219c821989021a3115424165ff7b052 drm-tip: 2018y-03m-20d-14h-56m-05s UTC integration manifest
f61c5df8f12d drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8420/issues.html
_______________________________________________
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection (rev2)
2018-03-20 18:37 [PATCH v3] drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection Oscar Mateo
` (2 preceding siblings ...)
2018-03-20 19:25 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-03-20 20:22 ` Patchwork
2018-03-21 2:32 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-03-20 20:22 UTC (permalink / raw)
To: Oscar Mateo; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection (rev2)
URL : https://patchwork.freedesktop.org/series/40315/
State : success
== Summary ==
Series 40315v2 drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection
https://patchwork.freedesktop.org/api/1.0/series/40315/revisions/2/mbox/
---- Possible new issues:
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS (fi-cfl-s2)
---- Known issues:
Test debugfs_test:
Subgroup read_all_entries:
pass -> INCOMPLETE (fi-snb-2520m) fdo#103713
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:285 pass:264 dwarn:0 dfail:0 fail:0 skip:21 time:432s
fi-bdw-gvtdvm total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:442s
fi-blb-e6850 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:379s
fi-bsw-n3050 total:285 pass:239 dwarn:0 dfail:0 fail:0 skip:46 time:534s
fi-bwr-2160 total:285 pass:180 dwarn:0 dfail:0 fail:0 skip:105 time:298s
fi-bxt-dsi total:285 pass:255 dwarn:0 dfail:0 fail:0 skip:30 time:511s
fi-bxt-j4205 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:512s
fi-byt-j1900 total:285 pass:250 dwarn:0 dfail:0 fail:0 skip:35 time:518s
fi-byt-n2820 total:285 pass:246 dwarn:0 dfail:0 fail:0 skip:39 time:503s
fi-cfl-8700k total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:411s
fi-cfl-s2 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:580s
fi-cfl-u total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:511s
fi-cnl-drrs total:285 pass:254 dwarn:3 dfail:0 fail:0 skip:28 time:530s
fi-elk-e7500 total:285 pass:225 dwarn:1 dfail:0 fail:0 skip:59 time:428s
fi-gdg-551 total:285 pass:177 dwarn:0 dfail:0 fail:0 skip:108 time:317s
fi-glk-1 total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:539s
fi-hsw-4770 total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:403s
fi-ilk-650 total:285 pass:225 dwarn:0 dfail:0 fail:0 skip:60 time:415s
fi-ivb-3520m total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:467s
fi-ivb-3770 total:285 pass:252 dwarn:0 dfail:0 fail:0 skip:33 time:430s
fi-kbl-7500u total:285 pass:260 dwarn:1 dfail:0 fail:0 skip:24 time:482s
fi-kbl-7567u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:467s
fi-kbl-r total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:514s
fi-pnv-d510 total:285 pass:219 dwarn:1 dfail:0 fail:0 skip:65 time:656s
fi-skl-6260u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:439s
fi-skl-6600u total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:541s
fi-skl-6700hq total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:538s
fi-skl-6700k2 total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:497s
fi-skl-6770hq total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:489s
fi-skl-guc total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:431s
fi-snb-2520m total:3 pass:2 dwarn:0 dfail:0 fail:0 skip:0
fi-snb-2600 total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:402s
9d737cebc219c821989021a3115424165ff7b052 drm-tip: 2018y-03m-20d-14h-56m-05s UTC integration manifest
34e5dd440841 drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8422/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection (rev2)
2018-03-20 18:37 [PATCH v3] drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection Oscar Mateo
` (3 preceding siblings ...)
2018-03-20 20:22 ` ✓ Fi.CI.BAT: success for drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection (rev2) Patchwork
@ 2018-03-21 2:32 ` Patchwork
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-03-21 2:32 UTC (permalink / raw)
To: Oscar Mateo; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection (rev2)
URL : https://patchwork.freedesktop.org/series/40315/
State : success
== Summary ==
---- Known issues:
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
pass -> FAIL (shard-hsw) fdo#102887
Test kms_setmode:
Subgroup basic:
pass -> FAIL (shard-apl) fdo#99912
Test kms_vblank:
Subgroup pipe-b-ts-continuation-dpms-suspend:
incomplete -> PASS (shard-hsw) fdo#105054
Subgroup pipe-b-ts-continuation-suspend:
pass -> SKIP (shard-snb) fdo#105411
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#105054 https://bugs.freedesktop.org/show_bug.cgi?id=105054
fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
shard-apl total:3478 pass:1814 dwarn:1 dfail:0 fail:7 skip:1655 time:13003s
shard-hsw total:3478 pass:1767 dwarn:1 dfail:0 fail:2 skip:1707 time:11765s
shard-snb total:3478 pass:1357 dwarn:1 dfail:0 fail:2 skip:2118 time:7270s
Blacklisted hosts:
shard-kbl total:3478 pass:1936 dwarn:1 dfail:0 fail:10 skip:1531 time:9977s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8422/shards.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2018-03-21 12:08 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-03-20 18:37 [PATCH v3] drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection Oscar Mateo
2018-03-20 18:55 ` Lionel Landwerlin
2018-03-20 19:45 ` [PATCH v4] " Oscar Mateo
2018-03-21 10:03 ` Tvrtko Ursulin
2018-03-21 12:08 ` Mika Kuoppala
2018-03-20 19:08 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2018-03-20 19:25 ` ✓ Fi.CI.BAT: success " Patchwork
2018-03-20 20:22 ` ✓ Fi.CI.BAT: success for drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection (rev2) Patchwork
2018-03-21 2:32 ` ✓ Fi.CI.IGT: " Patchwork
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