From: "Tulio Magno Quites Machado Filho" <tuliom@linux.vnet.ibm.com>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
linuxppc-dev@lists.ozlabs.org
Cc: Steven Munroe <munroesj@linux.vnet.ibm.com>
Subject: Re: [PATCH 9/9] powerpc: A new cache shape aux vectors
Date: Wed, 04 Jan 2017 11:04:07 -0200 [thread overview]
Message-ID: <87lgurkmd4.fsf@linux.vnet.ibm.com> (raw)
In-Reply-To: <20170104051535.9454-9-benh@kernel.crashing.org>
Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:
> diff --git a/arch/powerpc/include/uapi/asm/auxvec.h b/arch/powerpc/include/uapi/asm/auxvec.h
> index ce17d2c..79183d2 100644
> --- a/arch/powerpc/include/uapi/asm/auxvec.h
> +++ b/arch/powerpc/include/uapi/asm/auxvec.h
> @@ -16,6 +16,37 @@
> */
> #define AT_SYSINFO_EHDR 33
>
> -#define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
> +/*
> + * AT_*CACHEBSIZE above represent the cache *block* size which is
> + * the size that is affected by the cache management instructions.
> + *
> + * It doesn't nececssarily matches the cache *line* size which is
> + * more of a performance tuning hint. Additionally the latter can
> + * be different for the different cache levels.
> + *
> + * The set of entries below represent more extensive information
> + * about the caches, in the form of two entry per cache type,
> + * one entry containing the cache size in bytes, and the other
> + * containing the cache line size in bytes in the bottom 16 bits
> + * and the cache associativity in the next 16 bits.
> + *
> + * The associativity is such that if N is the 16-bit value, the
> + * cache is N way set associative. A value if 0xffff means fully
> + * associative, a value of 1 means directly mapped.
> + *
> + * For all these fields, a value of 0 means that the information
> + * is not known.
> + */
> +
> +#define AT_L1I_CACHESIZE 40
> +#define AT_L1I_CACHESHAPE 41
> +#define AT_L1D_CACHESIZE 42
> +#define AT_L1D_CACHESHAPE 43
> +#define AT_L2_CACHESIZE 44
> +#define AT_L2_CACHESHAPE 45
> +#define AT_L3_CACHESIZE 46
> +#define AT_L3_CACHESHAPE 47
These names will clash with the other ones defined by alpha and sh:
/* Shapes of the caches. Bits 0-3 contains associativity; bits 4-7 contains
log2 of line size; mask those to get cache size. */
#define AT_L1I_CACHESHAPE 34
#define AT_L1D_CACHESHAPE 35
#define AT_L2_CACHESHAPE 36
#define AT_L3_CACHESHAPE 37
--
Tulio Magno
next prev parent reply other threads:[~2017-01-04 13:04 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-04 5:15 [PATCH 1/9] powerpc: Move ARCH_DLINFO out of uapi Benjamin Herrenschmidt
2017-01-04 5:15 ` [PATCH 2/9] powerpc: Move {d, i, u}cache_bsize definitions to a common place Benjamin Herrenschmidt
2017-01-04 5:15 ` [PATCH 3/9] powerpc: Remove obsolete comment about patching instructions Benjamin Herrenschmidt
2017-01-04 5:15 ` [PATCH 4/9] powerpc/64: Fix naming of cache block vs. cache line Benjamin Herrenschmidt
2017-01-04 5:15 ` [PATCH 5/9] powerpc/64: Retrieve number of L1 cache sets from device-tree Benjamin Herrenschmidt
2017-01-04 5:15 ` [PATCH 6/9] powerpc/64: Clean up ppc64_caches using a struct per cache Benjamin Herrenschmidt
2017-01-04 5:15 ` [PATCH 7/9] powerpc/64: Add L2 and L3 cache shape info Benjamin Herrenschmidt
2017-01-04 5:15 ` [PATCH 8/9] powerpc/64: Hard code cache geometry on POWER8 Benjamin Herrenschmidt
2017-01-04 5:15 ` [PATCH 9/9] powerpc: A new cache shape aux vectors Benjamin Herrenschmidt
2017-01-04 13:04 ` Tulio Magno Quites Machado Filho [this message]
2017-01-04 22:03 ` Benjamin Herrenschmidt
2017-01-05 11:15 ` Tulio Magno Quites Machado Filho
2017-01-10 13:15 ` Segher Boessenkool
2017-01-10 15:18 ` Benjamin Herrenschmidt
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