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From: Esben Haabendal <esben@geanix.com>
To: <sashiko-bot@kernel.org>
Cc: <sashiko-reviews@lists.linux.dev>,  <dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH v4 1/4] drm/bridge: nwl-dsi: Cleanup endpoint mux control selection
Date: Mon, 31 Aug 2026 17:13:47 +0200	[thread overview]
Message-ID: <87mru2uxuc.fsf@geanix.com> (raw)
In-Reply-To: <20260831133448.DB07A1F00A3E@smtp.kernel.org> (sashiko-bot@kernel.org's message of "Mon, 31 Aug 2026 13:34:48 +0000")

<sashiko-bot@kernel.org> writes:

> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
>
> Pre-existing issues:
> - [High] Dangling pointer to stack variable left in dsi->xfer after transfer completes or times out.

I will add a fix for this pre-existing issue to the next patch series I
have lined up for the nwl-dsi.c driver.

So let's try and get this one merged :)

/Esben

  reply	other threads:[~2026-08-31 15:13 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-31 13:27 [PATCH v4 0/4] drm/bridge: nwl-dsi: Various fixes Esben Haabendal
2026-08-31 13:27 ` [PATCH v4 1/4] drm/bridge: nwl-dsi: Cleanup endpoint mux control selection Esben Haabendal
2026-08-31 13:34   ` sashiko-bot
2026-08-31 15:13     ` Esben Haabendal [this message]
2026-08-31 13:27 ` [PATCH v4 2/4] drm/bridge: nwl-dsi: Limit LCDIF specific sync override Esben Haabendal
2026-08-31 13:27 ` [PATCH v4 3/4] drm/bridge: nwl-dsi: Correct auto-insert EOTP behavior Esben Haabendal
2026-08-31 13:27 ` [PATCH v4 4/4] drm/bridge: nwl-dsi: Correct MIPI DSI horizontal sync timing Esben Haabendal

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