[PATCH 0/3] Implement CMRR Support

[PATCH 0/3] Implement CMRR Support

[Mitul Golani]

CMRR is a display feature that uses adaptive sync
framework to vary Vtotal slightly to match the
content rate exactly without frame drops. This
feature is a variation of VRR where it varies Vtotal
slightly (between additional 0 and 1 Vtotal scanlines)
to match content rate exactly without frame drops
using the adaptive sync framework.

enable this feature by programing new registers for
CMRR enable, CMRR_M, CMRR_N, vmin=vmax=flipline.The
CMRR_M/CMRR_N ratio represents the fractional part
in (actual refresh rate/target refresh rate) * origVTotal.

--v6:
- CMRR handling in co-existatnce of LRR and DRRS
- Correct vtotal paramas accuracy and add 2 digit precision.

--v7:
- Rebased patches in-accordance to AS SDP merge.
- Add neccessary gaurd to prevent crtc_state mismatch
during intel_vrr_get_config.

Mitul Golani (3):
  drm/i915: Define and compute Transcoder CMRR registers
  drm/i915: Add Enable/Disable for CMRR based on VRR state
  drm/i915: Compute CMRR and calculate vtotal

 drivers/gpu/drm/i915/display/intel_display.c  |  61 ++++++-
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_types.h    |   6 +
 drivers/gpu/drm/i915/display/intel_vrr.c      | 153 +++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h               |  10 ++
 5 files changed, 201 insertions(+), 30 deletions(-)

-- 
2.25.1

[PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers

[Mitul Golani]

Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.

--v2:
- Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
- Fix indent and order based on register offset. [Jani]

--v3:
- Removing RFC tag.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 23 ++++++++++++++++++-
 .../drm/i915/display/intel_display_types.h    |  6 +++++
 drivers/gpu/drm/i915/display/intel_vrr.c      | 22 ++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h               | 10 ++++++++
 4 files changed, 60 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a92b67adee9c..c4f212e8177b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1000,6 +1000,13 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
 		old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
 }
 
+static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
+				const struct intel_crtc_state *new_crtc_state)
+{
+	return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
+		old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
+}
+
 static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
 			 const struct intel_crtc_state *new_crtc_state)
 {
@@ -5067,6 +5074,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	} \
 } while (0)
 
+#define PIPE_CONF_CHECK_LLI(name) do { \
+	if (current_config->name != pipe_config->name) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected %lli, found %lli)", \
+				     current_config->name, \
+				     pipe_config->name); \
+		ret = false; \
+	} \
+} while (0)
+
 #define PIPE_CONF_CHECK_BOOL(name) do { \
 	if (current_config->name != pipe_config->name) { \
 		BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
@@ -5431,10 +5448,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_I(vrr.guardband);
 		PIPE_CONF_CHECK_I(vrr.vsync_start);
 		PIPE_CONF_CHECK_I(vrr.vsync_end);
+		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
+		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
 	}
 
 #undef PIPE_CONF_CHECK_X
 #undef PIPE_CONF_CHECK_I
+#undef PIPE_CONF_CHECK_LLI
 #undef PIPE_CONF_CHECK_BOOL
 #undef PIPE_CONF_CHECK_P
 #undef PIPE_CONF_CHECK_FLAGS
@@ -6816,7 +6836,8 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state,
 		    intel_crtc_needs_fastset(new_crtc_state))
 			icl_set_pipe_chicken(new_crtc_state);
 
-		if (vrr_params_changed(old_crtc_state, new_crtc_state))
+		if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
+		    cmrr_params_changed(old_crtc_state, new_crtc_state))
 			intel_vrr_set_transcoder_timings(new_crtc_state);
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0f4bd5710796..2db714f3efa4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1437,6 +1437,12 @@ struct intel_crtc_state {
 		u32 vsync_end, vsync_start;
 	} vrr;
 
+	/* Content Match Refresh Rate state */
+	struct {
+		bool enable;
+		u64 cmrr_n, cmrr_m;
+	} cmrr;
+
 	/* Stream Splitter for eDP MSO */
 	struct {
 		bool enable;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 894ee97b3e1b..831554ea46b2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -217,6 +217,19 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 		return;
 	}
 
+	if (crtc_state->cmrr.enable) {
+		intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
+			       VRR_CTL_CMRR_ENABLE | trans_vrr_ctl(crtc_state));
+		intel_de_write(dev_priv, TRANS_CMRR_M_HI(cpu_transcoder),
+			       upper_32_bits(crtc_state->cmrr.cmrr_m));
+		intel_de_write(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder),
+			       lower_32_bits(crtc_state->cmrr.cmrr_m));
+		intel_de_write(dev_priv, TRANS_CMRR_N_HI(cpu_transcoder),
+			       upper_32_bits(crtc_state->cmrr.cmrr_n));
+		intel_de_write(dev_priv, TRANS_CMRR_N_LO(cpu_transcoder),
+			       lower_32_bits(crtc_state->cmrr.cmrr_n));
+	}
+
 	intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
 	intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
 	intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state));
@@ -296,6 +309,15 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 
 	crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
 
+	if (crtc_state->cmrr.enable) {
+		crtc_state->cmrr.cmrr_n =
+			intel_de_read64_2x32(dev_priv, TRANS_CMRR_N_LO(cpu_transcoder),
+					     TRANS_CMRR_N_HI(cpu_transcoder));
+		crtc_state->cmrr.cmrr_m =
+			intel_de_read64_2x32(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder),
+					     TRANS_CMRR_M_HI(cpu_transcoder));
+	}
+
 	if (DISPLAY_VER(dev_priv) >= 13)
 		crtc_state->vrr.guardband =
 			REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f34efcd7d6c..02a9c381c90b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2009,6 +2009,7 @@
 #define   VRR_CTL_VRR_ENABLE			REG_BIT(31)
 #define   VRR_CTL_IGN_MAX_SHIFT			REG_BIT(30)
 #define   VRR_CTL_FLIP_LINE_EN			REG_BIT(29)
+#define   VRR_CTL_CMRR_ENABLE			REG_BIT(27)
 #define   VRR_CTL_PIPELINE_FULL_MASK		REG_GENMASK(10, 3)
 #define   VRR_CTL_PIPELINE_FULL(x)		REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
 #define   VRR_CTL_PIPELINE_FULL_OVERRIDE	REG_BIT(0)
@@ -2085,6 +2086,15 @@
 #define TRANS_VRR_STATUS2(trans)	_MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
 #define   VRR_STATUS2_VERT_LN_CNT_MASK	REG_GENMASK(19, 0)
 
+#define	_TRANS_CMRR_M_LO_A		0x604F0
+#define	TRANS_CMRR_M_LO(trans)		_MMIO_TRANS2(trans, _TRANS_CMRR_M_LO_A)
+#define	_TRANS_CMRR_M_HI_A		0x604F4
+#define	TRANS_CMRR_M_HI(trans)		_MMIO_TRANS2(trans, _TRANS_CMRR_M_HI_A)
+#define	_TRANS_CMRR_N_LO_A		0x604F8
+#define	TRANS_CMRR_N_LO(trans)		_MMIO_TRANS2(trans, _TRANS_CMRR_N_LO_A)
+#define	_TRANS_CMRR_N_HI_A		0x604FC
+#define	TRANS_CMRR_N_HI(trans)		_MMIO_TRANS2(trans, _TRANS_CMRR_N_HI_A)
+
 #define _TRANS_PUSH_A			0x60A70
 #define _TRANS_PUSH_B			0x61A70
 #define _TRANS_PUSH_C			0x62A70
-- 
2.25.1

Re: [PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers

[Jani Nikula]

On Fri, 12 Apr 2024, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> Add register definitions for Transcoder Fixed Average
> Vtotal mode/CMRR function, with the necessary bitfields.
> Compute these registers when CMRR is enabled, extending
> Adaptive refresh rate capabilities.
>
> --v2:
> - Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
> - Fix indent and order based on register offset. [Jani]
>
> --v3:
> - Removing RFC tag.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 23 ++++++++++++++++++-
>  .../drm/i915/display/intel_display_types.h    |  6 +++++
>  drivers/gpu/drm/i915/display/intel_vrr.c      | 22 ++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h               | 10 ++++++++
>  4 files changed, 60 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a92b67adee9c..c4f212e8177b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1000,6 +1000,13 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
>  		old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
>  }
>  
> +static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
> +				const struct intel_crtc_state *new_crtc_state)
> +{
> +	return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
> +		old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
> +}
> +
>  static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
>  			 const struct intel_crtc_state *new_crtc_state)
>  {
> @@ -5067,6 +5074,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	} \
>  } while (0)
>  
> +#define PIPE_CONF_CHECK_LLI(name) do { \
> +	if (current_config->name != pipe_config->name) { \
> +		pipe_config_mismatch(fastset, crtc, __stringify(name), \
> +				     "(expected %lli, found %lli)", \
> +				     current_config->name, \
> +				     pipe_config->name); \
> +		ret = false; \
> +	} \
> +} while (0)
> +
>  #define PIPE_CONF_CHECK_BOOL(name) do { \
>  	if (current_config->name != pipe_config->name) { \
>  		BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
> @@ -5431,10 +5448,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  		PIPE_CONF_CHECK_I(vrr.guardband);
>  		PIPE_CONF_CHECK_I(vrr.vsync_start);
>  		PIPE_CONF_CHECK_I(vrr.vsync_end);
> +		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
> +		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
>  	}
>  
>  #undef PIPE_CONF_CHECK_X
>  #undef PIPE_CONF_CHECK_I
> +#undef PIPE_CONF_CHECK_LLI
>  #undef PIPE_CONF_CHECK_BOOL
>  #undef PIPE_CONF_CHECK_P
>  #undef PIPE_CONF_CHECK_FLAGS
> @@ -6816,7 +6836,8 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state,
>  		    intel_crtc_needs_fastset(new_crtc_state))
>  			icl_set_pipe_chicken(new_crtc_state);
>  
> -		if (vrr_params_changed(old_crtc_state, new_crtc_state))
> +		if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
> +		    cmrr_params_changed(old_crtc_state, new_crtc_state))
>  			intel_vrr_set_transcoder_timings(new_crtc_state);
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 0f4bd5710796..2db714f3efa4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1437,6 +1437,12 @@ struct intel_crtc_state {
>  		u32 vsync_end, vsync_start;
>  	} vrr;
>  
> +	/* Content Match Refresh Rate state */
> +	struct {
> +		bool enable;
> +		u64 cmrr_n, cmrr_m;
> +	} cmrr;
> +
>  	/* Stream Splitter for eDP MSO */
>  	struct {
>  		bool enable;
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 894ee97b3e1b..831554ea46b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -217,6 +217,19 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
>  		return;
>  	}
>  
> +	if (crtc_state->cmrr.enable) {
> +		intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
> +			       VRR_CTL_CMRR_ENABLE | trans_vrr_ctl(crtc_state));
> +		intel_de_write(dev_priv, TRANS_CMRR_M_HI(cpu_transcoder),
> +			       upper_32_bits(crtc_state->cmrr.cmrr_m));
> +		intel_de_write(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder),
> +			       lower_32_bits(crtc_state->cmrr.cmrr_m));
> +		intel_de_write(dev_priv, TRANS_CMRR_N_HI(cpu_transcoder),
> +			       upper_32_bits(crtc_state->cmrr.cmrr_n));
> +		intel_de_write(dev_priv, TRANS_CMRR_N_LO(cpu_transcoder),
> +			       lower_32_bits(crtc_state->cmrr.cmrr_n));
> +	}
> +
>  	intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
>  	intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
>  	intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state));
> @@ -296,6 +309,15 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>  
>  	crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
>  
> +	if (crtc_state->cmrr.enable) {
> +		crtc_state->cmrr.cmrr_n =
> +			intel_de_read64_2x32(dev_priv, TRANS_CMRR_N_LO(cpu_transcoder),
> +					     TRANS_CMRR_N_HI(cpu_transcoder));
> +		crtc_state->cmrr.cmrr_m =
> +			intel_de_read64_2x32(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder),
> +					     TRANS_CMRR_M_HI(cpu_transcoder));
> +	}
> +
>  	if (DISPLAY_VER(dev_priv) >= 13)
>  		crtc_state->vrr.guardband =
>  			REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3f34efcd7d6c..02a9c381c90b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2009,6 +2009,7 @@
>  #define   VRR_CTL_VRR_ENABLE			REG_BIT(31)
>  #define   VRR_CTL_IGN_MAX_SHIFT			REG_BIT(30)
>  #define   VRR_CTL_FLIP_LINE_EN			REG_BIT(29)
> +#define   VRR_CTL_CMRR_ENABLE			REG_BIT(27)
>  #define   VRR_CTL_PIPELINE_FULL_MASK		REG_GENMASK(10, 3)
>  #define   VRR_CTL_PIPELINE_FULL(x)		REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
>  #define   VRR_CTL_PIPELINE_FULL_OVERRIDE	REG_BIT(0)
> @@ -2085,6 +2086,15 @@
>  #define TRANS_VRR_STATUS2(trans)	_MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
>  #define   VRR_STATUS2_VERT_LN_CNT_MASK	REG_GENMASK(19, 0)
>  
> +#define	_TRANS_CMRR_M_LO_A		0x604F0
> +#define	TRANS_CMRR_M_LO(trans)		_MMIO_TRANS2(trans, _TRANS_CMRR_M_LO_A)
> +#define	_TRANS_CMRR_M_HI_A		0x604F4
> +#define	TRANS_CMRR_M_HI(trans)		_MMIO_TRANS2(trans, _TRANS_CMRR_M_HI_A)
> +#define	_TRANS_CMRR_N_LO_A		0x604F8
> +#define	TRANS_CMRR_N_LO(trans)		_MMIO_TRANS2(trans, _TRANS_CMRR_N_LO_A)
> +#define	_TRANS_CMRR_N_HI_A		0x604FC
> +#define	TRANS_CMRR_N_HI(trans)		_MMIO_TRANS2(trans, _TRANS_CMRR_N_HI_A)
> +

Please look around the code you're changing, and please look at the big
comment block near the top of i915_reg.h (this file).

>  #define _TRANS_PUSH_A			0x60A70
>  #define _TRANS_PUSH_B			0x61A70
>  #define _TRANS_PUSH_C			0x62A70

-- 
Jani Nikula, Intel

[PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state

[Mitul Golani]

Add CMRR/Fixed Average Vtotal mode enable and disable
functions based on change in VRR mode of operation.
When Adaptive Sync Vtotal is enabled, Fixed Average Vtotal
mode is disabled and vice versa. With this commit setting
the stage for subsequent CMRR enablement.

--v2:
- Check pipe active state in cmrr enabling. [Jani]
- Remove usage of bitwise OR on booleans. [Jani]
- Revert unrelated changes. [Jani]
- Update intel_vrr_enable, vrr and cmrr enable conditions. [Jani]
- Simplify whole if-ladder in intel_vrr_enable. [Jani]
- Revert patch restructuring mistakes in intel_vrr_get_config. [Jani]

--v3:
- Check pipe active state in cmrr disabling.[Jani]
- Correct messed up condition in intel_vrr_enable. [Jani]

--v4:
- Removing RFC tag.

--v5:
- CMRR handling in co-existatnce of LRR and DRRS.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 37 +++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_vrr.c     | 34 +++++++++++-------
 2 files changed, 54 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c4f212e8177b..78d7d2505c15 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1019,6 +1019,18 @@ static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
 		  vrr_params_changed(old_crtc_state, new_crtc_state)));
 }
 
+static bool cmrr_enabling(const struct intel_crtc_state *old_crtc_state,
+			  const struct intel_crtc_state *new_crtc_state)
+{
+	if (!new_crtc_state->hw.active)
+		return false;
+
+	return is_enabling(cmrr.enable, old_crtc_state, new_crtc_state) ||
+		(new_crtc_state->cmrr.enable &&
+		 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
+		  cmrr_params_changed(old_crtc_state, new_crtc_state)));
+}
+
 static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
 			  const struct intel_crtc_state *new_crtc_state)
 {
@@ -1031,6 +1043,18 @@ static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
 		  vrr_params_changed(old_crtc_state, new_crtc_state)));
 }
 
+static bool cmrr_disabling(const struct intel_crtc_state *old_crtc_state,
+			   const struct intel_crtc_state *new_crtc_state)
+{
+	if (!old_crtc_state->hw.active)
+		return false;
+
+	return is_disabling(cmrr.enable, old_crtc_state, new_crtc_state) ||
+		(old_crtc_state->cmrr.enable &&
+		 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
+		  cmrr_params_changed(old_crtc_state, new_crtc_state)));
+}
+
 static bool audio_enabling(const struct intel_crtc_state *old_crtc_state,
 			   const struct intel_crtc_state *new_crtc_state)
 {
@@ -1052,7 +1076,6 @@ static bool audio_disabling(const struct intel_crtc_state *old_crtc_state,
 		(old_crtc_state->has_audio &&
 		 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);
 }
-
 #undef is_disabling
 #undef is_enabling
 
@@ -1174,7 +1197,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	enum pipe pipe = crtc->pipe;
 
-	if (vrr_disabling(old_crtc_state, new_crtc_state)) {
+	if (vrr_disabling(old_crtc_state, new_crtc_state) ||
+	    cmrr_disabling(old_crtc_state, new_crtc_state)) {
 		intel_vrr_disable(old_crtc_state);
 		intel_crtc_update_active_timings(old_crtc_state, false);
 	}
@@ -6776,7 +6800,8 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
 	    !intel_crtc_needs_modeset(new_crtc_state))
 		skl_detach_scalers(new_crtc_state);
 
-	if (vrr_enabling(old_crtc_state, new_crtc_state))
+	if (vrr_enabling(old_crtc_state, new_crtc_state) ||
+	    cmrr_enabling(old_crtc_state, new_crtc_state))
 		intel_vrr_enable(new_crtc_state);
 }
 
@@ -6877,9 +6902,11 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 	 * FIXME Should be synchronized with the start of vblank somehow...
 	 */
 	if (vrr_enabling(old_crtc_state, new_crtc_state) ||
-	    new_crtc_state->update_m_n || new_crtc_state->update_lrr)
+	    new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
+	    cmrr_enabling(old_crtc_state, new_crtc_state))
 		intel_crtc_update_active_timings(new_crtc_state,
-						 new_crtc_state->vrr.enable);
+						 new_crtc_state->vrr.enable ||
+						 new_crtc_state->cmrr.enable);
 
 	/*
 	 * We usually enable FIFO underrun interrupts as part of the
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 831554ea46b2..369769e46c8d 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -242,7 +242,7 @@ void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
-	if (!crtc_state->vrr.enable)
+	if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable))
 		return;
 
 	intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder),
@@ -255,7 +255,7 @@ bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
-	if (!crtc_state->vrr.enable)
+	if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable))
 		return false;
 
 	return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND;
@@ -266,18 +266,28 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
-	if (!crtc_state->vrr.enable)
+	if (drm_WARN_ON(&dev_priv->drm, crtc_state->vrr.enable &&
+			crtc_state->cmrr.enable))
 		return;
 
-	intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN);
-
-	if (HAS_AS_SDP(dev_priv))
-		intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder),
+	if (crtc_state->vrr.enable) {
+		intel_de_write(dev_priv,
+			       TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN);
+		if (HAS_AS_SDP(dev_priv))
+			intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder),
 			       VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
 			       VRR_VSYNC_START(crtc_state->vrr.vsync_start));
+		intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
+			       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+	}
 
-	intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
-		       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+	if (crtc_state->cmrr.enable) {
+		intel_de_write(dev_priv,
+			       TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN);
+		intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
+			       VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
+			       trans_vrr_ctl(crtc_state));
+	}
 }
 
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@@ -286,7 +296,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 
-	if (!old_crtc_state->vrr.enable)
+	if (!(old_crtc_state->vrr.enable || old_crtc_state->cmrr.enable))
 		return;
 
 	intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
@@ -332,10 +342,10 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 		crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1;
 	}
 
-	if (crtc_state->vrr.enable) {
+	if (crtc_state->vrr.enable || crtc_state->cmrr.enable)
 		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 
-		if (HAS_AS_SDP(dev_priv)) {
+		if (HAS_AS_SDP(dev_priv) && crtc_state->vrr.enable) {
 			trans_vrr_vsync =
 				intel_de_read(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder));
 			crtc_state->vrr.vsync_start =
-- 
2.25.1

[PATCH 3/3] drm/i915: Compute CMRR and calculate vtotal

[Mitul Golani]

Compute Fixed Average Vtotal/CMRR with resepect to
userspace VRR enablement. Also calculate required
parameters in case of CMRR is  enabled. During
intel_vrr_compute_config, CMRR is getting enabled
based on userspace has enabled Adaptive Sync Vtotal
mode (Legacy VRR) or not.

--v2:
- Update is_cmrr_frac_required function return as bool, not int. [Jani]
- Use signed int math instead of unsigned in cmrr_get_vtotal2. [Jani]
- Fix typo and usage of camel case in cmrr_get_vtotal. [Jani]
- Use do_div in cmrr_get_vtotalwhile calculating cmrr_m. [ Jani]
- Simplify cmrr and vrr compute config in intel_vrr_compute_config. [Jani]
- Correct valiable name usage in is_cmrr_frac_required. [Ville]

--v3:
- Removing RFC tag.

--v4:
- Added edp check to address edp usecase for now. (ville)
- Updated is_cmrr_fraction_required to more simplified calculation.
- on longterm goal to be worked upon uapi as suggestion from ville.

--v5:
- Correct vtotal paramas accuracy and add 2 digit precision.
- Avoid using DIV_ROUND_UP and improve scanline precision.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |  1 +
 .../drm/i915/display/intel_display_device.h   |  1 +
 drivers/gpu/drm/i915/display/intel_vrr.c      | 97 ++++++++++++++++---
 3 files changed, 87 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 78d7d2505c15..15b9c5815c34 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5474,6 +5474,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_I(vrr.vsync_end);
 		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
 		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
+		PIPE_CONF_CHECK_BOOL(cmrr.enable);
 	}
 
 #undef PIPE_CONF_CHECK_X
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 66b51de86e38..97d9ccd169ae 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -70,6 +70,7 @@ struct drm_printer;
 					  BIT(trans)) != 0)
 #define HAS_VRR(i915)			(DISPLAY_VER(i915) >= 11)
 #define HAS_AS_SDP(i915)		(DISPLAY_VER(i915) >= 13)
+#define HAS_CMRR(i915)			(DISPLAY_VER(i915) >= 20)
 #define INTEL_NUM_PIPES(i915)		(hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
 #define I915_HAS_HOTPLUG(i915)		(DISPLAY_INFO(i915)->has_hotplug)
 #define OVERLAY_NEEDS_PHYSICAL(i915)	(DISPLAY_INFO(i915)->overlay_needs_physical)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 369769e46c8d..546a689dd4fb 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -11,6 +11,9 @@
 #include "intel_vrr.h"
 #include "intel_dp.h"
 
+#define FIXED_POINT_PRECISION		100
+#define CMRR_PRECISION_TOLERANCE	10
+
 bool intel_vrr_is_capable(struct intel_connector *connector)
 {
 	const struct drm_display_info *info = &connector->base.display_info;
@@ -106,6 +109,57 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
 	return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state);
 }
 
+static bool
+is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
+{
+	int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
+	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+
+	actual_refresh_k =
+		drm_mode_vrefresh(adjusted_mode) * FIXED_POINT_PRECISION;
+	pixel_clock_per_line =
+		adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal;
+	calculated_refresh_k =
+		pixel_clock_per_line * FIXED_POINT_PRECISION / adjusted_mode->crtc_vtotal;
+
+	if ((actual_refresh_k - calculated_refresh_k) < CMRR_PRECISION_TOLERANCE)
+		return false;
+
+	return true;
+}
+
+static unsigned int
+cmrr_get_vtotal(struct intel_crtc_state *crtc_state)
+{
+	int multiplier_m = 1, multiplier_n = 1, vtotal;
+	int actual_refresh_rate, desired_refresh_rate;
+	long long actual_pixel_rate, adjusted_pixel_rate, pixel_clock_per_line;
+	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+
+	pixel_clock_per_line =
+		adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal;
+	actual_refresh_rate =
+		pixel_clock_per_line * FIXED_POINT_PRECISION / adjusted_mode->crtc_vtotal;
+	desired_refresh_rate = drm_mode_vrefresh(adjusted_mode);
+	actual_pixel_rate = actual_refresh_rate * adjusted_mode->crtc_vtotal;
+	actual_pixel_rate =
+		(actual_pixel_rate * adjusted_mode->crtc_htotal) / FIXED_POINT_PRECISION;
+
+	if (is_cmrr_frac_required(crtc_state)) {
+		multiplier_m = 1001;
+		multiplier_n = 1000;
+	}
+
+	crtc_state->cmrr.cmrr_n =
+		((desired_refresh_rate * adjusted_mode->crtc_htotal * multiplier_n) / multiplier_m);
+	crtc_state->cmrr.cmrr_n *= multiplier_n;
+	vtotal = (actual_pixel_rate * multiplier_n) / crtc_state->cmrr.cmrr_n;
+	adjusted_pixel_rate = actual_pixel_rate * multiplier_m;
+	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
+
+	return vtotal;
+}
+
 void
 intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 			 struct drm_connector_state *conn_state)
@@ -115,6 +169,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
+	bool is_edp = intel_dp_is_edp(intel_dp);
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	const struct drm_display_info *info = &connector->base.display_info;
 	int vmin, vmax;
@@ -159,18 +214,10 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
 
 	/*
-	 * For XE_LPD+, we use guardband and pipeline override
-	 * is deprecated.
+	 * When panel is VRR capable and userspace has
+	 * not enabled adaptive sync mode then Fixed Average
+	 * Vtotal mode should be enabled.
 	 */
-	if (DISPLAY_VER(i915) >= 13) {
-		crtc_state->vrr.guardband =
-			crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start;
-	} else {
-		crtc_state->vrr.pipeline_full =
-			min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
-			    crtc_state->framestart_delay - 1);
-	}
-
 	if (crtc_state->uapi.vrr_enabled) {
 		crtc_state->vrr.enable = true;
 		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
@@ -182,6 +229,25 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 				(crtc_state->hw.adjusted_mode.crtc_vtotal -
 					crtc_state->hw.adjusted_mode.vsync_end);
 		}
+	} else if (HAS_CMRR(i915) && is_edp) {
+		crtc_state->cmrr.enable = true;
+		crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state);
+		crtc_state->vrr.vmin = crtc_state->vrr.vmax;
+		crtc_state->vrr.flipline = crtc_state->vrr.vmin;
+		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+	}
+
+	/*
+	 * For XE_LPD+, we use guardband and pipeline override
+	 * is deprecated.
+	 */
+	if (DISPLAY_VER(i915) >= 13) {
+		crtc_state->vrr.guardband =
+			crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start;
+	} else {
+		crtc_state->vrr.pipeline_full =
+			min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
+			    crtc_state->framestart_delay - 1);
 	}
 }
 
@@ -317,7 +383,14 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 
 	trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
 
-	crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
+	if (HAS_CMRR(dev_priv)) {
+		crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE) &&
+					  (trans_vrr_ctl & VRR_CTL_VRR_ENABLE);
+		crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE &&
+					 !(trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
+	} else {
+		crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
+	}
 
 	if (crtc_state->cmrr.enable) {
 		crtc_state->cmrr.cmrr_n =
-- 
2.25.1

✗ Fi.CI.BUILD: failure for Implement CMRR Support (rev7)

[Patchwork]

== Series Details ==

Series: Implement CMRR Support (rev7)
URL   : https://patchwork.freedesktop.org/series/126443/
State : failure

== Summary ==

Error: make failed
  CALL    scripts/checksyscalls.sh
  DESCEND objtool
  INSTALL libsubcmd_headers
  CC [M]  drivers/gpu/drm/i915/display/intel_display.o
drivers/gpu/drm/i915/display/intel_display.c: In function ‘intel_pipe_config_compare’:
drivers/gpu/drm/i915/display/intel_display.c:5103:24: error: incompatible type for argument 1 of ‘pipe_config_mismatch’
 5103 |   pipe_config_mismatch(fastset, crtc, __stringify(name), \
      |                        ^~~~~~~
      |                        |
      |                        bool {aka _Bool}
drivers/gpu/drm/i915/display/intel_display.c:5103:24: note: in definition of macro ‘PIPE_CONF_CHECK_LLI’
 5103 |   pipe_config_mismatch(fastset, crtc, __stringify(name), \
      |                        ^~~~~~~
drivers/gpu/drm/i915/display/intel_display.c:4904:42: note: expected ‘struct drm_printer *’ but argument is of type ‘bool’ {aka ‘_Bool’}
 4904 | pipe_config_mismatch(struct drm_printer *p, bool fastset,
      |                      ~~~~~~~~~~~~~~~~~~~~^
In file included from ./include/linux/linkage.h:6,
                 from ./arch/x86/include/asm/cache.h:5,
                 from ./include/linux/cache.h:6,
                 from ./arch/x86/include/asm/current.h:10,
                 from ./include/linux/mutex.h:14,
                 from ./include/linux/ww_mutex.h:20,
                 from ./include/linux/dma-resv.h:42,
                 from drivers/gpu/drm/i915/display/intel_display.c:27:
drivers/gpu/drm/i915/display/intel_display.c:5475:34: error: passing argument 3 of ‘pipe_config_mismatch’ from incompatible pointer type [-Werror=incompatible-pointer-types]
 5475 |   PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
      |                                  ^
      |                                  |
      |                                  char *
./include/linux/stringify.h:9:30: note: in definition of macro ‘__stringify_1’
    9 | #define __stringify_1(x...) #x
      |                              ^
drivers/gpu/drm/i915/display/intel_display.c:5103:39: note: in expansion of macro ‘__stringify’
 5103 |   pipe_config_mismatch(fastset, crtc, __stringify(name), \
      |                                       ^~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_display.c:5475:3: note: in expansion of macro ‘PIPE_CONF_CHECK_LLI’
 5475 |   PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
      |   ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_display.c:4905:33: note: expected ‘const struct intel_crtc *’ but argument is of type ‘char *’
 4905 |        const struct intel_crtc *crtc,
      |        ~~~~~~~~~~~~~~~~~~~~~~~~~^~~~
drivers/gpu/drm/i915/display/intel_display.c:5475:27: error: passing argument 5 of ‘pipe_config_mismatch’ makes pointer from integer without a cast [-Werror=int-conversion]
 5105 |          current_config->name, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~
 5106 |          pipe_config->name); \
      |          ~~~~~~~~~~~~~~~~~~~~~
 5107 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5108 |  } \
      |  ~~~                       
 5109 | } while (0)
      | ~~~~~~~~~~~                
 5110 | 
      |                            
 5111 | #define PIPE_CONF_CHECK_BOOL(name) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5112 |  if (current_config->name != pipe_config->name) { \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5113 |   BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5114 |      __stringify(name) " is not bool"); \
      |      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5115 |   pipe_config_mismatch(&p, fastset, crtc,  __stringify(name), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5116 |          "(expected %s, found %s)", \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5117 |          str_yes_no(current_config->name), \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5118 |          str_yes_no(pipe_config->name)); \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5119 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5120 |  } \
      |  ~~~                       
 5121 | } while (0)
      | ~~~~~~~~~~~                
 5122 | 
      |                            
 5123 | #define PIPE_CONF_CHECK_P(name) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5124 |  if (current_config->name != pipe_config->name) { \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5125 |   pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5126 |          "(expected %p, found %p)", \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5127 |          current_config->name, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~
 5128 |          pipe_config->name); \
      |          ~~~~~~~~~~~~~~~~~~~~~
 5129 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5130 |  } \
      |  ~~~                       
 5131 | } while (0)
      | ~~~~~~~~~~~                
 5132 | 
      |                            
 5133 | #define PIPE_CONF_CHECK_M_N(name) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5134 |  if (!intel_compare_link_m_n(&current_config->name, \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5135 |         &pipe_config->name)) { \
      |         ~~~~~~~~~~~~~~~~~~~~~~~~
 5136 |   pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5137 |          "(expected tu %i data %i/%i link %i/%i, " \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5138 |          "found tu %i, data %i/%i link %i/%i)", \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5139 |          current_config->name.tu, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~
 5140 |          current_config->name.data_m, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5141 |          current_config->name.data_n, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5142 |          current_config->name.link_m, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5143 |          current_config->name.link_n, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5144 |          pipe_config->name.tu, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~
 5145 |          pipe_config->name.data_m, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5146 |          pipe_config->name.data_n, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5147 |          pipe_config->name.link_m, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5148 |          pipe_config->name.link_n); \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5149 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5150 |  } \
      |  ~~~                       
 5151 | } while (0)
      | ~~~~~~~~~~~                
 5152 | 
      |                            
 5153 | #define PIPE_CONF_CHECK_PLL(name) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5154 |  if (!intel_dpll_compare_hw_state(dev_priv, &current_config->name, \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5155 |       &pipe_config->name)) { \
      |       ~~~~~~~~~~~~~~~~~~~~~~~~
 5156 |   pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5157 |       &current_config->name, \
      |       ~~~~~~~~~~~~~~~~~~~~~~~~
 5158 |       &pipe_config->name); \
      |       ~~~~~~~~~~~~~~~~~~~~~~
 5159 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5160 |  } \
      |  ~~~                       
 5161 | } while (0)
      | ~~~~~~~~~~~                
 5162 | 
      |                            
 5163 | #define PIPE_CONF_CHECK_TIMINGS(name) do {     \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5164 |  PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5165 |  PIPE_CONF_CHECK_I(name.crtc_htotal); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5166 |  PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5167 |  PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5168 |  PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5169 |  PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5170 |  PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5171 |  PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5172 |  PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5173 |  PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5174 |  if (!fastset || !pipe_config->update_lrr) { \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5175 |   PIPE_CONF_CHECK_I(name.crtc_vtotal); \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5176 |   PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5177 |  } \
      |  ~~~                       
 5178 | } while (0)
      | ~~~~~~~~~~~                
 5179 | 
      |                            
 5180 | #define PIPE_CONF_CHECK_RECT(name) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5181 |  PIPE_CONF_CHECK_I(name.x1); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5182 |  PIPE_CONF_CHECK_I(name.x2); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5183 |  PIPE_CONF_CHECK_I(name.y1); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5184 |  PIPE_CONF_CHECK_I(name.y2); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5185 | } while (0)
      | ~~~~~~~~~~~                
 5186 | 
      |                            
 5187 | #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5188 |  if ((current_config->name ^ pipe_config->name) & (mask)) { \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5189 |   pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5190 |          "(%x) (expected %i, found %i)", \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5191 |          (mask), \
      |          ~~~~~~~~~         
 5192 |          current_config->name & (mask), \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5193 |          pipe_config->name & (mask)); \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5194 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5195 |  } \
      |  ~~~                       
 5196 | } while (0)
      | ~~~~~~~~~~~                
 5197 | 
      |                            
 5198 | #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5199 |  if (!intel_compare_infoframe(&current_config->infoframes.name, \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5200 |          &pipe_config->infoframes.name)) { \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5201 |   pipe_config_infoframe_mismatch(&p, fastset, crtc, __stringify(name), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5202 |             &current_config->infoframes.name, \
      |             ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5203 |             &pipe_config->infoframes.name); \
      |             ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5204 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5205 |  } \
      |  ~~~                       
 5206 | } while (0)
      | ~~~~~~~~~~~                
 5207 | 
      |                            
 5208 | #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5209 |  if (!intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5210 |           &pipe_config->infoframes.name)) { \
      |           ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5211 |   pipe_config_dp_vsc_sdp_mismatch(&p, fastset, crtc, __stringify(name), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5212 |       &current_config->infoframes.name, \
      |       ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5213 |       &pipe_config->infoframes.name); \
      |       ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5214 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5215 |  } \
      |  ~~~                       
 5216 | } while (0)
      | ~~~~~~~~~~~                
 5217 | 
      |                            
 5218 | #define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5219 |  if (!intel_compare_dp_as_sdp(&current_config->infoframes.name, \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5220 |           &pipe_config->infoframes.name)) { \
      |           ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5221 |   pipe_config_dp_as_sdp_mismatch(dev_priv, fastset, __stringify(name), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5222 |       &current_config->infoframes.name, \
      |       ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5223 |       &pipe_config->infoframes.name); \
      |       ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5224 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5225 |  } \
      |  ~~~                       
 5226 | } while (0)
      | ~~~~~~~~~~~                
 5227 | 
      |                            
 5228 | #define PIPE_CONF_CHECK_BUFFER(name, len) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5229 |  BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5230 |  BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5231 |  if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5232 |   pipe_config_buffer_mismatch(&p, fastset, crtc, __stringify(name), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5233 |          current_config->name, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~
 5234 |          pipe_config->name, \
      |          ~~~~~~~~~~~~~~~~~~~~
 5235 |          (len)); \
      |          ~~~~~~~~~         
 5236 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5237 |  } \
      |  ~~~                       
 5238 | } while (0)
      | ~~~~~~~~~~~                
 5239 | 
      |                            
 5240 | #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5241 |  if (current_config->gamma_mode == pipe_config->gamma_mode && \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5242 |      !intel_color_lut_equal(current_config, \
      |      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5243 |        current_config->lut, pipe_config->lut, \
      |        ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5244 |        is_pre_csc_lut)) { \
      |        ~~~~~~~~~~~~~~~~~~~~
 5245 |   pipe_config_mismatch(&p, fastset, crtc, __stringify(lut), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5246 |          "hw_state doesn't match sw_state"); \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5247 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5248 |  } \
      |  ~~~                       
 5249 | } while (0)
      | ~~~~~~~~~~~                
 5250 | 
      |                            
 5251 | #define PIPE_CONF_CHECK_CSC(name) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5252 |  PIPE_CONF_CHECK_X(name.preoff[0]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5253 |  PIPE_CONF_CHECK_X(name.preoff[1]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5254 |  PIPE_CONF_CHECK_X(name.preoff[2]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5255 |  PIPE_CONF_CHECK_X(name.coeff[0]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5256 |  PIPE_CONF_CHECK_X(name.coeff[1]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5257 |  PIPE_CONF_CHECK_X(name.coeff[2]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5258 |  PIPE_CONF_CHECK_X(name.coeff[3]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5259 |  PIPE_CONF_CHECK_X(name.coeff[4]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5260 |  PIPE_CONF_CHECK_X(name.coeff[5]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5261 |  PIPE_CONF_CHECK_X(name.coeff[6]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5262 |  PIPE_CONF_CHECK_X(name.coeff[7]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5263 |  PIPE_CONF_CHECK_X(name.coeff[8]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5264 |  PIPE_CONF_CHECK_X(name.postoff[0]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5265 |  PIPE_CONF_CHECK_X(name.postoff[1]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5266 |  PIPE_CONF_CHECK_X(name.postoff[2]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5267 | } while (0)
      | ~~~~~~~~~~~                
 5268 | 
      |                            
 5269 | #define PIPE_CONF_QUIRK(quirk) \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5270 |  ((current_config->quirks | pipe_config->quirks) & (quirk))
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5271 | 
      |                            
 5272 |  PIPE_CONF_CHECK_BOOL(hw.enable);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5273 |  PIPE_CONF_CHECK_BOOL(hw.active);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5274 | 
      |                            
 5275 |  PIPE_CONF_CHECK_I(cpu_transcoder);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5276 |  PIPE_CONF_CHECK_I(mst_master_transcoder);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5277 | 
      |                            
 5278 |  PIPE_CONF_CHECK_BOOL(has_pch_encoder);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5279 |  PIPE_CONF_CHECK_I(fdi_lanes);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5280 |  PIPE_CONF_CHECK_M_N(fdi_m_n);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5281 | 
      |                            
 5282 |  PIPE_CONF_CHECK_I(lane_count);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5283 |  PIPE_CONF_CHECK_X(lane_lat_optim_mask);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5284 | 
      |                            
 5285 |  if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5286 |   if (!fastset || !pipe_config->update_m_n)
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5287 |    PIPE_CONF_CHECK_M_N(dp_m_n);
      |    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5288 |  } else {
      |  ~~~~~~~~                  
 5289 |   PIPE_CONF_CHECK_M_N(dp_m_n);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5290 |   PIPE_CONF_CHECK_M_N(dp_m2_n2);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5291 |  }
      |  ~                         
 5292 | 
      |                            
 5293 |  PIPE_CONF_CHECK_X(output_types);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5294 | 
      |                            
 5295 |  PIPE_CONF_CHECK_I(framestart_delay);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5296 |  PIPE_CONF_CHECK_I(msa_timing_delay);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5297 | 
      |                            
 5298 |  PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5299 |  PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5300 | 
      |                            
 5301 |  PIPE_CONF_CHECK_I(pixel_multiplier);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5302 | 
      |                            
 5303 |  PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5304 |          DRM_MODE_FLAG_INTERLACE);
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~
 5305 | 
      |                            
 5306 |  if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5307 |   PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5308 |           DRM_MODE_FLAG_PHSYNC);
      |           ~~~~~~~~~~~~~~~~~~~~~~
 5309 |   PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5310 |           DRM_MODE_FLAG_NHSYNC);
      |           ~~~~~~~~~~~~~~~~~~~~~~
 5311 |   PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5312 |           DRM_MODE_FLAG_PVSYNC);
      |           ~~~~~~~~~~~~~~~~~~~~~~
 5313 |   PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5314 |           DRM_MODE_FLAG_NVSYNC);
      |           ~~~~~~~~~~~~~~~~~~~~~~
 5315 |  }
      |  ~                         
 5316 | 
      |                            
 5317 |  PIPE_CONF_CHECK_I(output_format);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5318 |  PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5319 |  if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5320 |      IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
      |      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5321 |   PIPE_CONF_CHECK_BOOL(limited_color_range);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5322 | 
      |                            
 5323 |  PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5324 |  PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5325 |  PIPE_CONF_CHECK_BOOL(has_infoframe);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5326 |  PIPE_CONF_CHECK_BOOL(enhanced_framing);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5327 |  PIPE_CONF_CHECK_BOOL(fec_enable);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5328 | 
      |                            
 5329 |  if (!fastset) {
      |  ~~~~~~~~~~~~~~~           
 5330 |   PIPE_CONF_CHECK_BOOL(has_audio);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5331 |   PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5332 |  }
      |  ~                         
 5333 | 
      |                            
 5334 |  PIPE_CONF_CHECK_X(gmch_pfit.control);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5335 |  /* pfit ratios are autocomputed by the hw on gen4+ */
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5336 |  if (DISPLAY_VER(dev_priv) < 4)
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5337 |   PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5338 |  PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5339 | 
      |                            
 5340 |  /*
      |  ~~                        
 5341 |   * Changing the EDP transcoder input mux
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5342 |   * (A_ONOFF vs. A_ON) requires a full modeset.
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5343 |   */
      |   ~~                       
 5344 |  PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5345 | 
      |                            
 5346 |  if (!fastset) {
      |  ~~~~~~~~~~~~~~~           
 5347 |   PIPE_CONF_CHECK_RECT(pipe_src);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5348 | 
      |                            
 5349 |   PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5350 |   PIPE_CONF_CHECK_RECT(pch_pfit.dst);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5351 | 
      |                            
 5352 |   PIPE_CONF_CHECK_I(scaler_state.scaler_id);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5353 |   PIPE_CONF_CHECK_I(pixel_rate);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5354 | 
      |                            
 5355 |   PIPE_CONF_CHECK_X(gamma_mode);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5356 |   if (IS_CHERRYVIEW(dev_priv))
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5357 |    PIPE_CONF_CHECK_X(cgm_mode);
      |    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5358 |   else
      |   ~~~~                     
 5359 |    PIPE_CONF_CHECK_X(csc_mode);
      |    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5360 |   PIPE_CONF_CHECK_BOOL(gamma_enable);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5361 |   PIPE_CONF_CHECK_BOOL(csc_enable);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5362 |   PIPE_CONF_CHECK_BOOL(wgc_enable);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5363 | 
      |                            
 5364 |   PIPE_CONF_CHECK_I(linetime);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5365 |   PIPE_CONF_CHECK_I(ips_linetime);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5366 | 
      |                            
 5367 |   PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5368 |   PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5369 | 
      |                            
 5370 |   PIPE_CONF_CHECK_CSC(csc);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~
 5371 |   PIPE_CONF_CHECK_CSC(output_csc);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5372 |  }
      |  ~                         
 5373 | 
      |                            
 5374 |  /*
      |  ~~                        
 5375 |   * Panel replay has to be enabled before link training. PSR doesn't have
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5376 |   * this requirement -> check these only if using panel replay
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5377 |   */
      |   ~~                       
 5378 |  if (current_config->has_panel_replay || pipe_config->has_panel_replay) {
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5379 |   PIPE_CONF_CHECK_BOOL(has_psr);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5380 |   PIPE_CONF_CHECK_BOOL(has_psr2);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5381 |   PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5382 |   PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5383 |   PIPE_CONF_CHECK_BOOL(has_panel_replay);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5384 |  }
      |  ~                         
 5385 | 
      |                            
 5386 |  PIPE_CONF_CHECK_BOOL(double_wide);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5387 | 
      |                            
 5388 |  if (dev_priv->display.dpll.mgr)
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5389 |   PIPE_CONF_CHECK_P(shared_dpll);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5390 | 
      |                            
 5391 |  /* FIXME convert everything over the dpll_mgr */
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5392 |  if (dev_priv->display.dpll.mgr || HAS_GMCH(dev_priv))
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5393 |   PIPE_CONF_CHECK_PLL(dpll_hw_state);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5394 | 
      |                            
 5395 |  PIPE_CONF_CHECK_X(dsi_pll.ctrl);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5396 |  PIPE_CONF_CHECK_X(dsi_pll.div);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5397 | 
      |                            
 5398 |  if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5399 |   PIPE_CONF_CHECK_I(pipe_bpp);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5400 | 
      |                            
 5401 |  if (!fastset || !pipe_config->update_m_n) {
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5402 |   PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5403 |   PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5404 |  }
      |  ~                         
 5405 |  PIPE_CONF_CHECK_I(port_clock);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5406 | 
      |                            
 5407 |  PIPE_CONF_CHECK_I(min_voltage_level);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5408 | 
      |                            
 5409 |  if (current_config->has_psr || pipe_config->has_psr)
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5410 |   PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5411 |          ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5412 |  else
      |  ~~~~                      
 5413 |   PIPE_CONF_CHECK_X(infoframes.enable);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5414 | 
      |                            
 5415 |  PIPE_CONF_CHECK_X(infoframes.gcp);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5416 |  PIPE_CONF_CHECK_INFOFRAME(avi);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5417 |  PIPE_CONF_CHECK_INFOFRAME(spd);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5418 |  PIPE_CONF_CHECK_INFOFRAME(hdmi);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5419 |  PIPE_CONF_CHECK_INFOFRAME(drm);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5420 |  PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5421 |  PIPE_CONF_CHECK_DP_AS_SDP(as_sdp);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5422 | 
      |                            
 5423 |  PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5424 |  PIPE_CONF_CHECK_I(master_transcoder);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5425 |  PIPE_CONF_CHECK_X(bigjoiner_pipes);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5426 | 
      |                            
 5427 |  PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5428 |  PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5429 |  PIPE_CONF_CHECK_BOOL(dsc.config.simple_422);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5430 |  PIPE_CONF_CHECK_BOOL(dsc.config.native_422);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5431 |  PIPE_CONF_CHECK_BOOL(dsc.config.native_420);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5432 |  PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5433 |  PIPE_CONF_CHECK_I(dsc.config.line_buf_depth);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5434 |  PIPE_CONF_CHECK_I(dsc.config.bits_per_component);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5435 |  PIPE_CONF_CHECK_I(dsc.config.pic_width);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5436 |  PIPE_CONF_CHECK_I(dsc.config.pic_height);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5437 |  PIPE_CONF_CHECK_I(dsc.config.slice_width);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5438 |  PIPE_CONF_CHECK_I(dsc.config.slice_height);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5439 |  PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5440 |  PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5441 |  PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5442 |  PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5443 |  PIPE_CONF_CHECK_I(dsc.config.initial_scale_value);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5444 |  PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5445 |  PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5446 |  PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5447 |  PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5448 |  PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5449 |  PIPE_CONF_CHECK_I(dsc.config.initial_offset);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5450 |  PIPE_CONF_CHECK_I(dsc.config.final_offset);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5451 |  PIPE_CONF_CHECK_I(dsc.config.rc_model_size);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5452 |  PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5453 |  PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5454 |  PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5455 |  PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5456 |  PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5457 | 
      |                            
 5458 |  PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5459 |  PIPE_CONF_CHECK_BOOL(dsc.dsc_split);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5460 |  PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5461 | 
      |                            
 5462 |  PIPE_CONF_CHECK_BOOL(splitter.enable);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5463 |  PIPE_CONF_CHECK_I(splitter.link_count);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5464 |  PIPE_CONF_CHECK_I(splitter.pixel_overlap);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5465 | 
      |                            
 5466 |  if (!fastset) {
      |  ~~~~~~~~~~~~~~~           
 5467 |   PIPE_CONF_CHECK_BOOL(vrr.enable);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5468 |   PIPE_CONF_CHECK_I(vrr.vmin);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5469 |   PIPE_CONF_CHECK_I(vrr.vmax);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5470 |   PIPE_CONF_CHECK_I(vrr.flipline);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5471 |   PIPE_CONF_CHECK_I(vrr.pipeline_full);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5472 |   PIPE_CONF_CHECK_I(vrr.guardband);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5473 |   PIPE_CONF_CHECK_I(vrr.vsync_start);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5474 |   PIPE_CONF_CHECK_I(vrr.vsync_end);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5475 |   PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
      |                           |
      |                           u64 {aka const long long unsigned int}
drivers/gpu/drm/i915/display/intel_display.c:5105:26: note: in definition of macro ‘PIPE_CONF_CHECK_LLI’
 5105 |          current_config->name, \
      |                          ^~~~
drivers/gpu/drm/i915/display/intel_display.c:4906:38: note: expected ‘const char *’ but argument is of type ‘u64’ {aka ‘const long long unsigned int’}
 4906 |        const char *name, const char *format, ...)
      |                          ~~~~~~~~~~~~^~~~~~
drivers/gpu/drm/i915/display/intel_display.c:5103:24: error: incompatible type for argument 1 of ‘pipe_config_mismatch’
 5103 |   pipe_config_mismatch(fastset, crtc, __stringify(name), \
      |                        ^~~~~~~
      |                        |
      |                        bool {aka _Bool}
drivers/gpu/drm/i915/display/intel_display.c:5103:24: note: in definition of macro ‘PIPE_CONF_CHECK_LLI’
 5103 |   pipe_config_mismatch(fastset, crtc, __stringify(name), \
      |                        ^~~~~~~
drivers/gpu/drm/i915/display/intel_display.c:4904:42: note: expected ‘struct drm_printer *’ but argument is of type ‘bool’ {aka ‘_Bool’}
 4904 | pipe_config_mismatch(struct drm_printer *p, bool fastset,
      |                      ~~~~~~~~~~~~~~~~~~~~^
In file included from ./include/linux/linkage.h:6,
                 from ./arch/x86/include/asm/cache.h:5,
                 from ./include/linux/cache.h:6,
                 from ./arch/x86/include/asm/current.h:10,
                 from ./include/linux/mutex.h:14,
                 from ./include/linux/ww_mutex.h:20,
                 from ./include/linux/dma-resv.h:42,
                 from drivers/gpu/drm/i915/display/intel_display.c:27:
drivers/gpu/drm/i915/display/intel_display.c:5476:34: error: passing argument 3 of ‘pipe_config_mismatch’ from incompatible pointer type [-Werror=incompatible-pointer-types]
 5476 |   PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
      |                                  ^
      |                                  |
      |                                  char *
./include/linux/stringify.h:9:30: note: in definition of macro ‘__stringify_1’
    9 | #define __stringify_1(x...) #x
      |                              ^
drivers/gpu/drm/i915/display/intel_display.c:5103:39: note: in expansion of macro ‘__stringify’
 5103 |   pipe_config_mismatch(fastset, crtc, __stringify(name), \
      |                                       ^~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_display.c:5476:3: note: in expansion of macro ‘PIPE_CONF_CHECK_LLI’
 5476 |   PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
      |   ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_display.c:4905:33: note: expected ‘const struct intel_crtc *’ but argument is of type ‘char *’
 4905 |        const struct intel_crtc *crtc,
      |        ~~~~~~~~~~~~~~~~~~~~~~~~~^~~~
drivers/gpu/drm/i915/display/intel_display.c:5476:27: error: passing argument 5 of ‘pipe_config_mismatch’ makes pointer from integer without a cast [-Werror=int-conversion]
 5105 |          current_config->name, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~
 5106 |          pipe_config->name); \
      |          ~~~~~~~~~~~~~~~~~~~~~
 5107 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5108 |  } \
      |  ~~~                       
 5109 | } while (0)
      | ~~~~~~~~~~~                
 5110 | 
      |                            
 5111 | #define PIPE_CONF_CHECK_BOOL(name) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5112 |  if (current_config->name != pipe_config->name) { \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5113 |   BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5114 |      __stringify(name) " is not bool"); \
      |      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5115 |   pipe_config_mismatch(&p, fastset, crtc,  __stringify(name), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5116 |          "(expected %s, found %s)", \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5117 |          str_yes_no(current_config->name), \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5118 |          str_yes_no(pipe_config->name)); \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5119 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5120 |  } \
      |  ~~~                       
 5121 | } while (0)
      | ~~~~~~~~~~~                
 5122 | 
      |                            
 5123 | #define PIPE_CONF_CHECK_P(name) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5124 |  if (current_config->name != pipe_config->name) { \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5125 |   pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5126 |          "(expected %p, found %p)", \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5127 |          current_config->name, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~
 5128 |          pipe_config->name); \
      |          ~~~~~~~~~~~~~~~~~~~~~
 5129 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5130 |  } \
      |  ~~~                       
 5131 | } while (0)
      | ~~~~~~~~~~~                
 5132 | 
      |                            
 5133 | #define PIPE_CONF_CHECK_M_N(name) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5134 |  if (!intel_compare_link_m_n(&current_config->name, \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5135 |         &pipe_config->name)) { \
      |         ~~~~~~~~~~~~~~~~~~~~~~~~
 5136 |   pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5137 |          "(expected tu %i data %i/%i link %i/%i, " \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5138 |          "found tu %i, data %i/%i link %i/%i)", \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5139 |          current_config->name.tu, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~
 5140 |          current_config->name.data_m, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5141 |          current_config->name.data_n, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5142 |          current_config->name.link_m, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5143 |          current_config->name.link_n, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5144 |          pipe_config->name.tu, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~
 5145 |          pipe_config->name.data_m, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5146 |          pipe_config->name.data_n, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5147 |          pipe_config->name.link_m, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5148 |          pipe_config->name.link_n); \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5149 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5150 |  } \
      |  ~~~                       
 5151 | } while (0)
      | ~~~~~~~~~~~                
 5152 | 
      |                            
 5153 | #define PIPE_CONF_CHECK_PLL(name) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5154 |  if (!intel_dpll_compare_hw_state(dev_priv, &current_config->name, \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5155 |       &pipe_config->name)) { \
      |       ~~~~~~~~~~~~~~~~~~~~~~~~
 5156 |   pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5157 |       &current_config->name, \
      |       ~~~~~~~~~~~~~~~~~~~~~~~~
 5158 |       &pipe_config->name); \
      |       ~~~~~~~~~~~~~~~~~~~~~~
 5159 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5160 |  } \
      |  ~~~                       
 5161 | } while (0)
      | ~~~~~~~~~~~                
 5162 | 
      |                            
 5163 | #define PIPE_CONF_CHECK_TIMINGS(name) do {     \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5164 |  PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5165 |  PIPE_CONF_CHECK_I(name.crtc_htotal); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5166 |  PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5167 |  PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5168 |  PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5169 |  PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5170 |  PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5171 |  PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5172 |  PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5173 |  PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5174 |  if (!fastset || !pipe_config->update_lrr) { \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5175 |   PIPE_CONF_CHECK_I(name.crtc_vtotal); \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5176 |   PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5177 |  } \
      |  ~~~                       
 5178 | } while (0)
      | ~~~~~~~~~~~                
 5179 | 
      |                            
 5180 | #define PIPE_CONF_CHECK_RECT(name) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5181 |  PIPE_CONF_CHECK_I(name.x1); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5182 |  PIPE_CONF_CHECK_I(name.x2); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5183 |  PIPE_CONF_CHECK_I(name.y1); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5184 |  PIPE_CONF_CHECK_I(name.y2); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5185 | } while (0)
      | ~~~~~~~~~~~                
 5186 | 
      |                            
 5187 | #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5188 |  if ((current_config->name ^ pipe_config->name) & (mask)) { \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5189 |   pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5190 |          "(%x) (expected %i, found %i)", \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5191 |          (mask), \
      |          ~~~~~~~~~         
 5192 |          current_config->name & (mask), \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5193 |          pipe_config->name & (mask)); \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5194 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5195 |  } \
      |  ~~~                       
 5196 | } while (0)
      | ~~~~~~~~~~~                
 5197 | 
      |                            
 5198 | #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5199 |  if (!intel_compare_infoframe(&current_config->infoframes.name, \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5200 |          &pipe_config->infoframes.name)) { \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5201 |   pipe_config_infoframe_mismatch(&p, fastset, crtc, __stringify(name), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5202 |             &current_config->infoframes.name, \
      |             ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5203 |             &pipe_config->infoframes.name); \
      |             ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5204 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5205 |  } \
      |  ~~~                       
 5206 | } while (0)
      | ~~~~~~~~~~~                
 5207 | 
      |                            
 5208 | #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5209 |  if (!intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5210 |           &pipe_config->infoframes.name)) { \
      |           ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5211 |   pipe_config_dp_vsc_sdp_mismatch(&p, fastset, crtc, __stringify(name), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5212 |       &current_config->infoframes.name, \
      |       ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5213 |       &pipe_config->infoframes.name); \
      |       ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5214 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5215 |  } \
      |  ~~~                       
 5216 | } while (0)
      | ~~~~~~~~~~~                
 5217 | 
      |                            
 5218 | #define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5219 |  if (!intel_compare_dp_as_sdp(&current_config->infoframes.name, \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5220 |           &pipe_config->infoframes.name)) { \
      |           ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5221 |   pipe_config_dp_as_sdp_mismatch(dev_priv, fastset, __stringify(name), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5222 |       &current_config->infoframes.name, \
      |       ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5223 |       &pipe_config->infoframes.name); \
      |       ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5224 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5225 |  } \
      |  ~~~                       
 5226 | } while (0)
      | ~~~~~~~~~~~                
 5227 | 
      |                            
 5228 | #define PIPE_CONF_CHECK_BUFFER(name, len) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5229 |  BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5230 |  BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5231 |  if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5232 |   pipe_config_buffer_mismatch(&p, fastset, crtc, __stringify(name), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5233 |          current_config->name, \
      |          ~~~~~~~~~~~~~~~~~~~~~~~
 5234 |          pipe_config->name, \
      |          ~~~~~~~~~~~~~~~~~~~~
 5235 |          (len)); \
      |          ~~~~~~~~~         
 5236 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5237 |  } \
      |  ~~~                       
 5238 | } while (0)
      | ~~~~~~~~~~~                
 5239 | 
      |                            
 5240 | #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5241 |  if (current_config->gamma_mode == pipe_config->gamma_mode && \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5242 |      !intel_color_lut_equal(current_config, \
      |      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5243 |        current_config->lut, pipe_config->lut, \
      |        ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5244 |        is_pre_csc_lut)) { \
      |        ~~~~~~~~~~~~~~~~~~~~
 5245 |   pipe_config_mismatch(&p, fastset, crtc, __stringify(lut), \
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5246 |          "hw_state doesn't match sw_state"); \
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5247 |   ret = false; \
      |   ~~~~~~~~~~~~~~           
 5248 |  } \
      |  ~~~                       
 5249 | } while (0)
      | ~~~~~~~~~~~                
 5250 | 
      |                            
 5251 | #define PIPE_CONF_CHECK_CSC(name) do { \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5252 |  PIPE_CONF_CHECK_X(name.preoff[0]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5253 |  PIPE_CONF_CHECK_X(name.preoff[1]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5254 |  PIPE_CONF_CHECK_X(name.preoff[2]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5255 |  PIPE_CONF_CHECK_X(name.coeff[0]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5256 |  PIPE_CONF_CHECK_X(name.coeff[1]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5257 |  PIPE_CONF_CHECK_X(name.coeff[2]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5258 |  PIPE_CONF_CHECK_X(name.coeff[3]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5259 |  PIPE_CONF_CHECK_X(name.coeff[4]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5260 |  PIPE_CONF_CHECK_X(name.coeff[5]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5261 |  PIPE_CONF_CHECK_X(name.coeff[6]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5262 |  PIPE_CONF_CHECK_X(name.coeff[7]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5263 |  PIPE_CONF_CHECK_X(name.coeff[8]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5264 |  PIPE_CONF_CHECK_X(name.postoff[0]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5265 |  PIPE_CONF_CHECK_X(name.postoff[1]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5266 |  PIPE_CONF_CHECK_X(name.postoff[2]); \
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5267 | } while (0)
      | ~~~~~~~~~~~                
 5268 | 
      |                            
 5269 | #define PIPE_CONF_QUIRK(quirk) \
      | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5270 |  ((current_config->quirks | pipe_config->quirks) & (quirk))
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5271 | 
      |                            
 5272 |  PIPE_CONF_CHECK_BOOL(hw.enable);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5273 |  PIPE_CONF_CHECK_BOOL(hw.active);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5274 | 
      |                            
 5275 |  PIPE_CONF_CHECK_I(cpu_transcoder);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5276 |  PIPE_CONF_CHECK_I(mst_master_transcoder);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5277 | 
      |                            
 5278 |  PIPE_CONF_CHECK_BOOL(has_pch_encoder);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5279 |  PIPE_CONF_CHECK_I(fdi_lanes);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5280 |  PIPE_CONF_CHECK_M_N(fdi_m_n);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5281 | 
      |                            
 5282 |  PIPE_CONF_CHECK_I(lane_count);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5283 |  PIPE_CONF_CHECK_X(lane_lat_optim_mask);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5284 | 
      |                            
 5285 |  if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5286 |   if (!fastset || !pipe_config->update_m_n)
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5287 |    PIPE_CONF_CHECK_M_N(dp_m_n);
      |    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5288 |  } else {
      |  ~~~~~~~~                  
 5289 |   PIPE_CONF_CHECK_M_N(dp_m_n);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5290 |   PIPE_CONF_CHECK_M_N(dp_m2_n2);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5291 |  }
      |  ~                         
 5292 | 
      |                            
 5293 |  PIPE_CONF_CHECK_X(output_types);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5294 | 
      |                            
 5295 |  PIPE_CONF_CHECK_I(framestart_delay);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5296 |  PIPE_CONF_CHECK_I(msa_timing_delay);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5297 | 
      |                            
 5298 |  PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5299 |  PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5300 | 
      |                            
 5301 |  PIPE_CONF_CHECK_I(pixel_multiplier);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5302 | 
      |                            
 5303 |  PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5304 |          DRM_MODE_FLAG_INTERLACE);
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~
 5305 | 
      |                            
 5306 |  if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5307 |   PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5308 |           DRM_MODE_FLAG_PHSYNC);
      |           ~~~~~~~~~~~~~~~~~~~~~~
 5309 |   PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5310 |           DRM_MODE_FLAG_NHSYNC);
      |           ~~~~~~~~~~~~~~~~~~~~~~
 5311 |   PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5312 |           DRM_MODE_FLAG_PVSYNC);
      |           ~~~~~~~~~~~~~~~~~~~~~~
 5313 |   PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5314 |           DRM_MODE_FLAG_NVSYNC);
      |           ~~~~~~~~~~~~~~~~~~~~~~
 5315 |  }
      |  ~                         
 5316 | 
      |                            
 5317 |  PIPE_CONF_CHECK_I(output_format);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5318 |  PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5319 |  if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5320 |      IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
      |      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5321 |   PIPE_CONF_CHECK_BOOL(limited_color_range);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5322 | 
      |                            
 5323 |  PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5324 |  PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5325 |  PIPE_CONF_CHECK_BOOL(has_infoframe);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5326 |  PIPE_CONF_CHECK_BOOL(enhanced_framing);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5327 |  PIPE_CONF_CHECK_BOOL(fec_enable);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5328 | 
      |                            
 5329 |  if (!fastset) {
      |  ~~~~~~~~~~~~~~~           
 5330 |   PIPE_CONF_CHECK_BOOL(has_audio);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5331 |   PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5332 |  }
      |  ~                         
 5333 | 
      |                            
 5334 |  PIPE_CONF_CHECK_X(gmch_pfit.control);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5335 |  /* pfit ratios are autocomputed by the hw on gen4+ */
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5336 |  if (DISPLAY_VER(dev_priv) < 4)
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5337 |   PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5338 |  PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5339 | 
      |                            
 5340 |  /*
      |  ~~                        
 5341 |   * Changing the EDP transcoder input mux
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5342 |   * (A_ONOFF vs. A_ON) requires a full modeset.
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5343 |   */
      |   ~~                       
 5344 |  PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5345 | 
      |                            
 5346 |  if (!fastset) {
      |  ~~~~~~~~~~~~~~~           
 5347 |   PIPE_CONF_CHECK_RECT(pipe_src);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5348 | 
      |                            
 5349 |   PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5350 |   PIPE_CONF_CHECK_RECT(pch_pfit.dst);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5351 | 
      |                            
 5352 |   PIPE_CONF_CHECK_I(scaler_state.scaler_id);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5353 |   PIPE_CONF_CHECK_I(pixel_rate);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5354 | 
      |                            
 5355 |   PIPE_CONF_CHECK_X(gamma_mode);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5356 |   if (IS_CHERRYVIEW(dev_priv))
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5357 |    PIPE_CONF_CHECK_X(cgm_mode);
      |    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5358 |   else
      |   ~~~~                     
 5359 |    PIPE_CONF_CHECK_X(csc_mode);
      |    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5360 |   PIPE_CONF_CHECK_BOOL(gamma_enable);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5361 |   PIPE_CONF_CHECK_BOOL(csc_enable);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5362 |   PIPE_CONF_CHECK_BOOL(wgc_enable);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5363 | 
      |                            
 5364 |   PIPE_CONF_CHECK_I(linetime);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5365 |   PIPE_CONF_CHECK_I(ips_linetime);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5366 | 
      |                            
 5367 |   PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5368 |   PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5369 | 
      |                            
 5370 |   PIPE_CONF_CHECK_CSC(csc);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~
 5371 |   PIPE_CONF_CHECK_CSC(output_csc);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5372 |  }
      |  ~                         
 5373 | 
      |                            
 5374 |  /*
      |  ~~                        
 5375 |   * Panel replay has to be enabled before link training. PSR doesn't have
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5376 |   * this requirement -> check these only if using panel replay
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5377 |   */
      |   ~~                       
 5378 |  if (current_config->has_panel_replay || pipe_config->has_panel_replay) {
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5379 |   PIPE_CONF_CHECK_BOOL(has_psr);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5380 |   PIPE_CONF_CHECK_BOOL(has_psr2);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5381 |   PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5382 |   PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5383 |   PIPE_CONF_CHECK_BOOL(has_panel_replay);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5384 |  }
      |  ~                         
 5385 | 
      |                            
 5386 |  PIPE_CONF_CHECK_BOOL(double_wide);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5387 | 
      |                            
 5388 |  if (dev_priv->display.dpll.mgr)
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5389 |   PIPE_CONF_CHECK_P(shared_dpll);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5390 | 
      |                            
 5391 |  /* FIXME convert everything over the dpll_mgr */
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5392 |  if (dev_priv->display.dpll.mgr || HAS_GMCH(dev_priv))
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5393 |   PIPE_CONF_CHECK_PLL(dpll_hw_state);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5394 | 
      |                            
 5395 |  PIPE_CONF_CHECK_X(dsi_pll.ctrl);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5396 |  PIPE_CONF_CHECK_X(dsi_pll.div);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5397 | 
      |                            
 5398 |  if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5399 |   PIPE_CONF_CHECK_I(pipe_bpp);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5400 | 
      |                            
 5401 |  if (!fastset || !pipe_config->update_m_n) {
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5402 |   PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5403 |   PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5404 |  }
      |  ~                         
 5405 |  PIPE_CONF_CHECK_I(port_clock);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5406 | 
      |                            
 5407 |  PIPE_CONF_CHECK_I(min_voltage_level);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5408 | 
      |                            
 5409 |  if (current_config->has_psr || pipe_config->has_psr)
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5410 |   PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5411 |          ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
      |          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5412 |  else
      |  ~~~~                      
 5413 |   PIPE_CONF_CHECK_X(infoframes.enable);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5414 | 
      |                            
 5415 |  PIPE_CONF_CHECK_X(infoframes.gcp);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5416 |  PIPE_CONF_CHECK_INFOFRAME(avi);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5417 |  PIPE_CONF_CHECK_INFOFRAME(spd);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5418 |  PIPE_CONF_CHECK_INFOFRAME(hdmi);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5419 |  PIPE_CONF_CHECK_INFOFRAME(drm);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5420 |  PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5421 |  PIPE_CONF_CHECK_DP_AS_SDP(as_sdp);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5422 | 
      |                            
 5423 |  PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5424 |  PIPE_CONF_CHECK_I(master_transcoder);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5425 |  PIPE_CONF_CHECK_X(bigjoiner_pipes);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5426 | 
      |                            
 5427 |  PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5428 |  PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5429 |  PIPE_CONF_CHECK_BOOL(dsc.config.simple_422);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5430 |  PIPE_CONF_CHECK_BOOL(dsc.config.native_422);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5431 |  PIPE_CONF_CHECK_BOOL(dsc.config.native_420);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5432 |  PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5433 |  PIPE_CONF_CHECK_I(dsc.config.line_buf_depth);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5434 |  PIPE_CONF_CHECK_I(dsc.config.bits_per_component);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5435 |  PIPE_CONF_CHECK_I(dsc.config.pic_width);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5436 |  PIPE_CONF_CHECK_I(dsc.config.pic_height);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5437 |  PIPE_CONF_CHECK_I(dsc.config.slice_width);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5438 |  PIPE_CONF_CHECK_I(dsc.config.slice_height);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5439 |  PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5440 |  PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5441 |  PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5442 |  PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5443 |  PIPE_CONF_CHECK_I(dsc.config.initial_scale_value);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5444 |  PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5445 |  PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5446 |  PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5447 |  PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5448 |  PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5449 |  PIPE_CONF_CHECK_I(dsc.config.initial_offset);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5450 |  PIPE_CONF_CHECK_I(dsc.config.final_offset);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5451 |  PIPE_CONF_CHECK_I(dsc.config.rc_model_size);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5452 |  PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5453 |  PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5454 |  PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5455 |  PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5456 |  PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5457 | 
      |                            
 5458 |  PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5459 |  PIPE_CONF_CHECK_BOOL(dsc.dsc_split);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5460 |  PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5461 | 
      |                            
 5462 |  PIPE_CONF_CHECK_BOOL(splitter.enable);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5463 |  PIPE_CONF_CHECK_I(splitter.link_count);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5464 |  PIPE_CONF_CHECK_I(splitter.pixel_overlap);
      |  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5465 | 
      |                            
 5466 |  if (!fastset) {
      |  ~~~~~~~~~~~~~~~           
 5467 |   PIPE_CONF_CHECK_BOOL(vrr.enable);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5468 |   PIPE_CONF_CHECK_I(vrr.vmin);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5469 |   PIPE_CONF_CHECK_I(vrr.vmax);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5470 |   PIPE_CONF_CHECK_I(vrr.flipline);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5471 |   PIPE_CONF_CHECK_I(vrr.pipeline_full);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5472 |   PIPE_CONF_CHECK_I(vrr.guardband);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5473 |   PIPE_CONF_CHECK_I(vrr.vsync_start);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5474 |   PIPE_CONF_CHECK_I(vrr.vsync_end);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5475 |   PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 5476 |   PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
      |                           |
      |                           u64 {aka const long long unsigned int}
drivers/gpu/drm/i915/display/intel_display.c:5105:26: note: in definition of macro ‘PIPE_CONF_CHECK_LLI’
 5105 |          current_config->name, \
      |                          ^~~~
drivers/gpu/drm/i915/display/intel_display.c:4906:38: note: expected ‘const char *’ but argument is of type ‘u64’ {aka ‘const long long unsigned int’}
 4906 |        const char *name, const char *format, ...)
      |                          ~~~~~~~~~~~~^~~~~~
cc1: all warnings being treated as errors
make[6]: *** [scripts/Makefile.build:244: drivers/gpu/drm/i915/display/intel_display.o] Error 1
make[5]: *** [scripts/Makefile.build:485: drivers/gpu/drm/i915] Error 2
make[4]: *** [scripts/Makefile.build:485: drivers/gpu/drm] Error 2
make[3]: *** [scripts/Makefile.build:485: drivers/gpu] Error 2
make[2]: *** [scripts/Makefile.build:485: drivers] Error 2
make[1]: *** [/home/kbuild2/kernel/Makefile:1919: .] Error 2
make: *** [Makefile:240: __sub-make] Error 2
Build failed, no error log produced