* [PATCH 1/2] drm: Add SDP Error Detection Configuration Register
@ 2023-01-13 4:36 ` Arun R Murthy
0 siblings, 0 replies; 27+ messages in thread
From: Arun R Murthy @ 2023-01-13 4:36 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula; +Cc: Arun R Murthy
DP2.0 E11 defines a new register to facilitate SDP error detection by a
128B/132B capable DPRX device.
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
include/drm/display/drm_dp.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 9bc22a02874d..8bf6f0a60c38 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -691,6 +691,9 @@
# define DP_FEC_LANE_2_SELECT (2 << 4)
# define DP_FEC_LANE_3_SELECT (3 << 4)
+#define DP_SDP_ERROR_DETECTION 0x121 /* DP 2.0 E11 */
+#define DP_SDP_CRC16_128B132B_EN BIT(0)
+
#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
2023-01-13 4:36 ` Arun R Murthy
@ 2023-01-13 4:36 ` Arun R Murthy
-1 siblings, 0 replies; 27+ messages in thread
From: Arun R Murthy @ 2023-01-13 4:36 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula
Enable SDP error detection configuration, this will set CRC16 in
128b/132b link layer.
For DISPLAY13 a hardware bit31 in register VIDEO_DIP_CTL is added to
enable/disable SDP CRC applicable for DP2.0 only, but the default value
of this bit will enable CRC16 in 128b/132b hence skipping this write.
Corrective actions on SDP corruption is yet to be defined.
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 30c55f980014..6096825a27ca 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -133,6 +133,7 @@ static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
/* update sink rates from dpcd */
static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
static const int dp_rates[] = {
162000, 270000, 540000, 810000
};
@@ -196,6 +197,18 @@ static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
intel_dp->sink_rates[i++] = 1350000;
if (uhbr_rates & DP_UHBR20)
intel_dp->sink_rates[i++] = 2000000;
+
+ /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
+ if (HAS_DP20(i915))
+ drm_dp_dpcd_writeb(&intel_dp->aux,
+ DP_SDP_ERROR_DETECTION,
+ DP_SDP_CRC16_128B132B_EN);
+ /*
+ * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
+ * disable SDP CRC. This is applicable for DISPLAY 13. Default
+ * value of bit 31 is '0' hence discarging the write
+ */
+ /* TODO: Corrective actions on SDP corruption yet to be defined */
}
intel_dp->num_sink_rates = i;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8b2cf980f323..77e265f59978 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2674,6 +2674,7 @@
#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
#define VIDEO_DIP_FREQ_MASK (3 << 16)
/* HSW and later: */
+#define VIDEO_DISABLE_SDP_CRC (1 << 31)
#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
#define PSR_VSC_BIT_7_SET (1 << 27)
#define VSC_SELECT_MASK (0x3 << 25)
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
@ 2023-01-13 4:36 ` Arun R Murthy
0 siblings, 0 replies; 27+ messages in thread
From: Arun R Murthy @ 2023-01-13 4:36 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula; +Cc: Arun R Murthy
Enable SDP error detection configuration, this will set CRC16 in
128b/132b link layer.
For DISPLAY13 a hardware bit31 in register VIDEO_DIP_CTL is added to
enable/disable SDP CRC applicable for DP2.0 only, but the default value
of this bit will enable CRC16 in 128b/132b hence skipping this write.
Corrective actions on SDP corruption is yet to be defined.
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 30c55f980014..6096825a27ca 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -133,6 +133,7 @@ static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
/* update sink rates from dpcd */
static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
static const int dp_rates[] = {
162000, 270000, 540000, 810000
};
@@ -196,6 +197,18 @@ static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
intel_dp->sink_rates[i++] = 1350000;
if (uhbr_rates & DP_UHBR20)
intel_dp->sink_rates[i++] = 2000000;
+
+ /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
+ if (HAS_DP20(i915))
+ drm_dp_dpcd_writeb(&intel_dp->aux,
+ DP_SDP_ERROR_DETECTION,
+ DP_SDP_CRC16_128B132B_EN);
+ /*
+ * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
+ * disable SDP CRC. This is applicable for DISPLAY 13. Default
+ * value of bit 31 is '0' hence discarging the write
+ */
+ /* TODO: Corrective actions on SDP corruption yet to be defined */
}
intel_dp->num_sink_rates = i;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8b2cf980f323..77e265f59978 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2674,6 +2674,7 @@
#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
#define VIDEO_DIP_FREQ_MASK (3 << 16)
/* HSW and later: */
+#define VIDEO_DISABLE_SDP_CRC (1 << 31)
#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
#define PSR_VSC_BIT_7_SET (1 << 27)
#define VSC_SELECT_MASK (0x3 << 25)
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
2023-01-13 4:36 ` Arun R Murthy
@ 2023-01-13 8:19 ` Jani Nikula
-1 siblings, 0 replies; 27+ messages in thread
From: Jani Nikula @ 2023-01-13 8:19 UTC (permalink / raw)
To: Arun R Murthy, intel-gfx, dri-devel
On Fri, 13 Jan 2023, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> Enable SDP error detection configuration, this will set CRC16 in
> 128b/132b link layer.
> For DISPLAY13 a hardware bit31 in register VIDEO_DIP_CTL is added to
> enable/disable SDP CRC applicable for DP2.0 only, but the default value
> of this bit will enable CRC16 in 128b/132b hence skipping this write.
> Corrective actions on SDP corruption is yet to be defined.
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 30c55f980014..6096825a27ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -133,6 +133,7 @@ static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
> /* update sink rates from dpcd */
> static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
Based on the function name and comment, this function updates the
driver's idea of what rates the sink supports. A quick look at the code
confirms this.
It should be clear that this is not the place to add unrelated DPCD
writes.
> {
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> static const int dp_rates[] = {
> 162000, 270000, 540000, 810000
> };
> @@ -196,6 +197,18 @@ static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
> intel_dp->sink_rates[i++] = 1350000;
> if (uhbr_rates & DP_UHBR20)
> intel_dp->sink_rates[i++] = 2000000;
> +
> + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
> + if (HAS_DP20(i915))
> + drm_dp_dpcd_writeb(&intel_dp->aux,
> + DP_SDP_ERROR_DETECTION,
> + DP_SDP_CRC16_128B132B_EN);
HAS_DP20() means the source has DP 2.0 support.
We're in a branch where we can assume the sink also has DP 2.0
support. But at this point we're not sure we'll be using 128b/132b at
all.
I did not look this up in the spec, but I assume this bit is only
supposed to be set when we're actually using a 128b/132b link?
In which case, this should probably be enabled at some point when we're
enabling a 128b/132b link, and at that time the check to use is
intel_dp_is_uhbr(). UHBR and 128b/132b go hand-in-hand, and we won't use
UHBR unless both source and sink support it.
> + /*
> + * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
> + * disable SDP CRC. This is applicable for DISPLAY 13. Default
> + * value of bit 31 is '0' hence discarging the write
> + */
> + /* TODO: Corrective actions on SDP corruption yet to be defined */
The above might belong in the commit message, but I'm not sure about
their usefulness as comments.
> }
>
> intel_dp->num_sink_rates = i;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8b2cf980f323..77e265f59978 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2674,6 +2674,7 @@
> #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
> #define VIDEO_DIP_FREQ_MASK (3 << 16)
> /* HSW and later: */
> +#define VIDEO_DISABLE_SDP_CRC (1 << 31)
Please read the comment at the top of the file.
> #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
> #define PSR_VSC_BIT_7_SET (1 << 27)
> #define VSC_SELECT_MASK (0x3 << 25)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
@ 2023-01-13 8:19 ` Jani Nikula
0 siblings, 0 replies; 27+ messages in thread
From: Jani Nikula @ 2023-01-13 8:19 UTC (permalink / raw)
To: Arun R Murthy, intel-gfx, dri-devel; +Cc: Arun R Murthy
On Fri, 13 Jan 2023, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> Enable SDP error detection configuration, this will set CRC16 in
> 128b/132b link layer.
> For DISPLAY13 a hardware bit31 in register VIDEO_DIP_CTL is added to
> enable/disable SDP CRC applicable for DP2.0 only, but the default value
> of this bit will enable CRC16 in 128b/132b hence skipping this write.
> Corrective actions on SDP corruption is yet to be defined.
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 30c55f980014..6096825a27ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -133,6 +133,7 @@ static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
> /* update sink rates from dpcd */
> static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
Based on the function name and comment, this function updates the
driver's idea of what rates the sink supports. A quick look at the code
confirms this.
It should be clear that this is not the place to add unrelated DPCD
writes.
> {
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> static const int dp_rates[] = {
> 162000, 270000, 540000, 810000
> };
> @@ -196,6 +197,18 @@ static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
> intel_dp->sink_rates[i++] = 1350000;
> if (uhbr_rates & DP_UHBR20)
> intel_dp->sink_rates[i++] = 2000000;
> +
> + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
> + if (HAS_DP20(i915))
> + drm_dp_dpcd_writeb(&intel_dp->aux,
> + DP_SDP_ERROR_DETECTION,
> + DP_SDP_CRC16_128B132B_EN);
HAS_DP20() means the source has DP 2.0 support.
We're in a branch where we can assume the sink also has DP 2.0
support. But at this point we're not sure we'll be using 128b/132b at
all.
I did not look this up in the spec, but I assume this bit is only
supposed to be set when we're actually using a 128b/132b link?
In which case, this should probably be enabled at some point when we're
enabling a 128b/132b link, and at that time the check to use is
intel_dp_is_uhbr(). UHBR and 128b/132b go hand-in-hand, and we won't use
UHBR unless both source and sink support it.
> + /*
> + * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
> + * disable SDP CRC. This is applicable for DISPLAY 13. Default
> + * value of bit 31 is '0' hence discarging the write
> + */
> + /* TODO: Corrective actions on SDP corruption yet to be defined */
The above might belong in the commit message, but I'm not sure about
their usefulness as comments.
> }
>
> intel_dp->num_sink_rates = i;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8b2cf980f323..77e265f59978 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2674,6 +2674,7 @@
> #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
> #define VIDEO_DIP_FREQ_MASK (3 << 16)
> /* HSW and later: */
> +#define VIDEO_DISABLE_SDP_CRC (1 << 31)
Please read the comment at the top of the file.
> #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
> #define PSR_VSC_BIT_7_SET (1 << 27)
> #define VSC_SELECT_MASK (0x3 << 25)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
2023-01-13 8:19 ` Jani Nikula
@ 2023-01-19 6:19 ` Murthy, Arun R
-1 siblings, 0 replies; 27+ messages in thread
From: Murthy, Arun R @ 2023-01-19 6:19 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Friday, January 13, 2023 1:49 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>
> Subject: Re: [PATCH 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
>
> On Fri, 13 Jan 2023, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> > Enable SDP error detection configuration, this will set CRC16 in
> > 128b/132b link layer.
> > For DISPLAY13 a hardware bit31 in register VIDEO_DIP_CTL is added to
> > enable/disable SDP CRC applicable for DP2.0 only, but the default
> > value of this bit will enable CRC16 in 128b/132b hence skipping this write.
> > Corrective actions on SDP corruption is yet to be defined.
> >
> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++++++++
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 2 files changed, 14 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 30c55f980014..6096825a27ca 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -133,6 +133,7 @@ static void intel_dp_set_default_sink_rates(struct
> > intel_dp *intel_dp)
> > /* update sink rates from dpcd */
> > static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
>
> Based on the function name and comment, this function updates the driver's
> idea of what rates the sink supports. A quick look at the code confirms this.
>
> It should be clear that this is not the place to add unrelated DPCD writes.
>
> > {
> > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > static const int dp_rates[] = {
> > 162000, 270000, 540000, 810000
> > };
> > @@ -196,6 +197,18 @@ static void intel_dp_set_dpcd_sink_rates(struct
> intel_dp *intel_dp)
> > intel_dp->sink_rates[i++] = 1350000;
> > if (uhbr_rates & DP_UHBR20)
> > intel_dp->sink_rates[i++] = 2000000;
> > +
> > + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
> > + if (HAS_DP20(i915))
> > + drm_dp_dpcd_writeb(&intel_dp->aux,
> > + DP_SDP_ERROR_DETECTION,
> > + DP_SDP_CRC16_128B132B_EN);
>
> HAS_DP20() means the source has DP 2.0 support.
>
> We're in a branch where we can assume the sink also has DP 2.0 support.
> But at this point we're not sure we'll be using 128b/132b at all.
>
> I did not look this up in the spec, but I assume this bit is only supposed to be
> set when we're actually using a 128b/132b link?
Yes.
>
> In which case, this should probably be enabled at some point when we're
> enabling a 128b/132b link, and at that time the check to use is
> intel_dp_is_uhbr(). UHBR and 128b/132b go hand-in-hand, and we won't use
> UHBR unless both source and sink support it.
Updated and also moved this part under link training init.
>
> > + /*
> > + * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
> > + * disable SDP CRC. This is applicable for DISPLAY 13. Default
> > + * value of bit 31 is '0' hence discarging the write
> > + */
> > + /* TODO: Corrective actions on SDP corruption yet to be
> defined */
>
> The above might belong in the commit message, but I'm not sure about their
> usefulness as comments.
This comment is just to ensure we keep track on what has to be done on error.
>
> > }
> >
> > intel_dp->num_sink_rates = i;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 8b2cf980f323..77e265f59978
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -2674,6 +2674,7 @@
> > #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
> > #define VIDEO_DIP_FREQ_MASK (3 << 16)
> > /* HSW and later: */
> > +#define VIDEO_DISABLE_SDP_CRC (1 << 31)
>
> Please read the comment at the top of the file.
Will remove this, as for now we are not using this and will add this once the corrective actions are added.
Thanks and Regards,
Arun R Murthy
--------------------
>
> > #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
> > #define PSR_VSC_BIT_7_SET (1 << 27)
> > #define VSC_SELECT_MASK (0x3 << 25)
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 27+ messages in thread* RE: [PATCH 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
@ 2023-01-19 6:19 ` Murthy, Arun R
0 siblings, 0 replies; 27+ messages in thread
From: Murthy, Arun R @ 2023-01-19 6:19 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Friday, January 13, 2023 1:49 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>
> Subject: Re: [PATCH 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
>
> On Fri, 13 Jan 2023, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> > Enable SDP error detection configuration, this will set CRC16 in
> > 128b/132b link layer.
> > For DISPLAY13 a hardware bit31 in register VIDEO_DIP_CTL is added to
> > enable/disable SDP CRC applicable for DP2.0 only, but the default
> > value of this bit will enable CRC16 in 128b/132b hence skipping this write.
> > Corrective actions on SDP corruption is yet to be defined.
> >
> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++++++++
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 2 files changed, 14 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 30c55f980014..6096825a27ca 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -133,6 +133,7 @@ static void intel_dp_set_default_sink_rates(struct
> > intel_dp *intel_dp)
> > /* update sink rates from dpcd */
> > static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
>
> Based on the function name and comment, this function updates the driver's
> idea of what rates the sink supports. A quick look at the code confirms this.
>
> It should be clear that this is not the place to add unrelated DPCD writes.
>
> > {
> > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > static const int dp_rates[] = {
> > 162000, 270000, 540000, 810000
> > };
> > @@ -196,6 +197,18 @@ static void intel_dp_set_dpcd_sink_rates(struct
> intel_dp *intel_dp)
> > intel_dp->sink_rates[i++] = 1350000;
> > if (uhbr_rates & DP_UHBR20)
> > intel_dp->sink_rates[i++] = 2000000;
> > +
> > + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
> > + if (HAS_DP20(i915))
> > + drm_dp_dpcd_writeb(&intel_dp->aux,
> > + DP_SDP_ERROR_DETECTION,
> > + DP_SDP_CRC16_128B132B_EN);
>
> HAS_DP20() means the source has DP 2.0 support.
>
> We're in a branch where we can assume the sink also has DP 2.0 support.
> But at this point we're not sure we'll be using 128b/132b at all.
>
> I did not look this up in the spec, but I assume this bit is only supposed to be
> set when we're actually using a 128b/132b link?
Yes.
>
> In which case, this should probably be enabled at some point when we're
> enabling a 128b/132b link, and at that time the check to use is
> intel_dp_is_uhbr(). UHBR and 128b/132b go hand-in-hand, and we won't use
> UHBR unless both source and sink support it.
Updated and also moved this part under link training init.
>
> > + /*
> > + * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
> > + * disable SDP CRC. This is applicable for DISPLAY 13. Default
> > + * value of bit 31 is '0' hence discarging the write
> > + */
> > + /* TODO: Corrective actions on SDP corruption yet to be
> defined */
>
> The above might belong in the commit message, but I'm not sure about their
> usefulness as comments.
This comment is just to ensure we keep track on what has to be done on error.
>
> > }
> >
> > intel_dp->num_sink_rates = i;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 8b2cf980f323..77e265f59978
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -2674,6 +2674,7 @@
> > #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
> > #define VIDEO_DIP_FREQ_MASK (3 << 16)
> > /* HSW and later: */
> > +#define VIDEO_DISABLE_SDP_CRC (1 << 31)
>
> Please read the comment at the top of the file.
Will remove this, as for now we are not using this and will add this once the corrective actions are added.
Thanks and Regards,
Arun R Murthy
--------------------
>
> > #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
> > #define PSR_VSC_BIT_7_SET (1 << 27)
> > #define VSC_SELECT_MASK (0x3 << 25)
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm: Add SDP Error Detection Configuration Register
2023-01-13 4:36 ` Arun R Murthy
(?)
(?)
@ 2023-01-13 5:14 ` Patchwork
-1 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-01-13 5:14 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm: Add SDP Error Detection Configuration Register
URL : https://patchwork.freedesktop.org/series/112774/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm: Add SDP Error Detection Configuration Register
2023-01-13 4:36 ` Arun R Murthy
` (2 preceding siblings ...)
(?)
@ 2023-01-13 5:41 ` Patchwork
-1 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-01-13 5:41 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4846 bytes --]
== Series Details ==
Series: series starting with [1/2] drm: Add SDP Error Detection Configuration Register
URL : https://patchwork.freedesktop.org/series/112774/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12579 -> Patchwork_112774v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/index.html
Participating hosts (43 -> 42)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_112774v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@execlists:
- fi-kbl-soraka: [PASS][1] -> [INCOMPLETE][2] ([i915#7156])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/fi-kbl-soraka/igt@i915_selftest@live@execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/fi-kbl-soraka/igt@i915_selftest@live@execlists.html
#### Possible fixes ####
* igt@gem_exec_gttfill@basic:
- fi-pnv-d510: [FAIL][3] ([i915#7229]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][5] ([i915#5334]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_pm:
- {bat-rpls-2}: [DMESG-FAIL][7] ([i915#4258]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@requests:
- {bat-rpls-2}: [INCOMPLETE][9] ([i915#4983] / [i915#6257]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/bat-rpls-2/igt@i915_selftest@live@requests.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/bat-rpls-2/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@slpc:
- {bat-adlp-6}: [DMESG-FAIL][11] ([i915#6367]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/bat-adlp-6/igt@i915_selftest@live@slpc.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/bat-adlp-6/igt@i915_selftest@live@slpc.html
#### Warnings ####
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [FAIL][13] ([fdo#103375]) -> [INCOMPLETE][14] ([i915#4817])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7156]: https://gitlab.freedesktop.org/drm/intel/issues/7156
[i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
Build changes
-------------
* Linux: CI_DRM_12579 -> Patchwork_112774v1
CI-20190529: 20190529
CI_DRM_12579: f06110201eddf1835258ba2efebe6442682b5ed2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7119: 1e6d24e6dfa42b22f950f7d5e436b8f9acf8747f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_112774v1: f06110201eddf1835258ba2efebe6442682b5ed2 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
d45133588520 i915/display/dp: SDP CRC16 for 128b132b link layer
7cccdce9e190 drm: Add SDP Error Detection Configuration Register
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/index.html
[-- Attachment #2: Type: text/html, Size: 5345 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm: Add SDP Error Detection Configuration Register
2023-01-13 4:36 ` Arun R Murthy
` (3 preceding siblings ...)
(?)
@ 2023-01-13 15:57 ` Patchwork
-1 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-01-13 15:57 UTC (permalink / raw)
To: Murthy, Arun R; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 18835 bytes --]
== Series Details ==
Series: series starting with [1/2] drm: Add SDP Error Detection Configuration Register
URL : https://patchwork.freedesktop.org/series/112774/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12579_full -> Patchwork_112774v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_112774v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_112774v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/index.html
Participating hosts (13 -> 10)
------------------------------
Missing (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_112774v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_mmap_gtt@cpuset-basic-small-copy-xy:
- shard-glk: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/shard-glk7/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-glk6/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
* igt@perf_pmu@cpu-hotplug:
- shard-glk: [PASS][3] -> [TIMEOUT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/shard-glk7/igt@perf_pmu@cpu-hotplug.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-glk6/igt@perf_pmu@cpu-hotplug.html
Known issues
------------
Here are the changes found in Patchwork_112774v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-none@vcs0:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#2842]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/shard-glk7/igt@gem_exec_fair@basic-none@vcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-glk6/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-glk1/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#3886])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-glk1/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-glk: NOTRUN -> [FAIL][9] ([i915#4767])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-glk1/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_hdr@static-toggle-dpms:
- shard-glk: NOTRUN -> [SKIP][10] ([fdo#109271]) +36 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-glk1/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-glk: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#658])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-glk1/igt@kms_psr2_sf@cursor-plane-update-sf.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- {shard-rkl}: [FAIL][12] ([i915#7742]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/shard-rkl-1/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-rkl-2/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@fbdev@unaligned-write:
- {shard-rkl}: [SKIP][14] ([i915#2582]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/shard-rkl-3/igt@fbdev@unaligned-write.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-rkl-6/igt@fbdev@unaligned-write.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- {shard-rkl}: [FAIL][16] ([i915#2842]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/shard-rkl-2/igt@gem_exec_fair@basic-none-share@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-rkl-5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_reloc@basic-cpu-read:
- {shard-rkl}: [SKIP][18] ([i915#3281]) -> [PASS][19] +8 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/shard-rkl-4/igt@gem_exec_reloc@basic-cpu-read.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-rkl-5/igt@gem_exec_reloc@basic-cpu-read.html
* igt@gem_pread@bench:
- {shard-rkl}: [SKIP][20] ([i915#3282]) -> [PASS][21] +4 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/shard-rkl-4/igt@gem_pread@bench.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-rkl-5/igt@gem_pread@bench.html
* igt@gen9_exec_parse@bb-chained:
- {shard-rkl}: [SKIP][22] ([i915#2527]) -> [PASS][23] +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/shard-rkl-4/igt@gen9_exec_parse@bb-chained.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-rkl-5/igt@gen9_exec_parse@bb-chained.html
* igt@i915_pm_rpm@drm-resources-equal:
- {shard-rkl}: [SKIP][24] ([fdo#109308]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/shard-rkl-3/igt@i915_pm_rpm@drm-resources-equal.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-rkl-6/igt@i915_pm_rpm@drm-resources-equal.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- {shard-dg1}: [SKIP][26] ([i915#1397]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/shard-dg1-14/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-dg1-12/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_atomic@plane-overlay-legacy:
- {shard-rkl}: [SKIP][28] ([i915#1845] / [i915#4098]) -> [PASS][29] +6 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/shard-rkl-3/igt@kms_atomic@plane-overlay-legacy.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-rkl-6/igt@kms_atomic@plane-overlay-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk: [FAIL][30] ([i915#2346]) -> [PASS][31] +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][32] ([i915#79]) -> [PASS][33] +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- {shard-dg1}: [FAIL][34] -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/shard-dg1-12/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-dg1-17/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render:
- {shard-rkl}: [SKIP][36] ([i915#1849] / [i915#4098]) -> [PASS][37] +3 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render.html
* igt@kms_hdmi_inject@inject-audio:
- {shard-tglu}: [SKIP][38] ([i915#433]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/shard-tglu-1/igt@kms_hdmi_inject@inject-audio.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-tglu-7/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_psr@sprite_mmap_gtt:
- {shard-rkl}: [SKIP][40] ([i915#1072]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/shard-rkl-3/igt@kms_psr@sprite_mmap_gtt.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-rkl-6/igt@kms_psr@sprite_mmap_gtt.html
* igt@perf@gen12-unprivileged-single-ctx-counters:
- {shard-rkl}: [SKIP][42] ([fdo#109289]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/shard-rkl-5/igt@perf@gen12-unprivileged-single-ctx-counters.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-rkl-3/igt@perf@gen12-unprivileged-single-ctx-counters.html
* igt@prime_vgem@coherency-gtt:
- {shard-rkl}: [SKIP][44] ([fdo#109295] / [fdo#111656] / [i915#3708]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12579/shard-rkl-4/igt@prime_vgem@coherency-gtt.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/shard-rkl-5/igt@prime_vgem@coherency-gtt.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2532]: https://gitlab.freedesktop.org/drm/intel/issues/2532
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6355]: https://gitlab.freedesktop.org/drm/intel/issues/6355
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#7276]: https://gitlab.freedesktop.org/drm/intel/issues/7276
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7679]: https://gitlab.freedesktop.org/drm/intel/issues/7679
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7756]: https://gitlab.freedesktop.org/drm/intel/issues/7756
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7863]: https://gitlab.freedesktop.org/drm/intel/issues/7863
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12579 -> Patchwork_112774v1
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_12579: f06110201eddf1835258ba2efebe6442682b5ed2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7119: 1e6d24e6dfa42b22f950f7d5e436b8f9acf8747f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_112774v1: f06110201eddf1835258ba2efebe6442682b5ed2 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112774v1/index.html
[-- Attachment #2: Type: text/html, Size: 13833 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 1/2] drm: Add SDP Error Detection Configuration Register
2023-01-13 4:36 ` Arun R Murthy
@ 2023-01-13 20:40 ` Harry Wentland
-1 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2023-01-13 20:40 UTC (permalink / raw)
To: Arun R Murthy, intel-gfx, dri-devel, jani.nikula
On 1/12/23 23:36, Arun R Murthy wrote:
> DP2.0 E11 defines a new register to facilitate SDP error detection by a
> 128B/132B capable DPRX device.
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
> include/drm/display/drm_dp.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index 9bc22a02874d..8bf6f0a60c38 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -691,6 +691,9 @@
> # define DP_FEC_LANE_2_SELECT (2 << 4)
> # define DP_FEC_LANE_3_SELECT (3 << 4)
>
> +#define DP_SDP_ERROR_DETECTION 0x121 /* DP 2.0 E11 */
If we're sticking with copying the exact naming from the DP spec
this might be more correctly be named DP_SDP_ERROR_DETECTION_CONFIGURATION
Harry
> +#define DP_SDP_CRC16_128B132B_EN BIT(0)
> +
> #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
> # define DP_AUX_FRAME_SYNC_VALID (1 << 0)
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 1/2] drm: Add SDP Error Detection Configuration Register
@ 2023-01-13 20:40 ` Harry Wentland
0 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2023-01-13 20:40 UTC (permalink / raw)
To: Arun R Murthy, intel-gfx, dri-devel, jani.nikula
On 1/12/23 23:36, Arun R Murthy wrote:
> DP2.0 E11 defines a new register to facilitate SDP error detection by a
> 128B/132B capable DPRX device.
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
> include/drm/display/drm_dp.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index 9bc22a02874d..8bf6f0a60c38 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -691,6 +691,9 @@
> # define DP_FEC_LANE_2_SELECT (2 << 4)
> # define DP_FEC_LANE_3_SELECT (3 << 4)
>
> +#define DP_SDP_ERROR_DETECTION 0x121 /* DP 2.0 E11 */
If we're sticking with copying the exact naming from the DP spec
this might be more correctly be named DP_SDP_ERROR_DETECTION_CONFIGURATION
Harry
> +#define DP_SDP_CRC16_128B132B_EN BIT(0)
> +
> #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
> # define DP_AUX_FRAME_SYNC_VALID (1 << 0)
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register
2023-01-13 4:36 ` Arun R Murthy
@ 2023-01-19 11:47 ` Arun R Murthy
-1 siblings, 0 replies; 27+ messages in thread
From: Arun R Murthy @ 2023-01-19 11:47 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula
DP2.0 E11 defines a new register to facilitate SDP error detection by a
128B/132B capable DPRX device.
v2: Update the macro name to reflect the DP spec(Harry)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
include/drm/display/drm_dp.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 632376c291db..358db4a9f167 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -692,6 +692,9 @@
# define DP_FEC_LANE_2_SELECT (2 << 4)
# define DP_FEC_LANE_3_SELECT (3 << 4)
+#define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */
+#define DP_SDP_CRC16_128B132B_EN BIT(0)
+
#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register
@ 2023-01-19 11:47 ` Arun R Murthy
0 siblings, 0 replies; 27+ messages in thread
From: Arun R Murthy @ 2023-01-19 11:47 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula; +Cc: Arun R Murthy
DP2.0 E11 defines a new register to facilitate SDP error detection by a
128B/132B capable DPRX device.
v2: Update the macro name to reflect the DP spec(Harry)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
include/drm/display/drm_dp.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 632376c291db..358db4a9f167 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -692,6 +692,9 @@
# define DP_FEC_LANE_2_SELECT (2 << 4)
# define DP_FEC_LANE_3_SELECT (3 << 4)
+#define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */
+#define DP_SDP_CRC16_128B132B_EN BIT(0)
+
#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCHv2 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
2023-01-19 11:47 ` Arun R Murthy
@ 2023-01-19 11:47 ` Arun R Murthy
-1 siblings, 0 replies; 27+ messages in thread
From: Arun R Murthy @ 2023-01-19 11:47 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula
Enable SDP error detection configuration, this will set CRC16 in
128b/132b link layer.
For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
added to enable/disable SDP CRC applicable for DP2.0 only, but the
default value of this bit will enable CRC16 in 128b/132b hence
skipping this write.
Corrective actions on SDP corruption is yet to be defined.
v2: Moved the CRC enable to link training init(Jani N)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
.../gpu/drm/i915/display/intel_dp_link_training.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 3d3efcf02011..7064e465423b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1453,4 +1453,16 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
if (!passed)
intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
+
+ /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
+ if (intel_dp_is_uhbr(crtc_state) && passed)
+ drm_dp_dpcd_writeb(&intel_dp->aux,
+ DP_SDP_ERROR_DETECTION_CONFIGURATION,
+ DP_SDP_CRC16_128B132B_EN);
+ /*
+ * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
+ * disable SDP CRC. This is applicable for Display version 13.
+ * Default value of bit 31 is '0' hence discarding the write
+ */
+ /* TODO: Corrective actions on SDP corruption yet to be defined */
}
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCHv2 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
@ 2023-01-19 11:47 ` Arun R Murthy
0 siblings, 0 replies; 27+ messages in thread
From: Arun R Murthy @ 2023-01-19 11:47 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula; +Cc: Arun R Murthy
Enable SDP error detection configuration, this will set CRC16 in
128b/132b link layer.
For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
added to enable/disable SDP CRC applicable for DP2.0 only, but the
default value of this bit will enable CRC16 in 128b/132b hence
skipping this write.
Corrective actions on SDP corruption is yet to be defined.
v2: Moved the CRC enable to link training init(Jani N)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
.../gpu/drm/i915/display/intel_dp_link_training.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 3d3efcf02011..7064e465423b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1453,4 +1453,16 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
if (!passed)
intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
+
+ /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
+ if (intel_dp_is_uhbr(crtc_state) && passed)
+ drm_dp_dpcd_writeb(&intel_dp->aux,
+ DP_SDP_ERROR_DETECTION_CONFIGURATION,
+ DP_SDP_CRC16_128B132B_EN);
+ /*
+ * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
+ * disable SDP CRC. This is applicable for Display version 13.
+ * Default value of bit 31 is '0' hence discarding the write
+ */
+ /* TODO: Corrective actions on SDP corruption yet to be defined */
}
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCHv2 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
2023-01-19 11:47 ` Arun R Murthy
@ 2023-01-25 1:58 ` Murthy, Arun R
-1 siblings, 0 replies; 27+ messages in thread
From: Murthy, Arun R @ 2023-01-25 1:58 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
Nikula, Jani
Any comments?
Thanks and Regards,
Arun R Murthy
--------------------
> -----Original Message-----
> From: Murthy, Arun R <arun.r.murthy@intel.com>
> Sent: Thursday, January 19, 2023 5:17 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Nikula,
> Jani <jani.nikula@intel.com>
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>
> Subject: [PATCHv2 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
>
> Enable SDP error detection configuration, this will set CRC16 in 128b/132b
> link layer.
> For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is added
> to enable/disable SDP CRC applicable for DP2.0 only, but the default value of
> this bit will enable CRC16 in 128b/132b hence skipping this write.
> Corrective actions on SDP corruption is yet to be defined.
>
> v2: Moved the CRC enable to link training init(Jani N)
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
> .../gpu/drm/i915/display/intel_dp_link_training.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 3d3efcf02011..7064e465423b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -1453,4 +1453,16 @@ void intel_dp_start_link_train(struct intel_dp
> *intel_dp,
>
> if (!passed)
> intel_dp_schedule_fallback_link_training(intel_dp,
> crtc_state);
> +
> + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
> + if (intel_dp_is_uhbr(crtc_state) && passed)
> + drm_dp_dpcd_writeb(&intel_dp->aux,
> +
> DP_SDP_ERROR_DETECTION_CONFIGURATION,
> + DP_SDP_CRC16_128B132B_EN);
> + /*
> + * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
> + * disable SDP CRC. This is applicable for Display version 13.
> + * Default value of bit 31 is '0' hence discarding the write
> + */
> + /* TODO: Corrective actions on SDP corruption yet to be
> defined */
> }
> --
> 2.25.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCHv2 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
@ 2023-01-25 1:58 ` Murthy, Arun R
0 siblings, 0 replies; 27+ messages in thread
From: Murthy, Arun R @ 2023-01-25 1:58 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
Nikula, Jani
Any comments?
Thanks and Regards,
Arun R Murthy
--------------------
> -----Original Message-----
> From: Murthy, Arun R <arun.r.murthy@intel.com>
> Sent: Thursday, January 19, 2023 5:17 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Nikula,
> Jani <jani.nikula@intel.com>
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>
> Subject: [PATCHv2 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
>
> Enable SDP error detection configuration, this will set CRC16 in 128b/132b
> link layer.
> For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is added
> to enable/disable SDP CRC applicable for DP2.0 only, but the default value of
> this bit will enable CRC16 in 128b/132b hence skipping this write.
> Corrective actions on SDP corruption is yet to be defined.
>
> v2: Moved the CRC enable to link training init(Jani N)
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
> .../gpu/drm/i915/display/intel_dp_link_training.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 3d3efcf02011..7064e465423b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -1453,4 +1453,16 @@ void intel_dp_start_link_train(struct intel_dp
> *intel_dp,
>
> if (!passed)
> intel_dp_schedule_fallback_link_training(intel_dp,
> crtc_state);
> +
> + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
> + if (intel_dp_is_uhbr(crtc_state) && passed)
> + drm_dp_dpcd_writeb(&intel_dp->aux,
> +
> DP_SDP_ERROR_DETECTION_CONFIGURATION,
> + DP_SDP_CRC16_128B132B_EN);
> + /*
> + * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
> + * disable SDP CRC. This is applicable for Display version 13.
> + * Default value of bit 31 is '0' hence discarding the write
> + */
> + /* TODO: Corrective actions on SDP corruption yet to be
> defined */
> }
> --
> 2.25.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register
2023-01-19 11:47 ` Arun R Murthy
@ 2023-01-19 15:35 ` Harry Wentland
-1 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2023-01-19 15:35 UTC (permalink / raw)
To: Arun R Murthy, intel-gfx, dri-devel, jani.nikula
On 1/19/23 06:47, Arun R Murthy wrote:
> DP2.0 E11 defines a new register to facilitate SDP error detection by a
> 128B/132B capable DPRX device.
>
> v2: Update the macro name to reflect the DP spec(Harry)
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Harry
> ---
> include/drm/display/drm_dp.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index 632376c291db..358db4a9f167 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -692,6 +692,9 @@
> # define DP_FEC_LANE_2_SELECT (2 << 4)
> # define DP_FEC_LANE_3_SELECT (3 << 4)
>
> +#define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */
> +#define DP_SDP_CRC16_128B132B_EN BIT(0)
> +
> #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
> # define DP_AUX_FRAME_SYNC_VALID (1 << 0)
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register
@ 2023-01-19 15:35 ` Harry Wentland
0 siblings, 0 replies; 27+ messages in thread
From: Harry Wentland @ 2023-01-19 15:35 UTC (permalink / raw)
To: Arun R Murthy, intel-gfx, dri-devel, jani.nikula
On 1/19/23 06:47, Arun R Murthy wrote:
> DP2.0 E11 defines a new register to facilitate SDP error detection by a
> 128B/132B capable DPRX device.
>
> v2: Update the macro name to reflect the DP spec(Harry)
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Harry
> ---
> include/drm/display/drm_dp.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index 632376c291db..358db4a9f167 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -692,6 +692,9 @@
> # define DP_FEC_LANE_2_SELECT (2 << 4)
> # define DP_FEC_LANE_3_SELECT (3 << 4)
>
> +#define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */
> +#define DP_SDP_CRC16_128B132B_EN BIT(0)
> +
> #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
> # define DP_AUX_FRAME_SYNC_VALID (1 << 0)
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [PATCHv2,2/2] i915/display/dp: SDP CRC16 for 128b132b link layer (rev3)
2023-01-13 4:36 ` Arun R Murthy
` (6 preceding siblings ...)
(?)
@ 2023-01-19 12:57 ` Patchwork
-1 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-01-19 12:57 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-gfx
== Series Details ==
Series: series starting with [PATCHv2,2/2] i915/display/dp: SDP CRC16 for 128b132b link layer (rev3)
URL : https://patchwork.freedesktop.org/series/112774/
State : failure
== Summary ==
Error: make failed
CALL scripts/checksyscalls.sh
DESCEND objtool
CC [M] drivers/gpu/drm/i915/display/intel_dp.o
drivers/gpu/drm/i915/display/intel_dp.c: In function ‘intel_dp_set_dpcd_sink_rates’:
drivers/gpu/drm/i915/display/intel_dp.c:204:9: error: ‘DP_SDP_ERROR_DETECTION’ undeclared (first use in this function)
204 | DP_SDP_ERROR_DETECTION,
| ^~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_dp.c:204:9: note: each undeclared identifier is reported only once for each function it appears in
drivers/gpu/drm/i915/display/intel_dp.c:205:9: error: ‘DP_SDP_CRC16_128B132B_EN’ undeclared (first use in this function)
205 | DP_SDP_CRC16_128B132B_EN);
| ^~~~~~~~~~~~~~~~~~~~~~~~
make[5]: *** [scripts/Makefile.build:252: drivers/gpu/drm/i915/display/intel_dp.o] Error 1
make[4]: *** [scripts/Makefile.build:504: drivers/gpu/drm/i915] Error 2
make[3]: *** [scripts/Makefile.build:504: drivers/gpu/drm] Error 2
make[2]: *** [scripts/Makefile.build:504: drivers/gpu] Error 2
make[1]: *** [scripts/Makefile.build:504: drivers] Error 2
make: *** [Makefile:2008: .] Error 2
^ permalink raw reply [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register
2023-01-13 4:36 ` Arun R Murthy
@ 2023-01-20 5:59 ` Arun R Murthy
-1 siblings, 0 replies; 27+ messages in thread
From: Arun R Murthy @ 2023-01-20 5:59 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula; +Cc: Harry Wentland
DP2.0 E11 defines a new register to facilitate SDP error detection by a
128B/132B capable DPRX device.
v2: Update the macro name to reflect the DP spec(Harry)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
---
include/drm/display/drm_dp.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 632376c291db..358db4a9f167 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -692,6 +692,9 @@
# define DP_FEC_LANE_2_SELECT (2 << 4)
# define DP_FEC_LANE_3_SELECT (3 << 4)
+#define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */
+#define DP_SDP_CRC16_128B132B_EN BIT(0)
+
#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register
@ 2023-01-20 5:59 ` Arun R Murthy
0 siblings, 0 replies; 27+ messages in thread
From: Arun R Murthy @ 2023-01-20 5:59 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula; +Cc: Arun R Murthy
DP2.0 E11 defines a new register to facilitate SDP error detection by a
128B/132B capable DPRX device.
v2: Update the macro name to reflect the DP spec(Harry)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
---
include/drm/display/drm_dp.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 632376c291db..358db4a9f167 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -692,6 +692,9 @@
# define DP_FEC_LANE_2_SELECT (2 << 4)
# define DP_FEC_LANE_3_SELECT (3 << 4)
+#define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */
+#define DP_SDP_CRC16_128B132B_EN BIT(0)
+
#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [RESEND PATCHv2 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
2023-01-20 5:59 ` Arun R Murthy
@ 2023-01-20 5:59 ` Arun R Murthy
-1 siblings, 0 replies; 27+ messages in thread
From: Arun R Murthy @ 2023-01-20 5:59 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula
Enable SDP error detection configuration, this will set CRC16 in
128b/132b link layer.
For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
added to enable/disable SDP CRC applicable for DP2.0 only, but the
default value of this bit will enable CRC16 in 128b/132b hence
skipping this write.
Corrective actions on SDP corruption is yet to be defined.
v2: Moved the CRC enable to link training init(Jani N)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
.../gpu/drm/i915/display/intel_dp_link_training.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 3d3efcf02011..7064e465423b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1453,4 +1453,16 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
if (!passed)
intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
+
+ /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
+ if (intel_dp_is_uhbr(crtc_state) && passed)
+ drm_dp_dpcd_writeb(&intel_dp->aux,
+ DP_SDP_ERROR_DETECTION_CONFIGURATION,
+ DP_SDP_CRC16_128B132B_EN);
+ /*
+ * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
+ * disable SDP CRC. This is applicable for Display version 13.
+ * Default value of bit 31 is '0' hence discarding the write
+ */
+ /* TODO: Corrective actions on SDP corruption yet to be defined */
}
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [RESEND PATCHv2 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
@ 2023-01-20 5:59 ` Arun R Murthy
0 siblings, 0 replies; 27+ messages in thread
From: Arun R Murthy @ 2023-01-20 5:59 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula; +Cc: Arun R Murthy
Enable SDP error detection configuration, this will set CRC16 in
128b/132b link layer.
For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
added to enable/disable SDP CRC applicable for DP2.0 only, but the
default value of this bit will enable CRC16 in 128b/132b hence
skipping this write.
Corrective actions on SDP corruption is yet to be defined.
v2: Moved the CRC enable to link training init(Jani N)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
.../gpu/drm/i915/display/intel_dp_link_training.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 3d3efcf02011..7064e465423b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1453,4 +1453,16 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
if (!passed)
intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
+
+ /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
+ if (intel_dp_is_uhbr(crtc_state) && passed)
+ drm_dp_dpcd_writeb(&intel_dp->aux,
+ DP_SDP_ERROR_DETECTION_CONFIGURATION,
+ DP_SDP_CRC16_128B132B_EN);
+ /*
+ * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
+ * disable SDP CRC. This is applicable for Display version 13.
+ * Default value of bit 31 is '0' hence discarding the write
+ */
+ /* TODO: Corrective actions on SDP corruption yet to be defined */
}
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [RESEND,PATCHv2,2/2] i915/display/dp: SDP CRC16 for 128b132b link layer (rev5)
2023-01-13 4:36 ` Arun R Murthy
` (8 preceding siblings ...)
(?)
@ 2023-01-20 6:08 ` Patchwork
-1 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-01-20 6:08 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-gfx
== Series Details ==
Series: series starting with [RESEND,PATCHv2,2/2] i915/display/dp: SDP CRC16 for 128b132b link layer (rev5)
URL : https://patchwork.freedesktop.org/series/112774/
State : failure
== Summary ==
Error: make failed
CALL scripts/checksyscalls.sh
DESCEND objtool
CC [M] drivers/gpu/drm/i915/display/intel_dp.o
drivers/gpu/drm/i915/display/intel_dp.c: In function ‘intel_dp_set_dpcd_sink_rates’:
drivers/gpu/drm/i915/display/intel_dp.c:204:9: error: ‘DP_SDP_ERROR_DETECTION’ undeclared (first use in this function)
204 | DP_SDP_ERROR_DETECTION,
| ^~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_dp.c:204:9: note: each undeclared identifier is reported only once for each function it appears in
drivers/gpu/drm/i915/display/intel_dp.c:205:9: error: ‘DP_SDP_CRC16_128B132B_EN’ undeclared (first use in this function)
205 | DP_SDP_CRC16_128B132B_EN);
| ^~~~~~~~~~~~~~~~~~~~~~~~
make[5]: *** [scripts/Makefile.build:252: drivers/gpu/drm/i915/display/intel_dp.o] Error 1
make[4]: *** [scripts/Makefile.build:504: drivers/gpu/drm/i915] Error 2
make[3]: *** [scripts/Makefile.build:504: drivers/gpu/drm] Error 2
make[2]: *** [scripts/Makefile.build:504: drivers/gpu] Error 2
make[1]: *** [scripts/Makefile.build:504: drivers] Error 2
make: *** [Makefile:2008: .] Error 2
^ permalink raw reply [flat|nested] 27+ messages in thread